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Whitespace removal.

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This commit is contained in:
Ralf Corsepius
2009-11-30 05:09:41 +00:00
parent ac7af4a359
commit 359e537416
199 changed files with 1685 additions and 1685 deletions
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12
c/src/lib/libcpu/arm/at91rm9200/clock/clock.c
View File

@@ -34,7 +34,7 @@ static unsigned long st_pimr_reload;
static void clock_isr_on(const rtems_irq_connect_data *unused)
{
/* enable timer interrupt */
ST_REG(ST_IER) = ST_SR_PITS;
ST_REG(ST_IER) = ST_SR_PITS;
}
/**
@@ -58,13 +58,13 @@ static void clock_isr_off(const rtems_irq_connect_data *unused)
static int clock_isr_is_on(const rtems_irq_connect_data *irq)
{
/* check timer interrupt */
return ST_REG(ST_IMR) & ST_SR_PITS;
return ST_REG(ST_IMR) & ST_SR_PITS;
}
rtems_isr Clock_isr(rtems_vector_number vector);
/* Replace the first value with the clock's interrupt name. */
rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ,
rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ,
(rtems_irq_hdl)Clock_isr,
clock_isr_on,
clock_isr_off,
@@ -88,11 +88,11 @@ void Clock_driver_support_initialize_hardware(void)
(((rtems_configuration_get_microseconds_per_tick() * slck) + (1000000/2))/ 1000000);
st_pimr_reload = st_pimr_value;
/* read the status to clear the int */
/* read the status to clear the int */
st_str = ST_REG(ST_SR);
/* set priority */
AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7);
AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7);
/* set the timer value */
ST_REG(ST_PIMR) = st_pimr_reload;

46
c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c
View File

@@ -1,7 +1,7 @@
/*
* Console driver for AT91RM9200 DBGU port
*
* This driver uses the shared console driver in
* This driver uses the shared console driver in
* ...../libbsp/shared/console.c
*
* Copyright (c) 2003 by Cogent Computer Systems
@@ -38,8 +38,8 @@ static void dbgu_write_polled(int minor, char c);
static int dbgu_set_attributes(int minor, const struct termios *t);
/* Pointers to functions for handling the UART. */
console_fns dbgu_fns =
{
console_fns dbgu_fns =
{
libchip_serial_default_probe,
dbgu_first_open,
dbgu_last_close,
@@ -54,23 +54,23 @@ console_fns dbgu_fns =
/* Functions called via callbacks (i.e. the ones in uart_fns */
/*********************************************************************/
/*
/*
* This is called the first time each device is opened. Since
* the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd enable interrupts here.
* the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd enable interrupts here.
*/
static int dbgu_first_open(int major, int minor, void *arg)
static int dbgu_first_open(int major, int minor, void *arg)
{
return 0;
}
/*
/*
* This is called the last time each device is closed. Since
* the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd disable interrupts here.
* the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd disable interrupts here.
*/
static int dbgu_last_close(int major, int minor, void *arg)
static int dbgu_last_close(int major, int minor, void *arg)
{
return 0;
}
@@ -82,7 +82,7 @@ static int dbgu_last_close(int major, int minor, void *arg)
* return -1 if there's no data, otherwise return
* the character in lowest 8 bits of returned int.
*/
static int dbgu_read(int minor)
static int dbgu_read(int minor)
{
char c;
console_tbl *console_entry;
@@ -99,15 +99,15 @@ static int dbgu_read(int minor)
if (!(dbgu->sr & DBGU_INT_RXRDY)) {
return -1;
}
c = dbgu->rhr & 0xff;
c = dbgu->rhr & 0xff;
return c;
}
/*
* Write buffer to UART
/*
* Write buffer to UART
*
* return 1 on success, -1 on error
*/
@@ -133,17 +133,17 @@ static int dbgu_write(int minor, const char *buf, int len)
break;
}
}
c = (char) buf[i];
dbgu->thr = c;
/* the TXRDY flag does not seem to update right away (is this true?) */
/* so we wait a bit before continuing */
for (x = 0; x < 100; x++) {
dbg_dly++; /* using a global so this doesn't get optimized out */
}
}
return 1;
}
@@ -186,7 +186,7 @@ static void dbgu_write_polled(int minor, char c)
}
/* This is for setting baud rate, bits, etc. */
static int dbgu_set_attributes(int minor, const struct termios *t)
static int dbgu_set_attributes(int minor, const struct termios *t)
{
return 0;
}
@@ -197,7 +197,7 @@ static int dbgu_set_attributes(int minor, const struct termios *t)
* functions use them instead.
*/
/***********************************************************************/
/*
/*
* Read from UART. This is used in the exit code, and can't
* rely on interrupts.
*/
@@ -208,7 +208,7 @@ int dbgu_poll_read(int minor)
/*
* Write a character to the console. This is used by printk() and
* Write a character to the console. This is used by printk() and
* maybe other low level functions. It should not use interrupts or any
* RTEMS system calls. It needs to be very simple
*/

10
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h
View File

@@ -32,7 +32,7 @@ typedef volatile unsigned long vulong;
#define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c))
/* Control Register - 32 of them */
#define AIC_CTL_BASE 0xFFFFF100
#define AIC_CTL_BASE 0xFFFFF100
#define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
/* Register Offsets */
@@ -103,9 +103,9 @@ typedef volatile unsigned long vulong;
/* AIC_SMR */
#define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0)
#define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */
#define AIC_SMR_SRC_EDGE_LOW (1 << 5)
#define AIC_SMR_SRC_LVL_HI (2 << 5)
#define AIC_SMR_SRC_EDGE_HI (3 << 5)
#define AIC_SMR_SRC_EDGE_LOW (1 << 5)
#define AIC_SMR_SRC_LVL_HI (2 << 5)
#define AIC_SMR_SRC_EDGE_HI (3 << 5)
/**************************************************************************/
/* Debug Unit */
@@ -192,7 +192,7 @@ typedef volatile unsigned long vulong;
* Note that each of the following peripherals has it's own
* set of these registers starting at offset 0x100 from it's
* base address: DBGU, SPI, USART and SSC
* To access the DMA for a peripheral, use the macro for that
* To access the DMA for a peripheral, use the macro for that
* peripheral but with these register offsets
**************************************************************************/
/* Register Offsets */

2
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2003 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*

6
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2003 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -104,7 +104,7 @@
#define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */
#define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */
#define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */
/* Receive Status Register, EMAC_RSR, Offset 0x20 */
#define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */
#define EMAC_RSR_REC BIT1 /* 1 = Frame received */
@@ -137,7 +137,7 @@
#define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */
#define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */
#define EMAC_MAN_HIGH BIT30 /* Must be set */
#define EMAC_MAN_LOW BIT31
#define EMAC_MAN_LOW BIT31
/*
* Bit assignments for Receive Buffer Descriptor

86
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2002 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -59,16 +59,16 @@
*
* PORT A
*/
#define GPIO_0 BIT0
#define GPIO_1 BIT1
#define GPIO_2 BIT2
#define GPIO_3 BIT3
#define GPIO_4 BIT4
#define GPIO_5 BIT5
#define GPIO_6 BIT6
#define GPIO_7 BIT7
#define GPIO_8 BIT8
#define GPIO_9 BIT9
#define GPIO_0 BIT0
#define GPIO_1 BIT1
#define GPIO_2 BIT2
#define GPIO_3 BIT3
#define GPIO_4 BIT4
#define GPIO_5 BIT5
#define GPIO_6 BIT6
#define GPIO_7 BIT7
#define GPIO_8 BIT8
#define GPIO_9 BIT9
#define GPIO_10 BIT10
#define GPIO_11 BIT11
#define GPIO_12 BIT12
@@ -92,16 +92,16 @@
#define GPIO_30 BIT30
#define GPIO_31 BIT31
/* PORT B */
#define GPIO_32 BIT0
#define GPIO_33 BIT1
#define GPIO_34 BIT2
#define GPIO_35 BIT3
#define GPIO_36 BIT4
#define GPIO_37 BIT5
#define GPIO_38 BIT6
#define GPIO_39 BIT7
#define GPIO_40 BIT8
#define GPIO_41 BIT9
#define GPIO_32 BIT0
#define GPIO_33 BIT1
#define GPIO_34 BIT2
#define GPIO_35 BIT3
#define GPIO_36 BIT4
#define GPIO_37 BIT5
#define GPIO_38 BIT6
#define GPIO_39 BIT7
#define GPIO_40 BIT8
#define GPIO_41 BIT9
#define GPIO_42 BIT10
#define GPIO_43 BIT11
#define GPIO_44 BIT12
@@ -125,16 +125,16 @@
#define GPIO_62 BIT30
#define GPIO_63 BIT31
/* PORT C */
#define GPIO_64 BIT0
#define GPIO_65 BIT1
#define GPIO_66 BIT2
#define GPIO_67 BIT3
#define GPIO_68 BIT4
#define GPIO_69 BIT5
#define GPIO_70 BIT6
#define GPIO_71 BIT7
#define GPIO_72 BIT8
#define GPIO_73 BIT9
#define GPIO_64 BIT0
#define GPIO_65 BIT1
#define GPIO_66 BIT2
#define GPIO_67 BIT3
#define GPIO_68 BIT4
#define GPIO_69 BIT5
#define GPIO_70 BIT6
#define GPIO_71 BIT7
#define GPIO_72 BIT8
#define GPIO_73 BIT9
#define GPIO_74 BIT10
#define GPIO_75 BIT11
#define GPIO_76 BIT12
@@ -158,16 +158,16 @@
#define GPIO_94 BIT30
#define GPIO_95 BIT31
/* PORT D */
#define GPIO_96 BIT0
#define GPIO_97 BIT1
#define GPIO_98 BIT2
#define GPIO_99 BIT3
#define GPIO_100 BIT4
#define GPIO_101 BIT5
#define GPIO_102 BIT6
#define GPIO_103 BIT7
#define GPIO_104 BIT8
#define GPIO_105 BIT9
#define GPIO_96 BIT0
#define GPIO_97 BIT1
#define GPIO_98 BIT2
#define GPIO_99 BIT3
#define GPIO_100 BIT4
#define GPIO_101 BIT5
#define GPIO_102 BIT6
#define GPIO_103 BIT7
#define GPIO_104 BIT8
#define GPIO_105 BIT9
#define GPIO_106 BIT10
#define GPIO_107 BIT11
#define GPIO_108 BIT12
@@ -376,9 +376,9 @@
#define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */
#define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */
#define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */
/* Port D, Alternate Function B */
#define PIOC_ASR_TSYNC BIT7 /* ETM Sync */
#define PIOC_ASR_TCLK BIT8 /* ETM Clock */
#define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */

2
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2002 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*

2
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2002 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*

2
c/src/lib/libcpu/arm/at91rm9200/include/bits.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2002 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*

8
c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S
View File

@@ -2,7 +2,7 @@
* Atmel AT91RM9200 Interrupt handler
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -12,7 +12,7 @@
* $Id$
*/
#define __asm__
.globl bsp_interrupt_dispatch
bsp_interrupt_dispatch :
/*
@@ -21,7 +21,7 @@ bsp_interrupt_dispatch :
* and load vector into r0 and handler address into r1.
*/
ldr r0, =0xFFFFF100 /* AIC_CTL_BASE + AIC_IVR */
ldr r1, [r0]
ldr r1, [r0]
str r1, [r0] /* write back in case we are using protect */
ldr r0, =0xFFFFF108 /* AIC_CTL_BASE + AIC_ISR */
@@ -35,7 +35,7 @@ bsp_interrupt_dispatch :
IRQ_return:
ldr r2, =0xFFFFF130 /* AIC_CTL_BASE + AIC_EIOCR */
str r1, [r2]
ldmia sp!,{lr}
mov pc, lr

6
c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c
View File

@@ -2,7 +2,7 @@
* Atmel AT91RM9200 Interrupt handler
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -17,8 +17,8 @@
extern void default_int_handler(void);
/*
* Interrupt system initialization. Disable interrupts, clear
/*
* Interrupt system initialization. Disable interrupts, clear
* any that are pending.
*/
void BSP_rtems_irq_mngt_init(void)

34
c/src/lib/libcpu/arm/at91rm9200/irq/irq.c
View File

@@ -2,7 +2,7 @@
* Atmel AT91RM9200 Interrupt handler
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -34,52 +34,52 @@ static int isValidInterrupt(int irq)
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
/*
* Check if default handler is actually connected. If not, issue
* an error. Note: irq->name is a number corresponding to the
* sources PID (see the at91rm9200_pid for this mapping). We
* convert it to a long word offset to get source's vector register
* Check if default handler is actually connected. If not, issue
* an error. Note: irq->name is a number corresponding to the
* sources PID (see the at91rm9200_pid for this mapping). We
* convert it to a long word offset to get source's vector register
*/
if (AIC_SVR_REG(irq->name * 4) != (uint32_t) default_int_handler) {
return 0;
}
rtems_interrupt_disable(level);
/*
* store the new handler
*/
AIC_SVR_REG(irq->name * 4) = (uint32_t) irq->hdl;
/*
* unmask interrupt
*/
AIC_CTL_REG(AIC_IECR) = 1 << irq->name;
/*
* Enable interrupt on device
*/
if(irq->on) {
irq->on(irq);
}
rtems_interrupt_enable(level);
return 1;
}
/*
/*
* Remove and interrupt handler
*/
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -96,7 +96,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* mask interrupt
*/
AIC_CTL_REG(AIC_IDCR) = 1 << irq->name;
/*
* Disable interrupt on device
*/
@@ -108,7 +108,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* restore the default irq value
*/
AIC_SVR_REG(irq->name * 4) = (uint32_t) default_int_handler;
rtems_interrupt_enable(level);
return 1;

10
c/src/lib/libcpu/arm/at91rm9200/irq/irq.h
View File

@@ -2,7 +2,7 @@
* Interrupt handler Header file
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -24,7 +24,7 @@ extern "C" {
/*
* Include some preprocessor value also used by assember code
*/
#include <rtems.h>
#include <at91rm9200.h>
@@ -35,7 +35,7 @@ extern void default_int_handler();
/* possible interrupt sources on the AT91RM9200 */
#define AT91RM9200_INT_FIQ 0
#define AT91RM9200_INT_SYSIRQ 1
#define AT91RM9200_INT_PIOA 2
#define AT91RM9200_INT_PIOA 2
#define AT91RM9200_INT_PIOB 3
#define AT91RM9200_INT_PIOC 4
#define AT91RM9200_INT_PIOD 5
@@ -71,7 +71,7 @@ extern void default_int_handler();
/* we can treat the AT91RM9200 AIC_SVR_BASE as */
/* a vector table */
#define VECTOR_TABLE AIC_SVR_BASE
typedef unsigned char rtems_irq_level;
typedef unsigned char rtems_irq_trigger;
@@ -117,7 +117,7 @@ void BSP_rtems_irq_mngt_init();
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);
/*
* function to get the current RTEMS irq handler for ptr->name.
* function to get the current RTEMS irq handler for ptr->name.
*/
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr);

2
c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c
View File

@@ -2,7 +2,7 @@
* Atmel AT91RM9200 PMC functions
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*

6
c/src/lib/libcpu/arm/at91rm9200/timer/timer.c
View File

@@ -4,7 +4,7 @@
* This uses timer 0 for timing measurments.
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -16,7 +16,7 @@
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted.
*
* It is important that the timer start/stop overhead be determined
* It is important that the timer start/stop overhead be determined
* when porting or modifying this code.
*
* $Id$
@@ -31,7 +31,7 @@ uint16_t tstart;
bool benchmark_timer_find_average_overhead;
uint32_t tick_time;
/*
* Set up TC0 -
* Set up TC0 -
* timer_clock2 (MCK/8)
* capture mode - this shouldn't matter
*/

12
c/src/lib/libcpu/arm/at91rm9200/usart/usart.c
View File

@@ -1,10 +1,10 @@
/*
* Driver for AT91RM9200 USART ports
*
* COPYRIGHT (c) 2006-2009.
* COPYRIGHT (c) 2006-2009.
* NCB - Sistemas Embarcados Ltda. (Brazil)
* Fernando Nicodemos <fgnicodemos@terra.com.br>
*
*
* and
*
* COPYRIGHT (c) 1989-2009.
@@ -60,7 +60,7 @@ at91rm9200_usart_regs_t *usart_get_base(int minor)
if (console_entry == NULL)
return 0;
port = (at91rm9200_usart_regs_t *) console_entry->ulCtrlPort1;
//printk( "minor=%d entry=%p port=%p\n", minor, console_entry, port );
@@ -241,11 +241,11 @@ static int usart_set_attributes(int minor, const struct termios *t)
mode |= US_MR_PAR_NONE;
baud_requested = t->c_cflag & CBAUD;
/* If not, set the dbgu console baud as USART baud default */
if (!baud_requested)
baud_requested = BSP_get_baud();
baud_requested = BSP_get_baud();
baud = rtems_termios_baud_to_number(baud_requested);
brgr = (at91rm9200_get_mck() / 16) / baud;

20
c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c
View File

@@ -35,7 +35,7 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0,
3, /* unused for ARM cpus */
0 }; /* unused for ARM cpus */
/* If you follow the code, this is never used, so any value
/* If you follow the code, this is never used, so any value
* should work
*/
#define CLOCK_VECTOR 0
@@ -72,16 +72,16 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0,
* - enable it
* - clear any pending interrupts
*
* Since you may want the clock always running, you can
* Since you may want the clock always running, you can
* enable interrupts here. If you do so, the clock_isr_on(),
* clock_isr_off(), and clock_isr_is_on() functions can be
* clock_isr_off(), and clock_isr_is_on() functions can be
* NOPs.
*/
/* set timer to generate interrupt every rtems_configuration_get_microseconds_per_tick()
* MR0/(LPC22xx_Fpclk/(PR0+1)) = 10/1000 = 0.01s
*/
*/
#define Clock_driver_support_initialize_hardware() \
do { \
T0TCR &= 0; /* disable and clear timer 0, set to */ \
@@ -95,7 +95,7 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0,
} while (0)
/**
* Do whatever you need to shut the clock down and remove the
* Do whatever you need to shut the clock down and remove the
* interrupt handler. Since this normally only gets called on
* RTEMS shutdown, you may not need to do anything other than
* remove the ISR.
@@ -110,12 +110,12 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0,
uint32_t bsp_clock_nanoseconds_since_last_tick(void)
{
uint32_t clicks;
clicks = T0TC; /*T0TC is the 32bit time counter 0*/
return (uint32_t) (rtems_configuration_get_microseconds_per_tick() - clicks) * 1000;
}
#define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick

6
c/src/lib/libcpu/arm/lpc22xx/include/lpc22xx.h
View File

@@ -2,7 +2,7 @@
* Philips LPC22XX/LPC21xx Register definitions
*
* Copyright (c) 2006 by Ray <rayx.cn@gmail.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -318,7 +318,7 @@
#define CAN5TDA3 (*((volatile unsigned long *) 0xE0054058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */
#define CAN5TDB3 (*((volatile unsigned long *) 0xE005405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */
#ifdef CONFIG_ARCH_LPC22xx
#ifdef CONFIG_ARCH_LPC22xx
#define CAN6MOD (*((volatile unsigned long *) 0xE0058000)) /* lpc2292\lpc2294 only */
#define CAN6CMR (*((volatile unsigned long *) 0xE0058004)) /* lpc2292\lpc2294 only */
#define CAN6GSR (*((volatile unsigned long *) 0xE0058008)) /* lpc2292\lpc2294 only */
@@ -455,7 +455,7 @@
/*
Register define for constant
*/
*/
#define REG_U0RBR 0xE000C000
#define REG_U1RBR 0xE0010000

6
c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S
View File

@@ -12,8 +12,8 @@
* $Id$
*/
#define __asm__
/*
/*
* BSP specific interrupt handler for INT or FIQ. In here
* you do determine which interrupt happened and call its
* handler.
@@ -30,7 +30,7 @@ bsp_interrupt_dispatch :
* From source, determine offset into expanded vector table
* and load handler address into r0.
*/
ldr r0, =0xFFFFF030 /* Read the vector number */
ldr r0, [r0]
#ifdef __thumb__

12
c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c
View File

@@ -1,6 +1,6 @@
/*
* NXP/Philips LPC22XX/LPC21xx Interrupt handler
* Ray 2007 <rayx.cn@gmail.com> to support LPC ARM
* Ray 2007 <rayx.cn@gmail.com> to support LPC ARM
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -16,8 +16,8 @@
extern void default_int_handler(void);
/*
* Interrupt system initialization. Disable interrupts, clear
/*
* Interrupt system initialization. Disable interrupts, clear
* any that are pending.
*/
void BSP_rtems_irq_mngt_init(void)
@@ -33,7 +33,7 @@ void BSP_rtems_irq_mngt_init(void)
for (i=0; i<BSP_MAX_INT; i++) {
*(vectorTable + i) = (long)(default_int_handler);
}
/*
* Set IRQHandler
*/
@@ -56,10 +56,10 @@ void BSP_rtems_irq_mngt_init(void)
* In case we must find an ABORT error,
* enable the next lines and set a breakpoint
* in ABORTHandler.
*/
*/
#if 1
DATA_ABORT_VECTOR_ADDR = 0xE59FF018;
#endif
#endif
/*
* Init the Vectored Interrupt Controller (VIC)

20
c/src/lib/libcpu/arm/lpc22xx/irq/irq.c
View File

@@ -1,7 +1,7 @@
/*
* Philps LPC22XX Interrupt handler
*
* Copyright (c) 2006 by Ray<rayx.cn@gmail.com> to support LPC ARM
*
* Copyright (c) 2006 by Ray<rayx.cn@gmail.com> to support LPC ARM
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -37,11 +37,11 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
rtems_interrupt_level level;
rtems_irq_hdl *bsp_tbl;
int *vic_cntl;
bsp_tbl = (rtems_irq_hdl *)VICVectAddrBase;
vic_cntl=(int *)VICVectCntlBase;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -66,8 +66,8 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
*/
vic_cntl[irq->name] = 0x20 | irq->name;
VICIntEnable |= 1 << irq->name;
VICIntEnable |= 1 << irq->name;
if(irq->on)
{
irq->on(irq);
@@ -75,11 +75,11 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
rtems_interrupt_enable(level);
return 1;
}
/*
/*
* Remove and interrupt handler
*
* You should only have to add the code to mask the interrupt.
@@ -91,7 +91,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
rtems_irq_hdl *bsp_tbl;
bsp_tbl = (rtems_irq_hdl *)&VICVectAddr0;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -116,7 +116,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* restore the default irq value
*/
bsp_tbl[irq->name] = default_int_handler;
rtems_interrupt_enable(level);
return 1;

14
c/src/lib/libcpu/arm/lpc22xx/irq/irq.h
View File

@@ -1,8 +1,8 @@
/*
* Interrupt handler Header file
*
* Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM
*
* Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -25,7 +25,7 @@ extern "C" {
/*
* Include some preprocessor value also used by assember code
*/
#include <rtems.h>
#include <lpc22xx.h>
@@ -66,7 +66,7 @@ extern void default_int_handler();
#define LPC22xx_INTERRUPT_CAN4RX 27 /* CAN2 Rx interrupt */
#define BSP_MAX_INT 28
#define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L)
#define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L)
#define SOFTWARE_INTERRUPT_VECTOR_ADDR (*(u_long *)0x00000008L)
#define PREFETCH_ABORT_VECTOR_ADDR (*(u_long *)0x0000000CL)
#define DATA_ABORT_VECTOR_ADDR (*(u_long *)0x00000010L)
@@ -77,7 +77,7 @@ extern void default_int_handler();
#define IRQ_ISR_ADDR (*(u_long *)0x00000038L)
#define FIQ_ISR_ADDR (*(u_long *)0x0000003CL)
typedef unsigned char rtems_irq_level;
typedef unsigned char rtems_irq_trigger;
@@ -91,7 +91,7 @@ typedef int (*rtems_irq_is_enabled)(const struct __rtems_irq_connect_data__*);
//extern rtems_irq_hdl bsp_vector_table[BSP_MAX_INT];
#define VECTOR_TABLE VICVectAddrBase
typedef struct __rtems_irq_connect_data__ {
/* IRQ line */
rtems_irq_number name;
@@ -127,7 +127,7 @@ void BSP_rtems_irq_mngt_init();
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);
/*
* function to get the current RTEMS irq handler for ptr->name.
* function to get the current RTEMS irq handler for ptr->name.
*/
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr);

8
c/src/lib/libcpu/arm/lpc22xx/timer/lpc_timer.h
View File

@@ -11,16 +11,16 @@
#define TCR_ENABLE_BIT 0
#define TCR_RESET_BIT 1
// The channel name which is used in matching, in fact they represent
// corresponding Match Register
// The channel name which is used in matching, in fact they represent
// corresponding Match Register
#define CH_MAXNUM 4
#define CH0 0
#define CH1 1
#define CH2 2
#define CH3 3
// The channel name which is used in capturing, in fact they represent
// corresponding Capture Register
// The channel name which is used in capturing, in fact they represent
// corresponding Capture Register
#define CPCH_MAXNUM 4
#define CPCH0 0
#define CPCH1 1

6
c/src/lib/libcpu/arm/lpc22xx/timer/timer.c
View File

@@ -2,7 +2,7 @@
* RTL22xx board Timer driver
*
* This uses Timer1 for timing measurments.
*
*
* By Ray xu<rayx.cn@gmail.com>, modify form Mc9328mxl RTEMS DSP
*
* The license and distribution terms for this file may be
@@ -16,7 +16,7 @@
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted.
*
* It is important that the timer start/stop overhead be determined
* It is important that the timer start/stop overhead be determined
* when porting or modifying this code.
*
* $Id$
@@ -31,7 +31,7 @@ uint32_t g_freq;
bool benchmark_timer_find_average_overhead;
/*
* Set up Timer 1
*/

10
c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c
View File

@@ -37,12 +37,12 @@ rtems_irq_connect_data clock_isr_data = {
.isOn = clock_isr_is_on,
};
/* If you follow the code, this is never used, so any value
/* If you follow the code, this is never used, so any value
* should work
*/
#define CLOCK_VECTOR 0
/**
* When we get the clock interrupt
* - clear the interrupt bit?
@@ -72,9 +72,9 @@ rtems_irq_connect_data clock_isr_data = {
* - enable it
* - clear any pending interrupts
*
* Since you may want the clock always running, you can
* Since you may want the clock always running, you can
* enable interrupts here. If you do so, the clock_isr_on(),
* clock_isr_off(), and clock_isr_is_on() functions can be
* clock_isr_off(), and clock_isr_is_on() functions can be
* NOPs.
*/
#define Clock_driver_support_initialize_hardware() \
@@ -95,7 +95,7 @@ rtems_irq_connect_data clock_isr_data = {
} while (0)
/**
* Do whatever you need to shut the clock down and remove the
* Do whatever you need to shut the clock down and remove the
* interrupt handler. Since this normally only gets called on
* RTEMS shutdown, you may not need to do anything other than
* remove the ISR.

10
c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2003 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -75,12 +75,12 @@
#define MC9328MXL_TMR_TCTL_CAP_FALL (2 << 6)
#define MC9328MXL_TMR_TCTL_CAP_ANY (3 << 6)
#define MC9328MXL_TMR_TCTL_OM (bit(5))
#define MC9328MXL_TMR_TCTL_IRQEN (bit(4))
#define MC9328MXL_TMR_TCTL_IRQEN (bit(4))
#define MC9328MXL_TMR_TCTL_CLKSRC_STOP (0 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 (1 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16 (2 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_TIN (3 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX (4 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX (4 << 1)
#define MC9328MXL_TMR_TCTL_TEN (bit(0))
#define MC9328MXL_UART1_RXD (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x00)))
@@ -221,7 +221,7 @@ typedef struct {
#define MC9328MXL_UART_CR3_INVT (bit(1))
#define MC9328MXL_UART_CR3_BPEN (bit(0))
#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)
#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)
#define MC9328MXL_UART_CR4_INVR (bit(9))
#define MC9328MXL_UART_CR4_ENIRI (bit(8))
#define MC9328MXL_UART_CR4_WKEN (bit(7))
@@ -313,7 +313,7 @@ typedef struct {
#define MC9328MXL_PLL_SPCTL_MFI_SHIFT (10)
#define MC9328MXL_PLL_SPCTL_MFN_MASK (0x000003ff)
#define MC9328MXL_PLL_SPCTL_MFN_SHIFT (0)
#define MC9328MXL_GPIOA_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00)))
#define MC9328MXL_GPIOA_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x04)))

6
c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S
View File

@@ -12,8 +12,8 @@
* $Id$
*/
#define __asm__
/*
/*
* BSP specific interrupt handler for INT or FIQ. In here
* you do determine which interrupt happened and call its
* handler.
@@ -29,7 +29,7 @@ bsp_interrupt_dispatch :
ldr r1, [r0]
mov r1, r1, LSR #16 /* get the NIVECTOR into 16 LSbits */
/* find the ISR's address based on the vector */
/* find the ISR's address based on the vector */
ldr r0, =bsp_vector_table
mov r1, r1, LSL #3 /* Shift vector to get offset into table */
add r1, r0, r1 /* r1 has address of vector entry */

6
c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c
View File

@@ -2,7 +2,7 @@
* Motorola MC9328MXL Interrupt handler
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -17,8 +17,8 @@
extern void default_int_handler(void);
/*
* Interrupt system initialization. Disable interrupts, clear
/*
* Interrupt system initialization. Disable interrupts, clear
* any that are pending.
*/
void BSP_rtems_irq_mngt_init(void)

10
c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c
View File

@@ -2,7 +2,7 @@
* Motorola MC9328MXL Interrupt handler
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -38,7 +38,7 @@ static int isValidInterrupt(int irq)
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -65,13 +65,13 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
irq->on(irq);
}
rtems_interrupt_enable(level);
return 1;
}
/*
/*
* Remove and interrupt handler
*
* You should only have to add the code to mask the interrupt.

114
c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h
View File

@@ -2,7 +2,7 @@
* Interrupt handler Header file
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -27,7 +27,7 @@ extern "C" {
/*
* Include some preprocessor value also used by assember code
*/
#include <rtems.h>
#include <mc9328mxl.h>
@@ -37,72 +37,72 @@ extern void default_int_handler();
**********************************************************************/
/* possible interrupt sources on the MC9328MXL */
#define BSP_INT_UART3_PFERR 0
#define BSP_INT_UART3_RTS 1
#define BSP_INT_UART3_DTR 2
#define BSP_INT_UART3_UARTC 3
#define BSP_INT_UART3_TX 4
#define BSP_INT_PEN_UP 5
#define BSP_INT_UART3_PFERR 0
#define BSP_INT_UART3_RTS 1
#define BSP_INT_UART3_DTR 2
#define BSP_INT_UART3_UARTC 3
#define BSP_INT_UART3_TX 4
#define BSP_INT_PEN_UP 5
#define BSP_INT_CSI 6
#define BSP_INT_MMA_MAC 7
#define BSP_INT_MMA_MAC 7
#define BSP_INT_MMA 8
#define BSP_INT_COMP 9
#define BSP_INT_MSIRQ 10
#define BSP_INT_GPIO_PORTA 11
#define BSP_INT_GPIO_PORTB 12
#define BSP_INT_GPIO_PORTC 13
#define BSP_INT_LCDC 14
#define BSP_INT_SIM_IRQ 15
#define BSP_INT_SIM_DATA 16
#define BSP_INT_MSIRQ 10
#define BSP_INT_GPIO_PORTA 11
#define BSP_INT_GPIO_PORTB 12
#define BSP_INT_GPIO_PORTC 13
#define BSP_INT_LCDC 14
#define BSP_INT_SIM_IRQ 15
#define BSP_INT_SIM_DATA 16
#define BSP_INT_RTC 17
#define BSP_INT_RTC_SAM 18
#define BSP_INT_UART2_PFERR 19
#define BSP_INT_UART2_RTS 20
#define BSP_INT_UART2_DTR 21
#define BSP_INT_UART2_UARTC 22
#define BSP_INT_UART2_TX 23
#define BSP_INT_UART2_RX 24
#define BSP_INT_UART1_PFERR 25
#define BSP_INT_UART1_RTS 26
#define BSP_INT_UART1_DTR 27
#define BSP_INT_UART1_UARTC 28
#define BSP_INT_UART1_TX 29
#define BSP_INT_UART1_RX 30
#define BSP_INT_RES31 31
#define BSP_INT_RES32 32
#define BSP_INT_PEN_DATA 33
#define BSP_INT_RTC_SAM 18
#define BSP_INT_UART2_PFERR 19
#define BSP_INT_UART2_RTS 20
#define BSP_INT_UART2_DTR 21
#define BSP_INT_UART2_UARTC 22
#define BSP_INT_UART2_TX 23
#define BSP_INT_UART2_RX 24
#define BSP_INT_UART1_PFERR 25
#define BSP_INT_UART1_RTS 26
#define BSP_INT_UART1_DTR 27
#define BSP_INT_UART1_UARTC 28
#define BSP_INT_UART1_TX 29
#define BSP_INT_UART1_RX 30
#define BSP_INT_RES31 31
#define BSP_INT_RES32 32
#define BSP_INT_PEN_DATA 33
#define BSP_INT_PWM 34
#define BSP_INT_MMC_IRQ 35
#define BSP_INT_SSI2_TX 36
#define BSP_INT_SSI2_RX 37
#define BSP_INT_SSI2_ERR 38
#define BSP_INT_MMC_IRQ 35
#define BSP_INT_SSI2_TX 36
#define BSP_INT_SSI2_RX 37
#define BSP_INT_SSI2_ERR 38
#define BSP_INT_I2C 39
#define BSP_INT_SPI2 40
#define BSP_INT_SPI1 41
#define BSP_INT_SSI_TX 42
#define BSP_INT_SSI_TX_ERR 43
#define BSP_INT_SSI_RX 44
#define BSP_INT_SSI_RX_ERR 45
#define BSP_INT_TOUCH 46
#define BSP_INT_USBD0 47
#define BSP_INT_USBD1 48
#define BSP_INT_USBD2 49
#define BSP_INT_USBD3 50
#define BSP_INT_USBD4 51
#define BSP_INT_USBD5 52
#define BSP_INT_USBD6 53
#define BSP_INT_UART3_RX 54
#define BSP_INT_BTSYS 55
#define BSP_INT_BTTIM 56
#define BSP_INT_BTWUI 57
#define BSP_INT_TIMER2 58
#define BSP_INT_TIMER1 59
#define BSP_INT_DMA_ERR 60
#define BSP_INT_SSI_TX 42
#define BSP_INT_SSI_TX_ERR 43
#define BSP_INT_SSI_RX 44
#define BSP_INT_SSI_RX_ERR 45
#define BSP_INT_TOUCH 46
#define BSP_INT_USBD0 47
#define BSP_INT_USBD1 48
#define BSP_INT_USBD2 49
#define BSP_INT_USBD3 50
#define BSP_INT_USBD4 51
#define BSP_INT_USBD5 52
#define BSP_INT_USBD6 53
#define BSP_INT_UART3_RX 54
#define BSP_INT_BTSYS 55
#define BSP_INT_BTTIM 56
#define BSP_INT_BTWUI 57
#define BSP_INT_TIMER2 58
#define BSP_INT_TIMER1 59
#define BSP_INT_DMA_ERR 60
#define BSP_INT_DMA 61
#define BSP_INT_GPIO_PORTD 62
#define BSP_INT_GPIO_PORTD 62
#define BSP_INT_WDT 63
#define BSP_MAX_INT 64
typedef struct {
rtems_irq_hdl vector;
rtems_irq_hdl_param data;

14
c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c
View File

@@ -5,7 +5,7 @@
*
* Copyright (c) 2004 Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -17,7 +17,7 @@
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted.
*
* It is important that the timer start/stop overhead be determined
* It is important that the timer start/stop overhead be determined
* when porting or modifying this code.
*
* $Id$
@@ -32,13 +32,13 @@ uint32_t g_freq;
bool benchmark_timer_find_average_overhead;
/*
* Set up Timer 1
*/
void benchmark_timer_initialize( void )
{
MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 |
MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 |
MC9328MXL_TMR_TCTL_FRR |
MC9328MXL_TMR_TCTL_TEN);
/* set prescaler to 1 (register value + 1) */ \
@@ -80,12 +80,12 @@ int benchmark_timer_read( void )
total = (t - g_start);
/* convert to nanoseconds */
total = (total * 1000)/ g_freq;
total = (total * 1000)/ g_freq;
if ( benchmark_timer_find_average_overhead == 1 ) {
return (int) total;
return (int) total;
} else if ( total < LEAST_VALID ) {
return 0;
return 0;
}
/*
* Somehow convert total into microseconds

50
c/src/lib/libcpu/arm/pxa255/ffuart/ffuart.c
View File

@@ -31,8 +31,8 @@ static void ffuart_write_polled(int minor, char c);
static int ffuart_set_attributes(int minor, const struct termios *t);
/* Pointers to functions for handling the UART. */
console_fns ffuart_fns =
{
console_fns ffuart_fns =
{
libchip_serial_default_probe,
ffuart_first_open,
ffuart_last_close,
@@ -45,23 +45,23 @@ console_fns ffuart_fns =
};
/*
/*
* This is called the first time each device is opened. Since
* the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd enable interrupts here.
* the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd enable interrupts here.
*/
static int ffuart_first_open(int major, int minor, void *arg)
static int ffuart_first_open(int major, int minor, void *arg)
{
return 0;
}
/*
/*
* This is called the last time each device is closed. Since
* the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd disable interrupts here.
* the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd disable interrupts here.
*/
static int ffuart_last_close(int major, int minor, void *arg)
static int ffuart_last_close(int major, int minor, void *arg)
{
return 0;
}
@@ -73,7 +73,7 @@ static int ffuart_last_close(int major, int minor, void *arg)
* return -1 if there's no data, otherwise return
* the character in lowest 8 bits of returned int.
*/
static int ffuart_read(int minor)
static int ffuart_read(int minor)
{
char c;
console_tbl *console_entry;
@@ -90,15 +90,15 @@ static int ffuart_read(int minor)
if (!(ffuart->lsr & FULL_RECEIVE)) {
return -1;
}
c = ffuart->rbr & 0xff;
c = ffuart->rbr & 0xff;
return c;
}
/*
* Write buffer to UART
/*
* Write buffer to UART
*
* return 1 on success, -1 on error
*/
@@ -124,7 +124,7 @@ static int ffuart_write(int minor, const char *buf, int len)
break;
}
}
c = (char) buf[i];
#if ON_SKYEYE != 1
if(c=='\n'){
@@ -140,14 +140,14 @@ static int ffuart_write(int minor, const char *buf, int len)
}
#endif
ffuart->rbr = c;
/* the TXRDY flag does not seem to update right away (is this true?) */
/* so we wait a bit before continuing */
for (x = 0; x < 100; x++) {
dbg_dly++; /* using a global so this doesn't get optimized out */
}
}
return 1;
}
@@ -155,7 +155,7 @@ static int ffuart_write(int minor, const char *buf, int len)
static void ffuart_init(int minor)
{
console_tbl *console_entry;
ffuart_reg_t *ffuart;
unsigned int divisor;
@@ -163,11 +163,11 @@ static void ffuart_init(int minor)
console_entry = BSP_get_uart_from_minor(minor);
if (console_entry == NULL) {
return;
}
ffuart = (ffuart_reg_t *)console_entry->ulCtrlPort1;
ffuart->lcr |= DLAB;
/*Set the Bound*/
@@ -191,7 +191,7 @@ static void ffuart_write_polled(int minor, char c)
}
/* This is for setting baud rate, bits, etc. */
static int ffuart_set_attributes(int minor, const struct termios *t)
static int ffuart_set_attributes(int minor, const struct termios *t)
{
return 0;
}
@@ -202,7 +202,7 @@ static int ffuart_set_attributes(int minor, const struct termios *t)
* functions use them instead.
*/
/***********************************************************************/
/*
/*
* Read from UART. This is used in the exit code, and can't
* rely on interrupts.
*/
@@ -213,7 +213,7 @@ int ffuart_poll_read(int minor)
/*
* Write a character to the console. This is used by printk() and
* Write a character to the console. This is used by printk() and
* maybe other low level functions. It should not use interrupts or any
* RTEMS system calls. It needs to be very simple
*/

2
c/src/lib/libcpu/arm/pxa255/include/ffuart.h
View File

@@ -47,4 +47,4 @@ typedef struct {
#define FULL_RECEIVE 0x01
#endif

4
c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S
View File

@@ -1,7 +1,7 @@
/*
* PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
@@ -10,7 +10,7 @@
*/
#define __asm__
.globl bsp_interrupt_dispatch
bsp_interrupt_dispatch :
/*

6
c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c
View File

@@ -1,7 +1,7 @@
/*
* PXA255 interrupt controller by Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
@@ -20,8 +20,8 @@ void dummy_handler(uint32_t vector)
void (*IRQ_table[PRIMARY_IRQS])(uint32_t vector);
/*
* Interrupt system initialization. Disable interrupts, clear
/*
* Interrupt system initialization. Disable interrupts, clear
* any that are pending.
*/
void BSP_rtems_irq_mngt_init(void)

34
c/src/lib/libcpu/arm/pxa255/irq/irq.c
View File

@@ -1,7 +1,7 @@
/*
* PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
@@ -32,54 +32,54 @@ static int isValidInterrupt(int irq)
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
/*
* Check if default handler is actually connected. If not, issue
* an error. Note: irq->name is a number corresponding to the
* interrupt number . We
* convert it to a long word offset to get source's vector register
* Check if default handler is actually connected. If not, issue
* an error. Note: irq->name is a number corresponding to the
* interrupt number . We
* convert it to a long word offset to get source's vector register
*/
if (IRQ_table[irq->name] != dummy_handler) {
return 0;
}
_CPU_ISR_Disable(level);
/*
* store the new handler
*/
IRQ_table[irq->name] = irq->hdl;
/*
* unmask interrupt
*/
XSCALE_INT_ICMR = XSCALE_INT_ICMR | 1 << irq->name;
/*
* Enable interrupt on device
*/
if(irq->on) {
irq->on(irq);
}
_CPU_ISR_Enable(level);
return 1;
}
/*
/*
* Remove and interrupt handler
*/
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -96,7 +96,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* mask interrupt
*/
XSCALE_INT_ICMR = XSCALE_INT_ICMR & (~(1 << irq->name));
/*
* Disable interrupt on device
*/
@@ -108,7 +108,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* restore the default irq value
*/
IRQ_table[irq->name] = dummy_handler;
_CPU_ISR_Enable(level);
return 1;

6
c/src/lib/libcpu/arm/pxa255/irq/irq.h
View File

@@ -1,7 +1,7 @@
/*
* Interrupt handler Header file for PXA By Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
@@ -21,7 +21,7 @@ extern "C" {
/*
* Include some preprocessor value also used by assember code
*/
#include <rtems.h>
#include <pxa255.h>
@@ -77,7 +77,7 @@ void BSP_rtems_irq_mngt_init();
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);
/*
* function to get the current RTEMS irq handler for ptr->name.
* function to get the current RTEMS irq handler for ptr->name.
*/
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr);

6
c/src/lib/libcpu/arm/pxa255/timer/timer.c
View File

@@ -8,7 +8,7 @@
* Timer_initialize() and Read_timer(). Read_timer() usually returns
* the number of microseconds since Timer_initialize() exitted.
*
* It is important that the timer start/stop overhead be determined
* It is important that the timer start/stop overhead be determined
* when porting or modifying this code.
*
* The license and distribution terms for this file may be
@@ -29,7 +29,7 @@ bool benchmark_timer_find_average_overhead;
bool benchmark_timer_is_initialized = false;
/*
* Use the timer count register to measure.
* Use the timer count register to measure.
* The frequency of it is 3.4864MHZ
* The longest period we are able to capture is 4G/3.4864MHZ
*/
@@ -62,7 +62,7 @@ int benchmark_timer_read(void)
total -= tick_time;
else
total += 0xffffffff - tick_time; /*Round up but not overflow*/
if ( benchmark_timer_find_average_overhead == true )
return total; /*Counter cycles*/

4
c/src/lib/libcpu/arm/s3c2400/clock/support.c
View File

@@ -41,10 +41,10 @@ uint32_t get_UCLK(void)
/* return HCLK frequency */
uint32_t get_HCLK(void)
{
if (rCLKDIVN & 0x2)
if (rCLKDIVN & 0x2)
return get_FCLK()/2;
else
return get_FCLK();
return get_FCLK();
}
/* return PCLK frequency */

2
c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h
View File

@@ -472,7 +472,7 @@ typedef union
unsigned long all;
} LCDCON1;
typedef union {
typedef union {
struct {
unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */
/* VSYNC pulse's high level width by counting the */

14
c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S
View File

@@ -14,24 +14,24 @@
*/
#define __asm__
/*
* Function to obtain, execute an IT handler and acknowledge the IT
/*
* Function to obtain, execute an IT handler and acknowledge the IT
*/
.globl bsp_interrupt_dispatch
bsp_interrupt_dispatch :
bsp_interrupt_dispatch :
ldr r0, =0x14400014 /* Read rINTOFFSET */
ldr r1, [r0]
ldr r0, =bsp_vector_table
ldr r0, [r0, r1, LSL #2] /* Read the address */
stmdb sp!,{lr}
ldr lr, =IRQ_return /* prepare the return from handler */
mov pc, r0
IRQ_return:

2
c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c
View File

@@ -18,7 +18,7 @@
extern void default_int_handler();
void BSP_rtems_irq_mngt_init()
void BSP_rtems_irq_mngt_init()
{
long *vectorTable;
int i;

8
c/src/lib/libcpu/arm/s3c2400/irq/irq.c
View File

@@ -41,7 +41,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_irq_hdl *HdlTable;
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -53,7 +53,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
if (*(HdlTable + irq->name) != default_int_handler) {
return 0;
}
rtems_interrupt_disable(level);
/*
@@ -78,7 +78,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_irq_hdl *HdlTable;
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -103,7 +103,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* restore the default irq value
*/
*(HdlTable + irq->name) = default_int_handler;
rtems_interrupt_enable(level);
return 1;

60
c/src/lib/libcpu/arm/s3c2400/irq/irq.h
View File

@@ -23,7 +23,7 @@ extern "C" {
/*
* Include some preprocessor value also used by assember code
*/
#include <rtems.h>
#include <s3c2400.h>
@@ -41,35 +41,35 @@ extern void default_int_handler();
#define BSP_EINT5 5
#define BSP_EINT6 6
#define BSP_EINT7 7
#define BSP_INT_TICK 8
#define BSP_INT_WDT 9
#define BSP_INT_TIMER0 10
#define BSP_INT_TIMER1 11
#define BSP_INT_TIMER2 12
#define BSP_INT_TIMER3 13
#define BSP_INT_TIMER4 14
#define BSP_INT_UERR01 15
#define _res0 16
#define BSP_INT_DMA0 17
#define BSP_INT_DMA1 18
#define BSP_INT_DMA2 19
#define BSP_INT_DMA3 20
#define BSP_INT_MMC 21
#define BSP_INT_SPI 22
#define BSP_INT_URXD0 23
#define BSP_INT_URXD1 24
#define BSP_INT_USBD 25
#define BSP_INT_USBH 26
#define BSP_INT_IIC 27
#define BSP_INT_UTXD0 28
#define BSP_INT_UTXD1 29
#define BSP_INT_RTC 30
#define BSP_INT_ADC 31
#define BSP_MAX_INT 32
#define BSP_INT_TICK 8
#define BSP_INT_WDT 9
#define BSP_INT_TIMER0 10
#define BSP_INT_TIMER1 11
#define BSP_INT_TIMER2 12
#define BSP_INT_TIMER3 13
#define BSP_INT_TIMER4 14
#define BSP_INT_UERR01 15
#define _res0 16
#define BSP_INT_DMA0 17
#define BSP_INT_DMA1 18
#define BSP_INT_DMA2 19
#define BSP_INT_DMA3 20
#define BSP_INT_MMC 21
#define BSP_INT_SPI 22
#define BSP_INT_URXD0 23
#define BSP_INT_URXD1 24
#define BSP_INT_USBD 25
#define BSP_INT_USBH 26
#define BSP_INT_IIC 27
#define BSP_INT_UTXD0 28
#define BSP_INT_UTXD1 29
#define BSP_INT_RTC 30
#define BSP_INT_ADC 31
#define BSP_MAX_INT 32
extern void *bsp_vector_table;
#define VECTOR_TABLE &bsp_vector_table
/*
* Type definition for RTEMS managed interrupts
*/
@@ -101,9 +101,9 @@ typedef struct __rtems_irq_connect_data__ {
* It is usually called immediately AFTER connecting the interrupt handler.
* RTEMS may well need such a function when restoring normal interrupt
* processing after a debug session.
*
*
*/
rtems_irq_enable on;
rtems_irq_enable on;
/*
* function for disabling interrupts at device level (ONLY!).
@@ -178,7 +178,7 @@ void BSP_rtems_irq_mngt_init();
* 4) perform rescheduling when necessary,
* 5) restore the C scratch registers...
* 6) restore initial execution flow
*
*
*/
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);

22
c/src/lib/libcpu/arm/s3c2400/timer/timer.c
View File

@@ -14,7 +14,7 @@
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted.
*
* It is important that the timer start/stop overhead be determined
* It is important that the timer start/stop overhead be determined
* when porting or modifying this code.
*
* $Id$
@@ -29,7 +29,7 @@ uint32_t g_freq;
bool benchmark_timer_find_average_overhead;
/*
* Set up Timer 1
*/
@@ -37,7 +37,7 @@ void benchmark_timer_initialize( void )
{
uint32_t cr;
/* stop TIMER1*/
/* stop TIMER1*/
cr=rTCON & 0xFFFFF0FF;
rTCON=(cr | (0x0 << 8));
@@ -45,15 +45,15 @@ void benchmark_timer_initialize( void )
cr=rTCFG1 & 0xFFFFFF0F;
rTCFG1=(cr | (0<<4));
/* input freq=PLCK/2 Mhz*/
g_freq = get_PCLK() / 2000;
/* input freq=PLCK/2 Mhz*/
g_freq = get_PCLK() / 2000;
rTCNTB1 = 0xFFFF;
/* start TIMER1 with manual reload */
/* start TIMER1 with manual reload */
cr=rTCON & 0xFFFFF0FF;
rTCON=(cr | (0x1 << 9));
rTCON=(cr | (0x1 << 8));
g_start = rTCNTO1;
}
@@ -83,16 +83,16 @@ int benchmark_timer_read( void )
* interrupts since the timer was initialized and clicks since the last
* interrupts.
*/
total = (g_start - t);
/* convert to microseconds */
total = (total*1000) / g_freq;
total = (total*1000) / g_freq;
if ( benchmark_timer_find_average_overhead == 1 ) {
return (int) total;
return (int) total;
} else if ( total < LEAST_VALID ) {
return 0;
return 0;
}
/*

58
c/src/lib/libcpu/arm/s3c2410/irq/irq.h
View File

@@ -23,7 +23,7 @@ extern "C" {
/*
* Include some preprocessor value also used by assember code
*/
#include <rtems.h>
#include <s3c2410.h>
@@ -40,34 +40,34 @@ extern void default_int_handler();
#define BSP_EINT4_7 4
#define BSP_EINT8_23 5
#define BSP_nBATT_FLT 7
#define BSP_INT_TICK 8
#define BSP_INT_WDT 9
#define BSP_INT_TIMER0 10
#define BSP_INT_TIMER1 11
#define BSP_INT_TIMER2 12
#define BSP_INT_TIMER3 13
#define BSP_INT_TIMER4 14
#define BSP_INT_UART2 15
#define BSP_INT_LCD 16
#define BSP_INT_DMA0 17
#define BSP_INT_DMA1 18
#define BSP_INT_DMA2 19
#define BSP_INT_DMA3 20
#define BSP_INT_SDI 21
#define BSP_INT_SPI0 22
#define BSP_INT_UART1 23
#define BSP_INT_USBD 25
#define BSP_INT_USBH 26
#define BSP_INT_IIC 27
#define BSP_INT_UART0 28
#define BSP_INT_SPI1 29
#define BSP_INT_RTC 30
#define BSP_INT_ADC 31
#define BSP_MAX_INT 32
#define BSP_INT_TICK 8
#define BSP_INT_WDT 9
#define BSP_INT_TIMER0 10
#define BSP_INT_TIMER1 11
#define BSP_INT_TIMER2 12
#define BSP_INT_TIMER3 13
#define BSP_INT_TIMER4 14
#define BSP_INT_UART2 15
#define BSP_INT_LCD 16
#define BSP_INT_DMA0 17
#define BSP_INT_DMA1 18
#define BSP_INT_DMA2 19
#define BSP_INT_DMA3 20
#define BSP_INT_SDI 21
#define BSP_INT_SPI0 22
#define BSP_INT_UART1 23
#define BSP_INT_USBD 25
#define BSP_INT_USBH 26
#define BSP_INT_IIC 27
#define BSP_INT_UART0 28
#define BSP_INT_SPI1 29
#define BSP_INT_RTC 30
#define BSP_INT_ADC 31
#define BSP_MAX_INT 32
extern void *bsp_vector_table;
#define VECTOR_TABLE &bsp_vector_table
/*
* Type definition for RTEMS managed interrupts
*/
@@ -99,9 +99,9 @@ typedef struct __rtems_irq_connect_data__ {
* It is usually called immediately AFTER connecting the interrupt handler.
* RTEMS may well need such a function when restoring normal interrupt
* processing after a debug session.
*
*
*/
rtems_irq_enable on;
rtems_irq_enable on;
/*
* function for disabling interrupts at device level (ONLY!).
@@ -176,7 +176,7 @@ void BSP_rtems_irq_mngt_init();
* 4) perform rescheduling when necessary,
* 5) restore the C scratch registers...
* 6) restore initial execution flow
*
*
*/
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);

8
c/src/lib/libcpu/arm/shared/arm920/mmu.c
View File

@@ -108,9 +108,9 @@ void mmu_init(mmu_sect_map_t *map)
while (sects > 0) {
lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20,
MMU_SECT_AP_ALL,
0,
c,
MMU_SECT_AP_ALL,
0,
c,
b);
pbase++;
vbase++;
@@ -249,4 +249,4 @@ void mmu_set_cpu_async_mode(void)
reg |= 0xc0000000;
mmu_set_ctrl(reg);
}

4
c/src/lib/libcpu/bfin/cache/cache.c vendored
View File

@@ -1,5 +1,5 @@
/* Blackfin Cache Support
*
*
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com>
*
@@ -9,7 +9,7 @@
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>

4
c/src/lib/libcpu/bfin/clock/clock.c
View File

@@ -1,5 +1,5 @@
/* RTEMS Clock Tick Driver for Blackfin. Uses Blackfin Core Timer.
*
*
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com>
*
@@ -9,7 +9,7 @@
*
* $Id$
*/
#include <rtems.h>
#include <stdlib.h>

32
c/src/lib/libcpu/bfin/clock/rtc.c
View File

@@ -10,7 +10,7 @@
*
* $Id$
*/
#include <rtems.h>
#include "tod.h"
@@ -21,7 +21,7 @@
/* The following are inside RTEMS -- we are violating visibility!!!
* Perhaps an API could be defined to get days since 1 Jan.
*/
*/
extern const uint16_t _TOD_Days_to_date[2][13];
/*
@@ -42,8 +42,8 @@ void setRealTimeFromRTEMS (void)
{
rtems_time_of_day time_buffer;
rtems_status_code status;
status = rtems_clock_get( RTEMS_CLOCK_GET_TOD, &time_buffer );
status = rtems_clock_get( RTEMS_CLOCK_GET_TOD, &time_buffer );
if (status == RTEMS_SUCCESSFUL){
setRealTime(&time_buffer);
}
@@ -56,9 +56,9 @@ void setRealTimeFromRTEMS (void)
void setRealTimeToRTEMS (void)
{
rtems_time_of_day time_buffer;
getRealTime(&time_buffer);
rtems_clock_set( &time_buffer );
getRealTime(&time_buffer);
rtems_clock_set( &time_buffer );
}
/*
@@ -70,16 +70,16 @@ int setRealTime(
{
uint32_t days;
rtems_time_of_day tod_temp;
tod_temp = *tod;
days = (tod_temp.year - TOD_BASE_YEAR) * 365 + \
_TOD_Days_to_date[0][tod_temp.month] + tod_temp.day - 1;
if (tod_temp.month < 3)
days += Leap_years_until_now (tod_temp.year - 1);
else
days += Leap_years_until_now (tod_temp.year);
*((uint32_t volatile *)RTC_STAT) = (days << RTC_STAT_DAYS_SHIFT)|
(tod_temp.hour << RTC_STAT_HOURS_SHIFT)|
(tod_temp.minute << RTC_STAT_MINUTES_SHIFT)|
@@ -99,21 +99,21 @@ void getRealTime(
uint32_t days, rtc_reg;
rtems_time_of_day tod_temp = { 0, 0, 0 };
int n, Leap_year;
rtc_reg = *((uint32_t volatile *)RTC_STAT);
rtc_reg = *((uint32_t volatile *)RTC_STAT);
days = (rtc_reg >> RTC_STAT_DAYS_SHIFT) + 1;
/* finding year */
tod_temp.year = days/365 + TOD_BASE_YEAR;
if (days%365 > Leap_years_until_now (tod_temp.year - 1)) {
days = (days%365) - Leap_years_until_now (tod_temp.year - 1);
} else {
} else {
tod_temp.year--;
days = (days%365) + 365 - Leap_years_until_now (tod_temp.year - 1);
}
/* finding month and day */
/* finding month and day */
Leap_year = (((!(tod_temp.year%4)) && (tod_temp.year%100)) ||
(!(tod_temp.year%400)))?1:0;
for (n=1; n<=12; n++) {

4
c/src/lib/libcpu/bfin/clock/tod.h
View File

@@ -1,5 +1,5 @@
/* tod.h
*
*
* Real Time Clock definitions for eZKit533.
*
* Copyright (c) 2006 by Atos Automacao Industrial Ltda.
@@ -11,7 +11,7 @@
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
*/
#ifndef TOD_H

2
c/src/lib/libcpu/bfin/include/sicRegs.h
View File

@@ -17,7 +17,7 @@
#define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c)
#define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010)
#define SIC_IAR_PITCH 0x04
#define SIC_IAR_PITCH 0x04
#define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010)
#if SIC_IAR_COUNT > 1
#define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014)

4
c/src/lib/libcpu/bfin/interrupt/interrupt.c
View File

@@ -1,5 +1,5 @@
/* Support for Blackfin interrupt controller
*
*
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com>
*
@@ -9,7 +9,7 @@
*
* $Id$
*/
#include <rtems.h>
#include <rtems/libio.h>

2
c/src/lib/libcpu/bfin/interrupt/interrupt.h
View File

@@ -73,7 +73,7 @@ void bfin_interrupt_enable_all(int source, bool enable);
/* disable a source independently of the individual ISR enables (starts
out all enabled) */
void bfin_interrupt_enable_global(int source, bool enable);
#ifdef __cplusplus
}
#endif

4
c/src/lib/libcpu/bfin/mmu/mmu.c
View File

@@ -1,5 +1,5 @@
/* Blackfin MMU Support
*
*
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com>
*
@@ -9,7 +9,7 @@
*
* $Id$
*/
#include <rtems.h>

4
c/src/lib/libcpu/bfin/serial/spi.c
View File

@@ -1,7 +1,7 @@
/* placeholder (just a shell) */
/* SPI driver for Blackfin
*
*
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com>
*
@@ -11,7 +11,7 @@
*
* $Id$
*/
#include <stdlib.h>
#include <rtems.h>

2
c/src/lib/libcpu/bfin/serial/spi.h
View File

@@ -40,7 +40,7 @@ typedef struct {
extern rtems_libi2c_bus_ops_t bfin_spi_libi2c_bus_ops;
void bfin_spi_isr(int source);

10
c/src/lib/libcpu/bfin/serial/twi.c
View File

@@ -1,7 +1,7 @@
/* this is not much more than a shell; it does not do anything useful yet */
/* TWI (I2C) driver for Blackfin
*
*
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com>
*
@@ -11,7 +11,7 @@
*
* $Id$
*/
#include <stdlib.h>
#include <rtems.h>
@@ -49,9 +49,9 @@ rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config) {
if (channel < 0 || channel >= N_BFIN_TWI)
return RTEMS_INVALID_NUMBER;
base = config->base;
twi[channel].base = base;
twi[channel].base = base;
result = rtems_semaphore_create(rtems_build_name('t','w','i','s'),
0,
@@ -77,7 +77,7 @@ rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config) {
TWI_CONTROL_TWI_ENA;
BFIN_REG16(base, TWI_CLKDIV_OFFSET) = config->fast ?
((8 << TWI_CLKDIV_CLKHI_SHIFT) |
(17 << TWI_CLKDIV_CLKLOW_SHIFT)) :
(17 << TWI_CLKDIV_CLKLOW_SHIFT)) :
((33 << TWI_CLKDIV_CLKHI_SHIFT) |
(67 << TWI_CLKDIV_CLKLOW_SHIFT));
BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = 0;

16
c/src/lib/libcpu/bfin/serial/uart.c
View File

@@ -1,5 +1,5 @@
/* UART driver for Blackfin
*
*
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com>
*
@@ -9,7 +9,7 @@
*
* $Id$
*/
#include <rtems.h>
#include <rtems/libio.h>
@@ -34,7 +34,7 @@ static void initializeHardware(int minor) {
uint16_t r;
base = uartsConfig->channels[minor].base_address;
*(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
if (uartsConfig->channels[minor].force_baud)
@@ -60,12 +60,12 @@ static void initializeHardware(int minor) {
static int pollRead(int minor) {
int c;
char *base;
base = uartsConfig->channels[minor].base_address;
/* check to see if driver is using interrupts so this call will be
harmless (though non-functional) in case some debug code tries to
use it */
use it */
if (!uartsConfig->channels[minor].use_interrupts &&
*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
c = *((uint16_t volatile *) (base + UART_RBR_OFFSET));
@@ -87,7 +87,7 @@ char bfin_uart_poll_read(int minor) {
void bfin_uart_poll_write(int minor, char c) {
char *base;
base = uartsConfig->channels[minor].base_address;
while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE))
@@ -158,7 +158,7 @@ static int pollWrite(int minor, const char *buf, int len) {
static void enableInterrupts(int minor) {
char *base;
base = uartsConfig->channels[minor].base_address;
*(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI |

2
c/src/lib/libcpu/bfin/serial/uart.h
View File

@@ -50,7 +50,7 @@ rtems_device_driver bfin_uart_open(rtems_device_major_number major,
void bfin_uart_isr(int source);
#ifdef __cplusplus
}
#endif

12
c/src/lib/libcpu/bfin/timer/timer.c
View File

@@ -4,7 +4,7 @@
* Suite. Each measured time period is demarcated by calls to
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted.
*
*
* Copyright (c) 2006 by Atos Automacao Industrial Ltda.
* written by Alain Schaefer <alain.schaefer@easc.ch>
* and Antonio Giovanini <antonio@atos.com.br>
@@ -15,7 +15,7 @@
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
@@ -26,7 +26,7 @@ bool benchmark_timer_find_average_overhead;
/*
* benchmark_timer_initialize
*
*
* Blackfin processor has a counter for clock cycles.
*/
void benchmark_timer_initialize( void )
@@ -40,7 +40,7 @@ void benchmark_timer_initialize( void )
asm ("R2 = SYSCFG;");
asm ("BITSET(R2,1);");
asm ("SYSCFG = R2");
}
/*
@@ -64,7 +64,7 @@ int benchmark_timer_read( void )
uint32_t total;
register uint32_t cycles asm ("R2");
/* stop counter */
/* stop counter */
asm("R2 = SYSCFG;");
asm("BITCLR(R2,1);");
asm("SYSCFG = R2;");
@@ -74,7 +74,7 @@ int benchmark_timer_read( void )
clicks = cycles; /* Clock cycles */
/* converting to microseconds */
total = clicks / (CCLK/1000000);
total = clicks / (CCLK/1000000);
if ( benchmark_timer_find_average_overhead == 1 )
return total; /* in XXX microsecond units */

2
c/src/lib/libcpu/m68k/shared/misc/m68kidle.c
View File

@@ -28,7 +28,7 @@
*
* Output parameters: NONE
*/
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
#if defined(mcf5272)

2
c/src/lib/libcpu/m68k/shared/misc/memProbe.c
View File

@@ -1,4 +1,4 @@
/*
/*
* Address Probing for M68k/ColdFire
*/

22
c/src/lib/libcpu/mips/au1x00/include/au1x00.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -189,15 +189,15 @@
#define MEM_STADDR3 0x11003f00
/*
* SDCS0 -
* SDCS1 -
* SDCS2 -
* SDCS0 -
* SDCS1 -
* SDCS2 -
*/
#define MEM_SDMODE0 0x00552229
#define MEM_SDMODE1 0x00552229
#define MEM_SDMODE2 0x00552229
#define MEM_SDADDR0 0x001003F8
#define MEM_SDADDR0 0x001003F8
#define MEM_SDADDR1 0x001023F8
#define MEM_SDADDR2 0x001043F8
@@ -245,7 +245,7 @@
#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00))
#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00))
#define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04))
#define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08))
#define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c))
@@ -315,7 +315,7 @@ typedef struct {
uint32_t _rsv0;
uint32_t _rsv1;
} au1x00_macdma_rx_t;
typedef struct {
volatile uint32_t stat;
@@ -323,7 +323,7 @@ typedef struct {
volatile uint32_t len;
uint32_t _rsv0;
} au1x00_macdma_tx_t;
#define AU1X00_MAC_CTRL_RA (bit(31))
#define AU1X00_MAC_CTRL_EM (bit(30))
#define AU1X00_MAC_CTRL_DO (bit(23))
@@ -392,7 +392,7 @@ typedef struct {
#define AU1X00_MAC_DMA_TXSTAT_PR (bit(31))
#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10)
#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10)
#define AU1X00_MAC_DMA_TXSTAT_LO (bit(9))
#define AU1X00_MAC_DMA_TXSTAT_DF (bit(8))
#define AU1X00_MAC_DMA_TXSTAT_UR (bit(7))
@@ -425,8 +425,8 @@ typedef struct {
volatile uint32_t enable;
} au1x00_uart_t;
extern au1x00_uart_t *uart0;
extern au1x00_uart_t *uart3;
extern au1x00_uart_t *uart0;
extern au1x00_uart_t *uart3;
/*
* Interrupt Vector Numbers

4
c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c
View File

@@ -1,6 +1,6 @@
/*
/*
* This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model.
* be determined without knowing the RTEMS CPU model.
*
* COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR).

20
c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c
View File

@@ -1,9 +1,9 @@
/*
* Au1x00 Interrupt Vectoring
* Au1x00 Interrupt Vectoring
*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
@@ -44,7 +44,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
if ( cause & 0x80 ) {
unsigned long zero = 0;
/*
* I don't see a good way to disable the compare
* I don't see a good way to disable the compare
* interrupt, so let's just ignore it.
*/
asm volatile ("mtc0 %0, $11\n" :: "r" (zero));
@@ -56,23 +56,23 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
if ( cause & 0x40 ) {
CALL_ISR( AU1X00_IRQ_PERF, frame );
}
/* Interrupt controller 0 */
if ( cause & 0x0c ) {
call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR);
}
/* Interrupt controller 1 */
if ( cause & 0x30 ) {
call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR);
}
/* SW[0] */
if ( cause & 0x01 )
CALL_ISR( AU1X00_IRQ_SW0, frame );
/* SW[1] */
if ( cause & 0x02 )
if ( cause & 0x02 )
CALL_ISR( AU1X00_IRQ_SW1, frame );
}
@@ -90,8 +90,8 @@ void mips_default_isr( int vector )
}
static void call_vectored_isr(
CPU_Interrupt_frame *frame,
uint32_t cause,
CPU_Interrupt_frame *frame,
uint32_t cause,
void *ctrlr
)
{

10
c/src/lib/libcpu/mips/clock/ckinit.c
View File

@@ -84,7 +84,7 @@ uint32_t Clock_isrs; /* ISRs until next tick */
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
@@ -160,7 +160,7 @@ void Install_clock(
* Hardware specific initialize goes here
*/
mips_timer_rate = rtems_configuration_get_microseconds_per_tick() *
mips_timer_rate = rtems_configuration_get_microseconds_per_tick() *
bsp_clicks_per_microsecond;
mips_set_timer( mips_timer_rate );
mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK);
@@ -195,13 +195,13 @@ rtems_device_driver Clock_initialize(
)
{
Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}

2
c/src/lib/libcpu/mips/clock/clock.S
View File

@@ -1,4 +1,4 @@
/* clock.s
/* clock.s
*
* This file contains the assembly code for the IDT 4650 clock driver.
*

36
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
View File

@@ -172,8 +172,8 @@ MG5UART_STATIC int mg5uart_set_attributes(
cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
(cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
@@ -305,8 +305,8 @@ MG5UART_STATIC int mg5uart_open(
MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
rtems_interrupt_enable(Irql);
@@ -352,8 +352,8 @@ MG5UART_STATIC int mg5uart_close(
rtems_interrupt_disable(Irql);
cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
(cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
rtems_interrupt_enable(Irql);
@@ -393,7 +393,7 @@ MG5UART_STATIC void mg5uart_write_polled(
*/
timeout = 2000;
while( --timeout )
while( --timeout )
{
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
@@ -411,7 +411,7 @@ MG5UART_STATIC void mg5uart_write_polled(
*/
#if 0
if(_System_state_Is_up(_System_state_Get()))
if(_System_state_Is_up(_System_state_Get()))
{
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
}
@@ -473,8 +473,8 @@ __ISR(rx_ready, MG5UART_IRQ_RX_READY)
MG5UART_STATIC void mg5uart_process_isr_rx_error(
int minor,
uint32_t mask
int minor,
uint32_t mask
)
{
uint32_t pMG5UART;
@@ -524,7 +524,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
{
uint32_t pMG5UART;
int shift;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
@@ -533,7 +533,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
MG5UART_SETREG(
pMG5UART,
MG5UART_STATUS_REGISTER,
@@ -549,7 +549,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
* There are no more characters to transmit. The tx interrupts are be cleared
* by writing data to the uart, so just disable the tx interrupt sources.
*/
Console_Port_Data[minor].bActive = FALSE;
/* mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); */
@@ -659,7 +659,7 @@ MG5UART_STATIC int mg5uart_write_support_int(
MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf);
if( Console_Port_Data[minor].bActive == FALSE )
if( Console_Port_Data[minor].bActive == FALSE )
{
Console_Port_Data[minor].bActive = TRUE;
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL);
@@ -690,7 +690,7 @@ MG5UART_STATIC int mg5uart_write_support_polled(
/*
* poll each byte in the string out of the port.
*/
while (nwrite < len)
while (nwrite < len)
{
mg5uart_write_polled(minor, *buf++);
nwrite++;
@@ -734,11 +734,11 @@ MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled(
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
}
if ( status & MONGOOSEV_UART_RX_READY )
if ( status & MONGOOSEV_UART_RX_READY )
{
return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
}
else
}
else
{
return -1;
}

4
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c
View File

@@ -20,13 +20,13 @@
#ifndef _MG5UART_MULTIPLIER
#define _MG5UART_MULTIPLIER 1
#define _MG5UART_NAME(_X) _X
#define _MG5UART_TYPE uint32_t
#define _MG5UART_TYPE uint32_t
#endif
#define CALCULATE_REGISTER_ADDRESS( _base, _reg ) \
(_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER ))
/*
/*
* MG5UART Get Register Routine
*/

10
c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
View File

@@ -122,10 +122,10 @@
#define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013
#define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F
/*
* The Peripheral Interrupt Status, Cause, and Mask registers have the
* same bit assignments although some revisions of the document have
* the Cause and Status registers incorrect.
/*
* The Peripheral Interrupt Status, Cause, and Mask registers have the
* same bit assignments although some revisions of the document have
* the Cause and Status registers incorrect.
*/
#define MONGOOSEV_UART0_IRQ_SHIFT 11
@@ -193,7 +193,7 @@
** Peripheral Command bits (non-uart, those are defined above)
*/
#define MONGOOSEV_COMMAND_ENABLE_EDAC MONGOOSEV_EDAC_SERR_BIT
#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT
#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT

8
c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c
View File

@@ -1,6 +1,6 @@
/*
/*
* This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model.
* be determined without knowing the RTEMS CPU model.
*
* COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR).
@@ -17,9 +17,9 @@
*/
/*
* The Synova Mongoose-V attached one of the eight interrupt bits
* The Synova Mongoose-V attached one of the eight interrupt bits
* to a Peripheral Function Interrupt Cause Register on-CPU.
* This results in: 2 software interrupts, 5 interrupts
* This results in: 2 software interrupts, 5 interrupts
* through the IP bits, and 32 more from the PFICR. Some of
* these are reserved but for simplicity in processing, we
* reserve slots for those bits anyway.

18
c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
View File

@@ -91,7 +91,7 @@ int assertSoftwareInterrupt( uint32_t n )
static volatile uint32_t _ivcause, _ivsr;
static uint32_t READ_CAUSE(void)
static uint32_t READ_CAUSE(void)
{
mips_get_cause( _ivcause );
_ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */
@@ -140,7 +140,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
if ( cshifted & 0x01 ) /* SW[0] */
{
CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame );
}
}
if ( cshifted & 0x02 ) /* SW[1] */
{
CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame );
@@ -156,7 +156,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CLR_ISR_FLAG( 0x4 );
if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect;
}
if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/
{
SET_ISR_FLAG( 0x8 );
@@ -164,7 +164,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CLR_ISR_FLAG( 0x8 );
if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect;
}
if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */
{
SET_ISR_FLAG( 0x10 );
@@ -172,7 +172,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CLR_ISR_FLAG( 0x10 );
if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect;
}
if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */
{
SET_ISR_FLAG( 0x20 );
@@ -180,7 +180,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CLR_ISR_FLAG( 0x20 );
if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect;
}
if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */
{
SET_ISR_FLAG( 0x40 );
@@ -198,7 +198,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
/*
for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 )
for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 )
{
if ( pf_icr & pf_mask )
{
@@ -208,7 +208,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
pf_reset |= pf_mask;
if( (cshifted = READ_CAUSE()) & 0xff ) break;
}
}
}
*/
/*
@@ -217,7 +217,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
* way thru a full 32 bits. pf_mask shifts left 8 bits at a time
* to serve as a interrupt cause test mask.
*/
for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) )
for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) )
{
if ( pf_icr & pf_mask )
{

4
c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c
View File

@@ -1,6 +1,6 @@
/*
/*
* This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model.
* be determined without knowing the RTEMS CPU model.
*
* COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR).

4
c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c
View File

@@ -1,6 +1,6 @@
/*
/*
* This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model.
* be determined without knowing the RTEMS CPU model.
*
* COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR).

2
c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c
View File

@@ -1,5 +1,5 @@
/*
* RM5231 Interrupt Vectoring
* RM5231 Interrupt Vectoring
*
* vectorisrs.c,v 1.6 2004/06/23 18:16:36
*/

8
c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
View File

@@ -32,7 +32,7 @@ FRAME(exc_dbg_code,sp,0,ra)
j k0
nop
ENDFRAME(exc_dbg_code)
/* XXX this is dependent on IDT/SIM and needs to be addressed */
FRAME(exc_utlb_code,sp,0,ra)
la k0, (R_VEC+((48)*8))
@@ -40,7 +40,7 @@ FRAME(exc_utlb_code,sp,0,ra)
nop
ENDFRAME(exc_utlb_code)
/*
/*
* MIPS ISA Level 32
* XXX Again, reliance on SIM. Not good.??????????
*/
@@ -69,8 +69,8 @@ FRAME(exc_norm_code,sp,0,ra)
j k0
nop
ENDFRAME(exc_norm_code)
/*
/*
* MIPS ISA Level 3
* XXX Again, reliance on SIM. Not good.
*/

4
c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c
View File

@@ -1,6 +1,6 @@
/*
/*
* This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model.
* be determined without knowing the RTEMS CPU model.
*
* COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR).

4
c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
View File

@@ -1,5 +1,5 @@
/*
* TX3904 Interrupt Vectoring
* TX3904 Interrupt Vectoring
*
* $Id$
*/
@@ -38,7 +38,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
unsigned int v = (cause >> 2) & 0x0f;
CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
}
if ( cause & 0x02 ) /* SW[0] */
CALL_ISR( TX3904_IRQ_SOFTWARE_1, frame );

4
c/src/lib/libcpu/mips/tx49/include/tx4925.h
View File

@@ -26,7 +26,7 @@
#define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */
/* Pin Configuration register bits */
#define SELCHI 0x00100000
#define SELCHI 0x00100000
#define SELTMR0 0x00000200
@@ -64,7 +64,7 @@
#define TWIS 0x8
/*
/*
* Interrupt Controller Registers
*/
#define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */

4
c/src/lib/libcpu/mips/tx49/include/tx4938.h
View File

@@ -41,7 +41,7 @@
#define TX4938_CFG_RAMP 0xE048 /* Register Address Mapping Register */
/* Pin Configuration register bits */
#define SELCHI 0x00100000
#define SELCHI 0x00100000
#define SELTMR0 0x00000200
@@ -79,7 +79,7 @@
#define TWIS 0x8
/*
/*
* Interrupt Controller Registers
*/
#define TX4938_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */

4
c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c
View File

@@ -1,6 +1,6 @@
/*
/*
* This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model.
* be determined without knowing the RTEMS CPU model.
*
* COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR).

8
c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c
View File

@@ -1,5 +1,5 @@
/*
* TX4925 Interrupt Vectoring
* TX4925 Interrupt Vectoring
*
* vectorisrs.c,v 1.6 2004/06/23 18:16:36
*/
@@ -35,7 +35,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f;
CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
}
if ( pending & 0x01 ) /* IP[0] */
CALL_ISR( TX4925_IRQ_SOFTWARE_1, frame );
@@ -53,9 +53,9 @@ void mips_default_isr( int vector )
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
vector, cause, sr );
while(1); /* Lock it up */
rtems_fatal_error_occurred(1);
}

20
c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h
View File

@@ -7,19 +7,19 @@
* is not very useful so we mostly focus on TLB1 (variable page size)
*/
/*
/*
* Authorship
* ----------
* This software was created by
* Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
* Stanford Linear Accelerator Center, Stanford University.
*
*
* Acknowledgement of sponsorship
* ------------------------------
* This software was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
@@ -28,18 +28,18 @@
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
@@ -48,9 +48,9 @@
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
*/
#include <rtems.h>
#include <inttypes.h>
@@ -98,7 +98,7 @@ extern E500_tlb_va_cache_t rtems_e500_tlb_va_cache[16];
void
rtems_e500_dmptlbc(FILE *f);
/*
/*
* Read a TLB entry from the hardware; if it is a TLB1 entry
* then the current settings are stored in the
* rtems_e500_tlb_va_cache[] structure.

32
c/src/lib/libcpu/powerpc/e500/mmu/mmu.c
View File

@@ -15,23 +15,23 @@
* (the 7 LSBs, that is) can be mapped with TLB0 since there
* are only two entries per 'way'.
*
* Since this is a real-time OS we want to stay away from
* Since this is a real-time OS we want to stay away from
* software TLB replacement.
*/
/*
/*
* Authorship
* ----------
* This software was created by
* Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
* Stanford Linear Accelerator Center, Stanford University.
*
*
* Acknowledgement of sponsorship
* ------------------------------
* This software was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
@@ -40,18 +40,18 @@
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
@@ -60,9 +60,9 @@
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
*/
/* 8450 MSR definitions; note that there are *substantial* differences
* compared to classic powerpc; in particular, IS/DS are *different*
@@ -230,8 +230,8 @@ int i;
return;
}
for ( i=0; i<16; i++ ) {
if ( !rtems_e500_tlb_va_cache[i].att.v )
continue;
if ( !rtems_e500_tlb_va_cache[i].att.v )
continue;
myprintf(f,"#%2i: TID 0x%03x, TS %i, ea 0x%08x .. 0x%08x\n",
i,
rtems_e500_tlb_va_cache[i].va.va_tid,
@@ -259,7 +259,7 @@ int idx = key & ~E500_SELTLB_1;
}
}
/*
/*
* Read a TLB entry from the hardware; if it is a TLB1 entry
* then the current settings are stored in the
* rtems_e500_tlb_va_cache[] structure.
@@ -500,7 +500,7 @@ rtems_interrupt_level lvl;
/* OK to proceed */
mas1 |= MAS1_IPROT | MAS1_TID(tid);
if ( sz >= 0 )
if ( sz >= 0 )
mas1 |= MAS1_V | MAS1_TSIZE(sz);
mas2 = MAS2_EPN( ea>>12 ) | E500_TLB_ATTR_WIMGE(attr);
@@ -668,11 +668,11 @@ rtems_interrupt_level lvl;
if ( (key & E500_SELTLB_1) ) {
if ( (key & ~E500_SELTLB_1) > 15 ) {
myprintf(stderr,"Invalid TLB index; TLB1 index must be < 16\n");
return -1;
return -1;
}
} else if ( key > 255 ) {
myprintf(stderr,"Invalid TLB index; TLB0 index must be < 256\n");
return -1;
return -1;
}
/* Must not invalidate page 0 which holds vectors, text etc... */

12
c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c
View File

@@ -190,7 +190,7 @@ static int mpc55xx_esci_termios_first_open( int major, int minor, void *arg)
}
/* Connect TTY */
e->tty = tty;
e->tty = tty;
/* Enable interrupts */
if (MPC55XX_ESCI_USE_INTERRUPTS( e)) {
@@ -380,7 +380,7 @@ static int mpc55xx_esci_termios_set_attributes( int minor, const struct termios
br = 0;
}
cr1.B.SBR = br;
/* Number of data bits */
if ((t->c_cflag & CSIZE) != CS8) {
return RTEMS_IO_ERROR;
@@ -390,7 +390,7 @@ static int mpc55xx_esci_termios_set_attributes( int minor, const struct termios
/* Parity */
cr1.B.PE = (t->c_cflag & PARENB) ? 1 : 0;
cr1.B.PT = (t->c_cflag & PARODD) ? 1 : 0;
/* Stop bits */
if ( t->c_cflag & CSTOPB ) {
/* Two stop bits */
@@ -484,11 +484,11 @@ static const rtems_termios_callbacks mpc55xx_esci_termios_callbacks_polled = {
rtems_device_driver console_initialize( rtems_device_major_number major, rtems_device_minor_number minor, void *arg)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
int console_done = 0;
int termios_do_init = 1;
int console_done = 0;
int termios_do_init = 1;
rtems_device_minor_number i = 0;
mpc55xx_esci_driver_entry *e = NULL;
for (i = 0; i < MPC55XX_ESCI_NUMBER; ++i) {
e = &mpc55xx_esci_driver_table [i];
sc = rtems_io_register_name ( e->device_name, major, i);

4
c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h
View File

@@ -18,9 +18,9 @@
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
*/
/**
/**
* @defgroup mpc55xx_dspi Deserial Serial Peripheral Interface (DSPI)
*
*
* @ingroup mpc55xx
*/

4
c/src/lib/libcpu/powerpc/mpc55xx/include/esci.h
View File

@@ -18,9 +18,9 @@
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
*/
/**
/**
* @defgroup mpc55xx_esci Enhanced Serial Communication Interface (eSCI).
*
*
* @ingroup mpc55xx
*/

6
c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h
View File

@@ -22,11 +22,11 @@
* @defgroup mpc55xx BSP for MPC55xx boards
*/
/**
/**
* @defgroup mpc55xx_config Configuration files
*
*
* @ingroup mpc55xx
*
*
* Makefiles, configure scripts etc.
*/

2
c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h
View File

@@ -2809,7 +2809,7 @@ extern "C" {
.DADDR = 0,
.CDF = { .R = 0 },
.DLAST_SGA = 0,
.BMF = { .R = 0 }
.BMF = { .R = 0 }
};
#define EDMA_TCD_BITER_MASK 0x7fff

8
c/src/lib/libcpu/powerpc/mpc55xx/irq/irq.c
View File

@@ -41,7 +41,7 @@ rtems_status_code mpc55xx_intc_get_priority( rtems_vector_number vector, unsigne
} else {
*priority = MPC55XX_INTC_INVALID_PRIORITY;
return RTEMS_INVALID_NUMBER;
}
}
}
/**
@@ -58,7 +58,7 @@ rtems_status_code mpc55xx_intc_set_priority( rtems_vector_number vector, unsigne
}
} else {
return RTEMS_INVALID_NUMBER;
}
}
}
/**
@@ -71,7 +71,7 @@ rtems_status_code mpc55xx_intc_raise_software_irq( rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
} else {
return RTEMS_INVALID_NUMBER;
}
}
}
/**
@@ -84,7 +84,7 @@ rtems_status_code mpc55xx_intc_clear_software_irq( rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
} else {
return RTEMS_INVALID_NUMBER;
}
}
}
/**

4
c/src/lib/libcpu/powerpc/mpc55xx/misc/copy.S
View File

@@ -95,7 +95,7 @@ zero_big_data:
evstddx r0, r3, r8
addi r8, r8, 32
bdnz zero_big_data
/* Return */
blr
@@ -145,6 +145,6 @@ zero_big_line:
dcbz r3, r8
addi r8, r8, 128
bdnz zero_big_line
/* Return */
blr

20
c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c
View File

@@ -58,10 +58,10 @@ void Clock_exit( void );
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
/*
* ISR Handler
*/
@@ -70,7 +70,7 @@ rtems_isr Clock_isr(rtems_vector_number vector)
usiu.piscrk = USIU_UNLOCK_KEY;
usiu.piscr |= USIU_PISCR_PS; /* acknowledge interrupt */
usiu.piscrk = 0;
Clock_driver_ticks++;
rtems_clock_tick();
}
@@ -81,10 +81,10 @@ void clockOn(void* unused)
uint32_t pit_value;
extern uint32_t bsp_clicks_per_usec;
/* calculate and set modulus */
/* calculate and set modulus */
pit_value = (rtems_configuration_get_microseconds_per_tick() *
bsp_clicks_per_usec) - 1 ;
if (pit_value > 0xffff) { /* pit is only 16 bits long */
rtems_fatal_error_occurred(-1);
}
@@ -114,13 +114,13 @@ clockOff(void* unused)
{
/* disable PIT and PIT interrupts */
usiu.piscrk = USIU_UNLOCK_KEY;
usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE);
usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE);
usiu.piscrk = 0;
}
int clockIsOn(void* unused)
{
if (usiu.piscr & USIU_PISCR_PIE)
if (usiu.piscr & USIU_PISCR_PIE)
return 1;
return 0;
}
@@ -157,13 +157,13 @@ rtems_device_driver Clock_initialize(
)
{
Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}

44
c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c
View File

@@ -14,7 +14,7 @@
* MPC5xx port sponsored by Defence Research and Development Canada - Suffield
* Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
*
* Derived from
* Derived from
* c/src/lib/libcpu/powerpc/mpc8xx/console_generic/console_generic.c:
* Author: Jay Monkman (jmonkman@frasca.com)
* Copyright (C) 1998 by Frasca International, Inc.
@@ -84,15 +84,15 @@ static struct termios default_termios = {
{ 0 } /* control characters */
};
/*
* Termios callback functions
*/
int
m5xx_uart_firstOpen(
int major,
int minor,
int major,
int minor,
void *arg
)
{
@@ -109,7 +109,7 @@ m5xx_uart_firstOpen(
int
m5xx_uart_lastClose(
int major,
int major,
int minor,
void* arg
)
@@ -129,7 +129,7 @@ m5xx_uart_pollRead(
{
volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs;
int c = -1;
if ( regs ) {
while ( (regs->scsr & QSMCM_SCI_RDRF) == 0 )
;
@@ -139,7 +139,7 @@ m5xx_uart_pollRead(
return c;
}
int
int
m5xx_uart_write(
int minor,
const char *buf,
@@ -170,7 +170,7 @@ m5xx_uart_pollWrite(
return 0;
}
int
int
m5xx_uart_setAttributes(
int minor,
const struct termios *t
@@ -179,11 +179,11 @@ m5xx_uart_setAttributes(
uint16_t sccr0 = sci_descs[minor].regs->sccr0;
uint16_t sccr1 = sci_descs[minor].regs->sccr1;
int baud;
/*
* Check that port number is valid
*/
if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) )
if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) )
return RTEMS_INVALID_NUMBER;
/* Baud rate */
@@ -212,10 +212,10 @@ m5xx_uart_setAttributes(
if (baud > 0) {
extern uint32_t bsp_clock_speed;
sccr0 &= ~QSMCM_SCI_BAUD(-1);
sccr0 |=
sccr0 |=
QSMCM_SCI_BAUD((bsp_clock_speed + (16 * baud)) / (32 * baud));
}
/* Number of data bits -- not available with MPC5xx SCI */
switch ( t->c_cflag & CSIZE ) {
case CS5: break;
@@ -236,7 +236,7 @@ m5xx_uart_setAttributes(
sccr1 |= QSMCM_SCI_PE;
else
sccr1 &= ~QSMCM_SCI_PE;
if ( t->c_cflag & PARODD )
sccr1 |= QSMCM_SCI_PT;
else
@@ -248,29 +248,29 @@ m5xx_uart_setAttributes(
sccr1 |= QSMCM_SCI_RE;
else
sccr1 &= ~QSMCM_SCI_RE;
/* Write hardware registers */
sci_descs[minor].regs->sccr0 = sccr0;
sci_descs[minor].regs->sccr1 = sccr1;
return RTEMS_SUCCESSFUL;
}
/*
/*
* Interrupt handling.
*/
static void
m5xx_sci_interrupt_handler (rtems_irq_hdl_param unused)
{
int minor;
for ( minor = 0; minor < NUM_PORTS; minor++ ) {
sci_desc *desc = &sci_descs[minor];
int sccr1 = desc->regs->sccr1;
int scsr = desc->regs->scsr;
/*
/*
* Character received?
*/
if ((sccr1 & QSMCM_SCI_RIE) && (scsr & QSMCM_SCI_RDRF)) {
@@ -306,14 +306,14 @@ m5xx_uart_initialize (int minor)
/*
* Check that minor number is valid.
*/
if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) )
if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) )
return;
/*
* Configure and enable receiver and transmitter.
*/
m5xx_uart_setAttributes(minor, &default_termios);
/*
* Connect interrupt if not yet done.
*/
@@ -325,7 +325,7 @@ m5xx_uart_initialize (int minor)
irq_data.on = m5xx_sci_nop; /* can't enable both channels here */
irq_data.off = m5xx_sci_nop; /* can't disable both channels here */
irq_data.isOn = m5xx_sci_isOn;
if (!CPU_install_rtems_irq_handler (&irq_data)) {
printk("Unable to connect SCI Irq handler\n");
rtems_fatal_error_occurred(1);

22
c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c
View File

@@ -61,7 +61,7 @@ int mpc5xx_vector_is_valid(rtems_vector vector)
case ASM_MEBREAK_VECTOR:
case ASM_NMEBREAK_VECTOR:
return 1;
default:
default:
return 0;
}
default:
@@ -85,19 +85,19 @@ int mpc5xx_set_exception (const rtems_raw_except_connect_data* except)
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
if (exception_handler_table[except->exceptIndex] !=
if (exception_handler_table[except->exceptIndex] !=
default_raw_except_entry.hdl.raw_hdl) {
return 0;
}
rtems_interrupt_disable(level);
raw_except_table[except->exceptIndex] = *except;
exception_handler_table[except->exceptIndex] = except->hdl.raw_hdl;
if (except->on)
except->on(except);
rtems_interrupt_enable(level);
return 1;
}
@@ -107,16 +107,16 @@ int mpc5xx_get_current_exception (rtems_raw_except_connect_data* except)
if (!mpc5xx_vector_is_valid(except->exceptIndex)){
return 0;
}
*except = raw_except_table[except->exceptIndex];
return 1;
}
int mpc5xx_delete_exception (const rtems_raw_except_connect_data* except)
{
rtems_interrupt_level level;
if (!mpc5xx_vector_is_valid(except->exceptIndex)){
return 0;
}
@@ -135,14 +135,14 @@ int mpc5xx_delete_exception (const rtems_raw_except_connect_data* except)
if (except->off)
except->off(except);
exception_handler_table[except->exceptIndex] =
exception_handler_table[except->exceptIndex] =
default_raw_except_entry.hdl.raw_hdl;
raw_except_table[except->exceptIndex] = default_raw_except_entry;
raw_except_table[except->exceptIndex].exceptIndex = except->exceptIndex;
rtems_interrupt_enable(level);
return 1;
}
@@ -156,7 +156,7 @@ int mpc5xx_init_exceptions (rtems_raw_except_global_settings* config)
{
unsigned i;
rtems_interrupt_level level;
/*
* store various accelerators
*/

10
c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h
View File

@@ -62,7 +62,7 @@
#ifndef ASM
/*
* Type definition for raw exceptions.
* Type definition for raw exceptions.
*/
typedef unsigned char rtems_vector;
@@ -73,7 +73,7 @@ typedef struct {
rtems_vector vector;
rtems_exception_handler_t* raw_hdl;
}rtems_raw_except_hdl;
typedef void (*rtems_raw_except_enable) (const struct __rtems_raw_except_connect_data__*);
typedef void (*rtems_raw_except_disable) (const struct __rtems_raw_except_connect_data__*);
typedef int (*rtems_raw_except_is_enabled) (const struct __rtems_raw_except_connect_data__*);
@@ -93,16 +93,16 @@ typedef struct __rtems_raw_except_connect_data__{
* libcpu library, this library should have no knowledge of
* board specific hardware to manage exceptions and thus the
* "on" routine must enable the except at processor level only.
*
*
*/
rtems_raw_except_enable on;
rtems_raw_except_enable on;
/*
* function for disabling raw exceptions. In order to be consistent
* with the fact that the raw connexion can defined in the
* libcpu library, this library should have no knowledge of
* board specific hardware to manage exceptions and thus the
* "on" routine must disable the except both at device and PIC level.
*
*
*/
rtems_raw_except_disable off;
/*

2
c/src/lib/libcpu/powerpc/mpc5xx/include/console.h
View File

@@ -8,7 +8,7 @@
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/

20
c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h
View File

@@ -44,7 +44,7 @@
* *
* Corrections/additions: *
* Copyright (c) 1999, National Research Council of Canada *
*
*
* MPC5xx port sponsored by Defence Research and Development Canada - Suffield
* Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
*
@@ -340,14 +340,14 @@ do { \
#define UIMB_UMCR_STOP (1<<31)
#define UIMB_UMCR_IRQMUX(x) ((x)<<29)
#define UIMB_UMCR_HSPEED (1<<28)
/*
*************************************************************************
* QSMCM Serial Communications Interface (SCI) *
*************************************************************************
*/
#define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */
#define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */
@@ -417,7 +417,7 @@ typedef struct usiu_ {
uint8_t _pad71[0x03C-0x034];
uint32_t pdmcr;
uint8_t _pad2[0x100-0x40];
/*
* MEMC Block
*/
@@ -428,7 +428,7 @@ typedef struct usiu_ {
uint8_t _pad8[0x178-0x148];
uint16_t mstat;
uint8_t _pad9[0x200-0x17A];
/*
* System integration timers
*/
@@ -450,7 +450,7 @@ typedef struct usiu_ {
uint16_t pitr;
uint16_t _pad_14_2;
uint8_t _pad15[0x280-0x24c];
/*
* Clocks and Reset
*/
@@ -462,7 +462,7 @@ typedef struct usiu_ {
uint16_t _pad73;
uint16_t vsrmcr;
uint8_t _pad16[0x300-0x292];
/*
* System integration timers keys
*/
@@ -479,7 +479,7 @@ typedef struct usiu_ {
uint32_t piscrk;
uint32_t pitck;
uint8_t _pad19[0x380-0x348];
/*
* Clocks and Reset Keys
*/
@@ -541,7 +541,7 @@ typedef struct m5xxSPIRegisters_ {
/*
* Queued Serial Multi-Channel Module (QSMCM)
*/
*/
typedef struct m5xxQSMCMRegisters_ {
uint16_t qsmcmmcr;
uint16_t qtest;

44
c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c
View File

@@ -16,7 +16,7 @@
*
* $Id$
*/
#include <rtems.h>
#include <rtems/score/apiext.h>
#include <mpc5xx.h>
@@ -28,12 +28,12 @@
* Convert an rtems_irq_number constant to an interrupt level
* suitable for programming into an I/O device's interrupt level field.
*/
int CPU_irq_level_from_symbolic_name(const rtems_irq_number name)
{
if (CPU_USIU_EXT_IRQ_0 <= name && name <= CPU_USIU_INT_IRQ_7)
return (name - CPU_USIU_EXT_IRQ_0) / 2;
if (CPU_UIMB_IRQ_8 <= name && name <= CPU_UIMB_IRQ_31)
return 8 + (name - CPU_UIMB_IRQ_8);
@@ -84,9 +84,9 @@ static inline int is_proc_irq(const rtems_irq_number irqLine)
/*
* Masks used to mask off the interrupts. For exmaple, for ILVL2, the
* mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7
* and ILVL7.
* Masks used to mask off the interrupts. For exmaple, for ILVL2, the
* mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7
* and ILVL7.
*
*/
const static unsigned int USIU_IvectMask[CPU_USIU_IRQ_COUNT] =
@@ -134,7 +134,7 @@ static void compute_USIU_IvectMask_from_prio ()
*/
static int isValidInterrupt(int irq)
{
if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET)
if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET)
|| (irq == CPU_UIMB_INTERRUPT) )
return 0;
return 1;
@@ -164,7 +164,7 @@ int CPU_irq_enabled_at_uimb(const rtems_irq_number irqLine)
int CPU_irq_enable_at_usiu(const rtems_irq_number irqLine)
{
int usiu_irq_index;
if (!is_usiu_irq(irqLine))
return 1;
@@ -181,7 +181,7 @@ int CPU_irq_disable_at_usiu(const rtems_irq_number irqLine)
if (!is_usiu_irq(irqLine))
return 1;
usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET);
ppc_cached_irq_mask &= ~(1 << (31-usiu_irq_index));
usiu.simask = ppc_cached_irq_mask;
@@ -207,7 +207,7 @@ int CPU_irq_enabled_at_usiu(const rtems_irq_number irqLine)
int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -228,14 +228,14 @@ int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
* store the data provided by user
*/
rtems_hdl_tbl[irq->name] = *irq;
if (is_uimb_irq(irq->name)) {
/*
* Enable interrupt at UIMB level
*/
CPU_irq_enable_at_uimb (irq->name);
}
if (is_usiu_irq(irq->name)) {
/*
* Enable interrupt at USIU level
@@ -254,7 +254,7 @@ int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
*/
if (irq->on)
irq->on(irq);
rtems_interrupt_enable(level);
return 1;
@@ -273,7 +273,7 @@ int CPU_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -311,7 +311,7 @@ int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
/*
* disable exception at processor level
*/
}
}
/*
* restore the default irq value
@@ -424,7 +424,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
rtems_hdl_tbl[CPU_DECREMENTER].hdl(rtems_hdl_tbl[CPU_DECREMENTER].handle);
_CPU_MSR_SET(msr);
@@ -448,20 +448,20 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
* interrupts.
*/
usiu.sipend = (1 << (31 - irq));
if (uimbIntr) {
/*
* Look at the bits set in the UIMB interrupt-pending register. The
* highest-order set bit indicates the handler we will run.
* highest-order set bit indicates the handler we will run.
*
* Unfortunately, we can't easily mask individual UIMB interrupts
* unless they use USIU levels 0 to 6, so we must mask all low-level
* (level > 7) UIMB interrupts while we service any interrupt.
*/
int uipend = imb.uimb.uipend << 8;
if (uipend == 0) { /* spurious interrupt? use last vector */
irq = CPU_UIMB_IRQ_MAX_OFFSET;
irq = CPU_UIMB_IRQ_MAX_OFFSET;
}
else {
irq = CPU_UIMB_IRQ_MIN_OFFSET;
@@ -473,7 +473,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
_CPU_MSR_SET(msr);
@@ -482,7 +482,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
usiu.simask = ppc_cached_irq_mask;
}
}
void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx)
{
/*

20
c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h
View File

@@ -1,4 +1,4 @@
/*
/*
* irq.h
*
* This include file describe the data structure and the functions implemented
@@ -40,8 +40,8 @@ extern volatile unsigned int ppc_cached_irq_mask;
* Symblolic IRQ names and related definitions.
*/
/*
* Base vector for our USIU IRQ handlers.
/*
* Base vector for our USIU IRQ handlers.
*/
#define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE)
/*
@@ -71,7 +71,7 @@ extern volatile unsigned int ppc_cached_irq_mask;
#define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET)
/*
* USIU IRQ symbolic name definitions.
*/
*/
#define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0)
#define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1)
@@ -80,19 +80,19 @@ extern volatile unsigned int ppc_cached_irq_mask;
#define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4)
#define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5)
#define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6)
#define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7)
#define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8)
#define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9)
#define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10)
#define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11)
#define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12)
#define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13)
#define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14)
#define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15)
@@ -101,7 +101,7 @@ extern volatile unsigned int ppc_cached_irq_mask;
*/
#define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6)
#define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7)
/*
* UIMB IRQ symbolic name definitions. The first 8 sources are aliases to
* the USIU interrupts of the same number, because they are detected in
@@ -140,7 +140,7 @@ extern volatile unsigned int ppc_cached_irq_mask;
#define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21)
#define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22)
#define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23)
/*
* Symbolic names for UIMB interrupt sources.
*/

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