RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>

Browse Source 
* shared/interrupts/installisrentries.c: Added support for debug
	exception vector.
	* shared/interrupts/isr_entries.S: Added support for debug exception
	vector.
This commit is contained in:
Joel Sherrill
2002-03-08 16:32:39 +00:00
parent 2f89140dba
commit 34f5067fef
3 changed files with 17 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
c/src/lib/libcpu/mips/ChangeLog
View File

@@ -1,3 +1,10 @@
2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>
* shared/interrupts/installisrentries.c: Added support for debug
exception vector.
* shared/interrupts/isr_entries.S: Added support for debug exception
vector.
2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov> 2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>
* mongoosev/include/mongoose-v.h: Added cache constants. * mongoosev/include/mongoose-v.h: Added cache constants.

4
c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
View File

@@ -10,10 +10,13 @@ void mips_install_isr_entries( void )
{ {
#if __mips == 1 #if __mips == 1
void exc_utlb_code(void); void exc_utlb_code(void);
void exc_dbg_code(void);
void exc_norm_code(void); void exc_norm_code(void);
memcpy( (void *)UT_VEC, exc_utlb_code, 40 ); /* utlbmiss vector */ memcpy( (void *)UT_VEC, exc_utlb_code, 40 ); /* utlbmiss vector */
memcpy( (void *)DB_VEC, exc_dbg_code, 40 );
memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vevtor */ memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vevtor */
#elif __mips == 3 #elif __mips == 3
void exc_tlb_code(void); void exc_tlb_code(void);
void exc_xtlb_code(void); void exc_xtlb_code(void);
@@ -25,5 +28,6 @@ void mips_install_isr_entries( void )
memcpy( (void *)C_VEC, exc_cache_code, 40 ); /* cache error vector */ memcpy( (void *)C_VEC, exc_cache_code, 40 ); /* cache error vector */
memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vector */ memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vector */
#endif #endif
rtems_cache_flush_entire_data(); rtems_cache_flush_entire_data();
} }

6
c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
View File

@@ -27,6 +27,12 @@ FRAME(exc_norm_code,sp,0,ra)
nop nop
ENDFRAME(exc_norm_code) ENDFRAME(exc_norm_code)
FRAME(exc_dbg_code,sp,0,ra)
la k0, _DBG_Handler /* debug interrupt */
j k0
nop
ENDFRAME(exc_dbg_code)
/* XXX this is dependent on IDT/SIM and needs to be addressed */ /* XXX this is dependent on IDT/SIM and needs to be addressed */
FRAME(exc_utlb_code,sp,0,ra) FRAME(exc_utlb_code,sp,0,ra)
la k0, (R_VEC+((48)*8)) la k0, (R_VEC+((48)*8))