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1. Fixes a typo in the code conditionalized by GEN68360_WITH_SRAM
  2. Mods the code to add support for an additional bank of SRAM (needed more RAM
     to run the web server!)

From <vac4050@cae597.rsc.raytheon.com> reviewed by Eric Norum <eric@cls.usask.ca>.
This commit is contained in:
Joel Sherrill
2000-05-31 15:27:40 +00:00
parent 3081446337
commit 322c894c08
1 changed files with 6 additions and 7 deletions
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13
c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
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@@ -347,6 +347,7 @@ void _Init68360 (void)
* But uses SRAM instead of DRAM * * But uses SRAM instead of DRAM *
* CS0* - 512kx8 flash memory * * CS0* - 512kx8 flash memory *
* CS1* - 512kx32 static RAM * * CS1* - 512kx32 static RAM *
* CS2* - 512kx32 static RAM *
*************************************************** ***************************************************
*/ */
@@ -418,12 +419,16 @@ void _Init68360 (void)
/* /*
* Step 12: Set up main memory * Step 12: Set up main memory
* 512Kx32 SRAM on CS1* * 512Kx32 SRAM on CS1*
* 512Kx32 SRAM on CS2*
* 0 wait states * 0 wait states
*/ */
ramSize = 1 * 1024 * 1024; ramSize = 4 * 1024 * 1024;
m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB | m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
M360_MEMC_OR_32BIT; M360_MEMC_OR_32BIT;
m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) | M360_MEMC_BR_V;
m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
M360_MEMC_OR_32BIT;
/* /*
* Step 13: Copy the exception vector table to system RAM * Step 13: Copy the exception vector table to system RAM
*/ */
@@ -463,12 +468,6 @@ void _Init68360 (void)
* SIM60 interrupt sources higher priority than CPM * SIM60 interrupt sources higher priority than CPM
*/ */
m360.mcr = 0x4C7F; m360.mcr = 0x4C7F;
* No show cycles
* User/supervisor access
* Bus clear interrupt service level 7
* SIM60 interrupt sources higher priority than CPM
*/
m360.mcr = 0x4C7F;
#else #else
/* /*