2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com>

* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
	parameter to indicate that the port uses the Simple Vectored
	Interrupt model or the Programmable Interrupt Controller Model. The
	PIC model is implemented primarily in the BSP and it is responsible
	for all memory allocation.

cpukit/score/cpu/avr/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2007-12-17	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.

cpukit/score/cpu/avr/rtems/score/cpu.h

@@ -155,6 +155,19 @@ extern "C" {
 
 #define CPU_ISR_PASSES_FRAME_POINTER 0
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  AVR Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /*
  *  Does the CPU have hardware floating point?
  *

cpukit/score/cpu/bfin/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2007-12-20	Joel Sherrill <joel.sherrill@OARcorp.com>
 
 	* rtems/score/cpu.h: Use correct register name.

cpukit/score/cpu/bfin/rtems/score/cpu.h

@@ -107,6 +107,19 @@ extern "C" {
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  BFIN Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /**
  *  Does this CPU have hardware support for a dedicated interrupt stack?
  *

cpukit/score/cpu/c4x/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2007-12-17	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.

cpukit/score/cpu/c4x/rtems/score/cpu.h

@@ -109,6 +109,19 @@ extern "C" {
 
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  C4x Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /*
  *  Does this CPU have hardware support for a dedicated interrupt stack?
  *

cpukit/score/cpu/h8300/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2007-12-17	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.

cpukit/score/cpu/h8300/rtems/score/cpu.h

@@ -109,6 +109,19 @@ extern "C" {
 
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  H8300 Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /*
  *  Does this CPU have hardware support for a dedicated interrupt stack?
  *

cpukit/score/cpu/m68k/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2008-01-22	Joel Sherrill <joel.sherrill@OARcorp.com>
 
 	* cpu_asm.S: Spacing and comment alignment.

cpukit/score/cpu/m68k/rtems/score/cpu.h

@@ -33,6 +33,19 @@ extern "C" {
 #define CPU_INLINE_ENABLE_DISPATCH       TRUE
 #define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  M68K Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /*
  *  Use the m68k's hardware interrupt stack support and have the
  *  interrupt manager allocate the memory for it.

cpukit/score/cpu/mips/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2008-06-04	Joel Sherrill <joel.sherrill@OARcorp.com>
 
 	* rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it

cpukit/score/cpu/mips/rtems/score/cpu.h

@@ -123,6 +123,19 @@ extern "C" {
 
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  MIPS Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /*
  *  Does this CPU have hardware support for a dedicated interrupt stack?
  *
@@ -675,7 +688,6 @@ extern unsigned int mips_interrupt_number_of_vectors;
 
 #define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
 
-
 /*
  *  CPU's worst alignment requirement for data types on a byte boundary.  This
  *  alignment does not take into account the requirements for the stack.

cpukit/score/cpu/nios2/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2007-12-17	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.

cpukit/score/cpu/nios2/rtems/score/cpu.h

@@ -118,6 +118,19 @@ extern "C" {
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
 
+/**
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /**
  *  Does this CPU have hardware support for a dedicated interrupt stack?
  *

cpukit/score/cpu/no_cpu/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2008-01-29	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* rtems/score/cpu.h: Remove most doxygen warnings.

cpukit/score/cpu/no_cpu/rtems/score/cpu.h

@@ -119,6 +119,19 @@ extern "C" {
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
 
+/**
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /**
  *  Does this CPU have hardware support for a dedicated interrupt stack?
  *

cpukit/score/cpu/sh/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2007-12-17	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.

cpukit/score/cpu/sh/rtems/score/cpu.h

@@ -82,6 +82,19 @@ extern "C" {
 
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  SH Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /*
  *  Does RTEMS manage a dedicated interrupt stack in software?
  *

cpukit/score/cpu/sparc/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2008-02-20	Alexandru Bugnar <a-bugnar@criticalsoftware.com>
 
 	PR 1278/cpukit

cpukit/score/cpu/sparc/rtems/score/cpu.h

@@ -68,6 +68,19 @@ extern "C" {
 
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  SPARC Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /*
  *  Does this CPU have hardware support for a dedicated interrupt stack?
  *

cpukit/score/cpu/unix/ChangeLog

@@ -1,3 +1,11 @@
+2008-06-05	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+	parameter to indicate that the port uses the Simple Vectored
+	Interrupt model or the Programmable Interrupt Controller Model. The
+	PIC model is implemented primarily in the BSP and it is responsible
+	for all memory allocation.
+
 2007-12-17	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.

cpukit/score/cpu/unix/rtems/score/cpu.h

@@ -105,6 +105,15 @@ extern "C" {
 
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
 
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
 /*
  *  Does this CPU have hardware support for a dedicated interrupt stack?
  *