forked from Imagelibrary/rtems
Sebastian Huber
309
bsps/include/grlib/ftmctrl-regs.h
Normal file
309
bsps/include/grlib/ftmctrl-regs.h
Normal file
@@ -0,0 +1,309 @@
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/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSDeviceGRLIBFTMCTRL
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*
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* @brief This header file defines the FTMCTRL register block interface.
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*/
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/*
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* Copyright (C) 2021 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file is part of the RTEMS quality process and was automatically
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* generated. If you find something that needs to be fixed or
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* worded better please post a report or patch to an RTEMS mailing list
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* or raise a bug report:
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*
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* https://www.rtems.org/bugs.html
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*
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* For information on updating and regenerating please refer to the How-To
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* section in the Software Requirements Engineering chapter of the
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* RTEMS Software Engineering manual. The manual is provided as a part of
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* a release. For development sources please refer to the online
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* documentation at:
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*
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* https://docs.rtems.org
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*/
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/* Generated from spec:/dev/grlib/if/ftmctrl-header */
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#ifndef _GRLIB_FTMCTRL_REGS_H
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#define _GRLIB_FTMCTRL_REGS_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Generated from spec:/dev/grlib/if/ftmctrl */
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/**
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* @defgroup RTEMSDeviceGRLIBFTMCTRL FTMCTRL
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*
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* @ingroup RTEMSDeviceGRLIB
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*
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* @brief This group contains the FTMCTRL interfaces.
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*
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* @{
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*/
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/**
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* @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG1 \
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* Memory configuration register 1 (MCFG1)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define FTMCTRL_MCFG1_PBRDY 0x80000000U
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#define FTMCTRL_MCFG1_ABRDY 0x40000000U
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#define FTMCTRL_MCFG1_IOBUSW 0x20000000U
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#define FTMCTRL_MCFG1_IBRDY_SHIFT 27
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#define FTMCTRL_MCFG1_IBRDY_MASK 0x18000000U
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#define FTMCTRL_MCFG1_IBRDY_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG1_IBRDY_MASK ) >> \
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FTMCTRL_MCFG1_IBRDY_SHIFT )
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#define FTMCTRL_MCFG1_IBRDY_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG1_IBRDY_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG1_IBRDY_SHIFT ) & \
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FTMCTRL_MCFG1_IBRDY_MASK ) )
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#define FTMCTRL_MCFG1_IBRDY( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG1_IBRDY_SHIFT ) & \
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FTMCTRL_MCFG1_IBRDY_MASK )
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#define FTMCTRL_MCFG1_BEXCN 0x4000000U
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#define FTMCTRL_MCFG1_IO_WAITSTATES 0x1000000U
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#define FTMCTRL_MCFG1_IOEN_SHIFT 20
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#define FTMCTRL_MCFG1_IOEN_MASK 0xf00000U
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#define FTMCTRL_MCFG1_IOEN_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG1_IOEN_MASK ) >> \
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FTMCTRL_MCFG1_IOEN_SHIFT )
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#define FTMCTRL_MCFG1_IOEN_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG1_IOEN_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG1_IOEN_SHIFT ) & \
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FTMCTRL_MCFG1_IOEN_MASK ) )
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#define FTMCTRL_MCFG1_IOEN( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG1_IOEN_SHIFT ) & \
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FTMCTRL_MCFG1_IOEN_MASK )
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#define FTMCTRL_MCFG1_ROMBANKSZ 0x80000U
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#define FTMCTRL_MCFG1_PWEN_SHIFT 14
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#define FTMCTRL_MCFG1_PWEN_MASK 0x3c000U
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#define FTMCTRL_MCFG1_PWEN_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG1_PWEN_MASK ) >> \
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FTMCTRL_MCFG1_PWEN_SHIFT )
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#define FTMCTRL_MCFG1_PWEN_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG1_PWEN_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG1_PWEN_SHIFT ) & \
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FTMCTRL_MCFG1_PWEN_MASK ) )
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#define FTMCTRL_MCFG1_PWEN( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG1_PWEN_SHIFT ) & \
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FTMCTRL_MCFG1_PWEN_MASK )
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#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 12
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#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x3000U
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#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WIDTH_MASK ) >> \
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FTMCTRL_MCFG1_PROM_WIDTH_SHIFT )
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#define FTMCTRL_MCFG1_PROM_WIDTH_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WIDTH_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
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FTMCTRL_MCFG1_PROM_WIDTH_MASK ) )
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#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
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FTMCTRL_MCFG1_PROM_WIDTH_MASK )
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#define FTMCTRL_MCFG1_PROM_WRITE_WS 0x800U
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#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 8
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#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0x300U
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#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG1_PROM_READ_WS_MASK ) >> \
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FTMCTRL_MCFG1_PROM_READ_WS_SHIFT )
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#define FTMCTRL_MCFG1_PROM_READ_WS_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_READ_WS_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \
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FTMCTRL_MCFG1_PROM_READ_WS_MASK ) )
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#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \
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FTMCTRL_MCFG1_PROM_READ_WS_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG3 \
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* Memory configuration register 3 (MCFG3)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define FTMCTRL_MCFG3_ME 0x8000000U
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#define FTMCTRL_MCFG3_WB 0x800U
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#define FTMCTRL_MCFG3_RB 0x400U
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#define FTMCTRL_MCFG3_PE 0x100U
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#define FTMCTRL_MCFG3_TCB_SHIFT 0
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#define FTMCTRL_MCFG3_TCB_MASK 0xffU
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#define FTMCTRL_MCFG3_TCB_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG3_TCB_MASK ) >> \
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FTMCTRL_MCFG3_TCB_SHIFT )
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#define FTMCTRL_MCFG3_TCB_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG3_TCB_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \
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FTMCTRL_MCFG3_TCB_MASK ) )
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#define FTMCTRL_MCFG3_TCB( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \
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FTMCTRL_MCFG3_TCB_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG5 \
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* Memory configuration register 5 (MCFG5)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define FTMCTRL_MCFG5_IOHWS_SHIFT 23
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#define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U
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#define FTMCTRL_MCFG5_IOHWS_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG5_IOHWS_MASK ) >> \
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FTMCTRL_MCFG5_IOHWS_SHIFT )
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#define FTMCTRL_MCFG5_IOHWS_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG5_IOHWS_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \
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FTMCTRL_MCFG5_IOHWS_MASK ) )
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#define FTMCTRL_MCFG5_IOHWS( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \
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FTMCTRL_MCFG5_IOHWS_MASK )
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#define FTMCTRL_MCFG5_ROMHWS_SHIFT 7
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#define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U
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#define FTMCTRL_MCFG5_ROMHWS_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG5_ROMHWS_MASK ) >> \
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FTMCTRL_MCFG5_ROMHWS_SHIFT )
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#define FTMCTRL_MCFG5_ROMHWS_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG5_ROMHWS_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \
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FTMCTRL_MCFG5_ROMHWS_MASK ) )
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#define FTMCTRL_MCFG5_ROMHWS( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \
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FTMCTRL_MCFG5_ROMHWS_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG7 \
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* Memory configuration register 7 (MCFG7)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define FTMCTRL_MCFG7_BRDYNCNT_SHIFT 16
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#define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U
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#define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNCNT_MASK ) >> \
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FTMCTRL_MCFG7_BRDYNCNT_SHIFT )
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#define FTMCTRL_MCFG7_BRDYNCNT_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNCNT_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \
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FTMCTRL_MCFG7_BRDYNCNT_MASK ) )
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#define FTMCTRL_MCFG7_BRDYNCNT( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \
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FTMCTRL_MCFG7_BRDYNCNT_MASK )
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#define FTMCTRL_MCFG7_BRDYNRLD_SHIFT 0
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#define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU
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#define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \
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( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNRLD_MASK ) >> \
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FTMCTRL_MCFG7_BRDYNRLD_SHIFT )
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#define FTMCTRL_MCFG7_BRDYNRLD_SET( _reg, _val ) \
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( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNRLD_MASK ) | \
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( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \
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FTMCTRL_MCFG7_BRDYNRLD_MASK ) )
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#define FTMCTRL_MCFG7_BRDYNRLD( _val ) \
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( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \
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FTMCTRL_MCFG7_BRDYNRLD_MASK )
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/** @} */
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/**
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* @brief This structure defines the FTMCTRL register block memory map.
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||||
*/
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typedef struct ftmctrl {
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||||
/**
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* @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG1.
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*/
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uint32_t mcfg1;
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uint32_t reserved_4_8;
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||||
/**
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||||
* @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG3.
|
||||
*/
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||||
uint32_t mcfg3;
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||||
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||||
uint32_t reserved_c_10;
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||||
|
||||
/**
|
||||
* @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG5.
|
||||
*/
|
||||
uint32_t mcfg5;
|
||||
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||||
uint32_t reserved_14_18;
|
||||
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||||
/**
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||||
* @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG7.
|
||||
*/
|
||||
uint32_t mcfg7;
|
||||
} ftmctrl;
|
||||
|
||||
/** @} */
|
||||
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||||
#ifdef __cplusplus
|
||||
}
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||||
#endif
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||||
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||||
#endif /* _GRLIB_FTMCTRL_REGS_H */
|
||||
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