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Remove make preinstall

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A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
This commit is contained in:
Chris Johns
2017-12-23 18:18:56 +11:00
committed by Sebastian Huber
parent 9704efb4ec
commit 2afb22b7e1
2356 changed files with 4032 additions and 19788 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
bsps/sh/gensh1/headers.am Normal file
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## This file was generated by "./boostrap -H".
include_HEADERS =
include_HEADERS += ../../../../../../bsps/sh/gensh1/include/bsp.h
include_HEADERS += include/bspopts.h
include_HEADERS += ../../../../../../bsps/sh/gensh1/include/tm27.h
include_rtems_scoredir = $(includedir)/rtems/score
include_rtems_score_HEADERS =
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh1/include/rtems/score/iosh7032.h
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh1/include/rtems/score/ispsh7032.h
include_shdir = $(includedir)/sh
include_sh_HEADERS =
include_sh_HEADERS += ../../../../../../bsps/sh/gensh1/include/sh/sci.h
include_sh_HEADERS += ../../../../../../bsps/sh/gensh1/include/sh/sh7_pfc.h
include_sh_HEADERS += ../../../../../../bsps/sh/gensh1/include/sh/sh7_sci.h

86
bsps/sh/gensh1/include/bsp.h Normal file
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/*
* generic sh1
*
* This include file contains all board IO definitions.
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_SH_GENSH1_BSP_H
#define LIBBSP_SH_GENSH1_BSP_H
#include <rtems.h>
#include <termios.h> /* for tcflag_t */
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#ifdef __cplusplus
extern "C" {
#endif
/* EDIT: To activate the sci driver, change the define below */
#if 1
#include <rtems/devnull.h>
#define BSP_CONSOLE_DEVNAME "/dev/null"
#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY
#else
#include <sh/sci.h>
#define BSP_CONSOLE_DEVNAME "/dev/sci0"
#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY
#endif
/* Constants */
/*
* Defined in the linker script 'linkcmds'
*/
extern void *CPU_Interrupt_stack_low;
extern void *CPU_Interrupt_stack_high;
/*
* Device Driver Table Entries
*/
/*
* We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console
*/
#undef CONSOLE_DRIVER_TABLE_ENTRY
#define CONSOLE_DRIVER_TABLE_ENTRY \
BSP_CONSOLE_DRIVER_TABLE_ENTRY, \
{ console_initialize, console_open, console_close, \
console_read, console_write, console_control }
/*
* BSP methods that cross file boundaries.
*/
void bsp_hw_init(void);
extern int _sci_get_brparms(
tcflag_t cflag,
unsigned char *smr,
unsigned char *brr
);
#ifdef __cplusplus
}
#endif
#endif

220
bsps/sh/gensh1/include/rtems/score/iosh7032.h Normal file
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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __IOSH7030_H
#define __IOSH7030_H
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
* 16 bit == short ( readw, writew, read16, write16 )
* 32 bit == long ( readl, writel, read32, write32 )
*/
#define SCI0_SMR 0x05fffec0 /* char */
#define SCI0_BRR 0x05fffec1 /* char */
#define SCI0_SCR 0x05fffec2 /* char */
#define SCI0_TDR 0x05fffec3 /* char */
#define SCI0_SSR 0x05fffec4 /* char */
#define SCI0_RDR 0x05fffec5 /* char */
#define SCI1_SMR 0x05fffec8 /* char */
#define SCI1_BRR 0x05fffec9 /* char */
#define SCI1_SCR 0x05fffeca /* char */
#define SCI1_TDR 0x05fffecb /* char */
#define SCI1_SSR 0x05fffecc /* char */
#define SCI1_RDR 0x05fffecd /* char */
#define ADDRAH 0x05fffee0 /* char */
#define ADDRAL 0x05fffee1 /* char */
#define ADDRBH 0x05fffee2 /* char */
#define ADDRBL 0x05fffee3 /* char */
#define ADDRCH 0x05fffee4 /* char */
#define ADDRCL 0x05fffee5 /* char */
#define ADDRDH 0x05fffee6 /* char */
#define ADDRDL 0x05fffee7 /* char */
#define AD_DRA 0x05fffee0 /* short */
#define AD_DRB 0x05fffee2 /* short */
#define AD_DRC 0x05fffee4 /* short */
#define AD_DRD 0x05fffee6 /* short */
#define ADCSR 0x05fffee8 /* char */
#define ADCR 0x05fffee9 /* char */
/*ITU SHARED*/
#define ITU_TSTR 0x05ffff00 /* char */
#define ITU_TSNC 0x05ffff01 /* char */
#define ITU_TMDR 0x05ffff02 /* char */
#define ITU_TFCR 0x05ffff03 /* char */
/*ITU CHANNEL 0*/
#define ITU_TCR0 0x05ffff04 /* char */
#define ITU_TIOR0 0x05ffff05 /* char */
#define ITU_TIER0 0x05ffff06 /* char */
#define ITU_TSR0 0x05ffff07 /* char */
#define ITU_TCNT0 0x05ffff08 /* short */
#define ITU_GRA0 0x05ffff0a /* short */
#define ITU_GRB0 0x05ffff0c /* short */
/*ITU CHANNEL 1*/
#define ITU_TCR1 0x05ffff0E /* char */
#define ITU_TIOR1 0x05ffff0F /* char */
#define ITU_TIER1 0x05ffff10 /* char */
#define ITU_TSR1 0x05ffff11 /* char */
#define ITU_TCNT1 0x05ffff12 /* short */
#define ITU_GRA1 0x05ffff14 /* short */
#define ITU_GRB1 0x05ffff16 /* short */
/*ITU CHANNEL 2*/
#define ITU_TCR2 0x05ffff18 /* char */
#define ITU_TIOR2 0x05ffff19 /* char */
#define ITU_TIER2 0x05ffff1A /* char */
#define ITU_TSR2 0x05ffff1B /* char */
#define ITU_TCNT2 0x05ffff1C /* short */
#define ITU_GRA2 0x05ffff1E /* short */
#define ITU_GRB2 0x05ffff20 /* short */
/*ITU CHANNEL 3*/
#define ITU_TCR3 0x05ffff22 /* char */
#define ITU_TIOR3 0x05ffff23 /* char */
#define ITU_TIER3 0x05ffff24 /* char */
#define ITU_TSR3 0x05ffff25 /* char */
#define ITU_TCNT3 0x05ffff26 /* short */
#define ITU_GRA3 0x05ffff28 /* short */
#define ITU_GRB3 0x05ffff2A /* short */
#define ITU_BRA3 0x05ffff2C /* short */
#define ITU_BRB3 0x05ffff2E /* short */
/*ITU CHANNELS 0-4 SHARED*/
#define ITU_TOCR 0x05ffff31 /* char */
/*ITU CHANNEL 4*/
#define ITU_TCR4 0x05ffff32 /* char */
#define ITU_TIOR4 0x05ffff33 /* char */
#define ITU_TIER4 0x05ffff34 /* char */
#define ITU_TSR4 0x05ffff35 /* char */
#define ITU_TCNT4 0x05ffff36 /* short */
#define ITU_GRA4 0x05ffff38 /* short */
#define ITU_GRB4 0x05ffff3A /* short */
#define ITU_BRA4 0x05ffff3C /* short */
#define ITU_BRB4 0x05ffff3E /* short */
/*DMAC CHANNELS 0-3 SHARED*/
#define DMAOR 0x05ffff48 /* short */
/*DMAC CHANNEL 0*/
#define DMA_SAR0 0x05ffff40 /* long */
#define DMA_DAR0 0x05ffff44 /* long */
#define DMA_TCR0 0x05ffff4a /* short */
#define DMA_CHCR0 0x05ffff4e /* short */
/*DMAC CHANNEL 1*/
#define DMA_SAR1 0x05ffff50 /* long */
#define DMA_DAR1 0x05ffff54 /* long */
#define DMA_TCR1 0x05fffF5a /* short */
#define DMA_CHCR1 0x05ffff5e /* short */
/*DMAC CHANNEL 3*/
#define DMA_SAR3 0x05ffff60 /* long */
#define DMA_DAR3 0x05ffff64 /* long */
#define DMA_TCR3 0x05fffF6a /* short */
#define DMA_CHCR3 0x05ffff6e /* short */
/*DMAC CHANNEL 4*/
#define DMA_SAR4 0x05ffff70 /* long */
#define DMA_DAR4 0x05ffff74 /* long */
#define DMA_TCR4 0x05fffF7a /* short */
#define DMA_CHCR4 0x05ffff7e /* short */
/*INTC*/
#define INTC_IPRA 0x05ffff84 /* short */
#define INTC_IPRB 0x05ffff86 /* short */
#define INTC_IPRC 0x05ffff88 /* short */
#define INTC_IPRD 0x05ffff8A /* short */
#define INTC_IPRE 0x05ffff8C /* short */
#define INTC_ICR 0x05ffff8E /* short */
/*UBC*/
#define UBC_BARH 0x05ffff90 /* short */
#define UBC_BARL 0x05ffff92 /* short */
#define UBC_BAMRH 0x05ffff94 /* short */
#define UBC_BAMRL 0x05ffff96 /* short */
#define UBC_BBR 0x05ffff98 /* short */
/*BSC*/
#define BSC_BCR 0x05ffffA0 /* short */
#define BSC_WCR1 0x05ffffA2 /* short */
#define BSC_WCR2 0x05ffffA4 /* short */
#define BSC_WCR3 0x05ffffA6 /* short */
#define BSC_DCR 0x05ffffA8 /* short */
#define BSC_PCR 0x05ffffAA /* short */
#define BSC_RCR 0x05ffffAC /* short */
#define BSC_RTCSR 0x05ffffAE /* short */
#define BSC_RTCNT 0x05ffffB0 /* short */
#define BSC_RTCOR 0x05ffffB2 /* short */
/*WDT*/
#define WDT_TCSR 0x05ffffB8 /* char */
#define WDT_TCNT 0x05ffffB9 /* char */
#define WDT_RSTCSR 0x05ffffBB /* char */
/*POWER DOWN STATE*/
#define PDT_SBYCR 0x05ffffBC /* char */
/*PORT A*/
#define PADR 0x05ffffC0 /* short */
/*PORT B*/
#define PBDR 0x05ffffC2 /* short */
/*PORT C*/
#define PCDR 0x05ffffD0 /* short */
/*PFC*/
#define PFC_PAIOR 0x05ffffC4 /* short */
#define PFC_PBIOR 0x05ffffC6 /* short */
#define PFC_PACR1 0x05ffffC8 /* short */
#define PFC_PACR2 0x05ffffCA /* short */
#define PFC_PBCR1 0x05ffffCC /* short */
#define PFC_PBCR2 0x05ffffCE /* short */
#define PFC_CASCR 0x05ffffEE /* short */
/*TPC*/
#define TPC_TPMR 0x05ffffF0 /* short */
#define TPC_TPCR 0x05ffffF1 /* short */
#define TPC_NDERH 0x05ffffF2 /* short */
#define TPC_NDERL 0x05ffffF3 /* short */
#define TPC_NDRB 0x05ffffF4 /* char */
#define TPC_NDRA 0x05ffffF5 /* char */
#define TPC_NDRB1 0x05ffffF6 /* char */
#define TPC_NDRA1 0x05ffffF7 /* char */
#endif

162
bsps/sh/gensh1/include/rtems/score/ispsh7032.h Normal file
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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/types.h>
extern void __ISR_Handler( uint32_t vector );
/*
* interrupt vector table offsets
*/
#define NMI_ISP_V 11
#define USB_ISP_V 12
#define IRQ0_ISP_V 64
#define IRQ1_ISP_V 65
#define IRQ2_ISP_V 66
#define IRQ3_ISP_V 67
#define IRQ4_ISP_V 68
#define IRQ5_ISP_V 69
#define IRQ6_ISP_V 70
#define IRQ7_ISP_V 71
#define DMA0_ISP_V 72
#define DMA1_ISP_V 74
#define DMA2_ISP_V 76
#define DMA3_ISP_V 78
#define IMIA0_ISP_V 80
#define IMIB0_ISP_V 81
#define OVI0_ISP_V 82
#define IMIA1_ISP_V 84
#define IMIB1_ISP_V 85
#define OVI1_ISP_V 86
#define IMIA2_ISP_V 88
#define IMIB2_ISP_V 89
#define OVI2_ISP_V 90
#define IMIA3_ISP_V 92
#define IMIB3_ISP_V 93
#define OVI3_ISP_V 94
#define IMIA4_ISP_V 96
#define IMIB4_ISP_V 97
#define OVI4_ISP_V 98
#define ERI0_ISP_V 100
#define RXI0_ISP_V 101
#define TXI0_ISP_V 102
#define TEI0_ISP_V 103
#define ERI1_ISP_V 104
#define RXI1_ISP_V 105
#define TXI1_ISP_V 106
#define TEI1_ISP_V 107
#define PRT_ISP_V 108
#define ADU_ISP_V 109
#define WDT_ISP_V 112
#define DREF_ISP_V 113
/* dummy ISP */
extern void _dummy_isp( void );
/* Non Maskable Interrupt */
extern void _nmi_isp( void );
/* User Break Controller */
extern void _usb_isp( void );
/* External interrupts 0-7 */
extern void _irq0_isp( void );
extern void _irq1_isp( void );
extern void _irq2_isp( void );
extern void _irq3_isp( void );
extern void _irq4_isp( void );
extern void _irq5_isp( void );
extern void _irq6_isp( void );
extern void _irq7_isp( void );
/* DMA - Controller */
extern void _dma0_isp( void );
extern void _dma1_isp( void );
extern void _dma2_isp( void );
extern void _dma3_isp( void );
/* Interrupt Timer Unit */
/* Timer 0 */
extern void _imia0_isp( void );
extern void _imib0_isp( void );
extern void _ovi0_isp( void );
/* Timer 1 */
extern void _imia1_isp( void );
extern void _imib1_isp( void );
extern void _ovi1_isp( void );
/* Timer 2 */
extern void _imia2_isp( void );
extern void _imib2_isp( void );
extern void _ovi2_isp( void );
/* Timer 3 */
extern void _imia3_isp( void );
extern void _imib3_isp( void );
extern void _ovi3_isp( void );
/* Timer 4 */
extern void _imia4_isp( void );
extern void _imib4_isp( void );
extern void _ovi4_isp( void );
/* seriell interfaces */
extern void _eri0_isp( void );
extern void _rxi0_isp( void );
extern void _txi0_isp( void );
extern void _tei0_isp( void );
extern void _eri1_isp( void );
extern void _rxi1_isp( void );
extern void _txi1_isp( void );
extern void _tei1_isp( void );
/* Parity Control Unit of the Bus State Controllers */
extern void _prt_isp( void );
/* ADC */
extern void _adu_isp( void );
/* Watchdog Timer */
extern void _wdt_isp( void );
/* DRAM refresh control unit of bus state controller */
extern void _dref_isp( void );
#ifdef __cplusplus
}
#endif
#endif

82
bsps/sh/gensh1/include/sh/sci.h Normal file
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/*
* Driver for the sh1 703x on-chip serial devices (sci)
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh_sci_h
#define _sh_sci_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* Devices are set to 9600 bps, 8 databits, 1 stopbit, no
* parity and asynchronous mode by default.
*
* NOTE:
* The onboard serial devices of the SH do not support hardware
* handshake.
*/
#define DEVSCI_DRIVER_TABLE_ENTRY \
{ sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
sh_sci_write, sh_sci_control }
extern rtems_device_driver sh_sci_initialize(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_open(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_close(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_read(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_write(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_control(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
#ifdef __cplusplus
}
#endif
#endif

115
bsps/sh/gensh1/include/sh/sh7_pfc.h Normal file
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/*
* Bit values for the pin function controller of the Hitachi SH703X
*
* From Hitachi tutorials
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh7_pfc_h
#define _sh7_pfc_h
#include <rtems/score/iosh7032.h>
/*
* Port B IO Register (PBIOR)
*/
#define PBIOR PFC_PBIOR
#define PB15IOR 0x8000
#define PB14IOR 0x4000
#define PB13IOR 0x2000
#define PB12IOR 0x1000
#define PB11IOR 0x0800
#define PB10IOR 0x0400
#define PB9IOR 0x0200
#define PB8IOR 0x0100
#define PB7IOR 0x0080
#define PB6IOR 0x0040
#define PB5IOR 0x0020
#define PB4IOR 0x0010
#define PB3IOR 0x0008
#define PB2IOR 0x0004
#define PB1IOR 0x0002
#define PB0IOR 0x0001
/*
* Port B Control Register (PBCR1)
*/
#define PBCR1 PFC_PBCR1
#define PB15MD1 0x8000
#define PB15MD0 0x4000
#define PB14MD1 0x2000
#define PB14MD0 0x1000
#define PB13MD1 0x0800
#define PB13MD0 0x0400
#define PB12MD1 0x0200
#define PB12MD0 0x0100
#define PB11MD1 0x0080
#define PB11MD0 0x0040
#define PB10MD1 0x0020
#define PB10MD0 0x0010
#define PB9MD1 0x0008
#define PB9MD0 0x0004
#define PB8MD1 0x0002
#define PB8MD0 0x0001
#define PB15MD PB15MD1|PB14MD0
#define PB14MD PB14MD1|PB14MD0
#define PB13MD PB13MD1|PB13MD0
#define PB12MD PB12MD1|PB12MD0
#define PB11MD PB11MD1|PB11MD0
#define PB10MD PB10MD1|PB10MD0
#define PB9MD PB9MD1|PB9MD0
#define PB8MD PB8MD1|PB8MD0
#define PB_TXD1 PB11MD1
#define PB_RXD1 PB10MD1
#define PB_TXD0 PB9MD1
#define PB_RXD0 PB8MD1
/*
* Port B Control Register (PBCR2)
*/
#define PBCR2 PFC_PBCR2
#define PB7MD1 0x8000
#define PB7MD0 0x4000
#define PB6MD1 0x2000
#define PB6MD0 0x1000
#define PB5MD1 0x0800
#define PB5MD0 0x0400
#define PB4MD1 0x0200
#define PB4MD0 0x0100
#define PB3MD1 0x0080
#define PB3MD0 0x0040
#define PB2MD1 0x0020
#define PB2MD0 0x0010
#define PB1MD1 0x0008
#define PB1MD0 0x0004
#define PB0MD1 0x0002
#define PB0MD0 0x0001
#define PB7MD PB7MD1|PB7MD0
#define PB6MD PB6MD1|PB6MD0
#define PB5MD PB5MD1|PB5MD0
#define PB4MD PB4MD1|PB4MD0
#define PB3MD PB3MD1|PB3MD0
#define PB2MD PB2MD1|PB2MD0
#define PB1MD PB1MD1|PB1MD0
#define PB0MD PB0MD1|PB0MD0
#endif /* _sh7_pfc_h */

79
bsps/sh/gensh1/include/sh/sh7_sci.h Normal file
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/*
* Bit values for the serial control registers of the Hitachi SH703X
*
* From Hitachi tutorials
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh7_sci_h
#define _sh7_sci_h
#include <rtems/score/iosh7032.h>
/*
* Serial mode register bits
*/
#define SCI_SYNC_MODE 0x80
#define SCI_SEVEN_BIT_DATA 0x40
#define SCI_PARITY_ON 0x20
#define SCI_ODD_PARITY 0x10
#define SCI_STOP_BITS_2 0x08
#define SCI_ENABLE_MULTIP 0x04
#define SCI_PHI_64 0x03
#define SCI_PHI_16 0x02
#define SCI_PHI_4 0x01
#define SCI_PHI_0 0x00
/*
* Serial register offsets, relative to SCI0_SMR or SCI1_SMR
*/
#define SCI_SMR 0x00
#define SCI_BRR 0x01
#define SCI_SCR 0x02
#define SCI_TDR 0x03
#define SCI_SSR 0x04
#define SCI_RDR 0x05
/*
* Serial control register bits
*/
#define SCI_TIE 0x80 /* Transmit interrupt enable */
#define SCI_RIE 0x40 /* Receive interrupt enable */
#define SCI_TE 0x20 /* Transmit enable */
#define SCI_RE 0x10 /* Receive enable */
#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
#define SCI_CKE1 0x02 /* Clock enable 1 */
#define SCI_CKE0 0x01 /* Clock enable 0 */
/*
* Serial status register bits
*/
#define SCI_TDRE 0x80 /* Transmit data register empty */
#define SCI_RDRF 0x40 /* Receive data register full */
#define SCI_ORER 0x20 /* Overrun error */
#define SCI_FER 0x10 /* Framing error */
#define SCI_PER 0x08 /* Parity error */
#define SCI_TEND 0x04 /* Transmit end */
#define SCI_MPB 0x02 /* Multiprocessor bit */
#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
#endif /* _sh7_sci_h */

1
bsps/sh/gensh1/include/tm27.h Normal file
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#include <rtems/tm27-default.h>

19
bsps/sh/gensh2/headers.am Normal file
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## This file was generated by "./boostrap -H".
include_HEADERS =
include_HEADERS += ../../../../../../bsps/sh/gensh2/include/bsp.h
include_HEADERS += include/bspopts.h
include_HEADERS += ../../../../../../bsps/sh/gensh2/include/tm27.h
include_rtems_scoredir = $(includedir)/rtems/score
include_rtems_score_HEADERS =
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh2/include/rtems/score/iosh7045.h
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh2/include/rtems/score/ispsh7045.h
include_shdir = $(includedir)/sh
include_sh_HEADERS =
include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/io_types.h
include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/sci.h
include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/sci_termios.h
include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/sh7_pfc.h
include_sh_HEADERS += ../../../../../../bsps/sh/gensh2/include/sh/sh7_sci.h

85
bsps/sh/gensh2/include/bsp.h Normal file
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/*
* generic sh2
*
* This include file contains all board IO definitions.
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Minor adaptations for sh2 by:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef LIBBSP_SH_GENSH2_BSP_H
#define LIBBSP_SH_GENSH2_BSP_H
#include <rtems.h>
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#include <termios.h> /* for tcflag_t */
#include <sh/sci.h>
#ifdef __cplusplus
extern "C" {
#endif
#if 1
/* FIXME:
* These definitions will be no longer necessary if the old
* implementation of SCI driver will be droped
*/
#define BSP_CONSOLE_DEVNAME "/dev/sci0"
#define BSP_CONSOLE_MINOR_NUMBER ((rtems_device_minor_number) 0)
#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY
#define BSP_CONSOLE_DEVICE_TERMIOS_HANDLERS (sh_sci_get_termios_handlers(TRUE))
#endif
/* Constants */
/*
* Defined in the linker script 'linkcmds'
*/
extern void *CPU_Interrupt_stack_low;
extern void *CPU_Interrupt_stack_high;
/*
* BSP methods that cross file boundaries.
*/
void bsp_hw_init(void);
extern int _sci_get_brparms(
tcflag_t cflag,
unsigned char *smr,
unsigned char *brr
);
#ifdef __cplusplus
}
#endif
#endif

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bsps/sh/gensh2/include/rtems/score/iosh7045.h Normal file
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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect on-chip registers for sh7045 processor, based on
* "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
* contained no copyright notice:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
* August, 1999
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef __IOSH7045_H
#define __IOSH7045_H
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
* 16 bit == short ( readw, writew, read16, write16 )
* 32 bit == long ( readl, writel, read32, write32 )
* JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
* ENGINE_..Hardware_Manual; alignment access-restrictions may apply
*/
#define REG_BASE 0xFFFF8000
/* SCI0 Registers */
#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */
#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */
#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */
#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */
#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */
#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */
#define SCI0_SMR SCI_SMR0
/* SCI1 Registers */
#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */
#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */
#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */
#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */
#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */
#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */
#define SCI1_SMR SCI_SMR1
/* ADI */
/* High Speed A/D (Excluding A-Mask Part)*/
#define ADDRA (REG_BASE + 0x03F0) /* short */
#define ADDRB (REG_BASE + 0x03F2) /* short */
#define ADDRC (REG_BASE + 0x03F4) /* short */
#define ADDRD (REG_BASE + 0x03F6) /* short */
#define ADDRE (REG_BASE + 0x03F8) /* short */
#define ADDRF (REG_BASE + 0x03FA) /* short */
#define ADDRG (REG_BASE + 0x03FC) /* short */
#define ADDRH (REG_BASE + 0x03FE) /* short */
#define ADCSR (REG_BASE + 0x03E0) /* char */
#define ADCR (REG_BASE + 0x03E1) /* char */
/* Mid-Speed A/D (A-Mask part)*/
#define ADDRA0 (REG_BASE + 0x0400) /* char, short */
#define ADDRA0H (REG_BASE + 0x0400) /* char, short */
#define ADDRA0L (REG_BASE + 0x0401) /* char */
#define ADDRB0 (REG_BASE + 0x0402) /* char, short */
#define ADDRB0H (REG_BASE + 0x0402) /* char, short */
#define ADDRB0L (REG_BASE + 0x0403) /* char */
#define ADDRC0 (REG_BASE + 0x0404) /* char, short */
#define ADDRC0H (REG_BASE + 0x0404) /* char, short */
#define ADDRC0L (REG_BASE + 0x0405) /* char */
#define ADDRD0 (REG_BASE + 0x0406) /* char, short */
#define ADDRD0H (REG_BASE + 0x0406) /* char, short */
#define ADDRD0L (REG_BASE + 0x0407) /* char */
#define ADCSR0 (REG_BASE + 0x0410) /* char */
#define ADCR0 (REG_BASE + 0x0412) /* char */
#define ADDRA1 (REG_BASE + 0x0408) /* char, short */
#define ADDRA1H (REG_BASE + 0x0408) /* char, short */
#define ADDRA1L (REG_BASE + 0x0409) /* char */
#define ADDRB1 (REG_BASE + 0x040A) /* char, short */
#define ADDRB1H (REG_BASE + 0x040A) /* char, short */
#define ADDRB1L (REG_BASE + 0x040B) /* char */
#define ADDRC1 (REG_BASE + 0x040C) /* char, short */
#define ADDRC1H (REG_BASE + 0x040C) /* char, short */
#define ADDRC1L (REG_BASE + 0x040D) /* char */
#define ADDRD1 (REG_BASE + 0x040E) /* char, short */
#define ADDRD1H (REG_BASE + 0x040E) /* char, short */
#define ADDRD1L (REG_BASE + 0x040F) /* char */
#define ADCSR1 (REG_BASE + 0x0411) /* char */
#define ADCR1 (REG_BASE + 0x0413) /* char */
/*MTU SHARED*/
#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */
#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */
#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */
#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */
/*MTU CHANNEL 0*/
#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */
#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */
#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */
#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */
#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */
#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */
#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */
#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */
#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */
#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */
#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */
/*MTU CHANNEL 1*/
#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */
#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */
#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */
#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */
#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */
#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */
#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */
#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */
/*MTU CHANNEL 2*/
#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */
#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */
#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */
#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */
#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */
#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */
#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */
#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */
/*MTU CHANNELS 3-4 SHARED*/
#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */
#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */
#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */
#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */
#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */
#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */
#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */
/*MTU CHANNEL 3*/
#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */
#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */
#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */
#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */
#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */
#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */
#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */
#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */
#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */
#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */
#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */
/*MTU CHANNEL 4*/
#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */
#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */
#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */
#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */
#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */
#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */
#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */
#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */
#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */
#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */
#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */
#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */
/*DMAC CHANNELS 0-3 SHARED*/
#define DMAOR (REG_BASE + 0x06B0) /* short */
/*DMAC CHANNEL 0*/
#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */
#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */
#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */
/*DMAC CHANNEL 1*/
#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */
#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */
#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */
/*DMAC CHANNEL 3*/
#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */
#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */
#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */
/*DMAC CHANNEL 4*/
#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */
#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */
#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */
/*Data Transfer Controller*/
#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */
#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */
#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */
#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */
#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */
#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */
#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */
/*Cache Memory*/
#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */
/*INTC*/
#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */
#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */
#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */
#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */
#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */
#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */
#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */
#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */
#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */
#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */
/*Flash (F-ZTAT)*/
#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
/*UBC*/
#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */
#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */
#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */
#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */
#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */
/*BSC*/
#define BSC_BCR1 (REG_BASE + 0x0620) /* short */
#define BSC_BCR2 (REG_BASE + 0x0622) /* short */
#define BSC_WCR1 (REG_BASE + 0x0624) /* short */
#define BSC_WCR2 (REG_BASE + 0x0626) /* short */
#define BSC_DCR (REG_BASE + 0x062A) /* short */
#define BSC_RTCSR (REG_BASE + 0x062C) /* short */
#define BSC_RTCNT (REG_BASE + 0x062E) /* short */
#define BSC_RTCOR (REG_BASE + 0x0630) /* short */
/*WDT*/
#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */
#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */
#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */
#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */
#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
/*POWER DOWN STATE*/
#define PDT_SBYCR (REG_BASE + 0x0614) /* char */
/* Port I/O Control Registers */
#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */
#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */
#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */
#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */
#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */
#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */
#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */
#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */
/*Pin Function Control Register*/
#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */
#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */
#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */
#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */
#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
/*Compare/Match Timer*/
#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
#endif

208
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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect isp entries for sh7045 processor:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/types.h>
extern void __ISR_Handler( uint32_t vector );
/*
* interrupt vector table offsets
*/
#define NMI_ISP_V 11
#define USB_ISP_V 12
#define IRQ0_ISP_V 64
#define IRQ1_ISP_V 65
#define IRQ2_ISP_V 66
#define IRQ3_ISP_V 67
#define IRQ4_ISP_V 68
#define IRQ5_ISP_V 69
#define IRQ6_ISP_V 70
#define IRQ7_ISP_V 71
#define DMA0_ISP_V 72
#define DMA1_ISP_V 76
#define DMA2_ISP_V 80
#define DMA3_ISP_V 84
#define MTUA0_ISP_V 88
#define MTUB0_ISP_V 89
#define MTUC0_ISP_V 90
#define MTUD0_ISP_V 91
#define MTUV0_ISP_V 92
#define MTUA1_ISP_V 96
#define MTUB1_ISP_V 97
#define MTUV1_ISP_V 100
#define MTUU1_ISP_V 101
#define MTUA2_ISP_V 104
#define MTUB2_ISP_V 105
#define MTUV2_ISP_V 108
#define MTUU2_ISP_V 109
#define MTUA3_ISP_V 112
#define MTUB3_ISP_V 113
#define MTUC3_ISP_V 114
#define MTUD3_ISP_V 115
#define MTUV3_ISP_V 116
#define MTUA4_ISP_V 120
#define MTUB4_ISP_V 121
#define MTUC4_ISP_V 122
#define MTUD4_ISP_V 123
#define MTUV4_ISP_V 124
#define ERI0_ISP_V 128
#define RXI0_ISP_V 129
#define TXI0_ISP_V 130
#define TEI0_ISP_V 131
#define ERI1_ISP_V 132
#define RXI1_ISP_V 133
#define TXI1_ISP_V 134
#define TEI1_ISP_V 135
#define ADI0_ISP_V 136
#define ADI1_ISP_V 137
#define DTC_ISP_V 140 /* Data Transfer Controller */
#define CMT0_ISP_V 144 /* Compare Match Timer */
#define CMT1_ISP_V 148
#define WDT_ISP_V 152 /* Wtachdog Timer */
#define CMI_ISP_V 153 /* BSC RAS interrupt */
#define OEI_ISP_V 156 /* I/O Port */
#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
#if 0
#define PRT_ISP_V /* parity error - no equivalent */
#endif
/* dummy ISP */
extern void _dummy_isp( void );
/* Non Maskable Interrupt */
extern void _nmi_isp( void );
/* User Break Controller */
extern void _usb_isp( void );
/* External interrupts 0-7 */
extern void _irq0_isp( void );
extern void _irq1_isp( void );
extern void _irq2_isp( void );
extern void _irq3_isp( void );
extern void _irq4_isp( void );
extern void _irq5_isp( void );
extern void _irq6_isp( void );
extern void _irq7_isp( void );
/* DMA - Controller */
extern void _dma0_isp( void );
extern void _dma1_isp( void );
extern void _dma2_isp( void );
extern void _dma3_isp( void );
/* Interrupt Timer Unit */
/* Timer 0 */
extern void _mtua0_isp( void );
extern void _mtub0_isp( void );
extern void _mtuc0_isp( void );
extern void _mtud0_isp( void );
extern void _mtuv0_isp( void );
/* Timer 1 */
extern void _mtua1_isp( void );
extern void _mtub1_isp( void );
extern void _mtuv1_isp( void );
extern void _mtuu1_isp( void );
/* Timer 2 */
extern void _mtua2_isp( void );
extern void _mtub2_isp( void );
extern void _mtuv2_isp( void );
extern void _mtuu2_isp( void );
/* Timer 3 */
extern void _mtua3_isp( void );
extern void _mtub3_isp( void );
extern void _mtuc3_isp( void );
extern void _mtud3_isp( void );
extern void _mtuv3_isp( void );
/* Timer 4 */
extern void _mtua4_isp( void );
extern void _mtub4_isp( void );
extern void _mtuc4_isp( void );
extern void _mtud4_isp( void );
extern void _mtuv4_isp( void );
/* serial interfaces */
extern void _eri0_isp( void );
extern void _rxi0_isp( void );
extern void _txi0_isp( void );
extern void _tei0_isp( void );
extern void _eri1_isp( void );
extern void _rxi1_isp( void );
extern void _txi1_isp( void );
extern void _tei1_isp( void );
/* ADC */
extern void _adi0_isp( void );
extern void _adi1_isp( void );
/* Data Transfer Controller */
extern void _dtci_isp( void );
/* Compare Match Timer */
extern void _cmt0_isp( void );
extern void _cmt1_isp( void );
/* Watchdog Timer */
extern void _wdt_isp( void );
/* DRAM refresh control unit of bus state controller */
extern void _bsc_isp( void );
/* I/O Port */
extern void _oei_isp( void );
/* Parity Control Unit of the Bus State Controllers */
/* extern void _prt_isp( void ); */
#ifdef __cplusplus
}
#endif
#endif

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/************************************************************************
*
* Data types and constants for Hitachi SH704X on-chip peripherals
*
* Author: John M.Mills (jmills@tga.com)
*
* COPYRIGHT (c) 1999, TGA Technologies, Norcross, GA, USA
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* This file may be distributed as part of the RTEMS software item.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*
*
************************************************************************/
#ifndef _sh_io_types_h
#define _sh_io_types_h
#include <rtems/score/iosh7045.h>
#include <termios.h>
typedef enum {SCI0, SCI1} portNo;
typedef enum {eight, seven} dataBits;
typedef enum {one, two} stopBits;
typedef enum {even, odd} parity;
typedef struct {
portNo line;
int speed_ix;
dataBits dBits;
int parEn;
parity par;
int mulPro;
stopBits sBits;
} sci_setup_t;
typedef union{
unsigned char Reg; /* By Register */
struct { /* By Field */
unsigned char Sync :1; /* Async/Sync */
unsigned char DBts :1; /* Char.Length */
unsigned char ParEn :1; /* Parity En.*/
unsigned char Odd :1; /* Even/Odd */
unsigned char SBts :1; /* No.Stop Bits */
unsigned char MulP :1; /* Multi-Proc. */
unsigned char Dvsr :2; /* Clock Sel. */
} Fld;
} sci_smr_t;
typedef union {
unsigned char Reg; /* By Register */
struct { /* By Field */
unsigned char TIE :1; /* Tx.Int.En. */
unsigned char RIE :1; /* Rx.Int.En. */
unsigned char TE :1; /* Tx.En. */
unsigned char RE :1; /* Rx.En. */
unsigned char MPIE:1; /* Mult.Pro.Int.En. */
unsigned char TEIE:1; /* Tx.End Int.En. */
unsigned char CkSrc :2; /* Clock Src. */
} Fld;
} sci_scr_t;
typedef struct {
unsigned char n ;
unsigned char N ;
} sci_bitrate_t;
#endif /* _sh_io_types_h */

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/*
* Driver for the sh2 704x on-chip serial devices (sci)
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh_sci_h
#define _sh_sci_h
#include <rtems/libio.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* Devices are set to 9600 bps, 8 databits, 1 stopbit, no
* parity and asynchronous mode by default.
*
* NOTE:
* The onboard serial devices of the SH do not support hardware
* handshake.
*/
#define DEVSCI_DRIVER_TABLE_ENTRY \
{ sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
sh_sci_write, sh_sci_control }
extern rtems_device_driver sh_sci_initialize(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_open(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_close(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_read(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_write(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_control(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern const rtems_termios_callbacks * sh_sci_get_termios_handlers(
bool poll
);
#ifdef __cplusplus
}
#endif
#endif

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/*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#ifndef _SH_SCI_TERMIOS_H_
#define _SH_SCI_TERMIOS_H_
#ifdef __cplusplus
extern "C"{
#endif
int sh_sci_set_attributes(
int minor,
const struct termios *t
);
void sh_sci_initialize_interrupts(int minor);
void sh_sci_init(int minor);
ssize_t sh_sci_write_support_int(
int minor,
const char *buf,
size_t len
);
ssize_t sh_sci_write_support_polled(
int minor,
const char *buf,
size_t len
);
void sh_sci_write_polled(
int minor,
char c
);
int sh_sci_inbyte_nonblocking_polled(int minor);
int sh_sci_first_open(
int major,
int minor,
void *arg
);
int sh_sci_last_close(
int major,
int minor,
void *arg
);
#ifdef __cplusplus
}
#endif
#endif /* _SH_SCI_TERMIOS_H_ */

202
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/*
* Bit values for the pin function controller of the Hitachi SH704x
*
* From Hitachi tutorials
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh7_pfc_h
#define _sh7_pfc_h
#include <rtems/score/iosh7045.h>
/*
* Port A IO Registers (PAIORH, PAIORL)
* 1 => OUTPUT
* 0 => INPUT
*/
#define PAIORH PFC_PAIORH
#define PAIORL PFC_PAIORL
/* PAIORH */
#define PA23IOR 0x0080
#define PA22IOR 0x0040
#define PA21IOR 0x0020
#define PA20IOR 0x0010
#define PA19IOR 0x0008
#define PA18IOR 0x0004
#define PA17IOR 0x0002
#define PA16IOR 0x0001
/* PAIORL */
#define PA15IOR 0x8000
#define PA14IOR 0x4000
#define PA13IOR 0x2000
#define PA12IOR 0x1000
#define PA11IOR 0x0800
#define PA10IOR 0x0400
#define PA9IOR 0x0200
#define PA8IOR 0x0100
#define PA7IOR 0x0080
#define PA6IOR 0x0040
#define PA5IOR 0x0020
#define PA4IOR 0x0010
#define PA3IOR 0x0008
#define PA2IOR 0x0004
#define PA1IOR 0x0002
#define PA0IOR 0x0001
/*
* Port A Control Registers (PACRH, PACRL1, PACRL2)
* and mode bits
*/
#define PACRH PFC_PACRH
#define PACRL1 PFC_PACRL1
#define PACRL2 PFC_PACRL2
/* PACRH */
#define PA23MD0 0x4000
#define PA22MD0 0x1000
#define PA21MD0 0x0400
#define PA20MD0 0x0100
#define PA19MD1 0x0080
#define PA19MD0 0x0040
#define PA18MD1 0x0020
#define PA18MD0 0x0010
#define PA17MD0 0x0004
#define PA16MD0 0x0001
/* PACRL1 */
#define PA15MD0 0x4000
#define PA14MD0 0x1000
#define PA13MD0 0x0400
#define PA12MD0 0x0100
#define PA11MD0 0x0040
#define PA10MD0 0x0010
#define PA9MD1 0x0008
#define PA9MD0 0x0004
#define PA8MD1 0x0002
#define PA8MD0 0x0001
/* PACRL2 */
#define PA7MD1 0x8000
#define PA7MD0 0x4000
#define PA6MD1 0x2000
#define PA6MD0 0x1000
#define PA5MD1 0x0800
#define PA5MD0 0x0400
#define PA4MD0 0x0100
#define PA3MD0 0x0040
#define PA2MD1 0x0020
#define PA2MD0 0x0010
#define PA1MD0 0x0004
#define PA0MD0 0x0001
#define PA_TXD1 PA4MD0
#define PA_RXD1 PA3MD0
#define PA_TXD0 PA1MD0
#define PA_RXD0 PA0MD0
/*
* Port B IO Register (PBIOR)
*/
#define PBIOR PFC_PBIOR
#define PB15IOR 0x8000
#define PB14IOR 0x4000
#define PB13IOR 0x2000
#define PB12IOR 0x1000
#define PB11IOR 0x0800
#define PB10IOR 0x0400
#define PB9IOR 0x0200
#define PB8IOR 0x0100
#define PB7IOR 0x0080
#define PB6IOR 0x0040
#define PB5IOR 0x0020
#define PB4IOR 0x0010
#define PB3IOR 0x0008
#define PB2IOR 0x0004
#define PB1IOR 0x0002
#define PB0IOR 0x0001
/*
* Port B Control Register (PBCR1)
*/
#define PBCR1 PFC_PBCR1
#define PB15MD1 0x8000
#define PB15MD0 0x4000
#define PB14MD1 0x2000
#define PB14MD0 0x1000
#define PB13MD1 0x0800
#define PB13MD0 0x0400
#define PB12MD1 0x0200
#define PB12MD0 0x0100
#define PB11MD1 0x0080
#define PB11MD0 0x0040
#define PB10MD1 0x0020
#define PB10MD0 0x0010
#define PB9MD1 0x0008
#define PB9MD0 0x0004
#define PB8MD1 0x0002
#define PB8MD0 0x0001
#define PB15MD PB15MD1|PB14MD0
#define PB14MD PB14MD1|PB14MD0
#define PB13MD PB13MD1|PB13MD0
#define PB12MD PB12MD1|PB12MD0
#define PB11MD PB11MD1|PB11MD0
#define PB10MD PB10MD1|PB10MD0
#define PB9MD PB9MD1|PB9MD0
#define PB8MD PB8MD1|PB8MD0
#define PB_TXD1 PB11MD1
#define PB_RXD1 PB10MD1
#define PB_TXD0 PB9MD1
#define PB_RXD0 PB8MD1
/*
* Port B Control Register (PBCR2)
*/
#define PBCR2 PFC_PBCR2
#define PB7MD1 0x8000
#define PB7MD0 0x4000
#define PB6MD1 0x2000
#define PB6MD0 0x1000
#define PB5MD1 0x0800
#define PB5MD0 0x0400
#define PB4MD1 0x0200
#define PB4MD0 0x0100
#define PB3MD1 0x0080
#define PB3MD0 0x0040
#define PB2MD1 0x0020
#define PB2MD0 0x0010
#define PB1MD1 0x0008
#define PB1MD0 0x0004
#define PB0MD1 0x0002
#define PB0MD0 0x0001
#define PB7MD PB7MD1|PB7MD0
#define PB6MD PB6MD1|PB6MD0
#define PB5MD PB5MD1|PB5MD0
#define PB4MD PB4MD1|PB4MD0
#define PB3MD PB3MD1|PB3MD0
#define PB2MD PB2MD1|PB2MD0
#define PB1MD PB1MD1|PB1MD0
#define PB0MD PB0MD1|PB0MD0
#endif /* _sh7_pfc_h */

88
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/*
* Bit values for the serial control registers of the Hitachi SH704X
*
* From Hitachi tutorials
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh7_sci_h
#define _sh7_sci_h
#include <rtems/score/iosh7045.h>
/*
* Serial mode register bits
*/
#define SCI_SYNC_MODE 0x80
#define SCI_SEVEN_BIT_DATA 0x40
#define SCI_PARITY_ON 0x20
#define SCI_ODD_PARITY 0x10
#define SCI_STOP_BITS_2 0x08
#define SCI_ENABLE_MULTIP 0x04
#define SCI_PHI_64 0x03
#define SCI_PHI_16 0x02
#define SCI_PHI_4 0x01
#define SCI_PHI_0 0x00
/*
* Serial register offsets, relative to SCI0_SMR or SCI1_SMR
*/
#define SCI_SMR 0x00
#define SCI_BRR 0x01
#define SCI_SCR 0x02
#define SCI_TDR 0x03
#define SCI_SSR 0x04
#define SCI_RDR 0x05
/*
* Serial control register bits
*/
#define SCI_TIE 0x80 /* Transmit interrupt enable */
#define SCI_RIE 0x40 /* Receive interrupt enable */
#define SCI_TE 0x20 /* Transmit enable */
#define SCI_RE 0x10 /* Receive enable */
#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
#define SCI_CKE1 0x02 /* Clock enable 1 */
#define SCI_CKE0 0x01 /* Clock enable 0 */
/*
* Serial status register bits
*/
#define SCI_TDRE 0x80 /* Transmit data register empty */
#define SCI_RDRF 0x40 /* Receive data register full */
#define SCI_ORER 0x20 /* Overrun error */
#define SCI_FER 0x10 /* Framing error */
#define SCI_PER 0x08 /* Parity error */
#define SCI_TEND 0x04 /* Transmit end */
#define SCI_MPB 0x02 /* Multiprocessor bit */
#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
/*
* INTC Priority Settings
*/
#define SCI0_IPMSK 0x00F0
#define SCI0_LOWIP 0x0010
#define SCI1_IPMSK 0x000F
#define SCI1_LOWIP 0x0001
#endif /* _sh7_sci_h */

1
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#include <rtems/tm27-default.h>

19
bsps/sh/gensh4/headers.am Normal file
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## This file was generated by "./boostrap -H".
include_HEADERS =
include_HEADERS += ../../../../../../bsps/sh/gensh4/include/bsp.h
include_HEADERS += include/bspopts.h
include_HEADERS += ../../../../../../bsps/sh/gensh4/include/sdram.h
include_HEADERS += ../../../../../../bsps/sh/gensh4/include/tm27.h
include_rtems_scoredir = $(includedir)/rtems/score
include_rtems_score_HEADERS =
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/iosh7750.h
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/ipl.h
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/ispsh7750.h
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/sh4_regs.h
include_rtems_score_HEADERS += ../../../../../../bsps/sh/gensh4/include/rtems/score/sh7750_regs.h
include_shdir = $(includedir)/sh
include_sh_HEADERS =
include_sh_HEADERS += ../../../../../../bsps/sh/gensh4/include/sh/sh4uart.h

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/*
* generic sh4 BSP
*
* This include file contains all board IO definitions.
*/
/*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* Based on work:
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Minor adaptations for sh2 by:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef LIBBSP_SH_GENSH4_BSP_H
#define LIBBSP_SH_GENSH4_BSP_H
#include <rtems.h>
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#include "rtems/score/sh7750_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Constants */
/*
* Defined in the linker script 'linkcmds'
*/
extern void *CPU_Interrupt_stack_low;
extern void *CPU_Interrupt_stack_high;
/*
* Defined in start.S
*/
extern uint32_t boot_mode;
#define SH4_BOOT_MODE_FLASH 0
#define SH4_BOOT_MODE_IPL 1
/*
* Device Driver Table Entries
*/
/*
* We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console
*/
#undef CONSOLE_DRIVER_TABLE_ENTRY
#define CONSOLE_DRIVER_TABLE_ENTRY \
{ console_initialize, console_open, console_close, \
console_read, console_write, console_control }
/*
* BSP methods that cross file boundaries.
*/
void bsp_hw_init(void);
void early_hw_init(void);
void bsp_cache_on(void);
#ifdef __cplusplus
}
#endif
#endif

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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect on-chip registers for sh7045 processor, based on
* "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
* contained no copyright notice:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
* August, 1999
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef __IOSH7750_H
#define __IOSH7750_H
#include <rtems/score/sh7750_regs.h>
#endif

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/* ipl.h
*
* IPL console driver
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* Based on work:
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __IPL_DRIVER_h
#define __IPL_DRIVER_h
#ifdef __cplusplus
extern "C" {
#endif
#define IPL_DRIVER_TABLE_ENTRY \
{ ipl_console_initialize, ipl_console_open, ipl_console_close, \
ipl_console_read, ipl_console_write, ipl_console_control }
#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL
rtems_device_driver ipl_console_initialize(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
rtems_device_driver ipl_console_open(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
rtems_device_driver ipl_console_close(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
rtems_device_driver ipl_console_read(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
rtems_device_driver ipl_console_write(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
rtems_device_driver ipl_console_control(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/*
* This include file contains information pertaining to the Hitachi
* SH7750 processor.
*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* Based on work of:
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect isp entries for sh7045 processor:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/types.h>
/* dummy ISP */
extern void _dummy_isp( void );
extern void __ISR_Handler( uint32_t vector );
/* This variable contains VBR value used to pass control when debug, error
* or virtual memory exceptions occured.
*/
extern void *_VBR_Saved;
#ifdef __cplusplus
}
#endif
#endif

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/*
* Bits on SH-4 registers.
* See SH-4 Programming manual for more details.
*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Alexandra Kossovsky <sasha@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __SH4_REGS_H__
#define __SH4_REGS_H__
/* SR -- Status Register */
#define SH4_SR_MD 0x40000000 /* Priveleged mode */
#define SH4_SR_RB 0x20000000 /* General register bank specifier */
#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */
#define SH4_SR_FD 0x00008000 /* FPU disable bit */
#define SH4_SR_M 0x00000200 /* For signed division:
divisor (module) is negative */
#define SH4_SR_Q 0x00000100 /* For signed division:
dividend (and quotient) is negative */
#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */
#define SH4_SR_IMASK_S 4
#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction:
if set, data in MACH/L register
is restricted to 48/32 bits
for MAC.W/L instructions */
#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */
#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */
/* FPSCR -- FPU Starus/Control Register */
#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */
#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */
#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point
operations flag */
/* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */
#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */
#define SH4_FPSCR_CAUSE_S 12
#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */
#define SH4_FPSCR_ENABLE_s 7
#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */
#define SH4_FPSCR_FLAG_S 2
#define SH4_FPSCR_RM 0x00000001 /* Rounding mode:
1/0 -- round to zero/nearest */
#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */
#endif

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/*
* SDRAM Mode Register
* Based on Fujitsu MB81F643242B data sheet.
*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __SDRAM_H__
#define __SDRAM_H__
/* SDRAM Mode Register */
#define SDRAM_MODE_BL 0x0007 /* Burst Length: */
#define SDRAM_MODE_BL_1 0x0000 /* 0 */
#define SDRAM_MODE_BL_2 0x0001 /* 2 */
#define SDRAM_MODE_BL_4 0x0002 /* 4 */
#define SDRAM_MODE_BL_8 0x0003 /* 8 */
#define SDRAM_MODE_BL_16 0x0004 /* 16 */
#define SDRAM_MODE_BL_32 0x0005 /* 32 */
#define SDRAM_MODE_BL_64 0x0006 /* 64 */
#define SDRAM_MODE_BL_FULL 0x0007 /* Full column */
#define SDRAM_MODE_BT 0x0008 /* Burst Type: */
#define SDRAM_MODE_BT_SEQ 0x0000 /* Sequential */
#define SDRAM_MODE_BT_ILV 0x0008 /* Interleave */
#define SDRAM_MODE_CL 0x0070 /* CAS Latency: */
#define SDRAM_MODE_CL_1 0x0010 /* 1 */
#define SDRAM_MODE_CL_2 0x0020 /* 2 */
#define SDRAM_MODE_CL_3 0x0030 /* 3 */
#define SDRAM_MODE_OPC 0x0200 /* Opcode: */
#define SDRAM_MODE_OPC_BRBW 0x0000 /* Burst read & Burst write */
#define SDRAM_MODE_OPC_BRSW 0x0200 /* Burst read & Single write */
#endif

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/*
* Generic UART Serial driver for SH-4 processors definitions
*
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed.
* Author: Alexandra Kossovsky <sasha@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __SH4UART_H__
#define __SH4UART_H__
#include <rtems/score/sh7750_regs.h>
/*
* Define this to work from gdb stub
*/
/* FIXME: This is BSP-specific */
#define SH4_WITH_IPL
#define SH4_SCI 1 /* Serial Communication Interface - SCI */
#define SH4_SCIF 2 /* Serial Communication Interface with FIFO - SCIF */
#define TRANSMIT_TRIGGER_VALUE(ttrg) ((ttrg) == SH7750_SCFCR2_RTRG_1 ? 1 : \
(ttrg) == SH7750_SCFCR2_RTRG_4 ? 4 : \
(ttrg) == SH7750_SCFCR2_RTRG_8 ? 8 : 14)
/*
* Macros to call UART registers
*/
#define SCRDR(n) (*(volatile uint8_t*)SH7750_SCRDR(n))
#define SCRDR1 SCRDR(1)
#define SCRDR2 SCRDR(2)
#define SCTDR(n) (*(volatile uint8_t*)SH7750_SCTDR(n))
#define SCTDR1 SCTDR(1)
#define SCTDR2 SCTDR(2)
#define SCSMR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSMR1 : \
*(volatile uint16_t*)SH7750_SCSMR2)
#define SCSMR1 SCSMR(1)
#define SCSMR2 SCSMR(2)
#define SCSCR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSCR1 : \
*(volatile uint16_t*)SH7750_SCSCR2)
#define SCSCR1 SCSCR(1)
#define SCSCR2 SCSCR(2)
#define SCSSR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSSR1 : \
*(volatile uint16_t*)SH7750_SCSSR2)
#define SCSSR1 SCSSR(1)
#define SCSSR2 SCSSR(2)
#define SCSPTR1 (*(volatile uint8_t*)SH7750_SCSPTR1)
#define SCSPTR2 (*(volatile uint16_t*)SH7750_SCSPTR2)
#define SCBRR(n) (*(volatile uint8_t*)SH7750_SCBRR(n))
#define SCBRR1 SCBRR(1)
#define SCBRR2 SCBRR(2)
#define SCFCR2 (*(volatile uint16_t*)SH7750_SCFCR2)
#define SCFDR2 (*(volatile uint16_t*)SH7750_SCFDR2)
#define SCLSR2 (*(volatile uint16_t*)SH7750_SCLSR2)
#define IPRB (*(volatile uint16_t*)SH7750_IPRB)
#define IPRC (*(volatile uint16_t*)SH7750_IPRC)
/*
* The following structure is a descriptor of single UART channel.
* It contains the initialization information about channel and
* current operating values
*/
typedef struct sh4uart {
uint8_t chn; /* UART channel number */
uint8_t int_driven; /* UART interrupt vector number, or
0 if polled I/O */
void *tty; /* termios channel descriptor */
volatile const char *tx_buf; /* Transmit buffer from termios */
volatile uint32_t tx_buf_len; /* Transmit buffer length */
volatile uint32_t tx_ptr; /* Index of next char to transmit*/
rtems_isr_entry old_handler_transmit; /* Saved interrupt handlers */
rtems_isr_entry old_handler_receive;
tcflag_t c_iflag; /* termios input mode flags */
bool parerr_mark_flag; /* Parity error processing state */
} sh4uart;
/*
* Functions from sh4uart.c
*/
/* sh4uart_init --
* This function verifies the input parameters and perform initialization
* of the Motorola Coldfire on-chip UART descriptor structure.
*
*/
rtems_status_code
sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven);
/* sh4uart_reset --
* This function perform the hardware initialization of Motorola
* Coldfire processor on-chip UART controller using parameters
* filled by the sh4uart_init function.
*/
rtems_status_code
sh4uart_reset(sh4uart *uart);
/* sh4uart_disable --
* This function disable the operations on Motorola Coldfire UART
* controller
*/
rtems_status_code
sh4uart_disable(sh4uart *uart, int disable_port);
/* sh4uart_set_attributes --
* This function parse the termios attributes structure and perform
* the appropriate settings in hardware.
*/
rtems_status_code
sh4uart_set_attributes(sh4uart *mcf, const struct termios *t);
/* sh4uart_poll_read --
* This function tried to read character from MCF UART and perform
* error handling.
*/
int
sh4uart_poll_read(sh4uart *uart);
#ifdef SH4_WITH_IPL
/* ipl_console_poll_read --
* This function tried to read character from MCF UART over SH-IPL.
*/
int
ipl_console_poll_read(int minor);
/* sh4uart_interrupt_write --
* This function initiate transmitting of the buffer in interrupt mode.
*/
rtems_status_code
sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len);
/* sh4uart_poll_write --
* This function transmit buffer byte-by-byte in polling mode.
*/
int
sh4uart_poll_write(sh4uart *uart, const char *buf, int len);
/* ipl_console_poll_write --
* This function transmit buffer byte-by-byte in polling mode over SH-IPL.
*/
int
ipl_console_poll_write(int minor, const char *buf, int len);
/*
* ipl_finish --
* Says gdb that program finished to get out from it.
*/
extern void ipl_finish(void);
#endif
/* sh4uart_stop_remote_tx --
* This function stop data flow from remote device.
*/
rtems_status_code
sh4uart_stop_remote_tx(sh4uart *uart);
/* sh4uart_start_remote_tx --
* This function resume data flow from remote device.
*/
rtems_status_code
sh4uart_start_remote_tx(sh4uart *uart);
/* Descriptor structures for two on-chip UART channels */
extern sh4uart sh4_uarts[2];
#endif

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/*
* @file
* @ingroup sh_gensh4
* @brief Implementations for interrupt mechanisms for Time Test 27
*/
/*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Stuff for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 1
#ifndef SH7750_EVT_WDT_ITI
# error "..."
#endif
#define Install_tm27_vector( handler ) \
{ \
rtems_isr_entry old_handler; \
rtems_status_code status; \
status = rtems_interrupt_catch( (handler), \
SH7750_EVT_TO_NUM(SH7750_EVT_WDT_ITI), &old_handler); \
if (status != RTEMS_SUCCESSFUL) \
printf("Status of rtems_interrupt_catch = %d", status); \
}
#define Cause_tm27_intr() \
{ \
*(volatile uint16_t*)SH7750_IPRB |= 0xf000; \
*(volatile uint16_t*)SH7750_WTCSR = SH7750_WTCSR_KEY; \
*(volatile uint16_t*)SH7750_WTCNT = SH7750_WTCNT_KEY | 0xfe; \
*(volatile uint16_t*)SH7750_WTCSR = \
SH7750_WTCSR_KEY | SH7750_WTCSR_TME; \
}
#define Clear_tm27_intr() \
{ \
*(volatile uint16_t*)SH7750_WTCSR = SH7750_WTCSR_KEY; \
}
#define Lower_tm27_intr() \
{ \
sh_set_interrupt_level((SH7750_IPRB & 0xf000) << SH4_SR_IMASK_S); \
}
#endif

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## This file was generated by "./boostrap -H".
include_HEADERS =
include_HEADERS += ../../../../../../bsps/sh/shsim/include/bsp.h
include_HEADERS += include/bspopts.h
include_HEADERS += ../../../../../../bsps/sh/shsim/include/tm27.h
include_bspdir = $(includedir)/bsp
include_bsp_HEADERS =
include_bsp_HEADERS += ../../../../../../bsps/sh/shsim/include/bsp/syscall.h

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/*
* SH-gdb simulator BSP
*
* This include file contains all board IO definitions.
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* COPYRIGHT (c) 2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_SH_SHSIM_BSP_H
#define LIBBSP_SH_SHSIM_BSP_H
#ifndef ASM
#include <rtems.h>
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
/*
* FIXME: One of these would be enough.
*/
#include <rtems/devnull.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Constants */
void *clock_driver_sim_idle_body(uintptr_t);
#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body
/*
* Defined in the linker script 'linkcmds'
*/
extern void *CPU_Interrupt_stack_low;
extern void *CPU_Interrupt_stack_high;
/*
* BSP methods that cross file boundaries.
*/
int _sys_exit (int n);
void bsp_hw_init(void);
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif

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#define SYS_exit 1
#define SYS_fork 2
#define SYS_read 3
#define SYS_write 4
#define SYS_open 5
#define SYS_close 6
#define SYS_wait4 7
#define SYS_creat 8
#define SYS_link 9
#define SYS_unlink 10
#define SYS_execv 11
#define SYS_chdir 12
#define SYS_mknod 14
#define SYS_chmod 15
#define SYS_chown 16
#define SYS_lseek 19
#define SYS_getpid 20
#define SYS_isatty 21
#define SYS_fstat 22
#define SYS_time 23
#define SYS_ARG 24
#define SYS_stat 38
#define SYS_pipe 42
#define SYS_execve 59
#define SYS_utime 201 /* not really a system call */
#define SYS_wait 202 /* nor is this */
int __trap34(int, int, void*, int );

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#include <rtems/tm27-default.h>