forked from Imagelibrary/rtems
bsp/altera-cyclone-v: Move SMP support
This commit is contained in:
Sebastian Huber
@@ -149,7 +149,11 @@ libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c
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# Startup
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libbsp_a_SOURCES += startup/bspreset.c
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libbsp_a_SOURCES += startup/bspstart.c
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libbsp_a_SOURCES += startup/bspstarthooks.c
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libbsp_a_SOURCES += startup/nocache-heap.c
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if HAS_SMP
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libbsp_a_SOURCES += startup/bspsmp.c
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endif
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# IRQ
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libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c
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@@ -181,13 +185,6 @@ libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
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libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h
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libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310
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# Start hooks
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libbsp_a_SOURCES += startup/bspstarthooks.c
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if HAS_SMP
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libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
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endif
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###############################################################################
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# Special Rules #
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###############################################################################
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89
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c
Normal file
89
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c
Normal file
@@ -0,0 +1,89 @@
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/*
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* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <assert.h>
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#include <rtems/score/smpimpl.h>
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#include <libcpu/arm-cp15.h>
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#include <bsp/irq.h>
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#include <bsp/linker-symbols.h>
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#include <bsp/start.h>
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#include <socal/alt_rstmgr.h>
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#include <socal/alt_sysmgr.h>
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#include <socal/hps.h>
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#include <socal/socal.h>
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static void bsp_inter_processor_interrupt(void *arg)
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{
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_SMP_Inter_processor_interrupt_handler();
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}
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uint32_t _CPU_SMP_Initialize(void)
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{
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uint32_t hardware_count = arm_gic_irq_processor_count();
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uint32_t linker_count = (uint32_t) bsp_processor_count;
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return hardware_count <= linker_count ? hardware_count : linker_count;
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}
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bool _CPU_SMP_Start_processor(uint32_t cpu_index)
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{
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bool started;
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if (cpu_index == 1) {
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alt_write_word(
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ALT_SYSMGR_ROMCODE_ADDR + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST,
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ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET((uint32_t) _start)
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);
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alt_clrbits_word(
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ALT_RSTMGR_MPUMODRST_ADDR,
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ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK
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);
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started = true;
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} else {
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started = false;
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}
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return started;
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}
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void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
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{
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if (cpu_count > 0) {
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rtems_status_code sc;
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sc = rtems_interrupt_handler_install(
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ARM_GIC_IRQ_SGI_0,
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"IPI",
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RTEMS_INTERRUPT_UNIQUE,
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bsp_inter_processor_interrupt,
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NULL
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);
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assert(sc == RTEMS_SUCCESSFUL);
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}
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}
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void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
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{
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arm_gic_irq_generate_software_irq(
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ARM_GIC_IRQ_SGI_0,
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ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
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(uint8_t) (1U << target_processor_index)
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);
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}
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
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* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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@@ -12,58 +12,12 @@
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <bsp.h>
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#include <bsp/bootcard.h>
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#include <bsp/irq-generic.h>
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#include <bsp/linker-symbols.h>
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#include <bsp/start.h>
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#include <bsp/nocache-heap.h>
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#include <rtems/config.h>
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#include "socal/alt_rstmgr.h"
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#include "socal/alt_sysmgr.h"
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#include "socal/hps.h"
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#ifndef MIN
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#define MIN( a, b ) ( ( a ) < ( b ) ? ( a ) : ( b ) )
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#endif
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#define BSPSTART_MAX_CORES_PER_CONTROLLER 2
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static void bsp_start_secondary_cores( void )
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{
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#ifdef RTEMS_SMP
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volatile uint32_t *mpumodrst = ALT_RSTMGR_MPUMODRST_ADDR;
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uint32_t *cpu1_start_addr = (
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ALT_SYSMGR_ROMCODE_ADDR + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST );
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const uint32_t CORES = MIN(
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(uintptr_t) bsp_processor_count,
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rtems_configuration_get_maximum_processors() );
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unsigned int index;
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/* Memory would get overwritten if a too small processor count
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* would be specified */
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assert(
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(uintptr_t) bsp_processor_count >= BSPSTART_MAX_CORES_PER_CONTROLLER );
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if ( (uintptr_t) bsp_processor_count >= BSPSTART_MAX_CORES_PER_CONTROLLER ) {
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for ( index = 1; index < CORES; ++index ) {
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/* set the start address from where the core will execute */
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(*cpu1_start_addr) = ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(
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(uintptr_t) _start );
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/* Make the core finish it's reset */
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(*mpumodrst) &= ~ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK;
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}
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}
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#endif /* #ifdef RTEMS_SMP */
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}
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void bsp_start( void )
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{
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bsp_interrupt_initialize();
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altera_cyclone_v_nocache_init_heap();
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bsp_start_secondary_cores();
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}
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