forked from Imagelibrary/rtems
added SSP support files, fixed some typos
This commit is contained in:
Thomas Doerfler
@@ -1,3 +1,17 @@
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2008-09-30 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* ssp/ssp.c, misc/dma.c, include/dma.h, include/ssp.h: New files.
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* Makefile.am, preinstall.am, README: Update.
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* include/irq.h: Fixed typos.
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* include/lpc24xx.h: New defines and types. Converted to UNIX line
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endings.
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* misc/system-clocks.c, startup/bspstart.c: Update for utility.h
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changes.
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2008-09-30 Ralf Corsépius <ralf.corsepius@rtems.org>
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* clock/clock-config.c: include "../../../shared/clockdrv_shell.h".
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@@ -2,7 +2,7 @@
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#
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# @file
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#
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# @brief Makefile of LibBSP for the LPC247X boards.
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# @brief Makefile of LibBSP for the LPC24XX boards.
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#
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# $Id$
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@@ -22,8 +22,8 @@ dist_project_lib_DATA = bsp_specs
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include_HEADERS = include/bsp.h
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nodist_include_HEADERS = include/bspopts.h
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nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
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DISTCLEANFILES = include/bspopts.h
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include_bsp_HEADERS = ../../shared/include/utility.h \
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../../shared/include/irq-generic.h \
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@@ -33,25 +33,32 @@ include_bsp_HEADERS = ../../shared/include/utility.h \
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include/irq-config.h \
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include/irq.h \
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include/lpc24xx.h \
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include/system-clocks.h
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include/system-clocks.h \
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include/ssp.h \
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include/dma.h
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###############################################################################
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# Data #
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###############################################################################
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noinst_LIBRARIES = libbspstart.a
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libbspstart_a_SOURCES = ../shared/start/start.S
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project_lib_DATA = start.$(OBJEXT)
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dist_project_lib_DATA += ../shared/startup/linkcmds.base startup/linkcmds
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dist_project_lib_DATA += ../shared/startup/linkcmds.base \
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startup/linkcmds
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###############################################################################
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# LibBSP #
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###############################################################################
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noinst_LIBRARIES += libbsp.a
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libbsp_a_SOURCES =
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# shared
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# Shared
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libbsp_a_SOURCES += ../../shared/bootcard.c \
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../../shared/bspclean.c \
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../../shared/bspreset.c \
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@@ -64,35 +71,39 @@ libbsp_a_SOURCES += ../../shared/bootcard.c \
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../../shared/sbrk.c \
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../shared/abort/simple_abort.c
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# startup
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# Startup
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libbsp_a_SOURCES += startup/bspstart.c
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# irq
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# IRQ
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libbsp_a_SOURCES += ../../shared/src/irq-generic.c \
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../../shared/src/irq-legacy.c \
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../shared/irq/irq_asm.S \
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irq/irq.c
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# console
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# Console
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libbsp_a_SOURCES += ../../shared/console.c \
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console/console-config.c
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# clock
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libbsp_a_SOURCES += clock/clock-config.c ../../../shared/clockdrv_shell.h
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# Clock
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libbsp_a_SOURCES += clock/clock-config.c \
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../../../shared/clockdrv_shell.h
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# rtc
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# RTC
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libbsp_a_SOURCES += ../../shared/tod.c \
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rtc/rtc-config.c
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# misc
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libbsp_a_SOURCES += misc/system-clocks.c
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# Misc
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libbsp_a_SOURCES += misc/system-clocks.c \
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misc/dma.c
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# SSP
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libbsp_a_SOURCES += ssp/ssp.c
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###############################################################################
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# Special Rules #
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###############################################################################
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start.$(OBJEXT): ../shared/start/start.S
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$(CPPASCOMPILE) -o $@ -c $<
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DISTCLEANFILES = include/bspopts.h
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include $(srcdir)/preinstall.am
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include $(top_srcdir)/../../../../automake/local.am
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@@ -10,3 +10,4 @@ Drivers:
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o Console
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o Clock
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o RTC
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o SSP (SPI mode): This driver is in active development. Use with care.
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42
c/src/lib/libbsp/arm/lpc24xx/include/dma.h
Normal file
42
c/src/lib/libbsp/arm/lpc24xx/include/dma.h
Normal file
@@ -0,0 +1,42 @@
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/**
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* @file
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*
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* @ingroup lpc24xx
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*
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* @brief DMA support.
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*/
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/*
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* Copyright (c) 2008
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* Embedded Brains GmbH
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* Obere Lagerstr. 30
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* D-82178 Puchheim
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* Germany
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* rtems@embedded-brains.de
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*
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* The license and distribution terms for this file may be found in the file
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* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_LPC24XX_DMA_H
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#define LIBBSP_ARM_LPC24XX_DMA_H
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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void lpc24xx_dma_initialize( void);
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bool lpc24xx_dma_channel_obtain( unsigned channel);
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void lpc24xx_dma_channel_release( unsigned channel);
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void lpc24xx_dma_channel_disable( unsigned channel, bool force);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_LPC24XX_DMA_H */
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@@ -35,16 +35,16 @@
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#define LPC24XX_IRQ_WDT 0
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#define LPC24XX_IRQ_SOFTWARE 1
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#define LPC24XX_IRQ_ARM CORE_0 2
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#define LPC24XX_IRQ_ARM CORE_1 3
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#define LPC24XX_IRQ_ARM_CORE_0 2
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#define LPC24XX_IRQ_ARM_CORE_1 3
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#define LPC24XX_IRQ_TIMER_0 4
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#define LPC24XX_IRQ_TIMER_1 5
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#define LPC24XX_IRQ_UART_0 6
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#define LPC24XX_IRQ_UART_1 7
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#define LPC24XX_IRQ_PWM 8
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#define LPC24XX_IRQ_I2C_0 9
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#define LPC24XX_IRQ_SPI_SSP0 10
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#define LPC24XX_IRQ_SSP1 11
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#define LPC24XX_IRQ_SPI_SSP_0 10
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#define LPC24XX_IRQ_SSP_1 11
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#define LPC24XX_IRQ_PLL 12
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#define LPC24XX_IRQ_RTC 13
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#define LPC24XX_IRQ_EINT_0 14
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@@ -61,8 +61,8 @@
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#define LPC24XX_IRQ_DMA 25
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#define LPC24XX_IRQ_TIMER_2 26
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#define LPC24XX_IRQ_TIMER_3 27
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#define LPC24XX_IRQ_UART2 28
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#define LPC24XX_IRQ_UART3 29
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#define LPC24XX_IRQ_UART_2 28
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#define LPC24XX_IRQ_UART_3 29
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#define LPC24XX_IRQ_I2C_2 30
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#define LPC24XX_IRQ_I2S 31
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@@ -76,8 +76,6 @@
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*/
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#define BSP_INTERRUPT_VECTOR_MAX LPC24XX_IRQ_I2S
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#define BSP_FEATURE_IRQ_EXTENSION
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/** @} */
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#endif /* ASM */
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@@ -944,6 +944,7 @@ Reset, and Code Security/Debugging */
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#define GPDMA_SYNC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x034))
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/* DMA channel 0 registers */
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#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100)
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#define GPDMA_CH0_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100))
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#define GPDMA_CH0_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104))
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#define GPDMA_CH0_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x108))
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@@ -951,6 +952,7 @@ Reset, and Code Security/Debugging */
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#define GPDMA_CH0_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x110))
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/* DMA channel 1 registers */
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#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120)
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#define GPDMA_CH1_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120))
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#define GPDMA_CH1_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124))
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#define GPDMA_CH1_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x128))
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@@ -1121,15 +1123,71 @@ Reset, and Code Security/Debugging */
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/* Register Fields */
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/* PCONP */
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#define PCONP_PCTIM0 0x00000002U
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#define PCONP_PCTIM1 0x00000004U
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#define PCONP_PCUART0 0x00000008U
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#define PCONP_PCUART1 0x00000010U
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#define PCONP_PCPWM0 0x00000020U
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#define PCONP_PCPWM1 0x00000040U
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#define PCONP_PCI2C0 0x00000080U
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#define PCONP_PCSPI 0x00000100U
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#define PCONP_PCRTC 0x00000200U
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#define PCONP_PCSSP1 0x00000400U
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#define PCONP_PCEMC 0x00000800U
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#define PCONP_PCAD 0x00001000U
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#define PCONP_PCCAN1 0x00002000U
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#define PCONP_PCCAN2 0x00004000U
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#define PCONP_PCI2C1 0x00080000U
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#define PCONP_PCLCD 0x00100000U
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#define PCONP_PCSSP0 0x00200000U
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#define PCONP_PCTIM2 0x00400000U
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#define PCONP_PCTIM3 0x00800000U
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#define PCONP_PCUART2 0x01000000U
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#define PCONP_PCUART3 0x02000000U
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#define PCONP_PCI2C2 0x04000000U
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#define PCONP_PCI2S 0x08000000U
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#define PCONP_PCSDC 0x10000000U
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#define PCONP_PCGPDMA 0x20000000U
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#define PCONP_PCENET 0x40000000U
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#define PCONP_PCUSB 0x80000000U
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/* CLKSRCSEL */
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#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
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#define GET_CLKSRCSEL_CLKSRC( reg) \
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GET_REG_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
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GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
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#define SET_CLKSRCSEL_CLKSRC( reg, val) \
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SET_REG_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
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SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
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/* PLLCON */
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@@ -1142,36 +1200,36 @@ Reset, and Code Security/Debugging */
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#define PLLCFG_MSEL_MASK 0x00007fffU
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#define GET_PLLCFG_MSEL( reg) \
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GET_REG_FIELD( reg, PLLCFG_MSEL_MASK, 0)
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GET_FIELD( reg, PLLCFG_MSEL_MASK, 0)
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#define SET_PLLCFG_MSEL( reg, val) \
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SET_REG_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
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SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
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#define PLLCFG_NSEL_MASK 0x00ff0000U
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#define GET_PLLCFG_NSEL( reg) \
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GET_REG_FIELD( reg, PLLCFG_NSEL_MASK, 16)
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GET_FIELD( reg, PLLCFG_NSEL_MASK, 16)
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#define SET_PLLCFG_NSEL( reg, val) \
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SET_REG_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
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SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
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/* PLLSTAT */
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#define PLLSTAT_MSEL_MASK 0x00007fffU
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#define GET_PLLSTAT_MSEL( reg) \
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GET_REG_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
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GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
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#define SET_PLLSTAT_MSEL( reg, val) \
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SET_REG_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
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SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
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#define PLLSTAT_NSEL_MASK 0x00ff0000U
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#define GET_PLLSTAT_NSEL( reg) \
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GET_REG_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
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GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
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#define SET_PLLSTAT_NSEL( reg, val) \
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SET_REG_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
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SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
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#define PLLSTAT_PLLE 0x01000000U
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@@ -1184,20 +1242,20 @@ Reset, and Code Security/Debugging */
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#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
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#define GET_CCLKCFG_CCLKSEL( reg) \
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GET_REG_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
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GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
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#define SET_CCLKCFG_CCLKSEL( reg, val) \
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SET_REG_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
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SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
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/* MEMMAP */
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#define MEMMAP_MAP_MASK 0x00000003U
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#define GET_MEMMAP_MAP( reg) \
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GET_REG_FIELD( reg, MEMMAP_MAP_MASK, 0)
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GET_FIELD( reg, MEMMAP_MAP_MASK, 0)
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#define SET_MEMMAP_MAP( reg, val) \
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SET_REG_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
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SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
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/* TIR */
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@@ -1254,228 +1312,228 @@ Reset, and Code Security/Debugging */
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#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
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#define GET_PCLKSEL0_PCLK_WDT( reg) \
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GET_REG_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
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GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
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#define SET_PCLKSEL0_PCLK_WDT( reg, val) \
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SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
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SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
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#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
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#define GET_PCLKSEL0_PCLK_TIMER0( reg) \
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GET_REG_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
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GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
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#define SET_PCLKSEL0_PCLK_TIMER0( reg, val) \
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SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
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SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
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#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
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#define GET_PCLKSEL0_PCLK_TIMER1( reg) \
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GET_REG_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
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GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
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#define SET_PCLKSEL0_PCLK_TIMER1( reg, val) \
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SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
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SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
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#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
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#define GET_PCLKSEL0_PCLK_UART0( reg) \
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GET_REG_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
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GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
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#define SET_PCLKSEL0_PCLK_UART0( reg, val) \
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SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
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SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
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#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
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#define GET_PCLKSEL0_PCLK_UART1( reg) \
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GET_REG_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
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GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
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#define SET_PCLKSEL0_PCLK_UART1( reg, val) \
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SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
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SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
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||||
#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
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#define GET_PCLKSEL0_PCLK_PWM0( reg) \
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GET_REG_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
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GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
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||||
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||||
#define SET_PCLKSEL0_PCLK_PWM0( reg, val) \
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SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
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SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
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||||
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||||
#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
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||||
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||||
#define GET_PCLKSEL0_PCLK_PWM1( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_PWM1( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
|
||||
|
||||
#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
|
||||
|
||||
#define GET_PCLKSEL0_PCLK_I2C0( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_I2C0( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
|
||||
|
||||
#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
|
||||
|
||||
#define GET_PCLKSEL0_PCLK_SPI( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_SPI( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
|
||||
|
||||
#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
|
||||
|
||||
#define GET_PCLKSEL0_PCLK_RTC( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_RTC( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
|
||||
|
||||
#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
|
||||
|
||||
#define GET_PCLKSEL0_PCLK_SSP1( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_SSP1( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
|
||||
|
||||
#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
|
||||
|
||||
#define GET_PCLKSEL0_PCLK_DAC( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_DAC( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
|
||||
|
||||
#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
|
||||
|
||||
#define GET_PCLKSEL0_PCLK_ADC( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_ADC( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
|
||||
|
||||
#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
|
||||
|
||||
#define GET_PCLKSEL0_PCLK_CAN1( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_CAN1( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
|
||||
|
||||
#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
|
||||
|
||||
#define GET_PCLKSEL0_PCLK_CAN2( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
|
||||
GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
|
||||
|
||||
#define SET_PCLKSEL0_PCLK_CAN2( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
|
||||
SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
|
||||
|
||||
/* PCLKSEL1 */
|
||||
|
||||
#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_BAT_RAM( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
|
||||
|
||||
#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_GPIO( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_GPIO( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
|
||||
|
||||
#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_PCB( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_PCB( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
|
||||
|
||||
#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_I2C1( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_I2C1( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
|
||||
|
||||
#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_SSP0( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_SSP0( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
|
||||
|
||||
#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_TIMER2( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_TIMER2( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
|
||||
|
||||
#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_TIMER3( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_TIMER3( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
|
||||
|
||||
#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_UART2( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_UART2( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
|
||||
|
||||
#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_UART3( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_UART3( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
|
||||
|
||||
#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_I2C2( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_I2C2( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
|
||||
|
||||
#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_I2S( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_I2S( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
|
||||
|
||||
#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_MCI( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_MCI( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
|
||||
|
||||
#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
|
||||
|
||||
#define GET_PCLKSEL1_PCLK_SYSCON( reg) \
|
||||
GET_REG_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
|
||||
GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
|
||||
|
||||
#define SET_PCLKSEL1_PCLK_SYSCON( reg, val) \
|
||||
SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
|
||||
SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
|
||||
|
||||
/* RTC_ILR */
|
||||
|
||||
@@ -1493,4 +1551,476 @@ Reset, and Code Security/Debugging */
|
||||
|
||||
#define RTC_CCR_CLKSRC 0x00000010U
|
||||
|
||||
/* SSP */
|
||||
|
||||
typedef struct {
|
||||
uint32_t cr0;
|
||||
uint32_t cr1;
|
||||
uint32_t dr;
|
||||
uint32_t sr;
|
||||
uint32_t cpsr;
|
||||
uint32_t imsc;
|
||||
uint32_t ris;
|
||||
uint32_t mis;
|
||||
uint32_t icr;
|
||||
uint32_t dmacr;
|
||||
} lpc24xx_ssp;
|
||||
|
||||
/* SSP_CR0 */
|
||||
|
||||
#define SSP_CR0_DSS_MASK 0x0000000fU
|
||||
|
||||
#define GET_SSP_CR0_DSS( reg) \
|
||||
GET_FIELD( reg, SSP_CR0_DSS_MASK, 0)
|
||||
|
||||
#define SET_SSP_CR0_DSS( reg, val) \
|
||||
SET_FIELD( reg, val, SSP_CR0_DSS_MASK, 0)
|
||||
|
||||
#define SSP_CR0_FRF_MASK 0x00000030U
|
||||
|
||||
#define GET_SSP_CR0_FRF( reg) \
|
||||
GET_FIELD( reg, SSP_CR0_FRF_MASK, 4)
|
||||
|
||||
#define SET_SSP_CR0_FRF( reg, val) \
|
||||
SET_FIELD( reg, val, SSP_CR0_FRF_MASK, 4)
|
||||
|
||||
#define SSP_CR0_CPOL 0x00000040U
|
||||
|
||||
#define SSP_CR0_CPHA 0x00000080U
|
||||
|
||||
#define SSP_CR0_SCR_MASK 0x0000ff00U
|
||||
|
||||
#define GET_SSP_CR0_SCR( reg) \
|
||||
GET_FIELD( reg, SSP_CR0_SCR_MASK, 8)
|
||||
|
||||
#define SET_SSP_CR0_SCR( reg, val) \
|
||||
SET_FIELD( reg, val, SSP_CR0_SCR_MASK, 8)
|
||||
|
||||
/* SSP_CR1 */
|
||||
|
||||
#define SSP_CR1_LBM 0x00000001U
|
||||
|
||||
#define SSP_CR1_SSE 0x00000002U
|
||||
|
||||
#define SSP_CR1_MS 0x00000004U
|
||||
|
||||
#define SSP_CR1_SOD 0x00000008U
|
||||
|
||||
/* SSP_SR */
|
||||
|
||||
#define SSP_SR_TFE 0x00000001U
|
||||
|
||||
#define SSP_SR_TNF 0x00000002U
|
||||
|
||||
#define SSP_SR_RNE 0x00000004U
|
||||
|
||||
#define SSP_SR_RFF 0x00000008U
|
||||
|
||||
#define SSP_SR_BSY 0x00000010U
|
||||
|
||||
/* SSP_IMSC */
|
||||
|
||||
#define SSP_IMSC_RORIM 0x00000001U
|
||||
|
||||
#define SSP_IMSC_RTIM 0x00000002U
|
||||
|
||||
#define SSP_IMSC_RXIM 0x00000004U
|
||||
|
||||
#define SSP_IMSC_TXIM 0x00000008U
|
||||
|
||||
/* SSP_RIS */
|
||||
|
||||
#define SSP_RIS_RORRIS 0x00000001U
|
||||
|
||||
#define SSP_RIS_RTRIS 0x00000002U
|
||||
|
||||
#define SSP_RIS_RXRIS 0x00000004U
|
||||
|
||||
#define SSP_RIS_TXRIS 0x00000008U
|
||||
|
||||
/* SSP_MIS */
|
||||
|
||||
#define SSP_MIS_RORRIS 0x00000001U
|
||||
|
||||
#define SSP_MIS_RTRIS 0x00000002U
|
||||
|
||||
#define SSP_MIS_RXRIS 0x00000004U
|
||||
|
||||
#define SSP_MIS_TXRIS 0x00000008U
|
||||
|
||||
/* SSP_ICR */
|
||||
|
||||
#define SSP_ICR_RORRIS 0x00000001U
|
||||
|
||||
#define SSP_ICR_RTRIS 0x00000002U
|
||||
|
||||
#define SSP_ICR_RXRIS 0x00000004U
|
||||
|
||||
#define SSP_ICR_TXRIS 0x00000008U
|
||||
|
||||
/* SSP_DMACR */
|
||||
|
||||
#define SSP_DMACR_RXDMAE 0x00000001U
|
||||
|
||||
#define SSP_DMACR_TXDMAE 0x00000002U
|
||||
|
||||
/* GPDMA */
|
||||
|
||||
typedef struct {
|
||||
uint32_t src;
|
||||
uint32_t dest;
|
||||
uint32_t lli;
|
||||
uint32_t ctrl;
|
||||
uint32_t cfg;
|
||||
} lpc24xx_dma_channel;
|
||||
|
||||
#define GPDMA_CH_NUMBER 2
|
||||
|
||||
#define GPDMA_STATUS_CH_0 0x00000001U
|
||||
|
||||
#define GPDMA_STATUS_CH_1 0x00000002U
|
||||
|
||||
#define GPDMA_CH_BASE_ADDR( i) \
|
||||
((volatile lpc24xx_dma_channel *) \
|
||||
((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
|
||||
|
||||
/* GPDMA_CONFIG */
|
||||
|
||||
#define GPDMA_CONFIG_EN 0x00000001U
|
||||
|
||||
#define GPDMA_CONFIG_MODE 0x00000002U
|
||||
|
||||
/* GPDMA_ENABLED_CHNS */
|
||||
|
||||
#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
|
||||
|
||||
#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
|
||||
|
||||
/* GPDMA_CH_CTRL */
|
||||
|
||||
#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
|
||||
|
||||
#define GET_GPDMA_CH_CTRL_TSZ( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
|
||||
|
||||
#define SET_GPDMA_CH_CTRL_TSZ( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
|
||||
|
||||
#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
|
||||
|
||||
#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
|
||||
|
||||
#define GET_GPDMA_CH_CTRL_SBSZ( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
|
||||
|
||||
#define SET_GPDMA_CH_CTRL_SBSZ( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
|
||||
|
||||
#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
|
||||
|
||||
#define GET_GPDMA_CH_CTRL_DBSZ( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
|
||||
|
||||
#define SET_GPDMA_CH_CTRL_DBSZ( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
|
||||
|
||||
#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
|
||||
|
||||
#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
|
||||
|
||||
#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
|
||||
|
||||
#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
|
||||
|
||||
#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
|
||||
|
||||
#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
|
||||
|
||||
#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
|
||||
|
||||
#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
|
||||
|
||||
#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
|
||||
|
||||
#define GET_GPDMA_CH_CTRL_SW( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18)
|
||||
|
||||
#define SET_GPDMA_CH_CTRL_SW( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
|
||||
|
||||
#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
|
||||
|
||||
#define GET_GPDMA_CH_CTRL_DW( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21)
|
||||
|
||||
#define SET_GPDMA_CH_CTRL_DW( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
|
||||
|
||||
#define GPDMA_CH_CTRL_W_8 0x00000000U
|
||||
|
||||
#define GPDMA_CH_CTRL_W_16 0x00000001U
|
||||
|
||||
#define GPDMA_CH_CTRL_W_32 0x00000002U
|
||||
|
||||
#define GPDMA_CH_CTRL_SI 0x04000000U
|
||||
|
||||
#define GPDMA_CH_CTRL_DI 0x08000000U
|
||||
|
||||
#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
|
||||
|
||||
#define GET_GPDMA_CH_CTRL_PROT( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28)
|
||||
|
||||
#define SET_GPDMA_CH_CTRL_PROT( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
|
||||
|
||||
#define GPDMA_CH_CTRL_ITC 0x80000000U
|
||||
|
||||
/* GPDMA_CH_CFG */
|
||||
|
||||
#define GPDMA_CH_CFG_EN 0x00000001U
|
||||
|
||||
#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
|
||||
|
||||
#define GET_GPDMA_CH_CFG_SRCPER( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
|
||||
|
||||
#define SET_GPDMA_CH_CFG_SRCPER( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
|
||||
|
||||
#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
|
||||
|
||||
#define GET_GPDMA_CH_CFG_DESTPER( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
|
||||
|
||||
#define SET_GPDMA_CH_CFG_DESTPER( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
|
||||
|
||||
#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
|
||||
|
||||
#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
|
||||
|
||||
#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
|
||||
|
||||
#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
|
||||
|
||||
#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
|
||||
|
||||
#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
|
||||
|
||||
#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
|
||||
|
||||
#define GET_GPDMA_CH_CFG_FLOW( reg) \
|
||||
GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11)
|
||||
|
||||
#define SET_GPDMA_CH_CFG_FLOW( reg, val) \
|
||||
SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
|
||||
|
||||
#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
|
||||
|
||||
#define GPDMA_CH_CFG_IE 0x00004000U
|
||||
|
||||
#define GPDMA_CH_CFG_ITC 0x00008000U
|
||||
|
||||
#define GPDMA_CH_CFG_LOCK 0x00010000U
|
||||
|
||||
#define GPDMA_CH_CFG_ACTIVE 0x00020000U
|
||||
|
||||
#define GPDMA_CH_CFG_HALT 0x00040000U
|
||||
|
||||
/* Ethernet (MAC) */
|
||||
|
||||
typedef struct {
|
||||
uint32_t start;
|
||||
uint32_t control;
|
||||
} lpc24xx_eth_transfer_descriptor;
|
||||
|
||||
typedef struct {
|
||||
uint32_t status;
|
||||
uint32_t hash_crc;
|
||||
} lpc24xx_eth_transfer_status;
|
||||
|
||||
#define ETH_TRANSFER_DESCRIPTOR_SIZE 8
|
||||
|
||||
#define ETH_TRANSFER_STATUS_SIZE 8
|
||||
|
||||
#define ETH_TRANSFER_CTRL_SIZE \
|
||||
(ETH_TRANSFER_DESCRIPTOR_SIZE + ETH_TRANSFER_STATUS_SIZE)
|
||||
|
||||
/* ETH_RX_CTRL */
|
||||
|
||||
#define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
|
||||
|
||||
#define GET_ETH_RX_CTRL_SIZE( reg) \
|
||||
GET_FIELD( reg, ETH_RX_CTRL_SIZE_MASK, 0)
|
||||
|
||||
#define SET_ETH_RX_CTRL_SIZE( reg, val) \
|
||||
SET_FIELD( reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
|
||||
|
||||
#define ETH_RX_CTRL_INTERRUPT 0x80000000U
|
||||
|
||||
/* ETH_RX_STAT */
|
||||
|
||||
#define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
|
||||
|
||||
#define GET_ETH_RX_STAT_RXSIZE( reg) \
|
||||
GET_FIELD( reg, ETH_RX_STAT_RXSIZE_MASK, 0)
|
||||
|
||||
#define SET_ETH_RX_STAT_RXSIZE( reg, val) \
|
||||
SET_FIELD( reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
|
||||
|
||||
#define ETH_RX_STAT_BYTES 0x00000100U
|
||||
|
||||
#define ETH_RX_STAT_CONTROL_FRAME 0x00040000U
|
||||
|
||||
#define ETH_RX_STAT_VLAN 0x00080000U
|
||||
|
||||
#define ETH_RX_STAT_FAIL_FILTER 0x00100000U
|
||||
|
||||
#define ETH_RX_STAT_MULTICAST 0x00200000U
|
||||
|
||||
#define ETH_RX_STAT_BROADCAST 0x00400000U
|
||||
|
||||
#define ETH_RX_STAT_CRC_ERROR 0x00800000U
|
||||
|
||||
#define ETH_RX_STAT_SYMBOL_ERROR 0x01000000U
|
||||
|
||||
#define ETH_RX_STAT_LENGTH_ERROR 0x02000000U
|
||||
|
||||
#define ETH_RX_STAT_RANGE_ERROR 0x04000000U
|
||||
|
||||
#define ETH_RX_STAT_ALIGNMENT_ERROR 0x08000000U
|
||||
|
||||
#define ETH_RX_STAT_OVERRUN 0x10000000U
|
||||
|
||||
#define ETH_RX_STAT_NO_DESCRIPTOR 0x20000000U
|
||||
|
||||
#define ETH_RX_STAT_LAST_FLAG 0x40000000U
|
||||
|
||||
#define ETH_RX_STAT_ERROR 0x80000000U
|
||||
|
||||
/* ETH_TX_CTRL */
|
||||
|
||||
#define ETH_TX_CTRL_SIZE_MASK 0x000007ffU
|
||||
|
||||
#define GET_ETH_TX_CTRL_SIZE( reg) \
|
||||
GET_FIELD( reg, ETH_TX_CTRL_SIZE_MASK, 0)
|
||||
|
||||
#define SET_ETH_TX_CTRL_SIZE( reg, val) \
|
||||
SET_FIELD( reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
|
||||
|
||||
#define ETH_TX_CTRL_OVERRIDE 0x04000000U
|
||||
|
||||
#define ETH_TX_CTRL_HUGE 0x08000000U
|
||||
|
||||
#define ETH_TX_CTRL_PAD 0x10000000U
|
||||
|
||||
#define ETH_TX_CTRL_CRC 0x20000000U
|
||||
|
||||
#define ETH_TX_CTRL_LAST 0x40000000U
|
||||
|
||||
#define ETH_TX_CTRL_INTERRUPT 0x80000000U
|
||||
|
||||
/* ETH_TX_STAT */
|
||||
|
||||
#define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
|
||||
|
||||
#define GET_ETH_TX_STAT_COLLISION_COUNT( reg) \
|
||||
GET_FIELD( reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
|
||||
|
||||
#define SET_ETH_TX_STAT_COLLISION_COUNT( reg, val) \
|
||||
SET_FIELD( reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
|
||||
|
||||
#define ETH_TX_STAT_DEFER 0x02000000U
|
||||
|
||||
#define ETH_TX_STAT_EXCESSIVE_DEFER 0x04000000U
|
||||
|
||||
#define ETH_TX_STAT_EXCESSIVE_COLLISION 0x08000000U
|
||||
|
||||
#define ETH_TX_STAT_LATE_COLLISION 0x10000000U
|
||||
|
||||
#define ETH_TX_STAT_UNDERRUN 0x20000000U
|
||||
|
||||
#define ETH_TX_STAT_NO_DESCRIPTOR 0x40000000U
|
||||
|
||||
#define ETH_TX_STAT_ERROR 0x80000000U
|
||||
|
||||
/* ETH_INT */
|
||||
|
||||
#define ETH_INT_RX_OVERRUN 0x00000001U
|
||||
|
||||
#define ETH_INT_RX_ERROR 0x00000002U
|
||||
|
||||
#define ETH_INT_RX_FINISHED 0x00000004U
|
||||
|
||||
#define ETH_INT_RX_DONE 0x00000008U
|
||||
|
||||
#define ETH_INT_TX_UNDERRUN 0x00000010U
|
||||
|
||||
#define ETH_INT_TX_ERROR 0x00000020U
|
||||
|
||||
#define ETH_INT_TX_FINISHED 0x00000040U
|
||||
|
||||
#define ETH_INT_TX_DONE 0x00000080U
|
||||
|
||||
#define ETH_INT_SOFT 0x00001000U
|
||||
|
||||
#define ETH_INT_WAKEUP 0x00002000U
|
||||
|
||||
/* ETH_RX_FIL_CTRL */
|
||||
|
||||
#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST 0x00000001U
|
||||
|
||||
#define ETH_RX_FIL_CTRL_ACCEPT_BROADCAST 0x00000002U
|
||||
|
||||
#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 0x00000004U
|
||||
|
||||
#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST_HASH 0x00000008U
|
||||
|
||||
#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 0x00000010U
|
||||
|
||||
#define ETH_RX_FIL_CTRL_ACCEPT_PERFECT 0x00000020U
|
||||
|
||||
#define ETH_RX_FIL_CTRL_MAGIC_PACKET_WOL 0x00001000U
|
||||
|
||||
#define ETH_RX_FIL_CTRL_RX_FILTER_WOL 0x00002000U
|
||||
|
||||
/* ETH_CMD */
|
||||
|
||||
#define ETH_CMD_RX_ENABLE 0x00000001U
|
||||
|
||||
#define ETH_CMD_TX_ENABLE 0x00000002U
|
||||
|
||||
#define ETH_CMD_REG_RESET 0x00000008U
|
||||
|
||||
#define ETH_CMD_TX_RESET 0x00000010U
|
||||
|
||||
#define ETH_CMD_RX_RESET 0x00000020U
|
||||
|
||||
#define ETH_CMD_PASS_RUNT_FRAME 0x00000040U
|
||||
|
||||
#define ETH_CMD_PASS_RX_FILTER 0X00000080U
|
||||
|
||||
#define ETH_CMD_TX_FLOW_CONTROL 0x00000100U
|
||||
|
||||
#define ETH_CMD_RMII 0x00000200U
|
||||
|
||||
#define ETH_CMD_FULL_DUPLEX 0x00000400U
|
||||
|
||||
#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
|
||||
|
||||
38
c/src/lib/libbsp/arm/lpc24xx/include/ssp.h
Normal file
38
c/src/lib/libbsp/arm/lpc24xx/include/ssp.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup lpc24xx
|
||||
*
|
||||
* @brief LibI2C bus driver for the Synchronous Serial Port (SSP).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008
|
||||
* Embedded Brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* D-82178 Puchheim
|
||||
* Germany
|
||||
* rtems@embedded-brains.de
|
||||
*
|
||||
* The license and distribution terms for this file may be found in the file
|
||||
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_LPC24XX_SSP_H
|
||||
#define LIBBSP_ARM_LPC24XX_SSP_H
|
||||
|
||||
#include <rtems/libi2c.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
extern rtems_libi2c_bus_t * const lpc24xx_ssp_0;
|
||||
|
||||
extern rtems_libi2c_bus_t * const lpc24xx_ssp_1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_LPC24XX_SSP_H */
|
||||
124
c/src/lib/libbsp/arm/lpc24xx/misc/dma.c
Normal file
124
c/src/lib/libbsp/arm/lpc24xx/misc/dma.c
Normal file
@@ -0,0 +1,124 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup lpc24xx
|
||||
*
|
||||
* @brief DMA support.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008
|
||||
* Embedded Brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* D-82178 Puchheim
|
||||
* Germany
|
||||
* rtems@embedded-brains.de
|
||||
*
|
||||
* The license and distribution terms for this file may be found in the file
|
||||
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <rtems/endian.h>
|
||||
|
||||
#include <bsp/lpc24xx.h>
|
||||
#include <bsp/dma.h>
|
||||
|
||||
/**
|
||||
* @brief Table that indicates if a channel is currently occupied.
|
||||
*/
|
||||
static bool lpc24xx_dma_channel_occupation [GPDMA_CH_NUMBER];
|
||||
|
||||
/**
|
||||
* @brief Initializes the general purpose DMA.
|
||||
*/
|
||||
void lpc24xx_dma_initialize( void)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
/* Enable power */
|
||||
rtems_interrupt_disable( level);
|
||||
PCONP = SET_FLAG( PCONP, PCONP_PCGPDMA);
|
||||
rtems_interrupt_enable( level);
|
||||
|
||||
/* Disable module */
|
||||
GPDMA_CONFIG = 0;
|
||||
|
||||
/* Enable module */
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
GPDMA_CONFIG = GPDMA_CONFIG_EN;
|
||||
#else
|
||||
GPDMA_CONFIG = GPDMA_CONFIG_EN | GPDMA_CONFIG_MODE;
|
||||
#endif
|
||||
|
||||
/* Reset registers */
|
||||
GPDMA_SOFT_SREQ = 0;
|
||||
GPDMA_SOFT_BREQ = 0;
|
||||
GPDMA_SOFT_LSREQ = 0;
|
||||
GPDMA_SOFT_LBREQ = 0;
|
||||
GPDMA_SYNC = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns true if the channel @a channel was obtained.
|
||||
*
|
||||
* If the channel number @a channel is out of range the last valid channel will
|
||||
* be used.
|
||||
*/
|
||||
bool lpc24xx_dma_channel_obtain( unsigned channel)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
bool occupation = true;
|
||||
|
||||
if (channel > GPDMA_CH_NUMBER) {
|
||||
channel = GPDMA_CH_NUMBER - 1;
|
||||
}
|
||||
|
||||
rtems_interrupt_disable( level);
|
||||
occupation = lpc24xx_dma_channel_occupation [channel];
|
||||
lpc24xx_dma_channel_occupation [channel] = true;
|
||||
rtems_interrupt_enable( level);
|
||||
|
||||
return !occupation;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Releases the channel @a channel. You must have obtained this channel
|
||||
* with lpc24xx_dma_channel_obtain() previously.
|
||||
*
|
||||
* If the channel number @a channel is out of range the last valid channel will
|
||||
* be used.
|
||||
*/
|
||||
void lpc24xx_dma_channel_release( unsigned channel)
|
||||
{
|
||||
if (channel > GPDMA_CH_NUMBER) {
|
||||
channel = GPDMA_CH_NUMBER - 1;
|
||||
}
|
||||
|
||||
lpc24xx_dma_channel_occupation [channel] = false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the channel @a channel.
|
||||
*
|
||||
* If @a force is false the channel will be halted and disabled when the
|
||||
* channel is inactive. If the channel number @a channel is out of range the
|
||||
* last valid channel will be used.
|
||||
*/
|
||||
void lpc24xx_dma_channel_disable( unsigned channel, bool force)
|
||||
{
|
||||
volatile lpc24xx_dma_channel *ch = GPDMA_CH_BASE_ADDR( channel);
|
||||
uint32_t cfg = ch->cfg;
|
||||
|
||||
if (!force) {
|
||||
/* Halt */
|
||||
ch->cfg = SET_FLAG( cfg, GPDMA_CH_CFG_HALT);
|
||||
|
||||
/* Wait for inactive */
|
||||
do {
|
||||
cfg = ch->cfg;
|
||||
} while (IS_FLAG_SET( cfg, GPDMA_CH_CFG_ACTIVE));
|
||||
}
|
||||
|
||||
/* Disable */
|
||||
ch->cfg = CLEAR_FLAG( cfg, GPDMA_CH_CFG_EN);
|
||||
}
|
||||
@@ -71,7 +71,7 @@ unsigned lpc24xx_cclk( void)
|
||||
}
|
||||
|
||||
/* Get PLL output frequency */
|
||||
if (REG_FLAG_IS_SET( PLLSTAT, PLLSTAT_PLLC)) {
|
||||
if (IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLC)) {
|
||||
uint32_t pllcfg = PLLCFG;
|
||||
unsigned n = GET_PLLCFG_NSEL( pllcfg) + 1;
|
||||
unsigned m = GET_PLLCFG_MSEL( pllcfg) + 1;
|
||||
@@ -110,10 +110,10 @@ static void lpc24xx_pll_config( uint32_t val)
|
||||
*/
|
||||
void lpc24xx_set_pll( unsigned clksrc, unsigned nsel, unsigned msel, unsigned cclksel)
|
||||
{
|
||||
bool pll_enabled = REG_FLAG_IS_SET( PLLSTAT, PLLSTAT_PLLE);
|
||||
bool pll_enabled = IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLE);
|
||||
|
||||
/* Disconnect PLL if necessary */
|
||||
if (REG_FLAG_IS_SET( PLLSTAT, PLLSTAT_PLLC)) {
|
||||
if (IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLC)) {
|
||||
if (pll_enabled) {
|
||||
lpc24xx_pll_config( PLLCON_PLLE);
|
||||
} else {
|
||||
@@ -139,7 +139,7 @@ void lpc24xx_set_pll( unsigned clksrc, unsigned nsel, unsigned msel, unsigned cc
|
||||
lpc24xx_pll_config( PLLCON_PLLE);
|
||||
|
||||
/* Wait for lock */
|
||||
while (REG_FLAG_IS_CLEARED( PLLSTAT, PLLSTAT_PLOCK)) {
|
||||
while (IS_FLAG_CLEARED( PLLSTAT, PLLSTAT_PLOCK)) {
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
|
||||
@@ -85,6 +85,14 @@ $(PROJECT_INCLUDE)/bsp/system-clocks.h: include/system-clocks.h $(PROJECT_INCLUD
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/system-clocks.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/system-clocks.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/ssp.h: include/ssp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ssp.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ssp.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/dma.h: include/dma.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/dma.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/dma.h
|
||||
|
||||
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
|
||||
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
|
||||
|
||||
654
c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c
Normal file
654
c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c
Normal file
@@ -0,0 +1,654 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup lpc24xx
|
||||
*
|
||||
* @brief LibI2C bus driver for the Synchronous Serial Port (SSP).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008
|
||||
* Embedded Brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* D-82178 Puchheim
|
||||
* Germany
|
||||
* rtems@embedded-brains.de
|
||||
*
|
||||
* The license and distribution terms for this file may be found in the file
|
||||
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <bsp/ssp.h>
|
||||
#include <bsp/lpc24xx.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/system-clocks.h>
|
||||
#include <bsp/dma.h>
|
||||
|
||||
#define RTEMS_STATUS_CHECKS_USE_PRINTK
|
||||
|
||||
#include <rtems/status-checks.h>
|
||||
|
||||
#define LPC24XX_SSP_NUMBER 2
|
||||
|
||||
#define LPC24XX_SSP_FIFO_SIZE 8
|
||||
|
||||
#define LPC24XX_SSP_BAUD_RATE 2000000
|
||||
|
||||
typedef enum {
|
||||
LPC24XX_SSP_DMA_INVALID = 0,
|
||||
LPC24XX_SSP_DMA_AVAILABLE = 1,
|
||||
LPC24XX_SSP_DMA_NOT_INITIALIZED = 2,
|
||||
LPC24XX_SSP_DMA_INITIALIZATION = 3,
|
||||
LPC24XX_SSP_DMA_TRANSFER_FLAG = 0x80000000U,
|
||||
LPC24XX_SSP_DMA_WAIT = 1 | LPC24XX_SSP_DMA_TRANSFER_FLAG,
|
||||
LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0 = 2 | LPC24XX_SSP_DMA_TRANSFER_FLAG,
|
||||
LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1 = 3 | LPC24XX_SSP_DMA_TRANSFER_FLAG,
|
||||
LPC24XX_SSP_DMA_ERROR = 4 | LPC24XX_SSP_DMA_TRANSFER_FLAG,
|
||||
LPC24XX_SSP_DMA_DONE = 5 | LPC24XX_SSP_DMA_TRANSFER_FLAG
|
||||
} lpc24xx_ssp_dma_status;
|
||||
|
||||
typedef struct {
|
||||
rtems_libi2c_bus_t bus;
|
||||
volatile lpc24xx_ssp *regs;
|
||||
unsigned clock;
|
||||
uint32_t idle_char;
|
||||
} lpc24xx_ssp_bus_entry;
|
||||
|
||||
typedef struct {
|
||||
lpc24xx_ssp_dma_status status;
|
||||
lpc24xx_ssp_bus_entry *bus;
|
||||
rtems_libi2c_read_write_done_t done;
|
||||
int n;
|
||||
void *arg;
|
||||
} lpc24xx_ssp_dma_entry;
|
||||
|
||||
static lpc24xx_ssp_dma_entry lpc24xx_ssp_dma_data = {
|
||||
.status = LPC24XX_SSP_DMA_NOT_INITIALIZED,
|
||||
.bus = NULL,
|
||||
.done = NULL,
|
||||
.n = 0,
|
||||
.arg = NULL
|
||||
};
|
||||
|
||||
static uint32_t lpc24xx_ssp_trash = 0;
|
||||
|
||||
static inline bool lpc24xx_ssp_is_busy( const lpc24xx_ssp_bus_entry *bus)
|
||||
{
|
||||
return lpc24xx_ssp_dma_data.bus == bus
|
||||
&& lpc24xx_ssp_dma_data.status != LPC24XX_SSP_DMA_AVAILABLE;
|
||||
}
|
||||
|
||||
static void lpc24xx_ssp_handler( rtems_vector_number vector, void *arg)
|
||||
{
|
||||
lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) arg;
|
||||
volatile lpc24xx_ssp *regs = e->regs;
|
||||
uint32_t mis = regs->mis;
|
||||
uint32_t icr = 0;
|
||||
|
||||
if (IS_FLAG_SET( mis, SSP_MIS_RORRIS)) {
|
||||
/* TODO */
|
||||
printk( "%s: Receiver overrun!\n", __func__);
|
||||
icr |= SSP_ICR_RORRIS;
|
||||
}
|
||||
|
||||
regs->icr = icr;
|
||||
}
|
||||
|
||||
static void lpc24xx_ssp_dma_handler( rtems_vector_number vector, void *arg)
|
||||
{
|
||||
lpc24xx_ssp_dma_entry *e = (lpc24xx_ssp_dma_entry *) arg;
|
||||
lpc24xx_ssp_dma_status status = e->status;
|
||||
uint32_t tc = 0;
|
||||
uint32_t err = 0;
|
||||
int rv = 0;
|
||||
|
||||
/* Return if we are not in a transfer status */
|
||||
if (IS_FLAG_CLEARED( status, LPC24XX_SSP_DMA_TRANSFER_FLAG)) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Get interrupt status */
|
||||
tc = GPDMA_INT_TCSTAT;
|
||||
err = GPDMA_INT_ERR_STAT;
|
||||
|
||||
/* Clear interrupt status */
|
||||
GPDMA_INT_TCCLR = tc;
|
||||
GPDMA_INT_ERR_CLR = err;
|
||||
|
||||
/* Change status */
|
||||
if (err == 0) {
|
||||
switch (status) {
|
||||
case LPC24XX_SSP_DMA_WAIT:
|
||||
if (ARE_FLAGS_SET( tc, GPDMA_STATUS_CH_0 | GPDMA_STATUS_CH_1)) {
|
||||
status = LPC24XX_SSP_DMA_DONE;
|
||||
} else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
|
||||
status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1;
|
||||
} else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
|
||||
status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0;
|
||||
}
|
||||
break;
|
||||
case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0:
|
||||
if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
|
||||
status = LPC24XX_SSP_DMA_ERROR;
|
||||
} else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
|
||||
status = LPC24XX_SSP_DMA_DONE;
|
||||
}
|
||||
break;
|
||||
case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1:
|
||||
if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
|
||||
status = LPC24XX_SSP_DMA_ERROR;
|
||||
} else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
|
||||
status = LPC24XX_SSP_DMA_DONE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
status = LPC24XX_SSP_DMA_ERROR;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
status = LPC24XX_SSP_DMA_ERROR;
|
||||
}
|
||||
|
||||
/* Error cleanup */
|
||||
if (status == LPC24XX_SSP_DMA_ERROR) {
|
||||
lpc24xx_dma_channel_disable( 0, true);
|
||||
lpc24xx_dma_channel_disable( 1, true);
|
||||
status = LPC24XX_SSP_DMA_DONE;
|
||||
rv = -RTEMS_IO_ERROR;
|
||||
}
|
||||
|
||||
/* Done */
|
||||
if (status == LPC24XX_SSP_DMA_DONE) {
|
||||
status = LPC24XX_SSP_DMA_AVAILABLE;
|
||||
if (e->done != NULL) {
|
||||
e->done( rv, e->n, e->arg);
|
||||
e->done = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set status */
|
||||
e->status = status;
|
||||
}
|
||||
|
||||
static rtems_status_code lpc24xx_ssp_init( rtems_libi2c_bus_t *bus)
|
||||
{
|
||||
rtems_status_code sc = RTEMS_SUCCESSFUL;
|
||||
rtems_interrupt_level level;
|
||||
lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
|
||||
volatile lpc24xx_ssp *regs = e->regs;
|
||||
unsigned pclk = lpc24xx_cclk();
|
||||
unsigned pre =
|
||||
((pclk + LPC24XX_SSP_BAUD_RATE - 1) / LPC24XX_SSP_BAUD_RATE + 1) & ~1U;
|
||||
rtems_vector_number vector = UINT32_MAX;
|
||||
|
||||
if (lpc24xx_ssp_dma_data.status == LPC24XX_SSP_DMA_NOT_INITIALIZED) {
|
||||
lpc24xx_ssp_dma_status status = LPC24XX_SSP_DMA_INVALID;
|
||||
|
||||
/* Test and set DMA support status */
|
||||
rtems_interrupt_disable( level);
|
||||
status = lpc24xx_ssp_dma_data.status;
|
||||
if (status == LPC24XX_SSP_DMA_NOT_INITIALIZED) {
|
||||
lpc24xx_ssp_dma_data.status = LPC24XX_SSP_DMA_INITIALIZATION;
|
||||
}
|
||||
rtems_interrupt_enable( level);
|
||||
|
||||
if (status == LPC24XX_SSP_DMA_NOT_INITIALIZED) {
|
||||
/* Install DMA interrupt handler */
|
||||
sc = rtems_interrupt_handler_install(
|
||||
LPC24XX_IRQ_DMA,
|
||||
"SSP DMA",
|
||||
RTEMS_INTERRUPT_SHARED,
|
||||
lpc24xx_ssp_dma_handler,
|
||||
&lpc24xx_ssp_dma_data
|
||||
);
|
||||
CHECK_SC( sc, "Install DMA interrupt handler");
|
||||
|
||||
/* Set DMA support status */
|
||||
lpc24xx_ssp_dma_data.status = LPC24XX_SSP_DMA_AVAILABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable module */
|
||||
regs->cr1 = 0;
|
||||
|
||||
/* Set clock select and get vector number */
|
||||
switch ((uintptr_t) regs) {
|
||||
case SSP0_BASE_ADDR:
|
||||
rtems_interrupt_disable( level);
|
||||
SET_PCLKSEL1_PCLK_SSP0( PCLKSEL1, 1);
|
||||
rtems_interrupt_enable( level);
|
||||
|
||||
vector = LPC24XX_IRQ_SPI_SSP_0;
|
||||
break;
|
||||
case SSP1_BASE_ADDR:
|
||||
rtems_interrupt_disable( level);
|
||||
SET_PCLKSEL0_PCLK_SSP1( PCLKSEL0, 1);
|
||||
rtems_interrupt_enable( level);
|
||||
|
||||
vector = LPC24XX_IRQ_SSP_1;
|
||||
break;
|
||||
default:
|
||||
return RTEMS_IO_ERROR;
|
||||
}
|
||||
|
||||
/* Set serial clock rate to save value */
|
||||
regs->cr0 = SET_SSP_CR0_SCR( 0, 255);
|
||||
|
||||
/* Set clock prescaler */
|
||||
if (pre > 254) {
|
||||
pre = 254;
|
||||
} else if (pre < 2) {
|
||||
pre = 2;
|
||||
}
|
||||
regs->cpsr = pre;
|
||||
|
||||
/* Save clock value */
|
||||
e->clock = pclk / pre;
|
||||
|
||||
/* Enable module and loop back mode */
|
||||
regs->cr1 = SSP_CR1_LBM | SSP_CR1_SSE;
|
||||
|
||||
/* Install interrupt handler */
|
||||
sc = rtems_interrupt_handler_install(
|
||||
vector,
|
||||
"SSP",
|
||||
RTEMS_INTERRUPT_UNIQUE,
|
||||
lpc24xx_ssp_handler,
|
||||
e
|
||||
);
|
||||
CHECK_SC( sc, "Install interrupt handler");
|
||||
|
||||
/* Enable receiver overrun interrupts */
|
||||
e->regs->imsc = SSP_IMSC_RORIM;
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static rtems_status_code lpc24xx_ssp_send_start( rtems_libi2c_bus_t *bus)
|
||||
{
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static rtems_status_code lpc24xx_ssp_send_stop( rtems_libi2c_bus_t *bus)
|
||||
{
|
||||
lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
|
||||
|
||||
/* Release DMA support */
|
||||
if (lpc24xx_ssp_dma_data.bus == e) {
|
||||
if (lpc24xx_ssp_dma_data.status == LPC24XX_SSP_DMA_AVAILABLE) {
|
||||
lpc24xx_dma_channel_release( 0);
|
||||
lpc24xx_dma_channel_release( 1);
|
||||
lpc24xx_ssp_dma_data.bus = NULL;
|
||||
} else {
|
||||
return RTEMS_RESOURCE_IN_USE;
|
||||
}
|
||||
}
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static rtems_status_code lpc24xx_ssp_send_addr(
|
||||
rtems_libi2c_bus_t *bus,
|
||||
uint32_t addr,
|
||||
int rw
|
||||
)
|
||||
{
|
||||
lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
|
||||
|
||||
if (lpc24xx_ssp_is_busy( e)) {
|
||||
return RTEMS_RESOURCE_IN_USE;
|
||||
}
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int lpc24xx_ssp_set_transfer_mode(
|
||||
rtems_libi2c_bus_t *bus,
|
||||
const rtems_libi2c_tfr_mode_t *mode
|
||||
)
|
||||
{
|
||||
lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
|
||||
volatile lpc24xx_ssp *regs = e->regs;
|
||||
unsigned clk = e->clock;
|
||||
unsigned br = mode->baudrate;
|
||||
unsigned scr = (clk + br - 1) / br;
|
||||
|
||||
if (lpc24xx_ssp_is_busy( e)) {
|
||||
return -RTEMS_RESOURCE_IN_USE;
|
||||
}
|
||||
|
||||
if (mode->bits_per_char != 8) {
|
||||
return -RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
if (mode->lsb_first) {
|
||||
return -RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
if (br == 0) {
|
||||
return -RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
/* Compute new prescaler if necessary */
|
||||
if (scr > 256 || scr < 1) {
|
||||
unsigned pre = regs->cpsr;
|
||||
unsigned pclk = clk * pre;
|
||||
|
||||
while (scr > 256) {
|
||||
if (pre > 252) {
|
||||
return -RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
pre += 2;
|
||||
clk = pclk / pre;
|
||||
scr = (clk + br - 1) / br;
|
||||
}
|
||||
|
||||
while (scr < 1) {
|
||||
if (pre < 4) {
|
||||
return -RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
pre -= 2;
|
||||
clk = pclk / pre;
|
||||
scr = (clk + br - 1) / br;
|
||||
}
|
||||
|
||||
regs->cpsr = pre;
|
||||
e->clock = clk;
|
||||
}
|
||||
|
||||
/* Adjust SCR */
|
||||
--scr;
|
||||
|
||||
e->idle_char = mode->idle_char;
|
||||
|
||||
while (IS_FLAG_CLEARED( regs->sr, SSP_SR_TFE)) {
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
regs->cr0 = SET_SSP_CR0_DSS( 0, 0x7)
|
||||
| SET_SSP_CR0_SCR( 0, scr)
|
||||
| (mode->clock_inv ? SSP_CR0_CPOL : 0)
|
||||
| (mode->clock_phs ? SSP_CR0_CPHA : 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc24xx_ssp_read_write(
|
||||
rtems_libi2c_bus_t *bus,
|
||||
unsigned char *in,
|
||||
const unsigned char *out,
|
||||
int n
|
||||
)
|
||||
{
|
||||
lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
|
||||
volatile lpc24xx_ssp *regs = e->regs;
|
||||
int r = 0;
|
||||
int w = 0;
|
||||
int dr = 1;
|
||||
int dw = 1;
|
||||
int m = 0;
|
||||
uint32_t sr = regs->sr;
|
||||
unsigned char trash = 0;
|
||||
unsigned char idle_char = (unsigned char) e->idle_char;
|
||||
|
||||
if (lpc24xx_ssp_is_busy( e)) {
|
||||
return -RTEMS_RESOURCE_IN_USE;
|
||||
}
|
||||
|
||||
if (n < 0) {
|
||||
return -RTEMS_INVALID_SIZE;
|
||||
}
|
||||
|
||||
/* Disable DMA on SSP */
|
||||
regs->dmacr = SSP_DMACR_RXDMAE | SSP_DMACR_TXDMAE;
|
||||
|
||||
if (in == NULL) {
|
||||
dr = 0;
|
||||
in = &trash;
|
||||
}
|
||||
|
||||
if (out == NULL) {
|
||||
dw = 0;
|
||||
out = &idle_char;
|
||||
}
|
||||
|
||||
/*
|
||||
* Assumption: The transmit and receive FIFOs are empty. If this assumption
|
||||
* is not true an input buffer overflow may occur or we may never exit the
|
||||
* loop due to data loss. This is only possible if entities external to this
|
||||
* driver operate on the SSP.
|
||||
*/
|
||||
|
||||
while (w < n) {
|
||||
/* FIFO capacity */
|
||||
m = w - r;
|
||||
|
||||
/* Write */
|
||||
if (IS_FLAG_SET( sr, SSP_SR_TNF) && m < LPC24XX_SSP_FIFO_SIZE) {
|
||||
regs->dr = *out;
|
||||
++w;
|
||||
out += dw;
|
||||
}
|
||||
|
||||
/* Read */
|
||||
if (IS_FLAG_SET( sr, SSP_SR_RNE)) {
|
||||
*in = (unsigned char) regs->dr;
|
||||
++r;
|
||||
in += dr;
|
||||
}
|
||||
|
||||
/* New status */
|
||||
sr = regs->sr;
|
||||
}
|
||||
|
||||
/* Read outstanding input */
|
||||
while (r < n) {
|
||||
/* Wait */
|
||||
do {
|
||||
sr = regs->sr;
|
||||
} while (IS_FLAG_CLEARED( sr, SSP_SR_RNE));
|
||||
|
||||
/* Read */
|
||||
*in = (unsigned char) regs->dr;
|
||||
++r;
|
||||
in += dr;
|
||||
}
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
static int lpc24xx_ssp_read_write_async(
|
||||
rtems_libi2c_bus_t *bus,
|
||||
unsigned char *in,
|
||||
const unsigned char *out,
|
||||
int n,
|
||||
rtems_libi2c_read_write_done_t done,
|
||||
void *arg
|
||||
)
|
||||
{
|
||||
rtems_status_code sc = RTEMS_SUCCESSFUL;
|
||||
rtems_interrupt_level level;
|
||||
lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
|
||||
volatile lpc24xx_ssp *ssp = e->regs;
|
||||
volatile lpc24xx_dma_channel *receive_channel = GPDMA_CH_BASE_ADDR( 0);
|
||||
volatile lpc24xx_dma_channel *transmit_channel = GPDMA_CH_BASE_ADDR( 1);
|
||||
uint32_t di = GPDMA_CH_CTRL_DI;
|
||||
uint32_t si = GPDMA_CH_CTRL_SI;
|
||||
|
||||
if (n < 0 || n > (int) GPDMA_CH_CTRL_TSZ_MAX) {
|
||||
return -RTEMS_INVALID_SIZE;
|
||||
}
|
||||
|
||||
/* Try to reserve DMA support for this bus */
|
||||
if (lpc24xx_ssp_dma_data.bus == NULL) {
|
||||
rtems_interrupt_disable( level);
|
||||
if (lpc24xx_ssp_dma_data.bus == NULL) {
|
||||
lpc24xx_ssp_dma_data.bus = e;
|
||||
}
|
||||
rtems_interrupt_enable( level);
|
||||
|
||||
/* Try to obtain DMA channels */
|
||||
if (lpc24xx_ssp_dma_data.bus == e) {
|
||||
bool channel_0 = lpc24xx_dma_channel_obtain( 0);
|
||||
bool channel_1 = lpc24xx_dma_channel_obtain( 1);
|
||||
|
||||
if (!channel_0 && channel_1) {
|
||||
lpc24xx_dma_channel_release( 1);
|
||||
lpc24xx_ssp_dma_data.bus = NULL;
|
||||
} else if (channel_0 && !channel_1) {
|
||||
lpc24xx_dma_channel_release( 0);
|
||||
lpc24xx_ssp_dma_data.bus = NULL;
|
||||
} else if (!channel_0 || !channel_1) {
|
||||
lpc24xx_ssp_dma_data.bus = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if DMA support is available */
|
||||
if (lpc24xx_ssp_dma_data.bus != e
|
||||
|| lpc24xx_ssp_dma_data.status != LPC24XX_SSP_DMA_AVAILABLE) {
|
||||
return -RTEMS_RESOURCE_IN_USE;
|
||||
}
|
||||
|
||||
/* Set DMA support status and parameter */
|
||||
lpc24xx_ssp_dma_data.status = LPC24XX_SSP_DMA_WAIT;
|
||||
lpc24xx_ssp_dma_data.done = done;
|
||||
lpc24xx_ssp_dma_data.n = n;
|
||||
lpc24xx_ssp_dma_data.arg = arg;
|
||||
|
||||
/* Enable DMA on SSP */
|
||||
ssp->dmacr = SSP_DMACR_RXDMAE | SSP_DMACR_TXDMAE;
|
||||
|
||||
/* Receive */
|
||||
if (in != NULL) {
|
||||
receive_channel->dest = (uint32_t) in;
|
||||
} else {
|
||||
receive_channel->dest = (uint32_t) &lpc24xx_ssp_trash;
|
||||
di = 0;
|
||||
}
|
||||
receive_channel->src = (uint32_t) &ssp->dr;
|
||||
receive_channel->lli = 0;
|
||||
receive_channel->ctrl = SET_GPDMA_CH_CTRL_TSZ( 0, n)
|
||||
| SET_GPDMA_CH_CTRL_SBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
|
||||
| SET_GPDMA_CH_CTRL_DBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
|
||||
| SET_GPDMA_CH_CTRL_SW( 0, GPDMA_CH_CTRL_W_8)
|
||||
| SET_GPDMA_CH_CTRL_DW( 0, GPDMA_CH_CTRL_W_8)
|
||||
| GPDMA_CH_CTRL_ITC
|
||||
| di;
|
||||
receive_channel->cfg = SET_GPDMA_CH_CFG_SRCPER( 0, GPDMA_CH_CFG_PER_SSP1_RX)
|
||||
| SET_GPDMA_CH_CFG_FLOW( 0, GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA)
|
||||
| GPDMA_CH_CFG_IE
|
||||
| GPDMA_CH_CFG_ITC
|
||||
| GPDMA_CH_CFG_EN;
|
||||
|
||||
/* Transmit */
|
||||
if (out != NULL) {
|
||||
transmit_channel->src = (uint32_t) out;
|
||||
} else {
|
||||
transmit_channel->src = (uint32_t) &e->idle_char;
|
||||
si = 0;
|
||||
}
|
||||
transmit_channel->dest = (uint32_t) &ssp->dr;
|
||||
transmit_channel->lli = 0;
|
||||
transmit_channel->ctrl = SET_GPDMA_CH_CTRL_TSZ( 0, n)
|
||||
| SET_GPDMA_CH_CTRL_SBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
|
||||
| SET_GPDMA_CH_CTRL_DBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
|
||||
| SET_GPDMA_CH_CTRL_SW( 0, GPDMA_CH_CTRL_W_8)
|
||||
| SET_GPDMA_CH_CTRL_DW( 0, GPDMA_CH_CTRL_W_8)
|
||||
| GPDMA_CH_CTRL_ITC
|
||||
| si;
|
||||
transmit_channel->cfg = SET_GPDMA_CH_CFG_DESTPER( 0, GPDMA_CH_CFG_PER_SSP1_TX)
|
||||
| SET_GPDMA_CH_CFG_FLOW( 0, GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA)
|
||||
| GPDMA_CH_CFG_IE
|
||||
| GPDMA_CH_CFG_ITC
|
||||
| GPDMA_CH_CFG_EN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc24xx_ssp_read( rtems_libi2c_bus_t *bus, unsigned char *in, int n)
|
||||
{
|
||||
return lpc24xx_ssp_read_write( bus, in, NULL, n);
|
||||
}
|
||||
|
||||
static int lpc24xx_ssp_write(
|
||||
rtems_libi2c_bus_t *bus,
|
||||
unsigned char *out,
|
||||
int n
|
||||
)
|
||||
{
|
||||
return lpc24xx_ssp_read_write( bus, NULL, out, n);
|
||||
}
|
||||
|
||||
static int lpc24xx_ssp_ioctl( rtems_libi2c_bus_t *bus, int cmd, void *arg)
|
||||
{
|
||||
int rv = -1;
|
||||
const rtems_libi2c_tfr_mode_t *tm = (const rtems_libi2c_tfr_mode_t *) arg;
|
||||
rtems_libi2c_read_write_t *rw = (rtems_libi2c_read_write_t *) arg;
|
||||
rtems_libi2c_read_write_async_t *rwa =
|
||||
(rtems_libi2c_read_write_async_t *) arg;
|
||||
|
||||
switch (cmd) {
|
||||
case RTEMS_LIBI2C_IOCTL_READ_WRITE:
|
||||
rv = lpc24xx_ssp_read_write( bus, rw->rd_buf, rw->wr_buf, rw->byte_cnt);
|
||||
break;
|
||||
case RTEMS_LIBI2C_IOCTL_READ_WRITE_ASYNC:
|
||||
rv = lpc24xx_ssp_read_write_async(
|
||||
bus,
|
||||
rwa->rd_buf,
|
||||
rwa->wr_buf,
|
||||
rwa->byte_cnt,
|
||||
rwa->done,
|
||||
rwa->arg
|
||||
);
|
||||
break;
|
||||
case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
|
||||
rv = lpc24xx_ssp_set_transfer_mode( bus, tm);
|
||||
break;
|
||||
default:
|
||||
rv = -RTEMS_NOT_DEFINED;
|
||||
break;
|
||||
}
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
static const rtems_libi2c_bus_ops_t lpc24xx_ssp_ops = {
|
||||
.init = lpc24xx_ssp_init,
|
||||
.send_start = lpc24xx_ssp_send_start,
|
||||
.send_stop = lpc24xx_ssp_send_stop,
|
||||
.send_addr = lpc24xx_ssp_send_addr,
|
||||
.read_bytes = lpc24xx_ssp_read,
|
||||
.write_bytes = lpc24xx_ssp_write,
|
||||
.ioctl = lpc24xx_ssp_ioctl
|
||||
};
|
||||
|
||||
static lpc24xx_ssp_bus_entry lpc24xx_ssp_bus_table [LPC24XX_SSP_NUMBER] = {
|
||||
{
|
||||
/* SSP 0 */
|
||||
.bus = {
|
||||
.ops = &lpc24xx_ssp_ops,
|
||||
.size = sizeof( lpc24xx_ssp_bus_entry)
|
||||
},
|
||||
.regs = (volatile lpc24xx_ssp *) SSP0_BASE_ADDR,
|
||||
.clock = 0,
|
||||
.idle_char = 0xffffffff
|
||||
}, {
|
||||
/* SSP 1 */
|
||||
.bus = {
|
||||
.ops = &lpc24xx_ssp_ops,
|
||||
.size = sizeof( lpc24xx_ssp_bus_entry)
|
||||
},
|
||||
.regs = (volatile lpc24xx_ssp *) SSP1_BASE_ADDR,
|
||||
.clock = 0,
|
||||
.idle_char = 0xffffffff
|
||||
}
|
||||
};
|
||||
|
||||
rtems_libi2c_bus_t * const lpc24xx_ssp_0 =
|
||||
(rtems_libi2c_bus_t *) &lpc24xx_ssp_bus_table [0];
|
||||
|
||||
rtems_libi2c_bus_t * const lpc24xx_ssp_1 =
|
||||
(rtems_libi2c_bus_t *) &lpc24xx_ssp_bus_table [1];
|
||||
@@ -22,6 +22,7 @@
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/bootcard.h>
|
||||
#include <bsp/dma.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
#include <bsp/lpc24xx.h>
|
||||
@@ -61,23 +62,26 @@ void bsp_start( void)
|
||||
/* Spin forever */
|
||||
}
|
||||
}
|
||||
|
||||
/* DMA */
|
||||
lpc24xx_dma_initialize();
|
||||
}
|
||||
|
||||
#define ULSR_THRE 0x00000020U
|
||||
|
||||
static void my_BSP_output_char( char c)
|
||||
static void lpc24xx_BSP_output_char( char c)
|
||||
{
|
||||
while (REG_FLAG_IS_CLEARED( U0LSR, ULSR_THRE)) {
|
||||
while (IS_FLAG_CLEARED( U0LSR, ULSR_THRE)) {
|
||||
/* Wait */
|
||||
}
|
||||
U0THR = c;
|
||||
|
||||
if (c == '\n') {
|
||||
while (REG_FLAG_IS_CLEARED( U0LSR, ULSR_THRE)) {
|
||||
while (IS_FLAG_CLEARED( U0LSR, ULSR_THRE)) {
|
||||
/* Wait */
|
||||
}
|
||||
U0THR = '\r';
|
||||
}
|
||||
}
|
||||
|
||||
BSP_output_char_function_type BSP_output_char = my_BSP_output_char;
|
||||
BSP_output_char_function_type BSP_output_char = lpc24xx_BSP_output_char;
|
||||
|
||||
Reference in New Issue
Block a user