bsps: Convert README to MarkDown

bsps/powerpc/shared/exceptions/README.md

@@ -1,10 +1,13 @@
+Exceptions
+==========
 
 BSP support middleware for 'new-exception' style PPC.
 
 T. Straumann, 12/2007
 
+
 EXPLANATION OF SOME TERMS
-=========================
+-------------------------
 
 In this README we refer to exceptions and sometimes
 to 'interrupts'. Interrupts simply are asynchronous
@@ -22,8 +25,9 @@ Asynchronous exceptions/interrupts, OTOH, use a dedicated
 interrupt stack and defer scheduling until after the last
 nested ISR has finished.
 
+
 RATIONALE
-=========
+---------
 The 'new-exception' processing API works at a rather
 low level. It provides functions for
 installing low-level code (which must be written in
@@ -111,9 +115,9 @@ that they could is beyond doubt...):
    only deal with EE]). See separate section titled
    'race condition...' below for a detailed explanation.
 
-STRUCTURE
-=========
 
+STRUCTURE
+---------
 The middleware uses exception 'categories' or
 'flavors' as defined in raw_exception.h.
 
@@ -167,10 +171,11 @@ The middleware consists of the following parts:
 	 the BSP.
 
 USAGE
-=====
+-----
 	BSP writers must provide the following routines 
 	(declared in irq_supp.h):
 	Interrupt controller (PIC) support:
+```c
 		BSP_setup_the_pic()        - initialize PIC hardware
 		BSP_enable_irq_at_pic()    - enable/disable given irq at PIC; IGNORE if
 		BSP_disable_irq_at_pic()     irq number out of range!
@@ -194,6 +199,7 @@ USAGE
 	  BSP_panic("cannot initialize exceptions");
 	}
 	BSP_rtems_irq_mngt_set();
+```
 
 	Note that BSP_rtems_irq_mngt_set() hooks the C_dispatch_irq_handler()
 	to the external and decrementer (PIT exception for bookE; a decrementer
@@ -237,24 +243,24 @@ USAGE
 
 		- add
 
+```shell
 		    ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h
 		    ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
-
+```
 		  to 'include_bsp_HEADERS'
 
 		- add
-
+```shell
 		    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel
 		    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel
-
+```
 		  to 'libbsp_a_LIBADD'
 
 		  (irq.c is in a separate '.rel' so that you can get support
 		  for exceptions only).
 
 CAVEATS
-=======
-
+-------
 On classic PPCs, early (and late) parts of the low-level
 exception handling code run with the MMU disabled which mean
 that the default caching attributes (write-back) are in effect
@@ -283,7 +289,7 @@ this situation is not detected).
 
 
 RACE CONDITION WHEN DEALING WITH CRITICAL INTERRUPTS
-====================================================
+----------------------------------------------------
 
    The problematic race condition is as follows:
 
@@ -411,8 +417,8 @@ RACE CONDITION WHEN DEALING WITH CRITICAL INTERRUPTS
 	use OS primitives and currently there are no
 	asynchronous machine-checks defined.
 
-   Epilogue:
-
+Epilogue
+--------
    You have to disable all asynchronous exceptions which may cause a context
    switch before the restoring of the SRRs and the RFI.  Reason: