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2002-02-28 Mike Panetta <ahuitzot@mindspring.com>

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* console/sci.c, console/sci.h,
	console/console.c: Added new SCI driver.
	* start/start.c: Removed file.
	* start/start.S: New file, the asm portion of the updated start code.
	* start/configure.am: Added start.S, removed start.c
	* startup/start_c.c: New file, the C portion of the updated start code. 	Contains most of the code that was in the old start.c.
	* startup/configure.am: Added start_c.c to C_FILES.
	* include/bsp.h: Added include <rtems/bspIo.h>
This commit is contained in:
Joel Sherrill
2002-02-28 23:10:39 +00:00
parent 098cdaf63f
commit 274fa77780
15 changed files with 2333 additions and 609 deletions
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11
c/src/lib/libbsp/m68k/mrm332/ChangeLog
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@@ -1,3 +1,14 @@
2002-02-28 Mike Panetta <ahuitzot@mindspring.com>
* console/sci.c, console/sci.h,
console/console.c: Added new SCI driver.
* start/start.c: Removed file.
* start/start.S: New file, the asm portion of the updated start code.
* start/configure.am: Added start.S, removed start.c
* startup/start_c.c: New file, the C portion of the updated start code. Contains most of the code that was in the old start.c.
* startup/configure.am: Added start_c.c to C_FILES.
* include/bsp.h: Added include <rtems/bspIo.h>
2001-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Introduce RTEMS_BSP_CONFIGURE.

4
c/src/lib/libbsp/m68k/mrm332/console/Makefile.am
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@@ -6,9 +6,11 @@ AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/console.rel
C_FILES = console.c
C_FILES = console.c sci.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
H_FILES = sci.h
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg

440
c/src/lib/libbsp/m68k/mrm332/console/console.c
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@@ -1,8 +1,12 @@
/*
* This file contains the mrm console IO package.
* This file contains the generic console driver shell used
* by all console drivers using libchip.
*
* COPYRIGHT (c) 1989-1999.
* This driver uses the termios pseudo driver.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -11,290 +15,21 @@
* $Id$
*/
#include <stdlib.h>
#include <bsp.h>
#include <rtems/libio.h>
#include <termios.h>
#include "sci.h"
//#include "../../../../../../rtems/c/src/lib/libbsp/m68k/opti/console/duart.h"
//#include "../../../../../../rtems/c/src/lib/libc/libio_.h"
/* BUFFER_LENGTH must be 2^n for n=1, 2, 3, .... */
#define BUFFER_LENGTH 256
#define RTS_STOP_SIZE BUFFER_LENGTH-64
#define RTS_START_SIZE 16
char xmt_buf[BUFFER_LENGTH];
char rcv_buf[BUFFER_LENGTH];
/* in: last entry into the buffer; always on a valid character */
/* out: points to the next character to be pull from the buffer */
/* in+1=out => buffer empty */
/* in+2=out => buffer full */
struct UART_buf {
char *offset;
char *in;
char *out;
};
static volatile struct UART_buf xmt = { xmt_buf, (char *)0, (char *)1};
static volatile struct UART_buf rcv = { rcv_buf, (char *)0, (char *)1};
static volatile char _debug_flag = 0;
#if 0
#define SET_RTS(a) {*PORTF0 = (*PORTF0 & ~0x4) | ( (a)? 0 : 0x4); }
#define GET_CTS (!(*PORTF0 & 0x2))
#else
#define SET_RTS(a) {;}
#define GET_CTS 1
#endif
/* _catchSCIint, _catchCTSint, and _catchSPURIOUSint are the
interrupt front-ends */
extern void _catchSCIint();
asm(" .text
.align 2
.globl _catchSCIint
_catchSCIint:
moveml %d0-%d7/%a0-%a6,%sp@- /* save registers */
jbsr uart_interrupt
moveml %sp@+,%d0-%d7/%a0-%a6
rts
");
extern void _catchCTSint();
asm(" .text
.align 2
.globl _catchCTSint
_catchCTSint:
moveml %d0-%d7/%a0-%a6,%sp@- /* save registers */
jbsr cts_interrupt
moveml %sp@+,%d0-%d7/%a0-%a6
rts
");
extern void _catchSPURIOUSint();
asm(" .text
.align 2
.globl _catchSPURIOUSint
_catchSPURIOUSint:
moveml %d0-%d7/%a0-%a6,%sp@- /* save registers */
jbsr spurious_interrupt
moveml %sp@+,%d0-%d7/%a0-%a6
rts
");
int _spurious_int_counter=0;
/* note: cts uses int1. If it "bounces", a spurious interrupt is generated */
void spurious_interrupt(void) {
_spurious_int_counter++; /* there should never be alot of these */
}
/* _fake_trap_1 will continue the UART interrupt (%sr *still*
UART_ISR_LEVEL) as a trap #1 to enter the debugger */
/* *****fix me; this is for 68000 w/jsr ram exception table ******* */
asm(" .text
.align 2
_fake_trap_1:
unlk %a6 /* clear interrupt frame */
lea %sp@(4),%sp /* remove jbsr instruction */
moveml %sp@+,%d0-%d7/%a0-%a6 /* pop registers */
jmp (33*6-12) /* jump exception 1 */
");
/* dispatch UART interrupt */
void xmit_interrupt(void);
void rcvr_interrupt(void);
void _fake_trap_1(void);
void uart_interrupt(void) {
/* receiver status bits are cleared by a SCSR read followed
by a SCDR read. transmitter status bits are cleared by
a SCSR read followed by a SCDR write. */
if ((*SCSR) & (TDRE | TC))
xmit_interrupt();
if ((*SCSR) & (RDRF))
rcvr_interrupt();
if (_debug_flag) {
_debug_flag = 0; /* reset the flag */
_fake_trap_1(); /* fake a trap #1 */
}
}
/* transfer received character to the buffer */
void rcvr_interrupt(void) {
register char *a, c;
register int length;
while((*SCSR) & (RDRF)) {
if ((c=*SCDR) == 0x1a) /* use ctl-z to reboot */
reboot();
/* else if (c == 0x03) { */ /* use ctl-c to enter debugger */
/* _debug_flag = 1; */
/* continue; */
/* } */
*(char *)((int)rcv.offset +(int)
(a=(char *)(((int)rcv.in+1) & ((int)BUFFER_LENGTH-1)))) = c;
if ((char *)(((int)rcv.in+2) & ((int)BUFFER_LENGTH-1)) != rcv.out)
rcv.in=a;
};
length = (BUFFER_LENGTH -1) & (
( ((int)rcv.out <= (int)rcv.in) ? 0 : BUFFER_LENGTH) - (int)rcv.out
+ (int)rcv.in + 1);
if (length >= RTS_STOP_SIZE)
SET_RTS(0);
}
/* tranfer buffered characters to the UART */
void xmit_interrupt(void) {
register short int oldsr;
_CPU_ISR_Disable( oldsr ); /* for when outbyte or flush calls */
while ((*SCSR) & (TDRE)) {
if ((char *)(((int)xmt.in+1) & ((int)BUFFER_LENGTH-1)) != xmt.out)
/* xmit buffer not empty */
if (GET_CTS) {
/* send next char */
*SCDR=*(char *)((int)xmt.offset+(int)xmt.out);
xmt.out= (char *)(((int)xmt.out+1) & ((int)BUFFER_LENGTH-1));
*SCCR1 = (*SCCR1 & ~(TIE | TCIE)) | (TIE);
}
else {
/* configue CTS interrupt and shutdown xmit interrupts */
*SCCR1 &= ~(TIE | TCIE);
*PFPAR |= 0x2;
break;
}
else {
/* xmit buffer empty; shutdown interrupts */
*SCCR1 &= ~(TIE | TCIE);
break;
}
}
_CPU_ISR_Enable( oldsr );
}
void cts_interrupt(void) {
register short int oldsr;
_CPU_ISR_Disable( oldsr ); /* for when outbyte calls */
*PFPAR &= ~0x2;
*SCCR1 = (*SCCR1 & ~(TIE | TCIE)) | (TIE);
_CPU_ISR_Enable( oldsr );
}
/* transfer character from the buffer */
char inbyte(void) {
register char a;
register int length;
while ((char *)(((int)rcv.in+1) & ((int)BUFFER_LENGTH-1))== rcv.out);
a=*(char *)((int)rcv.offset+(int)rcv.out);
rcv.out= (char *)(((int)rcv.out+1) & ((int)BUFFER_LENGTH-1));
length = (BUFFER_LENGTH -1) & (
( ((int)rcv.out <= (int)rcv.in) ? 0 : BUFFER_LENGTH) - (int)rcv.out
+ (int)rcv.in + 1);
if (length < RTS_START_SIZE)
SET_RTS(1);
return (a);
}
/* once room is avaliable in the buffer, transfer
the character into the buffer and enable
the xmtr interrupt */
void outbyte(char c) {
register char *a;
while ((char *)(((int)xmt.in+2) & ((int)BUFFER_LENGTH-1)) == xmt.out);
*(char *)((int)xmt.offset+(int)
(a=(char *)(((int)xmt.in+1) & ((int)BUFFER_LENGTH-1))))=c;
xmt.in=a;
if (!(*SCCR1 & (TIE | TCIE)) && (!(*PFPAR & 0x2)) )
/* if neither interrupts are running, */
xmit_interrupt(); /* we need to restart the xmiter */
}
void _UART_flush(void) {
/* loop till xmt buffer empty. Works with interrupts disabled */
while ((char *)(((int)xmt.in+1) & ((int)BUFFER_LENGTH-1)) != xmt.out)
xmit_interrupt();
/* loop till UART buffer empty */
while ( (*SCSR & TC) == 0 );
}
/* console_initialize
/*PAGE
*
* This routine initializes the console IO driver.
* console_open
*
* Input parameters: NONE
* open a port as a termios console.
*
* Output parameters: NONE
* the console is opened in bsp_postdriver_hook() in bsppost.c
*
* Return values:
*/
void console_init()
{
*QSMCR = ( SAM(QSM_IARB,0,IARB) );
*QILR = ( SAM(ISRL_QSPI,4,ILQSPI) | SAM(ISRL_SCI,0,ILSCI) );
*QIVR = ( SAM(EFI_QIVR,0,INTV) );
*SCCR0 = ( (int)( SYS_CLOCK/SCI_BAUD/32.0+0.5 ) & 0x1fff );
*SCCR1 = ( RIE | TE | RE );
set_vector(_catchSPURIOUSint, EFI_SPINT, 1);
set_vector(_catchSCIint, EFI_QIVR, 1);
/* set_vector(_catchCTSint, EFI_INT1, 1); */
}
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code status;
status = rtems_io_register_name(
"/dev/console",
major,
(rtems_device_minor_number) 0
);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
return RTEMS_SUCCESSFUL;
}
/* is_character_ready
*
* This routine returns TRUE if a character is available.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values:
*/
rtems_boolean is_character_ready(
char *ch
)
{
if ((char *)(((int)rcv.in+1) & ((int)BUFFER_LENGTH-1))== rcv.out)
return(FALSE);
else
return(TRUE);
}
/*
* Open entry point
*/
rtems_device_driver console_open(
@@ -303,11 +38,28 @@ rtems_device_driver console_open(
void * arg
)
{
return RTEMS_SUCCESSFUL;
rtems_status_code status;
/* the console is opened three times at startup */
/* for standard input, output, and error */
/* Get correct callback structure for the device */
/* argument of FALSE gives us interrupt driven serial io */
/* argument of TRUE gives us polling based serial io */
/* SCI internal uart */
status = rtems_termios_open( major, minor, arg, SciGetTermiosHandlers( TRUE ) );
return status;
}
/*
* Close entry point
/*PAGE
*
* console_close
*
* This routine closes a port that has been opened as console.
*/
rtems_device_driver console_close(
@@ -316,11 +68,14 @@ rtems_device_driver console_close(
void * arg
)
{
return RTEMS_SUCCESSFUL;
return rtems_termios_close (arg);
}
/*
* read bytes from the serial port. We only have stdin.
/*PAGE
*
* console_read
*
* This routine uses the termios driver to read a character.
*/
rtems_device_driver console_read(
@@ -329,30 +84,14 @@ rtems_device_driver console_read(
void * arg
)
{
rtems_libio_rw_args_t *rw_args;
char *buffer;
int maximum;
int count;
rw_args = (rtems_libio_rw_args_t *) arg;
buffer = rw_args->buffer;
maximum = rw_args->count;
for (count = 0; count < maximum; count++) {
buffer[ count ] = inbyte();
if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
buffer[ count++ ] = '\n';
break;
}
}
rw_args->bytes_moved = count;
return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
return rtems_termios_read (arg);
}
/*
* write bytes to the serial port. Stdout and stderr are the same.
/*PAGE
*
* console_write
*
* this routine uses the termios driver to write a character.
*/
rtems_device_driver console_write(
@@ -361,29 +100,14 @@ rtems_device_driver console_write(
void * arg
)
{
int count;
int maximum;
rtems_libio_rw_args_t *rw_args;
char *buffer;
rw_args = (rtems_libio_rw_args_t *) arg;
buffer = rw_args->buffer;
maximum = rw_args->count;
for (count = 0; count < maximum; count++) {
if ( buffer[ count ] == '\n') {
outbyte('\r');
}
outbyte( buffer[ count ] );
}
rw_args->bytes_moved = maximum;
return 0;
return rtems_termios_write (arg);
}
/*
* IO Control entry point
/*PAGE
*
* console_control
*
* this routine uses the termios driver to process io
*/
rtems_device_driver console_control(
@@ -392,6 +116,66 @@ rtems_device_driver console_control(
void * arg
)
{
return rtems_termios_ioctl (arg);
}
/*PAGE
*
* console_initialize
*
* Routine called to initialize the console device driver.
*/
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor_arg,
void *arg
)
{
rtems_status_code status;
/*
* initialize the termio interface.
*/
rtems_termios_initialize();
/*
* register the SCI device name for termios
* do this over in the sci driver init routine?
*/
status = rtems_io_register_name( "/dev/sci", major, 0 );
if (status != RTEMS_SUCCESSFUL)
{
rtems_fatal_error_occurred(status);
}
/*
* Link the uart device to the console device
*/
#if 1
status = rtems_io_register_name( "/dev/console", major, 0 );
if (status != RTEMS_SUCCESSFUL)
{
rtems_fatal_error_occurred(status);
}
#else
if ( link( "/dev/sci", "/dev/console") < 0 )
{
rtems_fatal_error_occurred( RTEMS_IO_ERROR );
}
#endif
/*
* Console Initialize Succesful
*/
return RTEMS_SUCCESSFUL;
}

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c/src/lib/libbsp/m68k/mrm332/console/sci.c Normal file
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c/src/lib/libbsp/m68k/mrm332/console/sci.h Normal file
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@@ -0,0 +1,245 @@
/****************************************************************************
* File: sci.h
*
* Desc: This is the include file for the serial communications interface.
*
* Note: See bsp.h,confdefs.h,system.h for installing drivers into RTEMS.
*
* $Id$
****************************************************************************/
#ifndef _sci_h_
#define _sci_h_
/*******************************************************************************
IOCTL commands for the sci driver.
I'm still working on these...
*******************************************************************************/
#define SCI_IOCTL_PARITY_NONE 0x00 // no parity bit after the data bits
#define SCI_IOCTL_PARITY_ODD 0x01 // parity bit added after data bits
#define SCI_IOCTL_PARITY_EVEN 0x02 // parity bit added after data bits
#define SCI_IOCTL_PARITY_MARK 0x03 // parity bit is lo, -12 volts, logical 1
#define SCI_IOCTL_PARITY_SPACE 0x04 // parity bit is hi, +12 volts, logical 0
#define SCI_IOCTL_PARITY_FORCED_ON 0x03 // parity bit is forced hi or lo
#define SCI_IOCTL_PARITY_FORCED_OFF 0x04 // parity bit is forced hi or lo
#define SCI_IOCTL_BAUD_RATE 0x20 // set the baud rate, arg is baud
#define SCI_IOCTL_DATA_BITS 0x30 // set the data bits, arg is # bits
#define SCI_IOCTL_STOP_BITS_1 0x40 // 1 stop bit after char frame
#define SCI_IOCTL_STOP_BITS_2 0x41 // 2 stop bit after char frame
#define SCI_IOCTL_MODE_NORMAL 0x50 // normal operating mode
#define SCI_IOCTL_MODE_LOOP 0x51 // internal loopback mode
#define SCI_IOCTL_FLOW_NONE 0x60 // no flow control
#define SCI_IOCTL_FLOW_RTS_CTS 0x61 // hardware flow control
#define SCI_IOCTL_SEND_BREAK 0x70 // send an rs-232 break
#define SCI_IOCTL_MODE_1200 0x80 // 1200,n,8,1 download mode
#define SCI_IOCTL_MODE_9600 0x81 // 9600,n,8,1 download mode
#define SCI_IOCTL_MODE_9_BIT 0x82 // 9600,forced,8,1 command mode
/*******************************************************************************
SCI Registers
*******************************************************************************/
// SCI Control Register 0 (SCCR0) $FFFC08
// 8 4 2 1 - 8 4 2 1 - 8 4 2 1 - 8 4 2 1
// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
// | | | | | | | | | | | | | | | |
// | | | | | | | | | | | | | | | +----- 0 baud rate divisor
// | | | | | | | | | | | | | | +------- 1 baud rate divisor
// | | | | | | | | | | | | | +--------- 2 baud rate divisor
// | | | | | | | | | | | | +----------- 3 baud rate divisor
// | | | | | | | | | | | |
// | | | | | | | | | | | +--------------- 4 baud rate divisor
// | | | | | | | | | | +----------------- 5 baud rate divisor
// | | | | | | | | | +------------------- 6 baud rate divisor
// | | | | | | | | +--------------------- 7 baud rate divisor
// | | | | | | | |
// | | | | | | | +------------------------- 8 baud rate divisor
// | | | | | | +--------------------------- 9 baud rate divisor
// | | | | | +----------------------------- 10 baud rate divisor
// | | | | +------------------------------- 11 baud rate divisor
// | | | |
// | | | +----------------------------------- 12 baud rate divisor
// | | +------------------------------------- 13 unused
// | +--------------------------------------- 14 unused
// +----------------------------------------- 15 unused
// 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 1 0 0 reset value - (64k baud?)
#define SCI_BAUD_57_6K 9
#define SCI_BAUD_38_4K 14
#define SCI_BAUD_19_2K 27
#define SCI_BAUD_9600 55
#define SCI_BAUD_4800 109
#define SCI_BAUD_2400 218
#define SCI_BAUD_1200 437
// SCI Control Register 1 (SCCR1) $FFFC0A
// 8 4 2 1 - 8 4 2 1 - 8 4 2 1 - 8 4 2 1
// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
// | | | | | | | | | | | | | | | |
// | | | | | | | | | | | | | | | +----- 0 send a break
// | | | | | | | | | | | | | | +------- 1 rcvr wakeup mode
// | | | | | | | | | | | | | +--------- 2 rcvr enable
// | | | | | | | | | | | | +----------- 3 xmtr enable
// | | | | | | | | | | | |
// | | | | | | | | | | | +--------------- 4 idle line intr enable
// | | | | | | | | | | +----------------- 5 rcvr intr enable
// | | | | | | | | | +------------------- 6 xmit complete intr enable
// | | | | | | | | +--------------------- 7 xmtr intr enable
// | | | | | | | |
// | | | | | | | +------------------------- 8 wakeup on address mark
// | | | | | | +--------------------------- 9 mode 1=9 bits, 0=8 bits
// | | | | | +----------------------------- 10 parity enable 1=on, 0=off
// | | | | +------------------------------- 11 parity type 1=odd, 0=even
// | | | |
// | | | +----------------------------------- 12 idle line select
// | | +------------------------------------- 13 wired-or mode
// | +--------------------------------------- 14 loop mode
// +----------------------------------------- 15 unused
// 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 reset value
#define SCI_SEND_BREAK 0x0001 // 0000-0000-0000-0001
#define SCI_RCVR_WAKEUP 0x0002 // 0000-0000-0000-0010
#define SCI_ENABLE_RCVR 0x0004 // 0000-0000-0000-0100
#define SCI_ENABLE_XMTR 0x0008 // 0000-0000-0000-1000
#define SCI_DISABLE_RCVR 0xFFFB // 1111-1111-1111-1011
#define SCI_DISABLE_XMTR 0xFFF7 // 1111-1111-1111-0111
#define SCI_ENABLE_INT_IDLE 0x0010 // 0000-0000-0001-0000
#define SCI_ENABLE_INT_RX 0x0020 // 0000-0000-0010-0000
#define SCI_ENABLE_INT_TX_DONE 0x0040 // 0000-0000-0100-0000
#define SCI_ENABLE_INT_TX 0x0080 // 0000-0000-1000-0000
#define SCI_DISABLE_INT_ALL 0xFF00 // 1111-1111-0000-0000 ???
#define SCI_DISABLE_INT_RX 0xFFDF // 1111-1111-1101-1111
#define SCI_CLEAR_RX_INT 0xFFBF // 1111-1111-1011-1111
#define SCI_DISABLE_INT_TX 0xFF7F // 1111-1111-0111-1111
#define SCI_CLEAR_TDRE 0xFEFF // 1111-1110-1111-1111
#define SCI_RCVR_WAKE_ON_MARK 0x0100 // 0000-0001-0000-0000
#define SCI_9_DATA_BITS 0x0200 // 0000-0010-0000-0000
#define SCI_PARITY_ENABLE 0x0400 // 0000-0100-0000-0000
#define SCI_PARITY_ODD 0x0800 // 0000-1000-0000-0000
#define SCI_RCVR_WAKE_ON_IDLE 0xFEFF // 1111-1110-1111-1111
#define SCI_8_DATA_BITS 0xFDFF // 1111-1101-1111-1111
#define SCI_PARITY_DISABLE 0xFBFF // 1111-1011-1111-1111
#define SCI_PARITY_EVEN 0xF7FF // 1111-0111-1111-1111
#define SCI_PARITY_NONE 0xF3FF // 1111-0011-1111-1111
#define SCI_IDLE_LINE_LONG 0x1000 // 0001-0000-0000-0000
#define SCI_TXD_OPEN_DRAIN 0x2000 // 0010-0000-0000-0000
#define SCI_LOOPBACK_MODE 0x4000 // 0100-0000-0000-0000
#define SCI_SCCR1_UNUSED 0x8000 // 1000-0000-0000-0000
// SCI Status Register (SCSR) $FFFC0C
// 8 4 2 1 - 8 4 2 1 - 8 4 2 1 - 8 4 2 1
// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
// | | | | | | | | | | | | | | | |
// | | | | | | | | | | | | | | | +----- 0 PF - parity error
// | | | | | | | | | | | | | | +------- 1 FE - framing error
// | | | | | | | | | | | | | +--------- 2 NF - noise flag
// | | | | | | | | | | | | +----------- 3 OR - overrun flag
// | | | | | | | | | | | |
// | | | | | | | | | | | +--------------- 4 IDLE - idle line detected
// | | | | | | | | | | +----------------- 5 RAF - rcvr active flag
// | | | | | | | | | +------------------- 6 RDRF - rcv data reg full
// | | | | | | | | +--------------------- 7 TC - xmt complete flag
// | | | | | | | |
// | | | | | | | +------------------------- 8 TDRE - xmt data reg empty
// | | | | | | +--------------------------- 9 always zero
// | | | | | +----------------------------- 10 always zero
// | | | | +------------------------------- 11 always zero
// | | | |
// | | | +----------------------------------- 12 always zero
// | | +------------------------------------- 13 always zero
// | +--------------------------------------- 14 always zero
// +----------------------------------------- 15 always zero
// 0 0 0 0 - 0 0 0 1 - 1 0 0 0 - 0 0 0 0 reset value
#define SCI_ERROR_PARITY 0x0001 // 0000-0000-0000-0001
#define SCI_ERROR_FRAMING 0x0002 // 0000-0000-0000-0010
#define SCI_ERROR_NOISE 0x0004 // 0000-0000-0000-0100
#define SCI_ERROR_OVERRUN 0x0008 // 0000-0000-0000-1000
#define SCI_IDLE_LINE 0x0010 // 0000-0000-0001-0000
#define SCI_RCVR_ACTIVE 0x0020 // 0000-0000-0010-0000
#define SCI_RCVR_READY 0x0040 // 0000-0000-0100-0000
#define SCI_XMTR_IDLE 0x0080 // 0000-0000-1000-0000
#define SCI_CLEAR_RX_INT 0xFFBF // 1111-1111-1011-1111
#define SCI_XMTR_READY 0x0100 // 0000-0001-0000-0000
#define SCI_CLEAR_TDRE 0xFEFF // 1111-1110-1111-1111
#define SCI_XMTR_AVAILABLE 0x0180 // 0000-0001-1000-0000
/*******************************************************************************
Function prototypes
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
// look at console_open to see how this is called
const rtems_termios_callbacks * SciGetTermiosHandlers( signed32 polled );
/* SCI interrupt */
//rtems_isr SciIsr( rtems_vector_number vector );
//signed32 SciOpenPolled ( signed32 major, signed32 minor, void *arg );
//signed32 SciOpenInterrupt ( signed32 major, signed32 minor, void *arg );
//signed32 SciClose ( signed32 major, signed32 minor, void *arg );
//signed32 SciWritePolled ( signed32 minor, const char *buf, signed32 len );
//signed32 SciWriteInterrupt( signed32 minor, const char *buf, signed32 len );
//signed32 SciReadPolled ( signed32 minor );
//signed32 SciSetAttributes ( signed32 minor, const struct termios *t );
#ifdef __cplusplus
}
#endif
#endif // _sci_h_

6
c/src/lib/libbsp/m68k/mrm332/include/bsp.h
View File

@@ -22,6 +22,7 @@ extern "C" {
#include <bspopts.h>
#include <rtems.h>
#include <rtems/bspIo.h>
#include <clockdrv.h>
#include <console.h>
#include <iosupp.h>
@@ -35,6 +36,7 @@ extern "C" {
* - Interrupt stack space is not minimum if defined.
*/
#define CONSOLE_SCI
/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
/* #define CONFIGURE_INTERRUPT_STACK_MEMORY (TBD * 1024) */
@@ -102,7 +104,7 @@ extern char _copy_data_from_rom[];
#define RAW_PUTS(str) \
{ register char *ptr = str; \
while (*ptr) outbyte(*ptr++); \
while (*ptr) SCI_output_char(*ptr++); \
}
#define RAW_PUTI(n) { \
@@ -111,7 +113,7 @@ extern char _copy_data_from_rom[];
RAW_PUTS("0x"); \
for (i=28;i>=0;i -= 4) { \
j = (n>>i) & 0xf; \
outbyte( (j>9 ? j-10+'a' : j+'0') ); \
SCI_output_char( (j>9 ? j-10+'a' : j+'0') ); \
} \
}

8
c/src/lib/libbsp/m68k/mrm332/include/mrm332.h
View File

@@ -33,7 +33,7 @@
/* System Clock definitions */
#define XTAL 32768.0 /* crystal frequency in Hz */
#if 0
#if 1
/* Default MRM clock rate (8.388688 MHz) set by CPU32: */
#define MRM_W 0 /* system clock parameters */
#define MRM_X 0
@@ -47,7 +47,7 @@
#define MRM_Y 0x0f
#endif
#if 1
#if 0
/* 25.16582 MHz: */
#define MRM_W 1 /* system clock parameters */
#define MRM_X 1
@@ -60,6 +60,8 @@
/* macros/functions */
#ifndef ASM
/*
* This prototype really should have the noreturn attribute but
* that causes a warning. Not sure how to fix that.
@@ -68,4 +70,6 @@
static void reboot(void);
__inline__ static void reboot() {asm("trap #15; .word 0x0063");}
#endif /* ASM */
#endif /* _MRM_H_ */

10
c/src/lib/libbsp/m68k/mrm332/spurious/spinit.c
View File

@@ -33,7 +33,7 @@ rtems_isr Spurious_Isr(
rtems_vector_number vector
)
{
int sp = 0;
//int sp = 0;
const char * const VectDescrip[] = {
_Spurious_Error_[0], _Spurious_Error_[0], _Spurious_Error_[1],
_Spurious_Error_[2], _Spurious_Error_[3], _Spurious_Error_[4],
@@ -58,11 +58,11 @@ rtems_isr Spurious_Isr(
_Spurious_Error_[27], _Spurious_Error_[27], _Spurious_Error_[27],
_Spurious_Error_[27], _Spurious_Error_[28]};
asm volatile ( "movea.l %%sp,%0 " : "=a" (sp) : "0" (sp) );
//asm volatile ( "movea.l %%sp,%0 " : "=a" (sp) : "0" (sp) );
_CPU_ISR_Set_level( 7 );
_UART_flush();
//_UART_flush();
#if 0
RAW_PUTS("\n\rRTEMS: Spurious interrupt: ");
RAW_PUTS((char *)VectDescrip[( (vector>64) ? 64 : vector )]);
RAW_PUTS("\n\rRTEMS: Vector: ");
@@ -70,7 +70,7 @@ rtems_isr Spurious_Isr(
RAW_PUTS(" sp: ");
RAW_PUTI(sp);
RAW_PUTS("\n\r");
#endif
bsp_cleanup();
/* BDM SIGEMT */

8
c/src/lib/libbsp/m68k/mrm332/start/Makefile.am
View File

@@ -6,10 +6,10 @@ AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/start.o
C_FILES = start.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
S_FILES = start.S
S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
OBJS = $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/compile.am
@@ -28,6 +28,6 @@ all-local: $(ARCH) $(OBJS) $(PGM) $(TMPINSTALL_FILES)
.PRECIOUS: $(PGM)
EXTRA_DIST = start.c
EXTRA_DIST = start.S
include $(top_srcdir)/../../../../../../automake/local.am

151
c/src/lib/libbsp/m68k/mrm332/start/start.S Normal file
View File

@@ -0,0 +1,151 @@
/*
* $Id
*/
#include "mrm332.h"
#include "asm.h"
#include <sim.h>
BEGIN_CODE
/* Put the header necessary for the modified CPU32bug to automatically
start up rtems: */
#if 0
.long 0xbeefbeef ;
#endif
.long 0 ;
.long start ;
.global start
start:
oriw #0x0700,sr
movel #end, d0
addl #_StackSize,d0
movel d0,sp
movel d0,a6
/* include in ram_init.S */
/*
* Initalize the SIM module.
* The stack pointer is not usable until the RAM chip select lines
* are configured. The following code must remain inline.
*/
/* Module Configuration Register */
/* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
lea SIMCR, a0
movew #FRZSW,d0
oriw #SAM(0,8,SHEN),d0
oriw #(MM*SIM_MM),d0
oriw #SAM(SIM_IARB,0,IARB),d0
movew d0, a0@
jsr start_c /* Jump to the C startup code */
END_CODE
#if 0
/* Synthesizer Control Register */
/* see section(s) 4.8 */
/* end include in ram_init.S */
*SYNCR = (unsigned short int)
( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
/* include in ram_init.S */
*SYNCR = (unsigned short int)
( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
/* System Protection Control Register */
/* !!! can only write to once after reset !!! */
/* see section 3.8.4 of the SIM Reference Manual */
*SYPCR = (unsigned char)( HME | BME );
/* Periodic Interrupr Control Register */
/* see section 3.8.2 of the SIM Reference Manual */
*PICR = (unsigned short int)
( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) );
/* ^^^ zero disables interrupt, don't enable here or ram_init will
be wrong. It's enabled below. */
/* Periodic Interrupt Timer Register */
/* see section 3.8.3 of the SIM Reference Manual */
*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
/* 1.098mS interrupt, assuming 32.768 KHz input clock */
/* Port C Data */
/* load values before enabled */
*PORTC = (unsigned char) 0x0;
/* Port E and F Data Register */
/* see section 9 of the SIM Reference Manual */
*PORTE0 = (unsigned char) 0;
*PORTF0 = (unsigned char) 0;
/* Port E and F Data Direction Register */
/* see section 9 of the SIM Reference Manual */
*DDRE = (unsigned char) 0xff;
*DDRF = (unsigned char) 0xfd;
/* Port E and F Pin Assignment Register */
/* see section 9 of the SIM Reference Manual */
*PEPAR = (unsigned char) 0;
*PFPAR = (unsigned char) 0;
/* end of SIM initalization code */
/* end include in ram_init.S */
/*
* Initialize RAM by copying the .data section out of ROM (if
* needed) and "zero-ing" the .bss section.
*/
{
register char *src = _etext;
register char *dst = _copy_start;
if (_copy_data_from_rom)
/* ROM has data at end of text; copy it. */
while (dst < _edata)
*dst++ = *src++;
/* Zero bss */
for (dst = _clear_start; dst< end; dst++)
{
*dst = 0;
}
}
/*
* Initialize vector table.
*/
{
m68k_isr_entry *monitors_vector_table;
m68k_get_vbr(monitors_vector_table);
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */
m68k_set_vbr(&M68Kvec);
}
/*
* Initalize the board.
*/
Spurious_Initialize();
console_init();
/*
* Execute main with arguments argc and agrv.
*/
boot_card(1,__argv);
reboot();
}
#endif

259
c/src/lib/libbsp/m68k/mrm332/start/start.c
View File

@@ -1,259 +0,0 @@
/*
* $Id
*/
#include <mrm332.h>
#include <sim.h>
#define __START_C__
#include "bsp.h"
m68k_isr_entry M68Kvec[256];
m68k_isr_entry vectors[256];
char * const __argv[]= {"main", ""};
void boot_card(int argc, char * const argv[]);
/*
* This prototype really should have the noreturn attribute but
* that causes a warning. Not sure how to fix that.
*/
/* void dumby_start () __attribute__ ((noreturn)); */
void dumby_start ();
void dumby_start() {
/* Put the header necessary for the modified CPU32bug to automatically
start up rtems: */
asm volatile ( ".long 0xbeefbeef ;
.long 0 ;
.long start");
/* We need to by-pass the link instruction since the RAM chip-
select pins are not yet configured. */
asm volatile ( ".global start ;
start:");
/* disable interrupts, copy CPU32bug vectors, load stack pointer */
asm volatile ( "oriw #0x0700, %sr;
movel #end, %d0;
addl #_StackSize,%d0;
movel %d0,%sp;
movel %d0,%a6"
);
/* include in ram_init.S */
/*
* Initalize the SIM module.
* The stack pointer is not usable until the RAM chip select lines
* are configured. The following code must remain inline.
*/
/* Module Configuration Register */
/* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
*SIMCR = (unsigned short int)
(FRZSW | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
/* Synthesizer Control Register */
/* see section(s) 4.8 */
/* end include in ram_init.S */
*SYNCR = (unsigned short int)
( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
/* include in ram_init.S */
*SYNCR = (unsigned short int)
( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
/* System Protection Control Register */
/* !!! can only write to once after reset !!! */
/* see section 3.8.4 of the SIM Reference Manual */
*SYPCR = (unsigned char)( HME | BME );
/* Periodic Interrupr Control Register */
/* see section 3.8.2 of the SIM Reference Manual */
*PICR = (unsigned short int)
( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) );
/* ^^^ zero disables interrupt, don't enable here or ram_init will
be wrong. It's enabled below. */
/* Periodic Interrupt Timer Register */
/* see section 3.8.3 of the SIM Reference Manual */
*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
/* 1.098mS interrupt, assuming 32.768 KHz input clock */
/* Port C Data */
/* load values before enabled */
*PORTC = (unsigned char) 0x0;
#if 0
/* Don't touch these on MRM, they are set up by CPU32bug at boot time. */
/* Chip-Select Base Address Register */
/* see section 7 of the SIM Reference Manual */
*CSBARBT = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
*CSBAR0 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_1M ); /* 1M bytes located at 0x0000 */
*CSBAR1 = (unsigned short int)
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
*CSBAR2 = (unsigned short int)
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
*CSBAR3 = (unsigned short int)
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
*CSBAR4 = (unsigned short int)
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
*CSBAR5 = (unsigned short int)
(0xfff8 | BS_64K); /* AVEC interrupts */
#if 0
#ifdef EFI332_v040b
*CSBAR6 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
*CSBAR8 = (unsigned short int) /* PCMCIA IOCS */
(((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */
*CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */
(((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */
#else /* EFI332_v040b */
*CSBAR10 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
#endif /* EFI332_v040b */
#endif
/* Chip-Select Options Registers */
/* see section 7 of the SIM Reference Manual */
#ifdef FLASHWRITE
*CSORBT = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | WaitStates_0 | UserSupSpace );
#else /* FLASHWRITE */
*CSORBT = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | WaitStates_0 | UserSupSpace );
#endif /* FLASHWRITE */
*CSOR0 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
*CSOR1 = (unsigned short int)
( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR2 = (unsigned short int)
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR3 = (unsigned short int)
( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR4 = (unsigned short int)
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR5 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
#if 0
#ifdef EFI332_v040b
*CSOR6 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
*CSOR8 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
*CSOR9 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
#else /* EFI332_v040b */
*CSOR10 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
#endif /* EFI332_v040b */
#endif
/* Chip Select Pin Assignment Register 0 */
/* see section 7 of the SIM Reference Manual */
*CSPAR0 = (unsigned short int)(
SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */
SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */
SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */
SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */
SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */
SAM(CS16bit,CS_0,0x000c)| /* W/!R */
SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */
);
/* Chip Select Pin Assignment Register 1 */
/* see section 7 of the SIM Reference Manual */
#ifdef EFI332_v040b
*CSPAR1 = (unsigned short int)(
SAM(DisOut,CS_10,0x300)| /* ECLK */
SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */
SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */
SAM(DisOut,CS_7,0x00c) | /* PC4 */
SAM(CS16bit,CS_6,0x003) /* ROM !OE */
);
#else /* EFI332_v040b */
*CSPAR1 = (unsigned short int)(
SAM(CS16bit,CS_10,0x300)| /* ROM !OE */
SAM(DisOut,CS_9,0x0c0) | /* PC6 */
SAM(DisOut,CS_8,0x030) | /* PC5 */
SAM(DisOut,CS_7,0x00c) | /* PC4 */
SAM(DisOut,CS_6,0x003) /* PC3 */
);
#endif /* EFI332_v040b */
#endif /* Don't touch on MRM */
/* Port E and F Data Register */
/* see section 9 of the SIM Reference Manual */
*PORTE0 = (unsigned char) 0;
*PORTF0 = (unsigned char) 0;
/* Port E and F Data Direction Register */
/* see section 9 of the SIM Reference Manual */
*DDRE = (unsigned char) 0xff;
*DDRF = (unsigned char) 0xfd;
/* Port E and F Pin Assignment Register */
/* see section 9 of the SIM Reference Manual */
*PEPAR = (unsigned char) 0;
*PFPAR = (unsigned char) 0;
/* end of SIM initalization code */
/* end include in ram_init.S */
/*
* Initialize RAM by copying the .data section out of ROM (if
* needed) and "zero-ing" the .bss section.
*/
{
register char *src = _etext;
register char *dst = _copy_start;
if (_copy_data_from_rom)
/* ROM has data at end of text; copy it. */
while (dst < _edata)
*dst++ = *src++;
/* Zero bss */
for (dst = _clear_start; dst< end; dst++)
{
*dst = 0;
}
}
/*
* Initialize vector table.
*/
{
m68k_isr_entry *monitors_vector_table;
m68k_get_vbr(monitors_vector_table);
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */
m68k_set_vbr(&M68Kvec);
}
/*
* Initalize the board.
*/
Spurious_Initialize();
console_init();
/*
* Execute main with arguments argc and agrv.
*/
boot_card(1,__argv);
reboot();
}

2
c/src/lib/libbsp/m68k/mrm332/startup/Makefile.am
View File

@@ -8,7 +8,7 @@ VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared
PGM = $(ARCH)/startup.rel
C_FILES = bsplibc.c bsppost.c bspstart.c bspclean.c bootcard.c \
C_FILES = start_c.c bsplibc.c bsppost.c bspstart.c bspclean.c bootcard.c \
m68kpretaskinghook.c main.c sbrk.c setvec.c gnatinstallhandler.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)

2
c/src/lib/libbsp/m68k/mrm332/startup/bspclean.c
View File

@@ -23,5 +23,5 @@ void bsp_cleanup(void)
{
/* interrupt driven stdio must be flushed */
_CPU_ISR_Set_level( 7 );
_UART_flush();
//_UART_flush();
}

4
c/src/lib/libbsp/m68k/mrm332/startup/linkcmds
View File

@@ -34,10 +34,10 @@ __DYNAMIC = 0;
* Declare some sizes.
*/
_RamBase = DEFINED(_RamBase) ? _RamBase : 0x03000;
_RamSize = DEFINED(_RamSize) ? _RamSize : 0x80000;
_RamSize = DEFINED(_RamSize) ? _RamSize : 0x7d000;
_RamEnd = _RamBase + _RamSize;
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
MEMORY
{

124
c/src/lib/libbsp/m68k/mrm332/startup/start_c.c Normal file
View File

@@ -0,0 +1,124 @@
/*
* $Id
*/
#include <mrm332.h>
#include <sim.h>
#define __START_C__
#include "bsp.h"
m68k_isr_entry M68Kvec[256];
m68k_isr_entry vectors[256];
char * const __argv[]= {"main", ""};
void boot_card(int argc, char * const argv[]);
/*
* This prototype really should have the noreturn attribute but
* that causes a warning. Not sure how to fix that.
*/
/* void dumby_start () __attribute__ ((noreturn)); */
void start_c ();
void start_c() {
/* Synthesizer Control Register */
/* see section(s) 4.8 */
/* end include in ram_init.S */
*SYNCR = (unsigned short int)
( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
/* include in ram_init.S */
*SYNCR = (unsigned short int)
( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
/* System Protection Control Register */
/* !!! can only write to once after reset !!! */
/* see section 3.8.4 of the SIM Reference Manual */
*SYPCR = (unsigned char)( HME | BME );
/* Periodic Interrupr Control Register */
/* see section 3.8.2 of the SIM Reference Manual */
*PICR = (unsigned short int)
( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) );
/* ^^^ zero disables interrupt, don't enable here or ram_init will
be wrong. It's enabled below. */
/* Periodic Interrupt Timer Register */
/* see section 3.8.3 of the SIM Reference Manual */
*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
/* 1.098mS interrupt, assuming 32.768 KHz input clock */
/* Port C Data */
/* load values before enabled */
*PORTC = (unsigned char) 0x0;
/* Port E and F Data Register */
/* see section 9 of the SIM Reference Manual */
*PORTE0 = (unsigned char) 0;
*PORTF0 = (unsigned char) 0;
/* Port E and F Data Direction Register */
/* see section 9 of the SIM Reference Manual */
*DDRE = (unsigned char) 0xff;
*DDRF = (unsigned char) 0xfd;
/* Port E and F Pin Assignment Register */
/* see section 9 of the SIM Reference Manual */
*PEPAR = (unsigned char) 0;
*PFPAR = (unsigned char) 0;
/* end of SIM initalization code */
/* end include in ram_init.S */
/*
* Initialize RAM by copying the .data section out of ROM (if
* needed) and "zero-ing" the .bss section.
*/
{
register char *src = _etext;
register char *dst = _copy_start;
if (_copy_data_from_rom)
/* ROM has data at end of text; copy it. */
while (dst < _edata)
*dst++ = *src++;
/* Zero bss */
for (dst = _clear_start; dst< end; dst++)
{
*dst = 0;
}
}
/*
* Initialize vector table.
*/
{
m68k_isr_entry *monitors_vector_table;
m68k_get_vbr(monitors_vector_table);
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */
m68k_set_vbr(&M68Kvec);
}
/*
* Initalize the board.
*/
Spurious_Initialize();
//console_init();
/*
* Execute main with arguments argc and agrv.
*/
boot_card(1,__argv);
reboot();
}