2011-06-17 Sebastian Huber <sebastian.huber@embedded-brains.de>

* Makefile.am: Added custom memcpy().  Update for network sources.
	* configure.ac: Enable interrupt driven Termios for all BSPs.
	* ide/pcmcia_ide.c: Disable broken DMA support.
	* include/bsp.h: Fixed NEED_LOW_LEVEL_INIT define.  Set default
	console baud to 115200.
	* include/irq.h, irq/irq.c: Fixed interrupt handling to avoid the
	following problems: 1. multiple invokation of peripheral interrupt
	handlers, 2. missing synchronization after mask write and enabling of
	external exceptions, and 3. logic overhead.
	* network_5200/network.c: Added MII interface.  Fixed controller
	restart after FIFO errors.  Performance improvements.
	* start/start.S: Fixed ROM startup.  Initialize XLB arbiter for all
	BSPs.
	* startup/bspstart.c: Special intialization for MPC5200B (B variant).
	Install standard alignment handler.
	* startup/cpuinit.c, startup/linkcmds.brs5l, startup/linkcmds.dp2,
	startup/linkcmds.icecube, startup/linkcmds.pm520_cr825,
	startup/linkcmds.pm520_ze30: Avoid accesses outside the RAM area.

c/src/lib/libbsp/powerpc/gen5200/ChangeLog

@@ -1,3 +1,24 @@
+2011-06-17	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* Makefile.am: Added custom memcpy().  Update for network sources.
+	* configure.ac: Enable interrupt driven Termios for all BSPs.
+	* ide/pcmcia_ide.c: Disable broken DMA support.
+	* include/bsp.h: Fixed NEED_LOW_LEVEL_INIT define.  Set default
+	console baud to 115200.
+	* include/irq.h, irq/irq.c: Fixed interrupt handling to avoid the
+	following problems: 1. multiple invokation of peripheral interrupt
+	handlers, 2. missing synchronization after mask write and enabling of
+	external exceptions, and 3. logic overhead.
+	* network_5200/network.c: Added MII interface.  Fixed controller
+	restart after FIFO errors.  Performance improvements.
+	* start/start.S: Fixed ROM startup.  Initialize XLB arbiter for all
+	BSPs.
+	* startup/bspstart.c: Special intialization for MPC5200B (B variant).
+	Install standard alignment handler.
+	* startup/cpuinit.c, startup/linkcmds.brs5l, startup/linkcmds.dp2,
+	startup/linkcmds.icecube, startup/linkcmds.pm520_cr825,
+	startup/linkcmds.pm520_ze30: Avoid accesses outside the RAM area.
+
 2011-06-07	Sebastian Huber <sebastian.huber@embedded-brains.de>
 
 	* configure.ac, startup/bspstart.c: Use standard cache BSP options.

c/src/lib/libbsp/powerpc/gen5200/Makefile.am

@@ -142,17 +142,13 @@ libbsp_a_SOURCES += ../../shared/bootcard.c \
 	startup/bspreset.c \
 	../../shared/bspgetworkarea.c \
 	../shared/startup/bspidle.c \
+	../shared/src/memcpy.c \
 	startup/bspstart.c \
 	startup/cpuinit.c  \
 	startup/uboot_support.c
 
 if HAS_NETWORKING
-network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
+libbsp_a_SOURCES += network_5200/network.c
-network_CPPFLAGS += -D__BSD_VISIBLE
-noinst_PROGRAMS += network.rel
-network_rel_SOURCES = network_5200/network.c
-network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
-network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
 libbsp_a_LIBADD =  ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
@@ -163,9 +159,5 @@ libbsp_a_LIBADD =  ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
 	../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
 	../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
 
-if HAS_NETWORKING
-libbsp_a_LIBADD += network.rel
-endif
-
 include $(srcdir)/preinstall.am
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/powerpc/gen5200/configure.ac

@@ -82,11 +82,10 @@ RTEMS_BSPOPTS_HELP([BSP_UART_AVAIL_MASK],
 RTEMS_BSPOPTS_SET([MPC5200_PSC_INDEX_FOR_GPS_MODULE],[dp2],[5])
 RTEMS_BSPOPTS_HELP([MPC5200_PSC_INDEX_FOR_GPS_MODULE],[PSC index for GPS module, if defined results in '/dev/gps'])
 
-RTEMS_BSPOPTS_SET([SINGLE_CHAR_MODE],[dp2],[])
+RTEMS_BSPOPTS_SET([SINGLE_CHAR_MODE],[*],[])
-RTEMS_BSPOPTS_SET([SINGLE_CHAR_MODE],[*],[1])
 RTEMS_BSPOPTS_HELP([SINGLE_CHAR_MODE],[enable single character mode for the PSC console driver])
 
-RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS_INT],[dp2],[1])
+RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS_INT],[*],[1])
 RTEMS_BSPOPTS_HELP([UARTS_USE_TERMIOS_INT],[enable interrupt support for the PSC console driver])
 
 RTEMS_BSPOPTS_SET([PRINTK_MINOR],[dp2],[1])

c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c

@@ -92,23 +92,13 @@
 #endif
 #define IDE_DMA_TEST            FALSE
 
-#ifdef BRS5L
+/* DMA supported PIO mode is broken */
-#define IDE_USE_INT             TRUE
-#define IDE_READ_USE_DMA        TRUE
-#define IDE_USE_READ_PIO_OPT    FALSE
-#define IDE_WRITE_USE_DMA       TRUE
-#define IDE_USE_WRITE_PIO_OPT   TRUE
-/* #define IDE_USE_DMA (IDE_READ_USE_DMA||IDE_WRITE_USE_DMA) */
-#define IDE_USE_DMA             TRUE
-#else
 #define IDE_USE_INT             TRUE
 #define IDE_READ_USE_DMA        FALSE
 #define IDE_USE_READ_PIO_OPT    FALSE
 #define IDE_WRITE_USE_DMA       FALSE
 #define IDE_USE_WRITE_PIO_OPT   FALSE
-/* #define IDE_USE_DMA (IDE_READ_USE_DMA||IDE_WRITE_USE_DMA) */
+#define IDE_USE_DMA (IDE_READ_USE_DMA || IDE_WRITE_USE_DMA)
-#define IDE_USE_DMA             FALSE
-#endif
 
 #define IDE_USE_STATISTICS      TRUE
 
@@ -464,6 +454,7 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write,
         (*cbuf)++;
         (*pos) += bufs[bufs_from_dma].length;
         bufs_from_dma++;
+        bds_free++;
 	  }
     } while ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) &&
              (nxt_bd_idx != TASK_ERR_BD_BUSY)       &&

c/src/lib/libbsp/powerpc/gen5200/include/bsp.h

@@ -79,6 +79,11 @@ LINKER_SYMBOL(MBAR);
 #define PM520
 #endif
 
+#if !defined(HAS_UBOOT)
+  /* we need the low level initialization in start.S*/
+  #define NEED_LOW_LEVEL_INIT
+#endif
+
 #if defined(BRS5L)
 /*
  * IMD Custom Board BRS5L
@@ -118,11 +123,6 @@ extern "C" {
 #include <bsp/vectors.h>
 #include <bsp/u-boot.h>
 
-#if !defined(HAS_UBOOT)
-  /* we need the low level initialization in start.S*/
-  #define NEED_LOW_LEVEL_INIT
-#endif
-
 /*
  * Network driver configuration
  */
@@ -179,7 +179,7 @@ extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig
 #if defined(HAS_UBOOT)
 #define GEN5200_CONSOLE_BAUD (bsp_uboot_board_info.bi_baudrate)
 #else
-#define GEN5200_CONSOLE_BAUD 9600
+#define GEN5200_CONSOLE_BAUD 115200
 #endif
 
 /*

c/src/lib/libbsp/powerpc/gen5200/include/irq.h

@@ -87,16 +87,13 @@
 #ifndef LIBBSP_POWERPC_GEN5200_IRQ_H
 #define LIBBSP_POWERPC_GEN5200_IRQ_H
 
-#define CHK_CE_SHADOW(_pmce)	((_pmce) & 0x00000001)
+#define PMCE_CE_SHADOW (1U << (31 - 31))
-#define CHK_CSE_STICKY(_pmce)	(((_pmce) >> 10) & 0x00000001)
+#define PMCE_CSE_STICKY (1U << (31 - 21))
-#define CHK_MSE_STICKY(_pmce)	(((_pmce) >> 21) & 0x00000001)
+#define PMCE_MSE_STICKY (1U << (31 - 10))
-#define CHK_PSE_STICKY(_pmce)	(((_pmce) >> 29) & 0x00000001)
+#define PMCE_PSE_STICKY (1U << (31 - 2))
-#define CLR_CSE_STICKY(_pmce)	((_pmce) |= (1 << 29 ))
+#define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U)
-#define CLR_MSE_STICKY(_pmce)	((_pmce) |= (1 << 21 ))
+#define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU)
-#define CLR_PSE_STICKY(_pmce)	((_pmce) |= (1 << 10 ))
+#define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU)
-#define CSE_SOURCE(_source)	(((_source) >> 8) & 0x00000003)
-#define MSE_SOURCE(_source)	(((_source) >> 16) & 0x0000001F)
-#define PSE_SOURCE(_source)	(((_source) >> 24) & 0x0000001F)
 
 /*
  * Peripheral IRQ handlers related definitions

c/src/lib/libbsp/powerpc/gen5200/irq/irq.c

@@ -171,10 +171,6 @@ static inline void BSP_enable_per_irq_at_siu(
   uint8_t lo_hi_ind = 0,
     prio_index_offset;
   uint32_t *reg;
-  volatile uint32_t per_pri_1,
-    main_pri_1,
-    crit_pri_main_mask,
-    per_mask;
 
   /* calculate the index offset of priority value bit field */
   prio_index_offset = (irqLine - BSP_PER_IRQ_LOWEST_OFFSET) % 8;
@@ -223,11 +219,11 @@ static inline void BSP_enable_per_irq_at_siu(
   /* enable (unmask) peripheral interrupt */
   mpc5200.per_mask &= ~(0x80000000 >> SIU_MaskBit [irqLine]);
 
-  main_pri_1 = mpc5200.main_pri_1;
+  /* FIXME: Why? */
-  crit_pri_main_mask = mpc5200.crit_pri_main_mask;
+  mpc5200.main_pri_1;
-  per_pri_1 = mpc5200.per_pri_1;
+  mpc5200.crit_pri_main_mask;
-  per_mask = mpc5200.per_mask;
+  mpc5200.per_pri_1;
-
+  mpc5200.per_mask;
 }
 
 static inline void BSP_enable_main_irq_at_siu(
@@ -484,15 +480,15 @@ static void dispatch(uint32_t irq, uint32_t offset, volatile uint32_t *maskreg)
 {
   #if (ALLOW_IRQ_NESTING == 1)
     uint32_t msr;
-  #endif
-
     uint32_t mask = *maskreg;
+  #endif
 
   irq += offset;
 
-  *maskreg = mask | irqMaskTable [irq];
-
   #if (ALLOW_IRQ_NESTING == 1)
+    *maskreg = mask | irqMaskTable [irq];
+    /* Make sure that the write operation completed (cache inhibited area) */
+    *maskreg;
     msr = ppc_external_exceptions_enable();
   #endif
 
@@ -500,9 +496,8 @@ static void dispatch(uint32_t irq, uint32_t offset, volatile uint32_t *maskreg)
 
   #if (ALLOW_IRQ_NESTING == 1)
     ppc_external_exceptions_disable(msr);
-  #endif
-
     *maskreg = mask;
+  #endif
 }
 
 /*
@@ -526,35 +521,36 @@ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum)
     printk( "not counting %d\n", excNum);
 #endif
 
-  switch (excNum) {
-      /*
-       * Handle decrementer interrupt
-       */
-    case ASM_DEC_VECTOR:
-
-      /* Dispatch interrupt handlers */
-      bsp_interrupt_handler_dispatch( BSP_DECREMENTER);
-
-      break;
-
-    case ASM_EXT_VECTOR:
-    case ASM_60X_SYSMGMT_VECTOR:
   /* get the content of main interrupt status register */
   pmce = mpc5200.pmce;
 
-      /* critical interrupts may be routed to the core_int
+  /* critical interrupts are routed to the core_int, see premature
-       * dependent on premature initialization, see bit 31 (CEbsH)
+   * initialization
    */
-      while ((CHK_CE_SHADOW( pmce) && CHK_CSE_STICKY( pmce))
+  while ((pmce & (PMCE_CSE_STICKY | PMCE_MSE_STICKY)) != 0) {
-             || CHK_MSE_STICKY( pmce) || CHK_PSE_STICKY( pmce)) {
-
     /* first: check for critical interrupt sources (hierarchical order)
      * -> HI_int indicates peripheral sources
      */
-        if (CHK_CE_SHADOW( pmce) && CHK_CSE_STICKY( pmce)) {
+    if ((pmce & PMCE_CSE_STICKY) != 0) {
       /* get source of critical interrupt */
-          irq = CSE_SOURCE( pmce);
+      irq = PMCE_CSE_SOURCE(pmce);
+
       switch (irq) {
+          /* peripheral HI_int interrupt source detected */
+        case 2:
+          /* check for valid peripheral interrupt source */
+          if ((pmce & PMCE_PSE_STICKY) != 0) {
+            /* get source of peripheral interrupt */
+            irq = PMCE_PSE_SOURCE(pmce);
+
+            dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask);
+          } else {
+            /* this case may not occur: no valid peripheral
+             * interrupt source */
+            printk( "No valid peripheral HI_int interrupt source\n");
+          }
+          break;
+
           /* irq0, slice timer 1 or ccs wakeup detected */
         case 0:
         case 1:
@@ -569,108 +565,48 @@ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum)
 
           break;
 
-              /* peripheral HI_int interrupt source detected */
-            case 2:
-              /* check for valid peripheral interrupt source */
-              if (CHK_PSE_STICKY( pmce)) {
-                /* get source of peripheral interrupt */
-                irq = PSE_SOURCE( pmce);
-
-                dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask);
-
-                /* force re-evaluation of peripheral interrupts */
-                CLR_PSE_STICKY( mpc5200.pmce);
-              } else {
-                /* this case may not occur: no valid peripheral
-                 * interrupt source */
-                printk( "No valid peripheral HI_int interrupt source\n");
-              }
-              break;
         default:
           /* error: unknown interrupt source */
           printk( "Unknown HI_int interrupt source\n");
           break;
       }
-          /* force re-evaluation of critical interrupts */
-          CLR_CSE_STICKY( mpc5200.pmce);
     }
 
     /* second: check for main interrupt sources (hierarchical order)
      * -> LO_int indicates peripheral sources */
-        if (CHK_MSE_STICKY( pmce)) {
+    if ((pmce & PMCE_MSE_STICKY) != 0) {
       /* get source of main interrupt */
-          irq = MSE_SOURCE( pmce);
+      irq = PMCE_MSE_SOURCE(pmce);
-
-          switch (irq) {
-
-              /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer
-               * 2 is always routed to SMI) */
-            case 0:
-            case 1:
-            case 2:
-            case 3:
-            case 5:
-            case 6:
-            case 7:
-            case 8:
-            case 9:
-            case 10:
-            case 11:
-            case 12:
-            case 13:
-            case 14:
-            case 15:
-            case 16:
-              dispatch(irq, BSP_MAIN_IRQ_LOWEST_OFFSET, &mpc5200.crit_pri_main_mask);
-              break;
 
+      if (irq == 4) {
           /* peripheral LO_int interrupt source detected */
-            case 4:
           /* check for valid peripheral interrupt source */
-              if (CHK_PSE_STICKY( pmce)) {
+          if ((pmce & PMCE_PSE_STICKY) != 0) {
             /* get source of peripheral interrupt */
-                irq = PSE_SOURCE( pmce);
+            irq = PMCE_PSE_SOURCE(pmce);
 
             dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask);
-
-                /* force re-evaluation of peripheral interrupts */
-                CLR_PSE_STICKY( mpc5200.pmce);
           } else {
             /* this case may not occur: no valid peripheral
              * interrupt source */
             printk( "No valid peripheral LO_int interrupt source\n");
           }
-              break;
+      } else if (irq <= 16) {
-
+          /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer
+           * 2 is always routed to SMI) */
+          dispatch(irq, BSP_MAIN_IRQ_LOWEST_OFFSET, &mpc5200.crit_pri_main_mask);
+      } else {
           /* error: unknown interrupt source */
-            default:
           printk( "Unknown peripheral LO_int interrupt source\n");
-              break;
       }
-          /* force re-evaluation of main interrupts */
-          CLR_MSE_STICKY( mpc5200.pmce);
     }
 
-        if (CHK_PSE_STICKY( pmce)) {
+    /* force re-evaluation of interrupts */
-          /* get source of peripheral interrupt */
+    mpc5200.pmce = PMCE_CSE_STICKY | PMCE_MSE_STICKY | PMCE_PSE_STICKY;
-          irq = PSE_SOURCE( pmce);
-
-          dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask);
-
-          /* force re-evaluation of peripheral interrupts */
-          CLR_PSE_STICKY( mpc5200.pmce);
-        }
 
     /* get the content of main interrupt status register */
     pmce = mpc5200.pmce;
   }
-      break;
-
-    default:
-      printk( "Unknown processor exception\n");
-      break;
-
-  }                             /* end of switch( excNum) */
 
 #if (BENCHMARK_IRQ_PROCESSING == 1)
   stop = PPC_Get_timebase_register();
@@ -771,9 +707,6 @@ rtems_status_code bsp_interrupt_facility_initialize( void)
   if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
     return RTEMS_IO_ERROR;
   }
-  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
-    return RTEMS_IO_ERROR;
-  }
   if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, C_dispatch_irq_handler)) {
     return RTEMS_IO_ERROR;
   }

c/src/lib/libbsp/powerpc/gen5200/start/start.S

@@ -156,6 +156,68 @@
 
 .extern boot_card
 
+.section ".vectors", "ax"
+	bl	start
+	.rep 63
+	.long 0x04000400
+	.endr
+__vec2:	b	__vec2
+	.rep 63
+	.long 0x04000400
+	.endr
+__vec3:	b	__vec3
+	.rep 63
+	.long 0x04000400
+	.endr
+__vec4:	b	__vec4
+	.rep 63
+	.long 0x04000400
+	.endr
+__vec5:	b	__vec5
+	.rep 63
+	.long 0x04000400
+	.endr
+__vec6:	b	__vec6
+	.rep 63
+	.long 0x04000400
+	.endr
+__vec7:	b	__vec7
+	.rep 63
+	.long 0x04000400
+	.endr
+__vec8:	b	__vec8
+	.rep 63
+	.long 0x04000400
+	.endr
+__vec9:	b	__vec9
+	.rep 63
+	.long 0x04000400
+	.endr
+__veca:	b	__veca
+	.rep 63
+	.long 0x04000400
+	.endr
+__vecb:	b	__vecb
+	.rep 63
+	.long 0x04000400
+	.endr
+__vecc:	b	__vecc
+	.rep 63
+	.long 0x04000400
+	.endr
+__vecd:	b	__vecd
+	.rep 63
+	.long 0x04000400
+	.endr
+__vece:	b	__vece
+	.rep 63
+	.long 0x04000400
+	.endr
+__vecf:	b	__vecf
+	.rep 63+1024
+	.long 0x04000400
+	.endr
+
 .section ".entry"
 PUBLIC_VAR (start)
 start:
@@ -243,7 +305,7 @@ start:
 	rlwinm	r30, r30,17,15,31
 	stw	r30, CS0STR(r31) 		/* Set CS0STR */
 
-	LWI	r30, bsp_rom_end
+	LWI	r30, bsp_rom_end - 1
 
 	rlwinm	r30, r30,17,15,31
 	stw	r30, CS0STP(r31) 		/* Set CS0STP */
@@ -279,18 +341,7 @@ reloc_in_CS0:
 
 	bl	SDRAM_init			/* Initialize SDRAM controller */
 
-/* init arbiter and stuff... */
+	bl	XLB_init
-	LWI	r30, 0x8000a06e
-	stw	r30, ARBCFG(r31) 		/* Set ARBCFG */
-
-	LWI	r30, 0x000000ff
-	stw	r30, ARBMPREN(r31) 		/* Set ARBMPREN */
-
-	LWI	r30, 0x00001234
-	stw	r30, ARBMPRIO(r31) 		/* Set ARBPRIO */
-
-	LWI	r30, 0x0000001e
-	stw	r30, ARBSNOOP(r31) 		/* Set ARBSNOOP */
 /* copy .text section from ROM to RAM location (unique for ROM startup) */
 	LA	r30, bsp_section_text_start	/* get start address of text section in RAM */
 
@@ -395,6 +446,8 @@ skip_ROM_start:
 
         bl      clr_mem				/* Clear onchip SRAM */
 
+#else /* defined(NEED_LOW_LEVEL_INIT) */
+	bl	XLB_init
 #endif /* defined(NEED_LOW_LEVEL_INIT) */
 /* clear .bss section (unique for ROM startup) */
 	LWI	r30, bsp_section_bss_start	/* get start address of bss section */
@@ -843,5 +896,18 @@ clr_mem_byte:
 clr_mem_end:
         blr					/* return */
 
+XLB_init:
+/* init arbiter and stuff... */
+	LWI	r30, 0x8000a06e
+	stw	r30, ARBCFG(r31) 		/* Set ARBCFG */
 
+	LWI	r30, 0x000000ff
+	stw	r30, ARBMPREN(r31) 		/* Set ARBMPREN */
 
+	LWI	r30, 0x00001234
+	stw	r30, ARBMPRIO(r31) 		/* Set ARBPRIO */
+
+	LWI	r30, 0x0000001e
+	stw	r30, ARBSNOOP(r31) 		/* Set ARBSNOOP */
+
+	blr

c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c

@@ -103,6 +103,7 @@
 #include <bsp/bootcard.h>
 #include <bsp/irq.h>
 #include <bsp/irq-generic.h>
+#include <bsp/mpc5200.h>
 
 /*
  *  Driver configuration parameters
@@ -144,6 +145,18 @@ void bsp_start(void)
 
   cpu_init();
 
+  if(get_ppc_cpu_revision() >= 0x2014) {
+    /* Special settings for MPC5200B (B variant) */
+    uint32_t xlb_cfg = mpc5200.config;
+
+    /* XXX: The Freescale documentation for BSDIS seems to be wrong */
+    xlb_cfg |= XLB_CFG_BSDIS;
+
+    xlb_cfg &= ~XLB_CFG_PLDIS;
+
+    mpc5200.config = xlb_cfg;
+  }
+
   bsp_clicks_per_usec    = (XLB_CLOCK/4000000);
 
   /*
@@ -166,6 +179,7 @@ void bsp_start(void)
   if (sc != RTEMS_SUCCESSFUL) {
     BSP_panic("cannot initialize exceptions");
   }
+  ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);
 
   /* Initalize interrupt support */
   sc = bsp_interrupt_initialize();

c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c

@@ -168,6 +168,14 @@ static void cpu_init_bsp(void)
   BAT dbat;
   uint32_t start = 0;
 
+  /*
+   * Accesses (also speculative accesses) outside of the RAM area are a
+   * disaster especially in combination with the BestComm.  For safety reasons
+   * we make the available RAM a little bit smaller to have an unused area at
+   * the end.
+   */
+  bsp_uboot_board_info.bi_memsize -= 4 * 1024;
+
   /*
    * Program BAT0 for RAM
    */

c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs5l

@@ -5,7 +5,8 @@
  */
 
 MEMORY {
-	RAM : ORIGIN = 0x0, LENGTH = 128M
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 128M - 4k
 	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
 	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
 	REGS : ORIGIN = 0xf0000000, LENGTH = 64k

c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.dp2

@@ -5,10 +5,11 @@
  */
 
 MEMORY {
-	RAM : ORIGIN = 0x0, LENGTH = 64M
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 64M - 4k
 	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
-	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
 	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+	DPRAM : ORIGIN = 0x0, LENGTH = 0
 	NIRVANA : ORIGIN = 0x0, LENGTH = 0
 }
 

c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.icecube

@@ -5,11 +5,12 @@
  */
 
 MEMORY {
-	RAM : ORIGIN = 0x0, LENGTH = 128M
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 128M - 4k
 	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
 	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
-	NIRVANA : ORIGIN = 0x0, LENGTH = 0
 	DPRAM : ORIGIN = 0x0, LENGTH = 0
+	NIRVANA : ORIGIN = 0x0, LENGTH = 0
 }
 
 INCLUDE linkcmds.base

c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.pm520_cr825

@@ -5,10 +5,11 @@
  */
 
 MEMORY {
-	RAM : ORIGIN = 0x0, LENGTH = 64M
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 64M - 4k
 	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
-	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
 	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
 	NIRVANA : ORIGIN = 0x0, LENGTH = 0
 }
 

c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.pm520_ze30

@@ -5,10 +5,11 @@
  */
 
 MEMORY {
-	RAM : ORIGIN = 0x0, LENGTH = 64M
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 64M - 4k
 	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
-	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
 	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
 	NIRVANA : ORIGIN = 0x0, LENGTH = 0
 }