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SMP: Fix and optimize thread dispatching

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According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order.  Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.
This commit is contained in:
Sebastian Huber
2015-09-25 14:34:24 +02:00
parent aee6a1d05f
commit 258ad71e96
11 changed files with 101 additions and 100 deletions
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9
c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h
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@@ -8,7 +8,7 @@
*/
/*
* Copyright (c) 2008-2014 embedded brains GmbH.
* Copyright (c) 2008-2015 embedded brains GmbH.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -206,6 +206,13 @@ static inline void ppc_synchronize_data(void)
__asm__ volatile ("sync");
}
static inline void ppc_light_weight_synchronize(void)
{
RTEMS_COMPILER_MEMORY_BARRIER();
__asm__ volatile ("lwsync");
}
static inline void ppc_synchronize_instructions(void)
{
RTEMS_COMPILER_MEMORY_BARRIER();