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2005-09-12 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>

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PR 527/bsps
	PR 822/bsps
	* mpc8xx/clock/clock.c: Currently the MBX8xx BSP does not boot,
	because some logical errors are in the startup code. Additionally,
	the mpc8xx shared clock driver does not support the clocking scheme
	of some of the board variants, which are clocked from a
	32768Hz (!) external crystal.
This commit is contained in:
Joel Sherrill
2005-10-05 02:34:17 +00:00
parent a3b4632866
commit 24b6d2f9a8
2 changed files with 39 additions and 5 deletions
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10
c/src/lib/libcpu/powerpc/ChangeLog
View File

@@ -1,3 +1,13 @@
2005-09-12 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
PR 527/bsps
PR 822/bsps
* mpc8xx/clock/clock.c: Currently the MBX8xx BSP does not boot,
because some logical errors are in the startup code. Additionally,
the mpc8xx shared clock driver does not support the clocking scheme
of some of the board variants, which are clocked from a
32768Hz (!) external crystal.
2005-08-12 Phil Torre <ptorre@zetron.com> 2005-08-12 Phil Torre <ptorre@zetron.com>
PR 816/bsps PR 816/bsps

34
c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c
View File

@@ -71,15 +71,39 @@ void clockOn(void* unused)
{ {
unsigned desiredLevel; unsigned desiredLevel;
rtems_unsigned32 pit_value; rtems_unsigned32 pit_value;
rtems_unsigned32 mf_value;
rtems_unsigned32 extclk_value;
pit_value = (rtems_configuration_get_microseconds_per_tick() * if (rtems_cpu_configuration_get_clicks_per_usec() == 0) {
rtems_cpu_configuration_get_clicks_per_usec()) - 1 ; /*
* oscclk is too low for PIT, compute extclk and derive PIT from there
*/
mf_value = m8xx.plprcr >> 20;
pit_value = (_CPU_Table.clock_speed
/ (mf_value+1)
/ 4
* rtems_configuration_get_microseconds_per_tick()
/ 1000000);
m8xx.sccr |= (1<<24);
}
else {
pit_value = (rtems_configuration_get_microseconds_per_tick() *
rtems_cpu_configuration_get_clicks_per_usec());
if (pit_value > 0xffff) { /* pit is only 16 bits long */ m8xx.sccr &= ~(1<<24);
}
if (pit_value > (0xffff+1)) {
/*
* try to activate prescaler
* NOTE: divider generates odd values now...
*/
pit_value = pit_value / 128;
m8xx.sccr |= (1<<25);
}
if (pit_value > (0xffff+1)) { /* pit is only 16 bits long */
rtems_fatal_error_occurred(-1); rtems_fatal_error_occurred(-1);
} }
m8xx.sccr &= ~(1<<24); m8xx.pitc = pit_value - 1;
m8xx.pitc = pit_value;
desiredLevel = BSP_get_clock_irq_level(); desiredLevel = BSP_get_clock_irq_level();
/* set PIT irq level, enable PIT, PIT interrupts */ /* set PIT irq level, enable PIT, PIT interrupts */