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score: Rename _ISR_Disable() and _ISR_Enable()

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Rename _ISR_Disable() into _ISR_Local_disable().  Rename _ISR_Enable()
into _ISR_Local_enable().  Remove _Debug_Is_owner_of_giant().

This is a preparation to remove the Giant lock.

Update #2555.
This commit is contained in:
Sebastian Huber
2016-05-18 08:06:54 +02:00
parent 4b04cb6155
commit 2471316321
25 changed files with 139 additions and 175 deletions
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4
c/src/lib/libbsp/m68k/gen68360/startup/alloc360.c
View File

@@ -47,7 +47,7 @@ M360AllocateBufferDescriptors (int count)
* form, but this routine is probably being run as part of an
* initialization sequence so the effect shouldn't be too severe.
*/
_ISR_Disable (level);
_ISR_Local_disable (level);
for (i = 0 ; i < sizeof(bdregions) / sizeof(bdregions[0]) ; i++) {
/*
* Verify that the region exists.
@@ -74,7 +74,7 @@ M360AllocateBufferDescriptors (int count)
break;
}
}
_ISR_Enable (level);
_ISR_Local_enable (level);
if (bdp == NULL)
rtems_panic ("Can't allocate %d buffer descriptor(s).\n", count);
return bdp;

16
c/src/lib/libbsp/m68k/mvme167/network/network.c
View File

@@ -568,7 +568,7 @@ static void uti596_addCmd(
pCmd->status = 0;
pCmd->next = I596_NULL;
_ISR_Disable(level);
_ISR_Local_disable(level);
if (uti596_softc.pCmdHead == I596_NULL) {
uti596_softc.pCmdHead = uti596_softc.pCmdTail = uti596_softc.scb.pCmd = pCmd;
@@ -578,12 +578,12 @@ static void uti596_addCmd(
uti596_softc.scb.command = CUC_START;
uti596_issueCA ( &uti596_softc, UTI596_NO_WAIT );
_ISR_Enable(level);
_ISR_Local_enable(level);
}
else {
uti596_softc.pCmdTail->next = (i596_cmd *) word_swap ((unsigned long)pCmd);
uti596_softc.pCmdTail = pCmd;
_ISR_Enable(level);
_ISR_Local_enable(level);
}
#ifdef DBG_ADD_CMD
@@ -1272,11 +1272,11 @@ i596_rfd * uti596_dequeue(
ISR_Level level;
i596_rfd * pRfd;
_ISR_Disable(level);
_ISR_Local_disable(level);
/* invalid address, or empty queue or emptied queue */
if( ppQ == NULL || *ppQ == NULL || *ppQ == I596_NULL) {
_ISR_Enable(level);
_ISR_Local_enable(level);
return I596_NULL;
}
@@ -1288,7 +1288,7 @@ i596_rfd * uti596_dequeue(
*ppQ = (i596_rfd *) word_swap ((unsigned long) pRfd->next);
pRfd->next = I596_NULL; /* unlink the rfd being returned */
_ISR_Enable(level);
_ISR_Local_enable(level);
return pRfd;
}
@@ -2083,9 +2083,9 @@ void uti596_txDaemon(
UTI_596_ASSERT(pRfd != I596_NULL, "Supplying NULL RFD\n")
_ISR_Disable(level);
_ISR_Local_disable(level);
uti596_supplyFD ( pRfd ); /* Return RFD to RFA. */
_ISR_Enable(level);
_ISR_Local_enable(level);
pRfd = uti596_dequeue( (i596_rfd **)&sc->pInboundFrameQueue); /* grab next frame */

60
c/src/lib/libcpu/or1k/shared/cache/cache.c vendored
View File

@@ -20,11 +20,11 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
uint32_t sr;
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_disable_data(void)
@@ -32,12 +32,12 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
uint32_t sr;
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE));
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_enable_instruction(void)
@@ -45,12 +45,12 @@ static inline void _CPU_OR1K_Cache_enable_instruction(void)
uint32_t sr;
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_disable_instruction(void)
@@ -58,96 +58,96 @@ static inline void _CPU_OR1K_Cache_disable_instruction(void)
uint32_t sr;
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE));
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_prefetch
(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_invalidate
(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_lock
(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
/* Implement RTEMS cache manager functions */
@@ -155,23 +155,23 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
void _CPU_cache_flush_1_data_line(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_CPU_OR1K_Cache_data_block_flush(d_addr);
//asm volatile("l.csync");
_ISR_Enable(level);
_ISR_Local_enable(level);
}
void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_CPU_OR1K_Cache_data_block_invalidate(d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
void _CPU_cache_freeze_data(void)
@@ -187,11 +187,11 @@ void _CPU_cache_unfreeze_data(void)
void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_ISR_Local_disable (level);
_CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
_ISR_Enable(level);
_ISR_Local_enable(level);
}
void _CPU_cache_freeze_instruction(void)

4
c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c
View File

@@ -57,7 +57,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
* form, but this routine is probably being run as part of an
* initialization sequence so the effect shouldn't be too severe.
*/
_ISR_Disable (level);
_ISR_Local_disable (level);
for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) {
/*
@@ -85,7 +85,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
}
}
_ISR_Enable(level);
_ISR_Local_enable(level);
if (blockp == NULL)
rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count);

4
c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
View File

@@ -55,7 +55,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
* form, but this routine is probably being run as part of an
* initialization sequence so the effect shouldn't be too severe.
*/
_ISR_Disable (level);
_ISR_Local_disable (level);
for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) {
/*
@@ -83,7 +83,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
}
}
_ISR_Enable(level);
_ISR_Local_enable(level);
if (blockp == NULL)
rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count);

12
c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
View File

@@ -111,14 +111,14 @@ unsigned int sh_set_irq_priority(
/*
* Set the interrupt priority register
*/
_ISR_Disable( level );
_ISR_Local_disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_ISR_Enable( level );
_ISR_Local_enable( level );
return 0;
}
@@ -131,7 +131,7 @@ void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
_ISR_Disable( level );
_ISR_Local_disable( level );
_Thread_Dispatch_disable();
@@ -147,13 +147,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
_ISR_Enable( level );
_ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_ISR_Disable( level );
_ISR_Local_disable( level );
_Thread_Dispatch_unnest( _Per_CPU_Get() );
@@ -166,7 +166,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
_ISR_Enable( level );
_ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;

12
c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
View File

@@ -112,14 +112,14 @@ unsigned int sh_set_irq_priority(
/*
* Set the interrupt priority register
*/
_ISR_Disable( level );
_ISR_Local_disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_ISR_Enable( level );
_ISR_Local_enable( level );
return 0;
}
@@ -132,7 +132,7 @@ void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
_ISR_Disable( level );
_ISR_Local_disable( level );
_Thread_Dispatch_disable();
@@ -148,13 +148,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
_ISR_Enable( level );
_ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_ISR_Disable( level );
_ISR_Local_disable( level );
_Thread_Dispatch_unnest( _Per_CPU_Get() );
@@ -167,7 +167,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
_ISR_Enable( level );
_ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;

8
c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
View File

@@ -56,7 +56,7 @@ void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
_ISR_Disable( level );
_ISR_Local_disable( level );
_Thread_Dispatch_disable();
@@ -72,13 +72,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
_ISR_Enable( level );
_ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_ISR_Disable( level );
_ISR_Local_disable( level );
_Thread_Dispatch_enable( _Per_CPU_Get() );
@@ -90,7 +90,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
_ISR_Enable( level );
_ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;

8
c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
View File

@@ -33,7 +33,7 @@ void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
_ISR_Disable( level );
_ISR_Local_disable( level );
_Thread_Dispatch_disable();
@@ -49,13 +49,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
_ISR_Enable( level );
_ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_ISR_Disable( level );
_ISR_Local_disable( level );
_Thread_Dispatch_unnest( _Per_CPU_Get() );
@@ -68,7 +68,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
_ISR_Enable( level );
_ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;

8
c/src/libchip/ide/ata.c
View File

@@ -387,9 +387,9 @@ ata_process_request(rtems_device_minor_number ctrl_minor)
return;
/* get first request in the controller's queue */
_ISR_Disable(level);
_ISR_Local_disable(level);
areq = (ata_req_t *)rtems_chain_first(&ata_ide_ctrls[ctrl_minor].reqs);
_ISR_Enable(level);
_ISR_Local_enable(level);
#if 0
/* get ATA device identifier (0 or 1) */
@@ -831,9 +831,9 @@ ata_queue_task(rtems_task_argument arg)
rtems_ata_lock();
/* get current request to the controller */
_ISR_Disable(level);
_ISR_Local_disable(level);
areq = (ata_req_t *)rtems_chain_first(&ata_ide_ctrls[ctrl_minor].reqs);
_ISR_Enable(level);
_ISR_Local_enable(level);
switch(msg.type)
{