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arm: Remove legacy execption support

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This commit is contained in:
Sebastian Huber
2017-03-07 14:32:42 +01:00
parent 6584eb2830
commit 2433a8ab1c
26 changed files with 175 additions and 889 deletions
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3
c/src/lib/libbsp/arm/Makefile.am
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@@ -18,9 +18,6 @@ EXTRA_DIST =
EXTRA_DIST += shared/comm/uart.h
EXTRA_DIST += shared/comm/uart.c
# abort
EXTRA_DIST += shared/abort/simple_abort.c
include $(srcdir)/preinstall.am
include $(top_srcdir)/../../../automake/subdirs.am
include $(top_srcdir)/../../../automake/local.am

2
c/src/lib/libbsp/arm/csb336/Makefile.am
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@@ -38,8 +38,6 @@ libbsp_a_SOURCES += ../../shared/cpucounterread.c
libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
# console
libbsp_a_SOURCES += console/uart.c
# abort
libbsp_a_SOURCES += ../shared/abort/abort.c
# IRQ
include_bsp_HEADERS += ../../shared/include/irq-generic.h \
../../shared/include/irq-info.h

51
c/src/lib/libbsp/arm/csb336/start/start.S
View File

@@ -132,28 +132,35 @@ _hang: b _hang
* of 16 words (64 bytes)
*/
vector_block:
ldr pc, Reset_Handler
ldr pc, Undefined_Handler
ldr pc, SWI_Handler
ldr pc, Prefetch_Handler
ldr pc, Abort_Handler
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, IRQ_Handler
ldr pc, FIQ_Handler
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
Reset_Handler: b bsp_reset
Undefined_Handler: b Undefined_Handler
SWI_Handler: b SWI_Handler
Prefetch_Handler: b Prefetch_Handler
Abort_Handler: b Abort_Handler
nop
IRQ_Handler: b IRQ_Handler
FIQ_Handler: b FIQ_Handler
handler_addr_reset:
.word bsp_reset
.globl Reset_Handler
.globl Undefined_Handler
.globl SWI_Handler
.globl Prefetch_Handler
.globl Abort_Handler
.globl IRQ_Handler
.globl FIQ_Handler
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

6
c/src/lib/libbsp/arm/csb336/startup/bspstart.c
View File

@@ -54,12 +54,6 @@ static void bsp_start_default( void )
/* Set interrupt priority to -1 (allow all priorities) */
MC9328MXL_AITC_NIMASK = 0x1f;
/*
* Init rtems exceptions management
*/
/* FIXME: Use shared start.S */
rtems_exception_init_mngt();
/*
* Init rtems interrupt management
*/

2
c/src/lib/libbsp/arm/csb337/Makefile.am
View File

@@ -75,8 +75,6 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
if ENABLE_LCD
libbsp_a_SOURCES += console/sed1356.c console/fbcons.c
endif
# abort
libbsp_a_SOURCES += ../shared/abort/abort.c
# umon
if ENABLE_UMON
libbsp_a_SOURCES += ../../shared/umon/umonrtemsglue.c \

51
c/src/lib/libbsp/arm/csb337/start/start.S
View File

@@ -118,28 +118,35 @@ _hang: b _hang
* of 16 words (64 bytes)
*/
vector_block:
ldr pc, Reset_Handler
ldr pc, Undefined_Handler
ldr pc, SWI_Handler
ldr pc, Prefetch_Handler
ldr pc, Abort_Handler
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, IRQ_Handler
ldr pc, FIQ_Handler
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
Reset_Handler: b bsp_reset
Undefined_Handler: b Undefined_Handler
SWI_Handler: b SWI_Handler
Prefetch_Handler: b Prefetch_Handler
Abort_Handler: b Abort_Handler
nop
IRQ_Handler: b IRQ_Handler
FIQ_Handler: b FIQ_Handler
handler_addr_reset:
.word bsp_reset
.globl Reset_Handler
.globl Undefined_Handler
.globl SWI_Handler
.globl Prefetch_Handler
.globl Abort_Handler
.globl IRQ_Handler
.globl FIQ_Handler
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

6
c/src/lib/libbsp/arm/csb337/startup/bspstart.c
View File

@@ -53,12 +53,6 @@ static void bsp_start_default( void )
*/
bsp_usart_init();
/*
* Init rtems exceptions management
*/
/* FIXME: Use shared start.S */
rtems_exception_init_mngt();
/*
* Init rtems interrupt management
*/

2
c/src/lib/libbsp/arm/edb7312/Makefile.am
View File

@@ -47,8 +47,6 @@ libbsp_a_SOURCES += console/uart.c ../../shared/console.c \
../../shared/console_read.c ../../shared/console_write.c
# timer
libbsp_a_SOURCES += timer/timer.c
# abort
libbsp_a_SOURCES += ../shared/abort/abort.c
# irq
include_bsp_HEADERS += ../../shared/include/irq-generic.h \

66
c/src/lib/libbsp/arm/edb7312/start/start.S
View File

@@ -37,44 +37,38 @@
********************************************************/
Vector_Init_Block:
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
.globl Reset_Addr
Reset_Addr: .long _start
Undefined_Addr: .long Undefined_Handler
SWI_Addr: .long SWI_Handler
Prefetch_Addr: .long Prefetch_Handler
Abort_Addr: .long Abort_Handler
.long 0
IRQ_Addr: .long IRQ_Handler
FIQ_Addr: .long FIQ_Handler
handler_addr_reset:
.word _start
/* The following handlers do not do anything useful */
.globl Undefined_Handler
Undefined_Handler:
B Undefined_Handler
.globl SWI_Handler
SWI_Handler:
B SWI_Handler
.globl Prefetch_Handler
Prefetch_Handler:
B Prefetch_Handler
.globl Abort_Handler
Abort_Handler:
B Abort_Handler
.globl IRQ_Handler
IRQ_Handler:
B IRQ_Handler
.globl FIQ_Handler
FIQ_Handler:
B FIQ_Handler
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default
.globl _start
_start:

6
c/src/lib/libbsp/arm/edb7312/startup/bspstart.c
View File

@@ -32,12 +32,6 @@ static void bsp_start_default( void )
*EP7312_INTMR1 = 0;
*EP7312_INTMR2 = 0;
/*
* Init rtems exceptions management
*/
/* FIXME: Use shared start.S */
rtems_exception_init_mngt();
/*
* Init rtems interrupt management
*/

2
c/src/lib/libbsp/arm/gumstix/Makefile.am
View File

@@ -49,8 +49,6 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
libbsp_a_SOURCES += ../../shared/src/irq-server.c
libbsp_a_SOURCES += ../../shared/src/irq-shell.c
#abort
libbsp_a_SOURCES += ../shared/abort/abort.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c

51
c/src/lib/libbsp/arm/gumstix/start/start.S
View File

@@ -122,28 +122,35 @@ _hang: b _hang
* of 16 words (64 bytes)
*/
vector_block:
ldr pc, Reset_Handler
ldr pc, Undefined_Handler
ldr pc, SWI_Handler
ldr pc, Prefetch_Handler
ldr pc, Abort_Handler
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, IRQ_Handler
ldr pc, FIQ_Handler
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
Reset_Handler: b bsp_reset
Undefined_Handler: b Undefined_Handler
SWI_Handler: b SWI_Handler
Prefetch_Handler: b Prefetch_Handler
Abort_Handler: b Abort_Handler
nop
IRQ_Handler: b IRQ_Handler
FIQ_Handler: b FIQ_Handler
handler_addr_reset:
.word bsp_reset
.globl Reset_Handler
.globl Undefined_Handler
.globl SWI_Handler
.globl Prefetch_Handler
.globl Abort_Handler
.globl IRQ_Handler
.globl FIQ_Handler
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

2
c/src/lib/libbsp/arm/gumstix/startup/bspstart.c
View File

@@ -30,8 +30,6 @@ static void bsp_start_default( void )
{
/* disable interrupts */
XSCALE_INT_ICMR = 0x0;
/* FIXME: Use shared start.S */
rtems_exception_init_mngt();
bsp_interrupt_initialize();
} /* bsp_start */

2
c/src/lib/libbsp/arm/rtl22xx/Makefile.am
View File

@@ -51,8 +51,6 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
libbsp_a_SOURCES += ../../shared/src/irq-server.c
libbsp_a_SOURCES += ../../shared/src/irq-shell.c
# simple_abort
libbsp_a_SOURCES += ../shared/abort/simple_abort.c
# debugio
libbsp_a_SOURCES += console/uart.c

103
c/src/lib/libbsp/arm/rtl22xx/start/start.S
View File

@@ -123,80 +123,35 @@ _hang: b _hang
********************************************************/
vector_block:
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
.globl Reset_Addr
Reset_Addr: .long _start
Undefined_Addr: .long Undefined_Handler
SWI_Addr: .long SWI_Handler
Prefetch_Addr: .long Prefetch_Handler
Abort_Addr: .long Abort_Handler
.long 0
IRQ_Addr: .long IRQ_Handler
FIQ_Addr: .long FIQ_Handler
/* The following handlers do not do anything useful */
.globl Undefined_Handler
Undefined_Handler:
B Undefined_Handler
.globl SWI_Handler
SWI_Handler:
B SWI_Handler
.globl Prefetch_Handler
Prefetch_Handler:
B Prefetch_Handler
.globl Abort_Handler
Abort_Handler:
B Abort_Handler
.globl IRQ_Handler
IRQ_Handler:
B IRQ_Handler
.globl FIQ_Handler
FIQ_Handler:
B FIQ_Handler
/*
* This is the exception vector table and the pointers to
* the functions that handle the exceptions. It's a total
* of 16 words (64 bytes)
*/
/*******************************************************
vector_block:
ldr pc, Reset_Handler
ldr pc, Undefined_Handler
ldr pc, SWI_Handler
ldr pc, Prefetch_Handler
ldr pc, Abort_Handler
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, IRQ_Handler
ldr pc, FIQ_Handler
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
Reset_Handler: b bsp_reset
Undefined_Handler: b Undefined_Handler
SWI_Handler: b SWI_Handler
Prefetch_Handler: b Prefetch_Handler
Abort_Handler: b Abort_Handler
nop
IRQ_Handler: b IRQ_Handler
FIQ_Handler: b FIQ_Handler
handler_addr_reset:
.word _start
.globl Reset_Handler
.globl Undefined_Handler
.globl SWI_Handler
.globl Prefetch_Handler
.globl Abort_Handler
.globl IRQ_Handler
.globl FIQ_Handler
*/
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

6
c/src/lib/libbsp/arm/rtl22xx/startup/bspstart.c
View File

@@ -71,12 +71,6 @@ static void bsp_start_default( void )
UART0_Ini();
/*
* Init rtems exceptions management
*/
/* FIXME: Use shared start.S */
rtems_exception_init_mngt();
/*
* Init rtems interrupt management
*/

145
c/src/lib/libbsp/arm/shared/abort/abort.c
View File

@@ -1,145 +0,0 @@
/*
* ARM CPU Dependent Source
*
* If you want a small footprint RTEMS, pls use simple_abort.c
*/
/*
* COPYRIGHT (c) 2007 Ray Xu.
* mailto: Rayx at gmail dot com
*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* Copyright (c) 2002 Advent Networks, Inc
* Jay Monkman <jmonkman@adventnetworks.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#include <rtems/system.h>
#include <rtems.h>
#include <rtems/bspIo.h>
#include "abort.h"
uint32_t g_data_abort_cnt = 0;
/*this is a big overhead for MCU only got 16K RAM*/
uint32_t g_data_abort_insn_list[1024];
char *_print_full_context_mode2txt[0x20]={
[0x0]="user", /* User */
[0x1]="fiq", /* FIQ - Fast Interrupt Request */
[0x2]="irq", /* IRQ - Interrupt Request */
[0x3]="super", /* Supervisor */
[0x7]="abort", /* Abort */
[0xb]="undef", /* Undefined */
[0xf]="system" /* System */
};
void _print_full_context(uint32_t spsr)
{
char *mode;
uint32_t prev_sp,prev_lr,cpsr,arm_switch_reg;
int i;
printk("active thread thread 0x%08x\n", rtems_task_self());
mode=_print_full_context_mode2txt[spsr&0x1f];
if(!mode) mode="unknown";
__asm__ volatile (ARM_SWITCH_TO_ARM
" MRS %[cpsr], cpsr \n"
" ORR %[arm_switch_reg], %[spsr], #0xc0 \n"
" MSR cpsr_c, %[arm_switch_reg] \n"
" MOV %[prev_sp], sp \n"
" MOV %[prev_lr], lr \n"
" MSR cpsr_c, %[cpsr] \n"
ARM_SWITCH_BACK
: [arm_switch_reg] "=&r" (arm_switch_reg), [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr),
[cpsr] "=&r" (cpsr)
: [spsr] "r" (spsr)
: "cc");
printk("Previous sp=0x%08x lr=0x%08x and actual cpsr=%08x\n",
prev_sp, prev_lr, cpsr);
for(i=0;i<48;){
printk(" 0x%08x",((uint32_t*)prev_sp)[i++]);
if((i%6) == 0)
printk("\n");
}
}
/* This function is supposed to figure out what caused the
* data abort, do that, then return.
*
* All unhandled instructions cause the system to hang.
*/
void do_data_abort(
uint32_t insn,
uint32_t spsr,
Context_Control *ctx
)
{
/* Clarify, which type is correct, CPU_Exception_frame or Context_Control */
uint8_t decode;
uint8_t insn_type;
rtems_interrupt_level level;
g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8;
g_data_abort_cnt++;
decode = ((insn >> 20) & 0xff);
insn_type = decode & INSN_MASK;
switch(insn_type) {
case INSN_STM1:
printk("\n\nINSN_STM1\n");
break;
case INSN_STM2:
printk("\n\nINSN_STM2\n");
break;
case INSN_STR:
printk("\n\nINSN_STR\n");
break;
case INSN_STRB:
printk("\n\nINSN_STRB\n");
break;
case INSN_LDM1:
printk("\n\nINSN_LDM1\n");
break;
case INSN_LDM23:
printk("\n\nINSN_LDM23\n");
break;
case INSN_LDR:
printk("\n\nINSN_LDR\n");
break;
case INSN_LDRB:
printk("\n\nINSN_LDRB\n");
break;
default:
printk("\n\nUnrecognized instruction\n");
break;
}
printk("data_abort at address 0x%x, instruction: 0x%x, spsr = 0x%x\n",
ctx->register_lr - 8, insn, spsr);
_print_full_context(spsr);
/* disable interrupts, wait forever */
rtems_interrupt_disable(level);
(void) level; /* avoid set but unused warning */
while(1) {
continue;
}
}

52
c/src/lib/libbsp/arm/shared/abort/abort.h
View File

@@ -1,52 +0,0 @@
/*
* COPYRIGHT (c) 2007 Ray Xu.
* mailto: Rayx at gmail dot com
*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* Copyright (c) 2002 Advent Networks, Inc
* Jay Monkman <jmonkman@adventnetworks.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#ifndef _BSPABORT_H
#define _BSPABORT_H
#include <rtems/system.h>
#include <rtems.h>
#include <rtems/bspIo.h>
#define INSN_MASK 0xc5
#define INSN_STM1 0x80
#define INSN_STM2 0x84
#define INSN_STR 0x40
#define INSN_STRB 0x44
#define INSN_LDM1 0x81
#define INSN_LDM23 0x85
#define INSN_LDR 0x41
#define INSN_LDRB 0x45
#define GET_RD(x) ((x & 0x0000f000) >> 12)
#define GET_RN(x) ((x & 0x000f0000) >> 16)
#define GET_U(x) ((x & 0x00800000) >> 23)
#define GET_I(x) ((x & 0x02000000) >> 25)
#define GET_REG(r, ctx) (((uint32_t *)ctx)[r])
#define SET_REG(r, ctx, v) (((uint32_t *)ctx)[r] = v)
#define GET_OFFSET(insn) (insn & 0xfff)
/*
* Prototypes
*/
void _print_full_context(uint32_t);
void do_data_abort(uint32_t, uint32_t, Context_Control *);
#endif /* _BSPABORT_H */

146
c/src/lib/libbsp/arm/shared/abort/simple_abort.c
View File

@@ -1,146 +0,0 @@
/*
* ARM CPU Dependent Source
*
* COPYRIGHT (c) 2007 Ray Xu.
* mailto: Rayx.cn at gmail dot com
*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* Copyright (c) 2002 Advent Networks, Inc
* Jay Monkman <jmonkman@adventnetworks.com>
*
* This is a simple implement of abort
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#include <rtems/system.h>
#include <rtems.h>
#include <rtems/bspIo.h>
#include "abort.h"
char *_print_full_context_mode2txt[0x10]={
[0x0]="user", /* User */
[0x1]="fiq", /* FIQ - Fast Interrupt Request */
[0x2]="irq", /* IRQ - Interrupt Request */
[0x3]="super", /* Supervisor */
[0x7]="abort", /* Abort */
[0xb]="undef", /* Undefined */
[0xf]="system" /* System */
};
void _print_full_context(uint32_t spsr)
{
char *mode;
uint32_t prev_sp,prev_lr,cpsr,arm_switch_reg;
int i, j;
printk("active thread thread 0x%08x\n", rtems_task_self());
mode=_print_full_context_mode2txt[(spsr&0x1f)-0x10];
if(!mode) mode="unknown";
__asm__ volatile (
ARM_SWITCH_TO_ARM
"mrs %[cpsr], cpsr\n"
"orr %[arm_switch_reg], %[spsr], #0xc0\n"
"msr cpsr_c, %[arm_switch_reg]\n"
"mov %[prev_sp], sp\n"
"mov %[prev_lr], lr\n"
"msr cpsr_c, %[cpsr]\n"
ARM_SWITCH_BACK
: [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr),
[cpsr] "=&r" (cpsr), [arm_switch_reg] "=&r" (arm_switch_reg)
: [spsr] "r" (spsr)
: "cc"
);
printk(
"Previous sp=0x%08x lr=0x%08x and actual cpsr=%08x\n",
prev_sp,
prev_lr,
cpsr
);
j=0;
for(i=0;i<48;) {
printk(" 0x%08x",((uint32_t*)prev_sp)[i++]);
j++;
/*try not to use % because it introduces hundreds of byte overhead*/
if((j-6)==0) {
printk("\n");
j=0;
}
}
}
/* This function is supposed to figure out what caused the
* data abort, do that, then return.
*
* All unhandled instructions cause the system to hang.
*/
void do_data_abort(
uint32_t insn,
uint32_t spsr,
Context_Control *ctx
)
{
/* Clarify, which type is correct, CPU_Exception_frame or Context_Control */
uint8_t decode;
uint8_t insn_type;
rtems_interrupt_level level;
decode = ((insn >> 20) & 0xff);
insn_type = decode & INSN_MASK;
switch(insn_type) {
case INSN_STM1:
printk("\n\nINSN_STM1\n");
break;
case INSN_STM2:
printk("\n\nINSN_STM2\n");
break;
case INSN_STR:
printk("\n\nINSN_STR\n");
break;
case INSN_STRB:
printk("\n\nINSN_STRB\n");
break;
case INSN_LDM1:
printk("\n\nINSN_LDM1\n");
break;
case INSN_LDM23:
printk("\n\nINSN_LDM23\n");
break;
case INSN_LDR:
printk("\n\nINSN_LDR\n");
break;
case INSN_LDRB:
printk("\n\nINSN_LDRB\n");
break;
default:
printk("\n\nUnrecognized instruction\n");
break;
}
printk("data_abort at address 0x%x, instruction: 0x%x, spsr = 0x%x\n",
ctx->register_lr - 8, insn, spsr);
_print_full_context(spsr);
/* disable interrupts, wait forever */
rtems_interrupt_disable(level);
(void)level;
while(1) {
continue;
}
return;
}

2
c/src/lib/libbsp/arm/smdk2410/Makefile.am
View File

@@ -57,8 +57,6 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
libbsp_a_SOURCES += ../../shared/src/irq-server.c
libbsp_a_SOURCES += ../../shared/src/irq-shell.c
# abort
libbsp_a_SOURCES += ../shared/abort/abort.c
# smc
libbsp_a_SOURCES += smc/smc.c
libbsp_a_SOURCES += smc/smc.h

51
c/src/lib/libbsp/arm/smdk2410/start/start.S
View File

@@ -171,28 +171,35 @@ _hang: b _hang
* of 16 words (64 bytes)
*/
vector_block:
ldr pc, Reset_Handler
ldr pc, Undefined_Handler
ldr pc, SWI_Handler
ldr pc, Prefetch_Handler
ldr pc, Abort_Handler
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, IRQ_Handler
ldr pc, FIQ_Handler
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
Reset_Handler: b bsp_reset
Undefined_Handler: b Undefined_Handler
SWI_Handler: b SWI_Handler
Prefetch_Handler: b Prefetch_Handler
Abort_Handler: b Abort_Handler
nop
IRQ_Handler: b IRQ_Handler
FIQ_Handler: b FIQ_Handler
handler_addr_reset:
.word bsp_reset
.globl Reset_Handler
.globl Undefined_Handler
.globl SWI_Handler
.globl Prefetch_Handler
.globl Abort_Handler
.globl IRQ_Handler
.globl FIQ_Handler
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

6
c/src/lib/libbsp/arm/smdk2410/startup/bspstart.c
View File

@@ -70,12 +70,6 @@ static void bsp_start_default( void )
cr = rTCFG0 & 0xFFFFFF00;
rTCFG0 = (cr | (0<<0));
/*
* Init rtems exceptions management
*/
/* FIXME: Use shared start.S */
rtems_exception_init_mngt();
/*
* Init rtems interrupt management
*/

2
cpukit/score/cpu/arm/Makefile.am
View File

@@ -23,8 +23,6 @@ libscorecpu_a_SOURCES += arm-context-validate.S
libscorecpu_a_SOURCES += arm-context-volatile-clobber.S
libscorecpu_a_SOURCES += arm_exc_abort.S
libscorecpu_a_SOURCES += arm_exc_interrupt.S
libscorecpu_a_SOURCES += arm_exc_handler_low.S
libscorecpu_a_SOURCES += arm_exc_handler_high.c
libscorecpu_a_SOURCES += arm-exception-frame-print.c
libscorecpu_a_SOURCES += arm-exception-default.c
libscorecpu_a_SOURCES += armv4-exception-default.S

127
cpukit/score/cpu/arm/arm_exc_handler_high.c
View File

@@ -1,127 +0,0 @@
/**
* @file
*
* @ingroup ScoreCPU
*
* @brief ARM exception support implementation.
*/
/*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* Copyright (c) 2002 Advent Networks, Inc
* Jay Monkman <jmonkman@adventnetworks.com>
*
* Copyright (c) 2007 Ray xu <rayx.cn@gmail.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Moved from file 'cpukit/score/cpu/arm/cpu.c'.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/system.h>
#include <rtems.h>
#include <rtems/bspIo.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
#include <rtems/score/thread.h>
#include <rtems/score/percpu.h>
#include <rtems/score/cpu.h>
#include <inttypes.h>
#ifdef ARM_MULTILIB_ARCH_V4
static void _defaultExcHandler (CPU_Exception_frame *ctx)
{
printk("\n\r");
printk("----------------------------------------------------------\n\r");
#if 1
printk("Exception 0x%x caught at PC 0x%" PRIxPTR
" by thread 0x%" PRIx32 "\n",
ctx->vector, (uintptr_t) ctx->register_lr - 4,
_Thread_Executing->Object.id);
#endif
printk("----------------------------------------------------------\n\r");
printk("Processor execution context at time of the fault was :\n\r");
printk("----------------------------------------------------------\n\r");
#if 0
printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r",
ctx->register_r0, ctx->register_r1,
ctx->register_r2, ctx->register_r3);
printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r",
ctx->register_r4, ctx->register_r5,
ctx->register_r6, ctx->register_r7);
printk(" r8 = %8x r9 = %8x r10 = %8x\n\r",
ctx->register_r8, ctx->register_r9, ctx->register_r10);
printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r",
ctx->register_fp, ctx->register_ip,
ctx->register_sp, ctx->register_lr - 4);
printk("----------------------------------------------------------\n\r");
#endif
if (_ISR_Nest_level > 0) {
/*
* In this case we shall not delete the task interrupted as
* it has nothing to do with the fault. We cannot return either
* because the eip points to the faulty instruction so...
*/
printk("Exception while executing ISR!!!. System locked\n\r");
while(1);
}
else {
printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r");
rtems_task_delete(_Thread_Executing->Object.id);
}
}
typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
cpuExcHandlerType _currentExcHandler = _defaultExcHandler;
extern void _Exception_Handler_Undef_Swi(void);
extern void _Exception_Handler_Abort(void);
extern void _exc_data_abort(void);
/* FIXME: put comments here */
void rtems_exception_init_mngt(void)
{
ISR_Level level;
_CPU_ISR_Disable(level);
_CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,
_Exception_Handler_Undef_Swi,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_SWI,
_Exception_Handler_Undef_Swi,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
_exc_data_abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_Enable(level);
}
#endif /* ARM_MULTILIB_ARCH_V4 */

166
cpukit/score/cpu/arm/arm_exc_handler_low.S
View File

@@ -1,166 +0,0 @@
/**
* @file
*
* @ingroup ScoreCPU
*
* @brief ARM exception support implementation.
*/
/*
* Copyright (c) 2007 by Ray Xu, <Rayx.cn@gmail.com>
* Thumb support added.
*
* Copyright (c) 2002 by Advent Networks, Inc.
* Jay Monkman <jmonkman@adventnetworks.com>
*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Moved from file 'cpukit/score/cpu/arm/cpu_asm.S'.
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/asm.h>
#include <rtems/score/cpu_asm.h>
#ifdef ARM_MULTILIB_ARCH_V4
.text
/* FIXME: _Exception_Handler_Undef_Swi is untested */
DEFINE_FUNCTION_ARM(_Exception_Handler_Undef_Swi)
/* FIXME: This should use load and store multiple instructions */
sub r13,r13,#SIZE_REGS
str r4, [r13, #REG_R4]
str r5, [r13, #REG_R5]
str r6, [r13, #REG_R6]
str r7, [r13, #REG_R7]
str r8, [r13, #REG_R8]
str r9, [r13, #REG_R9]
str r10, [r13, #REG_R10]
str r11, [r13, #REG_R11]
str sp, [r13, #REG_SP]
str lr, [r13, #REG_LR]
mrs r0, cpsr /* read the status */
and r0, r0,#0x1f /* we keep the mode as exception number */
str r0, [r13, #REG_PC] /* we store it in a free place */
mov r0, r13 /* put frame address in r0 (C arg 1) */
ldr r1, =SWI_Handler
ldr lr, =_go_back_1
ldr pc,[r1] /* call handler */
_go_back_1:
ldr r4, [r13, #REG_R4]
ldr r5, [r13, #REG_R5]
ldr r6, [r13, #REG_R6]
ldr r7, [r13, #REG_R7]
ldr r8, [r13, #REG_R8]
ldr r9, [r13, #REG_R9]
ldr r10, [r13, #REG_R10]
ldr r11, [r13, #REG_R11]
ldr sp, [r13, #REG_SP]
ldr lr, [r13, #REG_LR]
add r13,r13,#SIZE_REGS
movs pc,r14 /* return */
/* FIXME: _Exception_Handler_Abort is untested */
DEFINE_FUNCTION_ARM(_Exception_Handler_Abort)
/* FIXME: This should use load and store multiple instructions */
sub r13,r13,#SIZE_REGS
str r4, [r13, #REG_R4]
str r5, [r13, #REG_R5]
str r6, [r13, #REG_R6]
str r7, [r13, #REG_R7]
str r8, [r13, #REG_R8]
str r9, [r13, #REG_R9]
str sp, [r13, #REG_R11]
str lr, [r13, #REG_SP]
str lr, [r13, #REG_LR]
mrs r0, cpsr /* read the status */
and r0, r0,#0x1f /* we keep the mode as exception number */
str r0, [r13, #REG_PC] /* we store it in a free place */
mov r0, r13 /* put frame address in ro (C arg 1) */
ldr r1, =_currentExcHandler
ldr lr, =_go_back_2
ldr pc,[r1] /* call handler */
_go_back_2:
ldr r4, [r13, #REG_R4]
ldr r5, [r13, #REG_R5]
ldr r6, [r13, #REG_R6]
ldr r7, [r13, #REG_R7]
ldr r8, [r13, #REG_R8]
ldr r9, [r13, #REG_R9]
ldr r10, [r13, #REG_R10]
ldr sp, [r13, #REG_R11]
ldr lr, [r13, #REG_SP]
ldr lr, [r13, #REG_LR]
add r13,r13,#SIZE_REGS
#ifdef __thumb__
subs r11, r14,#4
bx r11
nop
#else
subs pc,r14,#4 /* return */
#endif
#define ABORT_REGS_OFFS 32-REG_R4
#define ABORT_SIZE_REGS SIZE_REGS+ABORT_REGS_OFFS
DEFINE_FUNCTION_ARM(_exc_data_abort)
sub sp, sp, #ABORT_SIZE_REGS /* reserve register frame */
stmia sp, {r0-r11}
add sp, sp, #ABORT_REGS_OFFS /* the Context_Control structure starts by CPSR, R4, ... */
str ip, [sp, #REG_PC] /* store R12 (ip) somewhere, oh hackery, hackery, hack */
str lr, [sp, #REG_LR]
mov r1, lr
ldr r0, [r1, #-8] /* r0 = bad instruction */
mrs r1, spsr /* r1 = spsr */
mov r2, r13 /* r2 = exception frame of Context_Control type */
#if defined(__thumb__)
.code 32
/*arm to thumb*/
adr r5, to_thumb + 1
bx r5
.code 16
to_thumb:
#endif
bl do_data_abort
#if defined(__thumb__)
/*back to arm*/
.code 16
thumb_to_arm:
.align 2
adr r5, arm_code
bx r5
nop
.code 32
arm_code:
#endif
ldr lr, [sp, #REG_LR]
ldr ip, [sp, #REG_PC] /* restore R12 (ip) */
sub sp, sp, #ABORT_REGS_OFFS
ldmia sp, {r0-r11}
add sp, sp, #ABORT_SIZE_REGS
#ifdef __thumb__
subs r11, r14, #4 /* return to the instruction */
bx r11
nop
#else
subs pc, r14, #4
#endif
/* _AFTER_ the aborted one */
#endif /* ARM_MULTILIB_ARCH_V4 */

6
cpukit/score/cpu/arm/rtems/score/cpu.h
View File

@@ -704,12 +704,6 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
void _ARM_Exception_default( CPU_Exception_frame *frame );
/*
* FIXME: In case your BSP uses this function, then convert it to use
* the shared start.S file for ARM.
*/
void rtems_exception_init_mngt( void );
/** @} */
#ifdef __cplusplus