RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2011-03-15 Till Straumann <strauman@slac.stanford.edu>

Browse Source 
* startup/bspstart.c: Fix clock code on qemu. Also ensure UART is
	initialized early for printk.
This commit is contained in:
Joel Sherrill
2011-03-15 21:34:56 +00:00
parent f6c010a7c2
commit 23005aab5a
2 changed files with 25 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
c/src/lib/libbsp/m68k/uC5282/ChangeLog
View File

@@ -1,3 +1,8 @@
2011-03-15 Till Straumann <strauman@slac.stanford.edu>
* startup/bspstart.c: Fix clock code on qemu. Also ensure UART is
initialized early for printk.
2011-03-04 Till Straumann <strauman@slac.stanford.edu> 2011-03-04 Till Straumann <strauman@slac.stanford.edu>
PR 1738/bsps PR 1738/bsps

21
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
View File

@@ -244,6 +244,14 @@ void bsp_start( void )
int i; int i;
const char *clk_speed_str; const char *clk_speed_str;
uint32_t clk_speed, mfd, rfd; uint32_t clk_speed, mfd, rfd;
uint8_t byte;
/*
* Make sure UART TX is running - necessary for
* early printk to work. The firmware monitor
* usually enables this anyways but qemu doesn't!
*/
MCF5282_UART_UCR(CONSOLE_PORT) = MCF5282_UART_UCR_TX_ENABLED;
/* /*
* Set up default exception handler * Set up default exception handler
@@ -334,12 +342,19 @@ void bsp_start( void )
if ( 0 == clk_speed ) { if ( 0 == clk_speed ) {
printk("Using some heuristics to determine clock speed...\n"); printk("Using some heuristics to determine clock speed...\n");
printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock); byte = MCF5282_CLOCK_SYNSR;
if ( 0xf8 != MCF5282_CLOCK_SYNSR ) { if ( 0 == byte ) {
printk("FATAL ERROR: Unexpected SYNSR contents, can't proceed\n"); printk("SYNSR == 0; assuming QEMU at 66MHz\n");
BSP_pll_ref_clock = 8250000;
mfd = ( 0 << 8 ) | ( 2 << 12 );
} else {
if ( 0xf8 != byte ) {
printk("FATAL ERROR: Unexpected SYNSR contents (0x%02x), can't proceed\n", byte);
bsp_sysReset(0); bsp_sysReset(0);
} }
mfd = MCF5282_CLOCK_SYNCR; mfd = MCF5282_CLOCK_SYNCR;
}
printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock);
rfd = (mfd >> 8) & 7; rfd = (mfd >> 8) & 7;
mfd = (mfd >> 12) & 7; mfd = (mfd >> 12) & 7;
/* Check against 'known' cases */ /* Check against 'known' cases */