forked from Imagelibrary/rtems
2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>
* include/lr33000.h, include/lr330x0.h, include/r3000.h, start/mg5.h: New files missed in previous commit. * timer/timer.c: Use rtems/bspIo.h not just bspIo.h.
This commit is contained in:
Joel Sherrill
100
c/src/lib/libbsp/mips/genmongoosev/include/lr33000.h
Normal file
100
c/src/lib/libbsp/mips/genmongoosev/include/lr33000.h
Normal file
@@ -0,0 +1,100 @@
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/* lr33000.h - LSI LR33000 CPU header */
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/* $Id$ */
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/*
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modification history
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--------------------
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01c,22sep92,rrr added support for c++
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01b,20apr92,ajm added CR_DCAS for ethernet support
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01a,10feb92,ajm written for FCS
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*/
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#ifndef __INClr33000h
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#define __INClr33000h
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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#define C0_DCIC $7 /* cache control */
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#define C0_BPC $3 /* breakpoint on instr */
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#define C0_BDA $5 /* breakpoint on data */
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#endif /* _ASMLANGUAGE */
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#define DEBUG_VECT 0x00000040
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#define K0_DEBUG_VECT (K0BASE+DEBUG_VECT)
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#define K1_DEBUG_VECT (K1BASE+DEBUG_VECT)
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/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
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#define DCIC_TR 0x80000000 /* Trap enable */
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#define DCIC_UD 0x40000000 /* User debug enable */
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#define DCIC_KD 0x20000000 /* Kernel debug enable */
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#define DCIC_TE 0x10000000 /* Trace enable */
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#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */
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#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */
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#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */
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#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */
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#define DCIC_DE 0x00800000 /* Debug enable */
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#define DCIC_DL 0x00008000 /* Data cache line invalidate */
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#define DCIC_IL 0x00004000 /* Instruction cache line invalidate */
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#define DCIC_D 0x00002000 /* Data cache invalidate enable */
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#define DCIC_I 0x00001000 /* Instr. cache invalidate enable */
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#define DCIC_T 0x00000020 /* Trace, set by CPU */
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#define DCIC_W 0x00000010 /* Write reference, set by CPU */
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#define DCIC_R 0x00000008 /* Read reference, set by CPU */
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#define DCIC_DA 0x00000004 /* Data address, set by CPU */
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#define DCIC_PC 0x00000002 /* Program counter, set by CPU */
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#define DCIC_DB 0x00000001 /* Debug, set by CPU */
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/* Define counter/timer register addresses */
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#define M_TIC1 0xfffe0000 /* timer 1 initial count */
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#define M_TC1 0xfffe0004 /* timer 1 control */
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#define M_TIC2 0xfffe0008 /* timer 2 initial count */
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#define M_TC2 0xfffe000c /* timer 2 control */
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#define M_RTIC 0xfffe0010 /* refresh timer */
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#define M_CFGREG 0xfffe0020 /* configuration reg */
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/* Definitions for counter/timer control register bits */
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#define TC_CE 0x00000004 /* count enable */
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#define TC_IE 0x00000002 /* interrupt enable (1 == enable) */
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#define TC_INT 0x00000001 /* interrupt acknowlege (0 == ack) */
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#define TCNT_MASK 0x00ffffff /* 24 bit timer mask */
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/* Definitions for Configuration register bits */
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#define CR_ICDISABLE 0x00800000 /* Instruction cache disable */
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#define CR_DCDISABLE 0x00400000 /* Data cache disable */
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#define CR_IBLK_2 0x00000000 /* Instruction cache block size */
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#define CR_IBLK_4 0x00100000 /* Instruction cache block size */
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#define CR_IBLK_8 0x00200000 /* Instruction cache block size */
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#define CR_IBLK_16 0x00300000 /* Instruction cache block size */
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#define CR_IBLKMSK 0x00300000 /* Instruction cache block size */
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#define CR_DBLK_2 0x00000000 /* Data cache block size */
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#define CR_DBLK_4 0x00040000 /* Data cache block size */
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#define CR_DBLK_8 0x00080000 /* Data cache block size */
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#define CR_DBLK_16 0x000c0000 /* Data cache block size */
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#define CR_DBLKMSK 0x000c0000 /* Data cache block size */
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#define CR_IODIS 0x00020000 /* Disable DRDY for I/O addresses */
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#define CR_IOWAITSHFT 13 /* I/O wait states */
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#define CR_PDIS 0x00001000 /* Disable DRDY for PROM addresses */
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#define CR_PWAITSHFT 8 /* PROM wait states */
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#define CR_DCAS 0x00000080 /* Define # cycles of DCAS */
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#define CR_DPEN 0x00000040 /* Enable parity check for DRAM */
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#define CR_RDYGEN 0x00000020 /* Disable DRDY for DRAM addresses */
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#define CR_BLKFDIS 0x00000010 /* Disable DRAM block refill */
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#define CR_RFSHEN 0x00000008 /* Enable refresh generator */
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#define CR_RASPCHG 0x00000004 /* Define RAS precharge */
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#define CR_CASLNTH 0x00000002 /* Define CAS active time */
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#define CR_DRAMEN 0x00000001 /* Enable DRAM controller */
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#define CR_PWT(x) ((x) << 8) /* memory wait states */
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#define CR_IOWT(x) ((x) << 13) /* io wait states */
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#define LR33000_DSIZE 0x400 /* Data cache = 1Kbytes */
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#define LR33000_ISIZE 0x2000 /* Instructrion cache = 8Kbytes */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INClr33000h */
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182
c/src/lib/libbsp/mips/genmongoosev/include/lr333x0.h
Normal file
182
c/src/lib/libbsp/mips/genmongoosev/include/lr333x0.h
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@@ -0,0 +1,182 @@
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/* lr333x0.h - LSI LR333x0 CPU header */
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/* $Id$ */
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#ifndef __INClr333x0h
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#define __INClr333x0h
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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#define C0_BPC $3 /* breakpoint on instr */
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#define C0_BDA $5 /* breakpoint on data */
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#define C0_TAR $6 /* target address register */
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#define C0_DCIC $7 /* cache control */
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#define C0_BDAM $9 /* breakpoint data addr mask */
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#define C0_BPCM $11 /* breakpoint instr addr mask */
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#else
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IMPORT int sysICsize; /* inst cache size defined in BSP */
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IMPORT int sysDCsize; /* data cache size defined in BSP */
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IMPORT BOOL sysICset0; /* inst cache set 0 present ? */
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#endif /* _ASMLANGUAGE */
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#define DEBUG_VECT 0x00000040
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#define K0_DEBUG_VECT (K0BASE+DEBUG_VECT)
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#define K1_DEBUG_VECT (K1BASE+DEBUG_VECT)
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/* Define register addresses */
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#define M_TIC1 0xfffe0000 /* timer 1 initial count */
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#define M_TC1 0xfffe0004 /* timer 1 control */
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#define M_TIC2 0xfffe0008 /* timer 2 initial count */
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#define M_TC2 0xfffe000c /* timer 2 control */
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#define M_RTIC 0xfffe0010 /* refresh timer */
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#define M_SRAM 0xfffe0100 /* SRAM config reg */
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#define M_SPEC0 0xfffe0104
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#define M_SPEC1 0xfffe0108
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#define M_SPEC2 0xfffe010c
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#define M_SPEC3 0xfffe0110
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#define M_DRAM 0xfffe0120 /* DRAM configuration */
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#define M_BIU 0xfffe0130 /* BIU/cache configuration */
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/* Definitions for Debug and Cache Invalidate control (DCIC) register bits */
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#define DCIC_TR 0x80000000 /* Trap enable */
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#define DCIC_UD 0x40000000 /* User debug enable */
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#define DCIC_KD 0x20000000 /* Kernel debug enable */
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#define DCIC_TE 0x10000000 /* Trace enable */
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#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */
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#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */
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#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */
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#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */
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#define DCIC_DE 0x00800000 /* Debug enable */
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#define DCIC_T 0x00000020 /* Trace, set by CPU */
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#define DCIC_W 0x00000010 /* Write reference, set by CPU */
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#define DCIC_R 0x00000008 /* Read reference, set by CPU */
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#define DCIC_DA 0x00000004 /* Data address, set by CPU */
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#define DCIC_PC 0x00000002 /* Program counter, set by CPU */
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#define DCIC_DB 0x00000001 /* Debug, set by CPU */
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/* Definitions for counter/timer control register bits */
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#define TC_CE 0x00000004 /* count enable */
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#define TC_IE 0x00000002 /* interrupt enable (1 == enable) */
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#define TC_INT 0x00000001 /* interrupt acknowlege (0 == ack) */
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/* Definitions for Wait-state configuration register bits */
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#define SPC_INHIBITSHFT 24 /* Inhibit shift count */
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#define SPC_EXTGNT 0x00800000 /* External data ready */
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#define SPC_16WIDE 0x00400000 /* 16-bit wide memory */
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#define SPC_8WIDE 0x00200000 /* 8-bit wide memory */
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#define SPC_PENA 0x00100000 /* Parity enable */
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#define SPC_CACHED 0x00080000 /* Cache data */
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#define SPC_CSDLY_3 0x00060000 /* Select delay, 3 cycles */
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#define SPC_CSDLY_2 0x00040000 /* Select delay, 2 cycles */
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#define SPC_CSDLY_1 0x00020000 /* Select delay, 1 cycles */
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#define SPC_CSDLY_0 0x00000000 /* Select delay, 0 cycles */
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#define SPC_BLKENA 0x00010000 /* Block enable */
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#define SPC_BLKWAIT_7 0x0000e000 /* Block delay, 7 cycles */
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#define SPC_BLKWAIT_6 0x0000c000 /* Block delay, 6 cycles */
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#define SPC_BLKWAIT_5 0x0000a000 /* Block delay, 5 cycles */
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#define SPC_BLKWAIT_4 0x00008000 /* Block delay, 4 cycles */
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#define SPC_BLKWAIT_3 0x00006000 /* Block delay, 3 cycles */
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#define SPC_BLKWAIT_2 0x00004000 /* Block delay, 2 cycles */
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#define SPC_BLKWAIT_1 0x00002000 /* Block delay, 1 cycles */
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#define SPC_BLKWAIT_0 0x00000000 /* Block delay, 0 cycles */
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#define SPC_RECSHFT 7 /* Recovery time shift count */
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#define SPC_WAITENA 0x00000040 /* Wait-state generator enable */
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#define SPC_WAITSHFT 0 /* Wait shift count */
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/* Definitions for DRAM configuration register bits */
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#define DRAM_DLP1 0x10000000 /* Data latch in phase 1 */
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#define DRAM_SYNC 0x08000000 /* Sunchronous DRAM mode */
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#define DRAM_SCFG 0x04000000 /* Synchronous Configuration mode */
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#define DRAM_DMARDY 0x02000000 /* DMA ready */
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#define DRAM_DMABLK_64 0x01400000 /* DMA block refill size, 64 words */
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#define DRAM_DMABLK_32 0x01000000 /* DMA block refill size, 32 words */
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#define DRAM_DMABLK_16 0x00c00000 /* DMA block refill size, 16 words */
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#define DRAM_DMABLK_8 0x00800000 /* DMA block refill size, 8 words */
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#define DRAM_DMABLK_4 0x00400000 /* DMA block refill size, 4 words */
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#define DRAM_DMABLK_2 0x00000000 /* DMA block refill size, 2 words */
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#define DRAM_DPTH_8 0x00300000 /* CAS ready depth, 8 per cycle */
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#define DRAM_DPTH_4 0x00200000 /* CAS ready depth, 4 per cycle */
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#define DRAM_DPTH_2 0x00100000 /* CAS ready depth, 2 per cycle */
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#define DRAM_DPTH_1 0x00000000 /* CAS ready depth, 1 per cycle */
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#define DRAM_RDYW 0x00080000 /* Ready Wait */
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#define DRAM_PGSZ_2K 0x00070000 /* Page size, 2K words */
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#define DRAM_PGSZ_1K 0x00060000 /* Page size, 1K words */
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#define DRAM_PGSZ_512 0x00050000 /* Page size, 512 words */
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#define DRAM_PGSZ_256 0x00040000 /* Page size, 256 words */
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#define DRAM_PGSZ_128 0x00030000 /* Page size, 128 words */
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#define DRAM_PGSZ_64 0x00020000 /* Page size, 64 words */
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#define DRAM_PGSZ_32 0x00010000 /* Page size, 32 words */
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#define DRAM_PGSZ_16 0x00000000 /* Page size, 16 words */
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#define DRAM_PGMW 0x00008000 /* Page mode write enable */
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#define DRAM_RFWE_0 0x00004000 /* Refresh write enable mode, bit 1 */
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#define DRAM_RFWE_1 0x00002000 /* Refresh write enable mode, bit 0 */
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#define DRAM_RFEN 0x00001000 /* Internal refresh enable */
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#define DRAM_RDYEN 0x00000800 /* Internal ready generation */
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#define DRAM_BFD 0x00000400 /* Block fetch disable */
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#define DRAM_PE 0x00000200 /* Parity checking enable */
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#define DRAM_RPC_3 0x00000180 /* RAS precharge, 3 */
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#define DRAM_RPC_2 0x00000100 /* RAS precharge, 2 */
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#define DRAM_RPC_1 0x00000080 /* RAS precharge, 1 */
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#define DRAM_RPC_0 0x00000000 /* RAS precharge, 0 */
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#define DRAM_RCD_3 0x00000060 /* RAS to CAS delay, 3 */
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#define DRAM_RCD_2 0x00000040 /* RAS to CAS delay, 2 */
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#define DRAM_RCD_1 0x00000020 /* RAS to CAS delay, 1 */
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#define DRAM_RCD_0 0x00000000 /* RAS to CAS delay, 0 */
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#define DRAM_CS 0x00000010 /* CAS short */
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#define DRAM_CL_8_5 0x0000000f /* CAS length, 8.5 cycles */
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#define DRAM_CL_7_5 0x0000000c /* CAS length, 7.5 cycles*/
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#define DRAM_CL_6_5 0x0000000a /* CAS length, 6.5 cycles */
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#define DRAM_CL_5_5 0x00000008 /* CAS length, 5.5 cycles */
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#define DRAM_CL_4_5 0x00000006 /* CAS length, 4.5 cycles */
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#define DRAM_CL_3_5 0x00000004 /* CAS length, 3.5 cycles*/
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#define DRAM_CL_2_5 0x00000002 /* CAS length, 2.5 cycles */
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#define DRAM_CL_1_5 0x00000000 /* CAS length, 1.5 cycles */
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#define DRAM_DCE 0x00000001 /* DRAM controller enable */
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/* Definitions for BIU/cache configuration register bits */
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#define BIU_NOSTR 0x00020000 /* no instruction streaming */
|
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#define BIU_LDSCH 0x00010000 /* enable load scheduling */
|
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#define BIU_BGNT 0x00008000 /* enable bus grant */
|
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#define BIU_NOPAD 0x00004000 /* no wait state */
|
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#define BIU_RDPRI 0x00002000 /* enable read priority */
|
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#define BIU_INTP 0x00001000 /* interrupt polarity */
|
||||
#define BIU_IS1 0x00000800 /* enable Inst cache, set 1 */
|
||||
#define BIU_IS0 0x00000400 /* enable Inst cache, set 0 */
|
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#define BIU_IBLKSZ_16 0x00000300 /* Inst cache fill sz = 16 words */
|
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#define BIU_IBLKSZ_8 0x00000200 /* Inst cache fill sz = 8 words */
|
||||
#define BIU_IBLKSZ_4 0x00000100 /* Inst cache fill sz = 4 words */
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||||
#define BIU_IBLKSZ_2 0x00000000 /* Inst cache fill sz = 2 words */
|
||||
#define BIU_DS 0x00000080 /* enable Data cache */
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#define BIU_DBLKSZ_16 0x00000030 /* Data cache fill sz = 16 words */
|
||||
#define BIU_DBLKSZ_8 0x00000020 /* Data cache fill sz = 8 words */
|
||||
#define BIU_DBLKSZ_4 0x00000010 /* Data cache fill sz = 4 words */
|
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#define BIU_DBLKSZ_2 0x00000000 /* Data cache fill sz = 2 words */
|
||||
#define BIU_RAM 0x00000008 /* scratchpad RAM */
|
||||
#define BIU_TAG 0x00000004 /* tag test mode */
|
||||
#define BIU_INV 0x00000002 /* invalidate mode */
|
||||
#define BIU_LOCK 0x00000001 /* lock mode */
|
||||
|
||||
/* Definitions for cache sizes */
|
||||
|
||||
#define LR33300_IC_SIZE 0x1000 /* 33300 Inst cache = 4Kbytes */
|
||||
#define LR33310_IC_SIZE 0x1000 /* 33310 Inst cache = 4Kbytes */
|
||||
/* Note: each set is 4Kbytes! */
|
||||
|
||||
#define LR33300_DC_SIZE 0x800 /* 33300 Data cache = 2Kbytes */
|
||||
#define LR33310_DC_SIZE 0x1000 /* 33310 Data cache = 4Kbytes */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INClr333x0h */
|
||||
229
c/src/lib/libbsp/mips/genmongoosev/include/r3000.h
Normal file
229
c/src/lib/libbsp/mips/genmongoosev/include/r3000.h
Normal file
@@ -0,0 +1,229 @@
|
||||
/* r3000.h - mips R3k architecture header file */
|
||||
|
||||
/*
|
||||
* Copyright 1985-1997 by MIPS Computer Systems, Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01k,17jan96,kkk made MINCACHE 512 (spr# 7556)
|
||||
01j,13jan96,kkk undid 01i.
|
||||
01i,18dec96,tam enabled FP exceptions via FP_TASK_STATUS (spr #7665).
|
||||
01h,13sep93,caf fixed K2SIZE (SPR #1880).
|
||||
01g,22sep92,rrr added support for c++
|
||||
01f,02jun92,ajm the 5.0.5 merge
|
||||
01e,26may92,rrr the tree shuffle
|
||||
01d,04oct91,rrr passed through the ansification filter
|
||||
-changed copyright notice
|
||||
01c,23jul91,ajm changed default fp status register to all exceptions
|
||||
off forcing the user to enable exceptions for signals
|
||||
Enable FPA interrupt to tasks
|
||||
01b,08jul91,ajm added SR_KUMSK for exception handling
|
||||
01a,21feb91,ajm written.
|
||||
*/
|
||||
|
||||
#ifndef __INCr3000h
|
||||
#define __INCr3000h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Segment base addresses and sizes
|
||||
*/
|
||||
|
||||
#define K0BASE 0x80000000
|
||||
#define K0SIZE 0x20000000
|
||||
#define K1BASE 0xA0000000
|
||||
#define K1SIZE 0x20000000
|
||||
#define K2BASE 0xC0000000
|
||||
#define K2SIZE 0x40000000
|
||||
|
||||
/*
|
||||
* Exception vectors
|
||||
*/
|
||||
|
||||
#define UT_VEC K0BASE /* utlbmiss vector */
|
||||
#define E_VEC (K0BASE+0x80) /* exception vector */
|
||||
#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
|
||||
|
||||
/*
|
||||
* Address conversion macros
|
||||
*/
|
||||
|
||||
#define K0_TO_K1(x) ((unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */
|
||||
#define K1_TO_K0(x) ((unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
|
||||
#define K0_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */
|
||||
#define K1_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */
|
||||
#define PHYS_TO_K0(x) ((unsigned)(x)|0x80000000) /* physical to kseg0 */
|
||||
#define PHYS_TO_K1(x) ((unsigned)(x)|0xA0000000) /* physical to kseg1 */
|
||||
|
||||
/*
|
||||
* Address predicates
|
||||
*/
|
||||
|
||||
#define IS_KSEG0(x) ((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE)
|
||||
#define IS_KSEG1(x) ((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE)
|
||||
#define IS_KUSEG(x) ((unsigned)(x) < K0BASE)
|
||||
|
||||
/*
|
||||
* Cache size constants
|
||||
*/
|
||||
|
||||
#define MINCACHE +(1*512) /* leading plus for mas's benefit */
|
||||
#define MAXCACHE +(256*1024) /* leading plus for mas's benefit */
|
||||
|
||||
/*
|
||||
* Cause bit definitions
|
||||
*/
|
||||
|
||||
#define CAUSE_BD 0x80000000 /* Branch delay slot */
|
||||
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
|
||||
#define CAUSE_CESHIFT 28
|
||||
|
||||
#define CAUSE_IP8 0x00008000 /* External level 8 pending */
|
||||
#define CAUSE_IP7 0x00004000 /* External level 7 pending */
|
||||
#define CAUSE_IP6 0x00002000 /* External level 6 pending */
|
||||
#define CAUSE_IP5 0x00001000 /* External level 5 pending */
|
||||
#define CAUSE_IP4 0x00000800 /* External level 4 pending */
|
||||
#define CAUSE_IP3 0x00000400 /* External level 3 pending */
|
||||
#define CAUSE_SW2 0x00000200 /* Software level 2 pending */
|
||||
#define CAUSE_SW1 0x00000100 /* Software level 1 pending */
|
||||
|
||||
#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
|
||||
#define CAUSE_IPSHIFT 8
|
||||
|
||||
#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */
|
||||
#define CAUSE_EXCSHIFT 2
|
||||
|
||||
/*
|
||||
* Status definition bits
|
||||
*/
|
||||
|
||||
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
|
||||
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
|
||||
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
|
||||
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
|
||||
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
|
||||
#define SR_BEV 0x00400000 /* use boot exception vectors */
|
||||
#define SR_TS 0x00200000 /* TLB shutdown */
|
||||
#define SR_PE 0x00100000 /* cache parity error */
|
||||
#define SR_CM 0x00080000 /* cache miss */
|
||||
#define SR_PZ 0x00040000 /* cache parity zero */
|
||||
#define SR_SWC 0x00020000 /* swap cache */
|
||||
#define SR_ISC 0x00010000 /* Isolate data cache */
|
||||
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
|
||||
#define SR_IMASK8 0x00000000 /* mask level 8 */
|
||||
#define SR_IMASK7 0x00008000 /* mask level 7 */
|
||||
#define SR_IMASK6 0x0000c000 /* mask level 6 */
|
||||
#define SR_IMASK5 0x0000e000 /* mask level 5 */
|
||||
#define SR_IMASK4 0x0000f000 /* mask level 4 */
|
||||
#define SR_IMASK3 0x0000f800 /* mask level 3 */
|
||||
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
|
||||
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
|
||||
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
|
||||
|
||||
#define SR_IBIT8 0x00008000 /* bit level 8 */
|
||||
#define SR_IBIT7 0x00004000 /* bit level 7 */
|
||||
#define SR_IBIT6 0x00002000 /* bit level 6 */
|
||||
#define SR_IBIT5 0x00001000 /* bit level 5 */
|
||||
#define SR_IBIT4 0x00000800 /* bit level 4 */
|
||||
#define SR_IBIT3 0x00000400 /* bit level 3 */
|
||||
#define SR_IBIT2 0x00000200 /* bit level 2 */
|
||||
#define SR_IBIT1 0x00000100 /* bit level 1 */
|
||||
|
||||
#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
|
||||
#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
|
||||
#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
|
||||
#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
|
||||
#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
|
||||
#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
|
||||
#define SR_KUMSK (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC)
|
||||
|
||||
#define SR_IMASKSHIFT 8
|
||||
|
||||
/*
|
||||
* fpa definitions
|
||||
*/
|
||||
|
||||
#define FP_ROUND 0x3 /* r3010 round mode mask */
|
||||
#define FP_STICKY 0x7c /* r3010 sticky bits mask */
|
||||
#define FP_ENABLE 0xf80 /* r3010 enable mode mask */
|
||||
#define FP_EXC 0x3f000 /* r3010 exception mask */
|
||||
|
||||
#define FP_ROUND_N 0x0 /* round to nearest */
|
||||
#define FP_ROUND_Z 0x1 /* round to zero */
|
||||
#define FP_ROUND_P 0x2 /* round to + infinity */
|
||||
#define FP_ROUND_M 0x3 /* round to - infinity */
|
||||
|
||||
#define FP_STICKY_I 0x4 /* sticky inexact operation */
|
||||
#define FP_STICKY_U 0x8 /* sticky underflow */
|
||||
#define FP_STICKY_O 0x10 /* sticky overflow */
|
||||
#define FP_STICKY_Z 0x20 /* sticky divide by zero */
|
||||
#define FP_STICKY_V 0x40 /* sticky invalid operation */
|
||||
|
||||
#define FP_ENABLE_I 0x80 /* enable inexact operation */
|
||||
#define FP_ENABLE_U 0x100 /* enable underflow exc */
|
||||
#define FP_ENABLE_O 0x200 /* enable overflow exc */
|
||||
#define FP_ENABLE_Z 0x400 /* enable divide by zero exc */
|
||||
#define FP_ENABLE_V 0x800 /* enable invalid operation exc */
|
||||
|
||||
#define FP_EXC_I 0x1000 /* inexact operation */
|
||||
#define FP_EXC_U 0x2000 /* underflow */
|
||||
#define FP_EXC_O 0x4000 /* overflow */
|
||||
#define FP_EXC_Z 0x8000 /* divide by zero */
|
||||
#define FP_EXC_V 0x10000 /* invalid operation */
|
||||
#define FP_EXC_E 0x20000 /* unimplemented operation */
|
||||
|
||||
#define FP_COND 0x800000 /* condition bit */
|
||||
|
||||
#define FP_EXC_SHIFT 12
|
||||
#define FP_ENABLE_SHIFT 7
|
||||
#define FP_EXC_MASK (FP_EXC_I|FP_EXC_U|FP_EXC_O|FP_EXC_Z|FP_EXC_V|FP_EXC_E)
|
||||
#define FP_ENABLE_MASK (FP_ENABLE_I|FP_ENABLE_U|FP_ENABLE_O|FP_ENABLE_Z| \
|
||||
FP_ENABLE_V)
|
||||
#define FP_TASK_STATUS 0x0 /* all FP exceptions are disabled
|
||||
(see fppAlib.s and spr #7665) */
|
||||
|
||||
/*
|
||||
* tlb definitions
|
||||
*/
|
||||
|
||||
#define TLB_ENTRIES 64
|
||||
#define TLBLO_PFNMASK 0xfffff000
|
||||
#define TLBLO_PFNSHIFT 12
|
||||
#define TLBLO_N 0x800 /* non-cacheable */
|
||||
#define TLBLO_D 0x400 /* writeable */
|
||||
#define TLBLO_V 0x200 /* valid bit */
|
||||
#define TLBHI_VPNMASK 0xfffff000
|
||||
#define TLBHI_VPNSHIFT 12
|
||||
#define TLBHI_PIDMASK 0xfc0
|
||||
#define TLBHI_PIDSHIFT 6
|
||||
#define TLBHI_NPID 64
|
||||
#define TLBINX_PROBE 0x80000000
|
||||
#define TLBINX_INXMASK 0x00003f00
|
||||
#define TLBINX_INXSHIFT 8
|
||||
#define TLBRAND_RANDMASK 0x00003f00
|
||||
#define TLBRAND_RANDSHIFT 8
|
||||
#define TLBCTXT_BASEMASK 0xffe00000
|
||||
#define TLBCTXT_BASESHIFT 21
|
||||
#define TLBCTXT_VPNMASK 0x001ffffc
|
||||
#define TLBCTXT_VPNSHIFT 2
|
||||
|
||||
/*
|
||||
* Coprocessor 0 operations
|
||||
*/
|
||||
|
||||
#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
|
||||
#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
|
||||
#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
|
||||
#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
|
||||
#define C0_RFE 0x10 /* restore for exception */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCr3000h */
|
||||
404
c/src/lib/libbsp/mips/genmongoosev/start/mg5.h
Normal file
404
c/src/lib/libbsp/mips/genmongoosev/start/mg5.h
Normal file
@@ -0,0 +1,404 @@
|
||||
/*
|
||||
**
|
||||
** Section 1: Registers
|
||||
**
|
||||
*/
|
||||
|
||||
/*
|
||||
**
|
||||
*/
|
||||
#define PMON_ADDRESS 0xbfc00000
|
||||
|
||||
|
||||
|
||||
/*
|
||||
** Mongoose V Peripheral Function Registers
|
||||
*/
|
||||
|
||||
#define MG5_COMMAND_REG 0xfffe0180
|
||||
|
||||
/*
|
||||
** Extended Interrupt Registers
|
||||
** These registers are used as follows:
|
||||
** 1. The mask register is used to allow peripheral function and external
|
||||
** interrupts to function. To enable an interrupt, set the appropriate
|
||||
** bit.
|
||||
** 2. The status register contains the state of the peripheral functions
|
||||
** and external devices. This register should be read to poll devices
|
||||
** such as the uart when the interrupts are not enabled. Writing to this
|
||||
** register will clear the interrupt.
|
||||
** 3. The Cause register is similar to the status register, with the
|
||||
** exception that it only shows the bits that are set in the mask
|
||||
** register. This register should be read to determine which interrupt(s)
|
||||
** need to be serviced. This register when written to will CAUSE the interrupt.
|
||||
*/
|
||||
#define MG5_INT_STATUS_REG 0xfffe0184 /* Read to determine state/Write to clear */
|
||||
#define MG5_INT_CAUSE_REG 0xfffe0188 /* Read to determine int/Write to cause int */
|
||||
#define MG5_INT_MASK_REG 0xfffe018c /* Set bit here to enable int */
|
||||
|
||||
/*
|
||||
** EDAC Registers
|
||||
*/
|
||||
#define MG5_EDAC_ADDR_REG 0xfffe0190 /* edac error address */
|
||||
#define MG5_EDAC_PARITY_REG 0xfffe0194 /* edac parity */
|
||||
|
||||
/*
|
||||
** High speed serial port registers
|
||||
** This section is reserved for future Mongoose Processors
|
||||
*/
|
||||
|
||||
/*
|
||||
** Floating Point Register
|
||||
*/
|
||||
#define MG5_FPU_CNTRL_REG 0xfffe0020 /* FPU control register */
|
||||
|
||||
/*
|
||||
** MAVN Registers
|
||||
*/
|
||||
#define MG5_MAVN_TEST_REG 0xfffe01b4 /* test mavn */
|
||||
#define MG5_MAVN_PRIVLEGE_REG 0xfffe01b8 /* privlege bits */
|
||||
#define MG5_MAVN_VIOLATION_REG 0xfffe01bc /* address of violation */
|
||||
#define MG5_MAVN_RANGE_0_REG 0xfffe01c0 /* Range 0 */
|
||||
#define MG5_MAVN_RANGE_1_REG 0xfffe01c4 /* Range 1 */
|
||||
#define MG5_MAVN_RANGE_2_REG 0xfffe01c8 /* Range 2 */
|
||||
#define MG5_MAVN_RANGE_3_REG 0xfffe01cc /* Range 3 */
|
||||
#define MG5_MAVN_RANGE_4_REG 0xfffe01d0 /* Range 4 */
|
||||
#define MG5_MAVN_RANGE_5_REG 0xfffe01d4 /* Range 5 */
|
||||
|
||||
|
||||
/*
|
||||
** Uart Specific Peripheral Function Registers
|
||||
*/
|
||||
#define MG5_UART_0_RX_REG 0xfffe01e8
|
||||
#define MG5_UART_0_TX_REG 0xfffe01ec
|
||||
#define MG5_UART_0_BAUD_REG 0xfffe01f0
|
||||
#define MG5_UART_1_RX_REG 0xfffe01f4
|
||||
#define MG5_UART_1_TX_REG 0xfffe01f8
|
||||
#define MG5_UART_1_BAUD_REG 0xfffe01fc
|
||||
|
||||
|
||||
/*
|
||||
** Section 2: Bit definitions
|
||||
**
|
||||
*/
|
||||
|
||||
/*
|
||||
** Command Register Bits - defined from 31 to 0
|
||||
*/
|
||||
#define EDAC_ENABLE_BIT 0x80000000
|
||||
#define EDAC_OVERRIDE_BIT 0x40000000
|
||||
/* 29 - 16 reserved */
|
||||
#define UART_1_PARITY_EVEN_BIT 0x00008000
|
||||
#define UART_1_PARITY_ENABLE_BIT 0x00004000
|
||||
#define UART_1_RTS_BIT 0x00002000
|
||||
#define UART_1_TX_ENABLE_BIT 0x00001000
|
||||
#define UART_1_RX_ENABLE_BIT 0x00000800
|
||||
#define UART_1_TX_BREAK_BIT 0x00000400
|
||||
|
||||
#define UART_0_PARITY_EVEN_BIT 0x00000200
|
||||
#define UART_0_PARITY_ENABLE_BIT 0x00000100
|
||||
#define UART_0_RTS_BIT 0x00000080
|
||||
#define UART_0_TX_ENABLE_BIT 0x00000040
|
||||
#define UART_0_RX_ENABLE_BIT 0x00000020
|
||||
#define UART_0_TX_BREAK_BIT 0x00000010
|
||||
|
||||
#define UART_LOOPBACK_MODE_BIT 0x00000008
|
||||
#define UART_CTSN_TEST_BIT 0x00000004
|
||||
#define UART_RESET_BIT 0x00000002
|
||||
|
||||
|
||||
/*
|
||||
** Interrupt Status/Cause/Mask register bits - from 31 to 0
|
||||
*/
|
||||
#define EDAC_SERR_BIT 0x80000000
|
||||
#define EDAC_MERR_BIT 0x40000000
|
||||
/* 29 - 24 reserved */
|
||||
#define UART_0_RX_READY_BIT 0x00008000
|
||||
#define UART_0_TX_READY_BIT 0x00004000
|
||||
#define UART_0_TX_EMPTY_BIT 0x00002000
|
||||
#define UART_0_RX_OVERRUN_BIT 0x00001000
|
||||
#define UART_0_FRAME_ERR_BIT 0x00000800
|
||||
#define UART_0_RESERVED_BIT 0x00000400
|
||||
#define UART_1_RX_READY_BIT 0x00200000
|
||||
#define UART_1_TX_READY_BIT 0x00100000
|
||||
#define UART_1_TX_EMPTY_BIT 0x00080000
|
||||
#define UART_1_RX_OVERRUN_BIT 0x00040000
|
||||
#define UART_1_FRAME_ERR_BIT 0x00020000
|
||||
#define UART_1_RESERVED_BIT 0x00010000
|
||||
#define MAVN_WRITE_ACC_BIT 0x00400000
|
||||
#define MAVN_READ_ACC_BIT 0x00800000
|
||||
#define EXTERN_INT_9_BIT 0x00000200
|
||||
#define EXTERN_INT_8_BIT 0x00000100
|
||||
#define EXTERN_INT_7_BIT 0x00000080
|
||||
#define EXTERN_INT_6_BIT 0x00000040
|
||||
#define EXTERN_INT_5_BIT 0x00000020
|
||||
#define EXTERN_INT_4_BIT 0x00000010
|
||||
#define EXTERN_INT_3_BIT 0x00000008
|
||||
#define EXTERN_INT_2_BIT 0x00000004
|
||||
#define EXTERN_INT_1_BIT 0x00000002
|
||||
#define EXTERN_INT_0_BIT 0x00000001
|
||||
|
||||
|
||||
/*
|
||||
** MAVN Range Bits
|
||||
*/
|
||||
|
||||
#define MAVN_RANGE_0_WRITE_BIT 0x00000001
|
||||
#define MAVN_RANGE_1_WRITE_BIT 0x00000002
|
||||
#define MAVN_RANGE_2_WRITE_BIT 0x00000004
|
||||
#define MAVN_RANGE_3_WRITE_BIT 0x00000008
|
||||
#define MAVN_RANGE_4_WRITE_BIT 0x00000010
|
||||
#define MAVN_RANGE_5_WRITE_BIT 0x00000020
|
||||
|
||||
#define MAVN_GLOBAL_WRITE_BIT 0x00000200
|
||||
|
||||
|
||||
#define MAVN_RANGE_0_READ_BIT 0x00000400
|
||||
#define MAVN_RANGE_1_READ_BIT 0x00000800
|
||||
#define MAVN_RANGE_2_READ_BIT 0x00001000
|
||||
#define MAVN_RANGE_3_READ_BIT 0x00002000
|
||||
#define MAVN_RANGE_4_READ_BIT 0x00004000
|
||||
#define MAVN_RANGE_5_READ_BIT 0x00008000
|
||||
|
||||
#define MAVN_GLOBAL_READ_BIT 0x00080000
|
||||
|
||||
#define MAVN_ENABLE_BIT 0x80000000
|
||||
#define MAVN_TEST_BIT 0x40000000
|
||||
|
||||
#define MAVN_RANGE_NO_ACESS 0x00000000
|
||||
|
||||
#define MAVN_PS_CODE_512 0x00000009
|
||||
#define MAVN_PS_CODE_1K 0x0000000a
|
||||
#define MAVN_PS_CODE_2K 0x0000000b
|
||||
#define MAVN_PS_CODE_4K 0x0000000c
|
||||
#define MAVN_PS_CODE_8K 0x0000000d
|
||||
#define MAVN_PS_CODE_16K 0x0000000e
|
||||
#define MAVN_PS_CODE_32K 0x0000000f
|
||||
#define MAVN_PS_CODE_64K 0x00000010
|
||||
#define MAVN_PS_CODE_128K 0x00000011
|
||||
#define MAVN_PS_CODE_256K 0x00000012
|
||||
#define MAVN_PS_CODE_512K 0x00000013
|
||||
#define MAVN_PS_CODE_1M 0x00000014
|
||||
#define MAVN_PS_CODE_2M 0x00000015
|
||||
|
||||
/*
|
||||
** FPU Control Bits
|
||||
*/
|
||||
#define FPU_CNTRL_CONDITION 0x00800000
|
||||
#define FPU_CNTRL_EXCEPT_E 0x00020000
|
||||
#define FPU_CNTRL_EXCEPT_V 0x00010000
|
||||
#define FPU_CNTRL_EXCEPT_Z 0x00008000
|
||||
#define FPU_CNTRL_EXCEPT_O 0x00004000
|
||||
#define FPU_CNTRL_EXCEPT_U 0x00002000
|
||||
#define FPU_CNTRL_EXCEPT_I 0x00001000
|
||||
#define FPU_CNTRL_TRAP_V 0x00000800
|
||||
#define FPU_CNTRL_TRAP_Z 0x00000400
|
||||
#define FPU_CNTRL_TRAP_O 0x00000200
|
||||
#define FPU_CNTRL_TRAP_U 0x00000100
|
||||
#define FPU_CNTRL_TRAP_I 0x00000080
|
||||
#define FPU_CNTRL_STICKY_V 0x00000040
|
||||
#define FPU_CNTRL_STICKY_Z 0x00000020
|
||||
#define FPU_CNTRL_STICKY_O 0x00000010
|
||||
#define FPU_CNTRL_STICKY_U 0x00000008
|
||||
#define FPU_CNTRL_STICKY_I 0x00000004
|
||||
#define FPU_CNTRL_ROUND_RN 0x00000000
|
||||
#define FPU_CNTRL_ROUND_RZ 0x00000001
|
||||
#define FPU_CNTRL_ROUND_RP 0x00000002
|
||||
#define FPU_CNTRL_ROUND_RM 0x00000003
|
||||
|
||||
#define FPU_EXCEPTIONS FPU_CNTRL_TRAP_V|FPU_CNTRL_TRAP_Z|FPU_CNTRL_TRAP_O|FPU_CNTRL_TRAP_U|FPU_CNTRL_TRAP_I
|
||||
#define FPU_CONFIGURATION FPU_EXCEPTIONS|FPU_CNTRL_ROUND_RN
|
||||
|
||||
/*
|
||||
**
|
||||
** Section 3 -- Masks
|
||||
**
|
||||
*/
|
||||
|
||||
#define UART_TX_BAUD_MASK 0x00007FFF
|
||||
#define UART_RX_BAUD_MASK 0x7FFF0000
|
||||
#define UART_DATA_MASK 0x000000FF
|
||||
|
||||
#define UART_TX_BAUD_4800(x) ((((x*1000000)/4800) - 1) & UART_TX_BAUD_MASK)
|
||||
#define UART_TX_BAUD_9600(x) ((((x*1000000)/9600) - 1) & UART_TX_BAUD_MASK)
|
||||
#define UART_TX_BAUD_19200(x) ((((x*1000000)/19200) - 1)& UART_TX_BAUD_MASK)
|
||||
#define UART_TX_BAUD_38400(x) ((((x*1000000)/38400) - 1)& UART_TX_BAUD_MASK)
|
||||
|
||||
#define UART_RX_BAUD_4800(x) (((((x*1000000)/4800) - 1) << 16) & UART_RX_BAUD_MASK)
|
||||
#define UART_RX_BAUD_9600(x) (((((x*1000000)/9600) - 1) << 16) & UART_RX_BAUD_MASK)
|
||||
#define UART_RX_BAUD_19200(x) (((((x*1000000)/19200) - 1) << 16)& UART_RX_BAUD_MASK)
|
||||
#define UART_RX_BAUD_38400(x) (((((x*1000000)/38400) - 1) << 16)& UART_RX_BAUD_MASK)
|
||||
|
||||
#define UART_BAUD_4800(x) ((((x*1000000)/4800) - 1) & UART_TX_BAUD_MASK) | (((((x*1000000)/4800) - 1) << 16) & UART_RX_BAUD_MASK)
|
||||
#define UART_BAUD_9600(x) ((((x*1000000)/9600) - 1) & UART_TX_BAUD_MASK) | (((((x*1000000)/9600) - 1) << 16) & UART_RX_BAUD_MASK)
|
||||
#define UART_BAUD_19200(x) ((((x*1000000)/19200) - 1)& UART_TX_BAUD_MASK) | (((((x*1000000)/19200) - 1) << 16)& UART_RX_BAUD_MASK)
|
||||
#define UART_BAUD_38400(x) ((((x*1000000)/38400) - 1)& UART_TX_BAUD_MASK) | (((((x*1000000)/38400) - 1) << 16)& UART_RX_BAUD_MASK)
|
||||
|
||||
#define EDAC_PARITY_MASK 0x000000FF
|
||||
|
||||
#define MAVN_START_ADDR_MASK 0xFFFFFE00
|
||||
#define MAVN_PS_CODE_MASK 0x0000001F
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* lr33000.h - defines for LSI Logic LR33000 */
|
||||
|
||||
/* Define counter/timer register addresses */
|
||||
#define M_TIC1 0xfffe0000 /* timer 1 initial count */
|
||||
#define M_TC1 0xfffe0004 /* timer 1 control */
|
||||
#define M_TIC2 0xfffe0008 /* timer 2 initial count */
|
||||
#define M_TC2 0xfffe000c /* timer 2 control */
|
||||
#define M_RTIC 0xfffe0010 /* refresh timer */
|
||||
|
||||
#ifdef LANGUAGE_C
|
||||
#define TIC1 (*((volatile unsigned long *)M_TIC1)) /* timer1 count */
|
||||
#define TC1 (*((volatile unsigned long *)M_TC1)) /* timer1 cntrl */
|
||||
#define TIC2 (*((volatile unsigned long *)M_TIC2)) /* timer2 count */
|
||||
#define TC2 (*((volatile unsigned long *)M_TC2)) /* timer2 cntrl */
|
||||
#define RTIC (*((volatile unsigned long *)M_RTIC)) /* refrsh timer */
|
||||
#endif
|
||||
|
||||
/* Definitions for counter/timer control register bits */
|
||||
#define TC_CE 0x00000004 /* count enable */
|
||||
#define TC_IE 0x00000002 /* interrupt enable */
|
||||
#define TC_INT 0x00000001 /* interrupt request */
|
||||
|
||||
/* lr33000.h */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define _LR33300_
|
||||
|
||||
#define M_SRAM 0xfffe0100 /* SRAM config reg */
|
||||
#define M_SPEC0 0xfffe0104
|
||||
#define M_SPEC1 0xfffe0108
|
||||
#define M_SPEC2 0xfffe010c
|
||||
#define M_SPEC3 0xfffe0110
|
||||
#define M_DRAM 0xfffe0120 /* DRAM config reg */
|
||||
|
||||
#ifdef LANGUAGE_C
|
||||
#define SRAM (*((volatile unsigned long *)M_SRAM))
|
||||
#define SPEC0 (*((volatile unsigned long *)M_SPEC0))
|
||||
#define SPEC1 (*((volatile unsigned long *)M_SPEC1))
|
||||
#define SPEC2 (*((volatile unsigned long *)M_SPEC2))
|
||||
#define SPEC3 (*((volatile unsigned long *)M_SPEC3))
|
||||
#define DRAM (*((volatile unsigned long *)M_DRAM))
|
||||
#endif
|
||||
|
||||
/* wait-state config registers */
|
||||
#define SPC_INHIBITMASK (0xf<<24)
|
||||
#define SPC_INHIBITSHFT 24
|
||||
#define SPC_EXTGNT (1<<23)
|
||||
#define SPC_16WIDE (1<<22)
|
||||
#define SPC_8WIDE (1<<21)
|
||||
#define SPC_PENA (1<<20)
|
||||
#define SPC_CACHED (1<<19)
|
||||
#define SPC_CSDLYMASK (3<<17)
|
||||
#define SPC_CSDLYSHFT 17
|
||||
#define SPC_BLKENA (1<<16)
|
||||
#define SPC_BLKWAITMASK (7<<13)
|
||||
#define SPC_BLKWAITSHFT 13
|
||||
#define SPC_RECMASK (63<<7)
|
||||
#define SPC_RECSHFT 7
|
||||
#define SPC_WAITENA (1<<6)
|
||||
#define SPC_WAITMASK (63<<0)
|
||||
#define SPC_WAITSHFT 0
|
||||
|
||||
/* DCR */
|
||||
#define DRAM_DLP1 (1<<28)
|
||||
#define DRAM_SYNC (1<<27)
|
||||
#define DRAM_SCFG (1<<26)
|
||||
#define DRAM_DMARDY (1<<25)
|
||||
#define DRAM_DMABLKMASK (7<<22)
|
||||
#define DRAM_DMABLKSHFT 22
|
||||
#define DRAM_DPTHMASK (3<<20)
|
||||
#define DRAM_DPTHSHFT 20
|
||||
#define DRAM_RDYW (1<<19)
|
||||
#define DRAM_PGSZMASK (7<<16)
|
||||
#define DRAM_PGSZSHFT 16
|
||||
#define DRAM_PGMW (1<<15)
|
||||
#define DRAM_RFWEMASK (3<<13)
|
||||
#define DRAM_RFWESHFT 13
|
||||
#define DRAM_RFEN (1<<12)
|
||||
#define DRAM_RDYEN (1<<11)
|
||||
#define DRAM_BFD (1<<10)
|
||||
#define DRAM_PE (1<<9)
|
||||
#define DRAM_RPCMASK (3<<7)
|
||||
#define DRAM_RPCSHFT 7
|
||||
#define DRAM_RCDMASK (3<<5)
|
||||
#define DRAM_RCDSHFT 5
|
||||
#define DRAM_CS (1<<4)
|
||||
#define DRAM_CLMASK (7<<1)
|
||||
#define DRAM_CLSHFT 1
|
||||
#define DRAM_DCE (1<<0)
|
||||
|
||||
/* _LR33300_ */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define _ERNIE_CORE_
|
||||
|
||||
#define M_BIU 0xfffe0130
|
||||
|
||||
#ifdef LANGUAGE_C
|
||||
#define BIU (*((volatile unsigned long *)M_BIU))
|
||||
|
||||
#define C0_TAR 6 /* target address register */
|
||||
#define C0_BDAM 9 /* breakpoint data addr mask */
|
||||
#define C0_BPCM 11 /* breakpoint instr addr mask */
|
||||
#else
|
||||
#define C0_TAR $6 /* target address register */
|
||||
#define C0_BDAM $9 /* breakpoint data addr mask */
|
||||
#define C0_BPCM $11 /* breakpoint instr addr mask */
|
||||
#endif
|
||||
|
||||
/* cause register */
|
||||
#define CAUSE_BT (1<<30) /* branch taken */
|
||||
|
||||
/* BIU */
|
||||
#define BIU_NOSTR (1<<17)
|
||||
#define BIU_LDSCH (1<<16)
|
||||
#define BIU_BGNT (1<<15)
|
||||
#define BIU_NOPAD (1<<14)
|
||||
#define BIU_RDPRI (1<<13)
|
||||
#define BIU_INTP (1<<12)
|
||||
#define BIU_IS1 (1<<11)
|
||||
#define BIU_IS0 (1<<10)
|
||||
#define BIU_IBLKSZMASK (3<<8)
|
||||
#define BIU_IBLKSZSHFT 8
|
||||
#define BIU_IBLKSZ2 (0<<BIU_IBLKSZSHFT)
|
||||
#define BIU_IBLKSZ4 (1<<BIU_IBLKSZSHFT)
|
||||
#define BIU_IBLKSZ8 (2<<BIU_IBLKSZSHFT)
|
||||
#define BIU_IBLKSZ16 (3<<BIU_IBLKSZSHFT)
|
||||
#define BIU_DS (1<<7)
|
||||
#define BIU_DS1 (1<<7)
|
||||
#define BIU_DS0 (1<<6)
|
||||
#define BIU_DBLKSZMASK (3<<4)
|
||||
#define BIU_DBLKSZSHFT 4
|
||||
#define BIU_DBLKSZ2 (0<<BIU_DBLKSZSHFT)
|
||||
#define BIU_DBLKSZ4 (1<<BIU_DBLKSZSHFT)
|
||||
#define BIU_DBLKSZ8 (2<<BIU_DBLKSZSHFT)
|
||||
#define BIU_DBLKSZ16 (3<<BIU_DBLKSZSHFT)
|
||||
#define BIU_RAM (1<<3)
|
||||
#define BIU_TAG (1<<2)
|
||||
#define BIU_INV (1<<1)
|
||||
#define BIU_LOCK (1<<0)
|
||||
|
||||
/* _ERNIE_CORE_ */
|
||||
|
||||
|
||||
/* Definitions for cache sizes */
|
||||
|
||||
#define LR33300_IC_SIZE 0x1000 /* 33300 Inst cache = 4Kbytes */
|
||||
#define LR33300_DC_SIZE 0x800 /* 33300 Data cache = 2Kbytes */
|
||||
|
||||
Reference in New Issue
Block a user