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adapt timebase macros to support MPC8xx again

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This commit is contained in:
Thomas Doerfler
2008-10-02 12:41:56 +00:00
parent e1efd54506
commit 224a429bcb
2 changed files with 40 additions and 11 deletions
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5
cpukit/ChangeLog
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@@ -1,3 +1,8 @@
2008-10-02 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* score/cpu/powerpc/rtems/score/cpu.h: adapt timebase macros to
support MPC8xx again
2008-10-01 Gene Smith <gene.smith@siemens.com> 2008-10-01 Gene Smith <gene.smith@siemens.com>
PR 1328/cpukit PR 1328/cpukit

46
cpukit/score/cpu/powerpc/rtems/score/cpu.h
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@@ -412,6 +412,11 @@ static inline uint32_t CPU_swap_u32(
* we run in supervisory mode so that should work on * we run in supervisory mode so that should work on
* all CPUs. In user mode we'd have a problem... * all CPUs. In user mode we'd have a problem...
* 2007/11/30, T.S. * 2007/11/30, T.S.
*
* Things _are_ even worse. MPC8xx does not support the SPRs,
* so we need a way to fetch the timebase either with a mftb or a mfspr
* Sigh.
* 2008/09/30 Th. Doerfler.
* *
* OTOH, PSIM currently lacks support for reading * OTOH, PSIM currently lacks support for reading
* SPRs 268/269. You need GDB patch sim/2376 to avoid * SPRs 268/269. You need GDB patch sim/2376 to avoid
@@ -419,9 +424,24 @@ static inline uint32_t CPU_swap_u32(
*/ */
#define CPU_Get_timebase_low( _value ) \ #define CPU_Get_timebase_low( _value ) \
asm volatile( "mftb %0" : "=r" (_value) ) asm volatile( "mftb %0" : "=r" (_value) )
#else #elif 0
#define CPU_Get_timebase_low( _value ) \ #define CPU_Get_timebase_low( _value ) \
asm volatile( "mfspr %0,268" : "=r" (_value) ) asm volatile( "mfspr %0,268" : "=r" (_value) )
#else
#define CPU_Get_timebase_low( _value ) \
do { \
uint32_t _pvr; \
\
asm volatile( "mfpvr %0" : "=r" (_pvr) ); \
if ((_pvr >> 16) == 0x0050) { \
/* we are on a MPC8xx, so use "mftb" */ \
asm volatile( "mftb %0" : "=r" (_value) ); \
} \
else { \
/* we are on a different PPC flavour, so use "mfspr" */ \
asm volatile( "mfspr %0,268" : "=r" (_value) ); \
} \
} while (0)
#endif #endif
#define rtems_bsp_delay( _microseconds ) \ #define rtems_bsp_delay( _microseconds ) \
@@ -474,16 +494,20 @@ static inline uint64_t PPC_Get_timebase_register( void )
uint64_t tbr; uint64_t tbr;
do { do {
#if 0 uint32_t _pvr;
/* See comment above (CPU_Get_timebase_low) */
asm volatile( "mftbu %0" : "=r" (tbr_high_old)); asm volatile( "mfpvr %0" : "=r" (_pvr) );
asm volatile( "mftb %0" : "=r" (tbr_low)); if ((_pvr >> 16) == 0x0050) {
asm volatile( "mftbu %0" : "=r" (tbr_high)); /* we are on a MPC8xx and can't access TB via SPRs */
#else asm volatile( "mftbu %0" : "=r" (tbr_high_old));
asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); asm volatile( "mftb %0" : "=r" (tbr_low));
asm volatile( "mfspr %0, 268" : "=r" (tbr_low)); asm volatile( "mftbu %0" : "=r" (tbr_high));
asm volatile( "mfspr %0, 269" : "=r" (tbr_high)); }
#endif else {
asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
asm volatile( "mfspr %0, 268" : "=r" (tbr_low));
asm volatile( "mfspr %0, 269" : "=r" (tbr_high));
}
} while ( tbr_high_old != tbr_high ); } while ( tbr_high_old != tbr_high );
tbr = tbr_high; tbr = tbr_high;