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2006-09-11 Joel Sherrill <joel@OARcorp.com>

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* mongoosev/vectorisrs/vectorisrs.c: Convert C++ style comments to C
	style.
This commit is contained in:
Joel Sherrill
2006-09-11 21:47:05 +00:00
parent 6094c1a4d9
commit 21d3049411
2 changed files with 50 additions and 47 deletions
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5
c/src/lib/libcpu/mips/ChangeLog
View File

@@ -1,3 +1,8 @@
2006-09-11 Joel Sherrill <joel@OARcorp.com>
* mongoosev/vectorisrs/vectorisrs.c: Convert C++ style comments to C
style.
2006-06-08 Bruce Robinson <brucer@pmccorp.com> 2006-06-08 Bruce Robinson <brucer@pmccorp.com>
* Makefile.am: add interruptmask.c * Makefile.am: add interruptmask.c

92
c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
View File

@@ -70,10 +70,10 @@ int assertSoftwareInterrupt( uint32_t n )
} while (0) } while (0)
// /*
// Instrumentation tweaks for isr timing measurement, turning them off * Instrumentation tweaks for isr timing measurement, turning them off
// via this #if will remove the code entirely from the RTEMS kernel. * via this #if will remove the code entirely from the RTEMS kernel.
// */
#if 0 #if 0
#define SET_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 1; #define SET_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 1;
@@ -94,26 +94,26 @@ static volatile uint32_t _ivcause, _ivsr;
static uint32_t READ_CAUSE(void) static uint32_t READ_CAUSE(void)
{ {
mips_get_cause( _ivcause ); mips_get_cause( _ivcause );
_ivcause &= SR_IMASK; // mask off everything other than the interrupt bits _ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */
return ((_ivcause & (_ivsr & SR_IMASK)) >> CAUSE_IPSHIFT); return ((_ivcause & (_ivsr & SR_IMASK)) >> CAUSE_IPSHIFT);
} }
// /*
// This rather strangely coded routine enforces an interrupt priority * This rather strangely coded routine enforces an interrupt priority
// scheme. As it runs thru finding whichever interrupt caused it to get * scheme. As it runs thru finding whichever interrupt caused it to get
// here, it test for other interrupts arriving in the meantime (maybe it * here, it test for other interrupts arriving in the meantime (maybe it
// occured while the vector code is executing for instance). Each new * occured while the vector code is executing for instance). Each new
// interrupt will be served in order of its priority. In an effort to * interrupt will be served in order of its priority. In an effort to
// minimize overhead, the cause register is only fetched after an * minimize overhead, the cause register is only fetched after an
// interrupt is serviced. Because of the intvect goto's, this routine * interrupt is serviced. Because of the intvect goto's, this routine
// will only exit when all interrupts have been serviced and no more * will only exit when all interrupts have been serviced and no more
// have arrived, this improves interrupt latency at the cost of * have arrived, this improves interrupt latency at the cost of
// increasing scheduling jitter; though scheduling jitter should only * increasing scheduling jitter; though scheduling jitter should only
// become apparent in high interrupt load conditions. * become apparent in high interrupt load conditions.
// */
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{ {
uint32_t cshifted; uint32_t cshifted;
@@ -127,11 +127,12 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
if( cshifted & 0x3 ) if( cshifted & 0x3 )
{ {
// making the software interrupt the highest priority is kind of /* making the software interrupt the highest priority is kind of
// stupid, but it makes the bit testing lots easier. On the other * stupid, but it makes the bit testing lots easier. On the other
// hand, these ints are infrequently used and the testing overhead * hand, these ints are infrequently used and the testing overhead
// is minimal. Who knows, high-priority software ints might be * is minimal. Who knows, high-priority software ints might be
// handy in some situation. * handy in some situation.
*/
/* unset both software int cause bits */ /* unset both software int cause bits */
mips_set_cause( _ivcause & ~(3 << CAUSE_IPSHIFT) ); mips_set_cause( _ivcause & ~(3 << CAUSE_IPSHIFT) );
@@ -210,21 +211,21 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
} }
*/ */
// /*
// iterate thru 32 bits in 4 chunks of 8 bits each. This lets us * iterate thru 32 bits in 4 chunks of 8 bits each. This lets us
// quickly get past unasserted interrupts instead of flogging our * quickly get past unasserted interrupts instead of flogging our
// way thru a full 32 bits. pf_mask shifts left 8 bits at a time * way thru a full 32 bits. pf_mask shifts left 8 bits at a time
// to serve as a interrupt cause test mask. * to serve as a interrupt cause test mask.
// */
for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) ) for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) )
{ {
if ( pf_icr & pf_mask ) if ( pf_icr & pf_mask )
{ {
// one or more of the 8 bits we're testing is high /* one or more of the 8 bits we're testing is high */
m = (1 << bit); m = (1 << bit);
// iterate thru the 8 bits, servicing any of the interrupts /* iterate thru the 8 bits, servicing any of the interrupts */
for(i=0; (i<8 && pf_icr); (i++, m <<= 1)) for(i=0; (i<8 && pf_icr); (i++, m <<= 1))
{ {
if( pf_icr & m ) if( pf_icr & m )
@@ -233,17 +234,18 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit + i, frame ); CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit + i, frame );
CLR_ISR_FLAG( 0x80 + ((bit + i) * 4) ); CLR_ISR_FLAG( 0x80 + ((bit + i) * 4) );
// or each serviced interrupt into our interrupt clear /* or each serviced interrupt into our interrupt clear mask */
// mask
pf_reset |= m; pf_reset |= m;
// xor off each int we service so we can immediately /* xor off each int we service so we can immediately
// exit once we get the last one * exit once we get the last one
*/
pf_icr %= m; pf_icr %= m;
// if another interrupt has arrived, jump out right /* if another interrupt has arrived, jump out right
// away but be sure to reset all the interrupts we've * away but be sure to reset all the interrupts we've
// already serviced * already serviced
*/
if( READ_CAUSE() & 0xff ) goto pfexit; if( READ_CAUSE() & 0xff ) goto pfexit;
} }
} }
@@ -253,14 +255,10 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, pf_reset ); MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, pf_reset );
} }
// /*
// this is a last ditch interrupt check, if an interrupt arrives * this is a last ditch interrupt check, if an interrupt arrives
// after this step, servicing it will incur the entire interrupt * after this step, servicing it will incur the entire interrupt
// overhead cost. * overhead cost.
// */
if( (cshifted = READ_CAUSE()) & 0xff ) goto intvect; if( (cshifted = READ_CAUSE()) & 0xff ) goto intvect;
} }
// eof