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m68k/mvme167: Remove obsolete BSP family

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Updates #5031
This commit is contained in:
Joel Sherrill
2025-02-05 15:30:28 -06:00
committed by Kinsey Moore
parent 17ae630e9a
commit 2188c428fb
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bsps/m68k/mvme167/README.md
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MVME167
=======
This is a README file for the MVME167 port of RTEMS 4.5.0.
Please send any comments, improvements, or bug reports to:
Charles-Antoine Gauthier
charles.gauthier@nrc.ca
or
Darlene Stewart
Darlene.Stewart@nrc.ca
Software Engineering Group
Institute for Information Technology
National Research Council of Canada
Ottawa, ON, K1A 0R6
Canada
Disclaimer
----------
The National Research Council of Canada is distributing this RTEMS
board support package for the Motorola MVME167 as free software; you
can redistribute it and/or modify it under terms of the GNU General
Public License as published by the Free Software Foundation; either
version 2, or (at your option) any later version. This software is
distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details. You should have received a copy of the GNU General
Public License along with RTEMS; see file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
Under no circumstances will the National Research Council of Canada
nor Her Majesty the Queen in right of Canada assume any liablility
for the use this software, nor any responsibility for its quality or
its support.
Installation
------------
Nothing unique to the MVME167. It uses the standard build process for
m68k targets. You will need to edit linkcmds to put in the start address
of your board. We do TFTP transfers to our target. The mvme167.cfg file
builds only the ELF images, which we download to the target, skipping
over the first 0x54 bytes; Motorola S-records are not generated. Edit
this file if you want S-records.
Port Description
Console driver
---------------
This BSP includes an termios-capable interrupt-driven I/O console driver
that supports all four serial ports on the MVME167 model. The port labelled
Serial Port 1/Console on the MVME712 is normally used by 167Bug; do not open
/dev/tty00 if you are debugging using 167Bug.
Limited support is provided for polled terminal I/O. This is used when
running the timing tests, and by the printk() debug output function.
Polled I/O may use termios, or it may bypass those services. The printk()
function does not use termios. When polled I/O is used, the terminal settings
must be set through 167-Bug; trying to change the line settings through RTEMS
has no effect.
Three is no support for using interrupt-driven I/O without termios support.
The default configuration is to use polled I/O and to bypass termios. This
is done so the test can be built at the same time as the rest of the system.
It is highly recommended that the defaults be changed in the mvme167.cfg file
to reflect the desired defaults, or that the appropriate parameters be set up
in NVRAM to select the appropriate I/O modes at boot time.
When configured for interrupt-driven I/O, the console is initialized with
whatever parameters are set up in termios before it calls the firtOpen driver
callback, EXCEPT THAT HARDWARE HANDSHAKING IS TURNED OFF, i.e. CLOCAL is set
in the struct termios c_cflag field. We use 3-wire cables for I/O, and find
hardware handshaking a pain. If you enable hardware handshaking, you must drive
CTS* low on the CD2401 for output to occur. If the port is in the DTE
configuration, you must drive the RS-232 CTS line to space; if the port is
in the DCE configuration, you must drive the RS-232 RTS line to space.
To use interrupt-driven I/O, set the CD2401_IO_MODE manifest constant to 1 in
rtems/make/custom/mvme167.cfg, or configure the appropriate parameter in
User Area Non-volatile RAM. See the Configuration Parameters section below
for instructions on setting up NVRAM.
To use termios, set the CD2401_USE_TERMIOS manifest constant to 1 in
rtems/make/custom/mvme167.cfg, or configure the appropriate parameter in
User Area Non-volatile RAM. See the Configuration Parameters section
below for instructions on setting up NVRAM.
The RTEMS console, i.e. the port used by stdin, stdout and stderr (do not
confuse it with the port labelled Console on the MVME712), must be
specified in the rtems/make/custom/mvme167.cfg file, or in the NVRAM
parameters. Set the value of CONSOLE_MINOR appropriately. See below for a
list of choices. See the Configuration Parameters section below for
instructions on setting up NVRAM.
The RTEMS printk port, i.e. the port where printk sends it debugging output
text, must be specified in the rtems/make/custom/mvme167.cfg file, or in the
NVRAM parameters. Set the value of PRINTK_MINOR appropriately. See below for a
list of choices. See the Configuration Parameters section below for
instructions on setting up NVRAM.
Interrupt-driven and polled I/O cannot be mixed in the MVME167, except that
printk always used polled I/O without termios. If interrupt-driven I/O is
used and printk is used, do not open the device that printk uses from an
RTEMS application.
Console and printk port choices:
```
0 - /dev/tty0, Serial Port 1/Console on the MVME712M.
1 - /dev/tty1, Serial Port 2/TTY01 on the MVME712M.
2 - /dev/tty2, Serial Port 3 on the MVME712M.
3 - /dev/tty3, Serial Port 4 on the MVME712M.
```
Setting the RTEMS console to port 0 when interrupt-driven I/O is specified
will prevent 167-Bug from using that port.
To use polled I/O on port 2 or 3, the port must be configured in 167-Bug. See
the "PF" command in the "Debugging Package for Motorola 68K CISC CPUs User's
Manual", part number 68KBUG.
Floating-point
--------------
The MC68040 has a built-in FPU. This FPU does not implement all the
instruction of the MC68881/MC68882 floating-point coprocessors in
hardware. The -m68040 compilation options instructs gcc to not generate
the missing instructions. All of the RTEMS code is built this way. Some
of the missing functionality must be supplied by external libraries. The
required functions are part of libgcc.a.
The issue gets complicated because libc, libm and libgcc do not come as
m68040-specific variants. The default variants of these libraries are for the
MC68020 and MC68030. There are specific variants for the MC68000 (which has
limited addressing modes with respect to later family members), and specific
variants for systems without a floating-point unit, either a built-in FPU or
a coprocessor. These latter variants will be referred to as the msoft-float
variants. There is a msoft-float variant for the MC68000, and one for the
other family members.
The default variants of libc, libm and libgcc appear to work just fine for the
MC68040, AS LONG AS NO FLOATING POINT FUNCTIONS ARE CALLED. In particular,
printf() and scanf() raise unimplemented floating-point instruction exceptions
at run time. Expect almost every function that must compute a floating-point
result to also raise unimplemented floating-point instruction exceptions. Do
not use these variants if your application does any floating-point operations,
unless you use the Motorola FPSP package (described further down).
The msoft-float variants do print out floating-point numbers properly, but we
have not tested them extensively, so use them with caution. In particular,
the Paranoia test fails when linked with the msoft-float variants of the
libraries; it goes into an infinite loop after milestone 40.
MSOFT_FLOAT VARIANTS MUST BE USED TOGETHER. If you use the msoft-float variant
of libc and libm, you must also linked with the msoft-float variant of libgcc,
otherwise calls such as printf() print out floating-point values incorrectly.
RTEMS comes with the Motorola FPSP (Floating-Point Support Package) for the
MC68040 (rtems/c/src/lib/libcp/m68k/m68040/fpsp). This package emulates the
missing floating-point instructions. It is built automatically for the
MVME167 and installed in bsp_start().
The FPSP allows the use of the default variants of libc, libm and libgcc.
It also runs the paranoia test properly, and prints out the correct results.
It should probably be used in preference to the msoft-float libraries, as it
appears to work better. The disadvantage of the FPSP is that it increases the
size of the executable by about 60KB and that it relies on run time
exceptions.
If your application does not do any floating-point operations at all, you
should consider disabling the FPSP. In bsp_start(), emove the call to
M68KFPSPInstallExceptionHandlers(), and uncomment the three lines in
mvme167.cfg that redefine which variants of libc, libm and libgcc to link
against.
Configuration Parameters
------------------------
If Jumper J1-4 is installed, certain configuration parameters may be read from
the first 31 bytes of User Area NVRAM starting at 0xFFFC0000. In this case, the
remaining J1-[5-7] jumpers are ignored, and the user is responsible for writing
the appropriate values in NVRAM (via 167-Bug) in order to alter the default
behaviour. A zero value in NVRAM results in the default behaviour. The paramaters
that are configurable and their default settings are described below.
Cache Mode (0xFFFC0000 - 1 byte)
Set the following bits in the byte to set the desired cache mode:
bit 0
0 - data cache disable
1 - data cache enable
bit 1
0 - instruction cache disable
1 - instruction cache enable
bits 2 & 3:
00 = cachable, write-through
01 = cachable, copyback
10 = noncachable, serialized
11 = noncachable
Console driver I/O mode (0xFFFC0001 - 1 byte)
Set the following bits in the byte to set the desired I/O mode:
bit 0
0 - do not use termios
1 - use termios
bit 1
0 - polled I/O
1 - interrupt-driven I/O
Console driver ports (0xFFFC0002 - 1 byte)
Set the following bits in the byte to select the console and printk ports:
bit 0 & 1 select the RTEMS console port
00 - /dev/tty0, Serial Port 1/Console on the MVME712M.
01 - /dev/tty1, Serial Port 2/TTY01 on the MVME712M.
10 - /dev/tty2, Serial Port 3 on the MVME712M.
11 - /dev/tty3, Serial Port 4 on the MVME712M.
bit 4 & 5 select the RTEMS printk port
00 - /dev/tty0, Serial Port 1/Console on the MVME712M.
01 - /dev/tty1, Serial Port 2/TTY01 on the MVME712M.
10 - /dev/tty2, Serial Port 3 on the MVME712M.
11 - /dev/tty3, Serial Port 4 on the MVME712M.
If the printk port is the same as some other port that will be opened by an
RTEMS application, then the driver must use polled I/O, or the printk port
must not be used.
IP Address (0xFFFC0004 - 4 bytes)
write the hexadecimal representation of the IP address of the board in this
locatio, e.g. 192.168.1.2 = 0xC0A80102
default: obtain the IP address from an rtems_bsdnet_ifconfig structure
Netmask (0xFFFC0008 - 4 bytes)
write the hexadecimal representation of the netmask in this location
for example, 255.255.255.0 = 0xFFFFFF00
default: obtain the netmask from an rtems_bsdnet_ifconfig structure
Ethernet Address (0xFFFC000C - 6 bytes)
write the Ethernet address of the board in this location
default: obtain the hardware address from an rtems_bsdnet_ifconfig
structure
Processor ID (0xFFFC0012 - 2 bytes)
reserved for future use
RMA start (0xFFFC0014 - 4 bytes)
reserved for future use
VMA start (0xFFFC0018 - 4 bytes)
reserved for future use
RamSize (0xFFFC001C - 4 bytes)
reserved for future use
Cache Control and Memory Mapping
--------------------------------
If configuration is not obtained from non-volatile RAM (ie. J1-4 is off),
cache control is done through the remaining J1 jumpers as follows:
If Jumper J1-7 is installed, the data cache will be turned on. If Jumper
J1-6 is installed, the instruction cache will be turned on. (If a jumper
is off, its corresponding cache will remain disabled).
If Jumper J1-5 is installed, the data cache will be placed in copyback
mode. If it is removed, it will be placed in writethrough mode.
Currently, block address translation is set up to map the virtual
0x00000000--0x7FFFFFFF to the physical range 0x00000000--0x7FFFFFFF. The
port relies on the hardware to raise exceptions when addressing
non-existent memory. Caching is not controllable on a finer grain.
Networking
----------
If configuration is not obtained from non-volatile RAM (ie. J1-4 is off),
the networking parameters shown above must be specified in an initialized
rtems_bsdnet_ifconfig struct. This structure is declared and initialized to
specify any network devices and includes entries for ip_address, ip_netmask
and hardware_address. See the Network Device Configuration section of the
RTEMS Networking Supplement.
When non-default (non-zero) networking paramaters are provided in NVRAM (ie.
j1-4 is on), the user MUST ensure that the corresponding entries in the
ifconfig struct are NULL. Failing to do so is an error, because it causes
the memory allocated for the initialized struct values to be lost.
Miscellaneous
-------------
The timer and clock drivers were patterned after the MVME162 and MVME152
ports.
At this time, we do not have an MPCI layer for the MVME167. We are planning
to write one.
This port supplies its own fatal_error_handler, which attempts to print some
error message through 167Bug (on the Serial Port 1/Console on the MVME712M).
Host System
-----------
The port was initially developed on an RS-6000 running AIX 4.2. The following
tools were used:
- GNU gcc 2.8.1 configured for a powerpc-ibm-aix4.2.0.0 host and
m68k-rtems target;
- GNU binutils 2.9.1 configured for a powerpc-ibm-aix4.2.0.0 host and
m68k-rtems target;
It was also tested on a Pentium II-based PC running Windows NT Workstation 4.0
and the Cygnus Cygwin32 release b20.1 environment, with the following tools:
- EGCS 1.1.1 configured for a i586-cygwin32 host and m68k-rtems target;
- GNU binutils 2.9.4 configured for a i586-cygwin32 host and m68k-rtems
target;
With the latter environment, be patient; builds take a very looong time...
Current development is done on a Pentium III PC running RedHat Linux 6.1.
At the time this README was composed, the latest working compiler that was
used successfully was gcc version 2.96 20000213 (experimental). Both the C
and C++ compilers were working. Binutils 2.10 are used.
Known Problems
--------------
Polled I/O without termios may not work very well on input. The problem
is that input processing is not done: applications may get characters too
early, and may get characters that they normally would not get, such as
backspace or delete. Furthermore, input is not buffered at all. The latest
versions of rtems seem to set the count field in the rtems_libio_rw_args_t
argument to the buffer size, not to the number of characters expected on
input. Rather than wait for 1024 characters on each call, the driver
returns each character when it is received.
The cdtest will not run with interrupt-driven I/O. The reason is that the
constructors for the static objects are called at boot time when the
interrupts are still disabled. The output buffer fills up, but never empties,
and the application goes into an infinite loop waiting for buffer space. This
should have been documented in the rtems/c/src/tests/PROBLEMS file. The moral
of this story is: do not do I/O from the constructors or destructors of static
objects.
Output stops prematurely in the termios test when the console is operating in
interrupt-driven mode because the serial port is re-initialized before all
characters in the last raw output buffer are sent. Adding calls to tcdrain()
in the test task helps, but it does not solve the problem. What happens is
that the CD2401 raises a transmit interrupt when the last character in the
DMA buffer is written into the transmit FIFO, not when the last character
has been transmitted. When tcdrain() returns, there might be up to 16
characters in the output FIFO. The call to tcsetattr() causes the serial port
to re-initialize, at which point the output FIFO is cleared. We could not find
a way to detect whether characters are still in the FIFO and to wait for them
to be transmitted.
The first raw buffer to be transmitted after the console is re-initialized
with tcsetattr() is garbled. At this time, it does not seem worth while to
track this problem down.
In the stackchk test, an access fault exception is raised after the stack is
blown. This is one case were overwritting the first or last 16 bytes of the
stack does cause problems (but hey, an exception occurred, which is better
than propagating the error).
In the stackchk test, an access fault exception is raised after the stack is
blown. This is one case were overwritting the first or last 16 bytes of the
stack does cause problems (but hey, an exception occurred, which is better
than propagating the error).
When using interrupt-driven I/O, psx08 produces all the expected output, but
it does not return control to 167Bug. Is this test supposed to work with
interrupt-driven console I/O?
What is new
-----------
Support for Java is being actively worked on.
Thanks
------
- to On-Line Applications Research Corporation (OAR) for developing
RTEMS and making it available on a Technology Transfer basis;
- to FSF and Cygnus Support for great free software;
Test Configuration
------------------
Board: Motorola MVME167
CPU: Motorola MC68040
Clock Speed: 25 MHz
RAM: 4 MBytes of 32-bit DRAM with parity
Cache Configuration: Instruction cache on; data cache on, copyback mode.
Times Reported in: microseconds
Timer Source: VMEchip2 Tick Timer 1
GCC Flags: -m68040 -g -O4 -fomit-frame-pointer
Console: Operate in polled mode. Set CD2401_POLLED_IO to 1 in
rtems/c/src/lib/libbsp/m68k/mvme167/console/console.c.
Test Results
------------
Single processor tests: All tests passed, except the following ones:
- paranoia required the FPSP and the default variants of libm (and libc and
libgcc) for us. It may work with the msoft-float variants for you, but it
does require the FPSP.
- cpuuse and malloctest did not work.
- The stackchk test got an access fault exception before the RTEMS stack
checker had had a chance to detect the corrupted stack.
Multi-processort tests: not applicable -- No MPCI layer yet.
Timing tests: See `rtems/c/src/lib/libbsp/m68k/mvme167/times`

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bsps/m68k/mvme167/btimer/btimer.c
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/**
* @file
*
* This file manages the benchmark timer used by the RTEMS Timing Test Suite.
* Each measured time period is demarcated by calls to
* benchmark_timer_initialize() and benchmark_timer_read().
* benchmark_timer_read() usually returns the number of microseconds
* since benchmark_timer_initialize() exitted.
*
* These functions are prototyped in rtems/btimer.h and
* must be implemented as part of the BSP.
*
* This port does not allow the application to select which timer on the
* MVME167 to use for the timer, nor does it allow the application to
* configure the timer. The timer uses the VMEchip2 Tick Timer #1. This timer
* is distinct from the clock, which uses Tick Timer #2 in the VMEchip2.
*
* All page references are to the MVME166/MVME167/MVME187 Single Board
* Computer Programmer's Reference Guide (MVME187PG/D2) with the April 1993
* supplements/addenda (MVME187PG/D2A1).
*/
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modifications of respective RTEMS file:
* Copyright (c) 1998, National Research Council of Canada
*/
#include <rtems.h>
#include <rtems/btimer.h>
#include <bsp.h>
/* Periodic tick interval */
#define TICK_INTERVAL 10000UL /* T1's countdown constant (10 ms) */
#define TIMER_INT_LEVEL 6 /* T1's interrupt level */
#define TIMER_VECTOR (VBR0 * 0x10 + 0x8) /* T1 is vector $X8 (p. 2-71)*/
/* Number of interrupts since timer was re-initialized */
uint32_t Ttimer_val;
/*
* Set to true to return raw value. Normally zero. Depends on being allocated
* in the .bss section and on that section being explicitly zeroed at boot
* time.
*/
bool benchmark_timer_find_average_overhead;
rtems_isr timerisr(rtems_vector_number);
/*
* This routine initializes the Tick Timer 1 on the MVME167 board.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* NOTE: This routine may not work if the optimizer is enabled for some
* compilers. The multiple writes may be optimized away.
*
* It is important that the timer start/stop overhead be
* determined when porting or modifying this code.
*
* THE VMECHIP2 PRESCALER REGISTER IS ASSUMED TO BE SET!
* The prescaler is used by all VMEchip2 timers, including the VMEbus grant
* timeout counter, the DMAC time off timer, the DMAC timer on timer, and the
* VMEbus global timeout timer. The prescaler value is normally set by the
* boot ROM to provide a 1 MHz clock to the timers. For a 25 MHz MVME167, the
* prescaler value should be 0xE7 (page 2-63).
*/
void benchmark_timer_initialize(void)
{
(void) set_vector( timerisr, TIMER_VECTOR, 0 );
Ttimer_val = 0; /* clear timer ISR count */
lcsr->intr_ena &= 0xFEFFFFFF; /* disable tick timer 1 interrupt */
lcsr->intr_clear |= 0x01000000; /* clear tick timer 1 interrupt */
lcsr->intr_level[0] = /* set int level */
(lcsr->intr_level[0] & 0xFFFFFFF0) | TIMER_INT_LEVEL;
lcsr->timer_cmp_1 = TICK_INTERVAL; /* period in compare register */
lcsr->timer_cnt_1 = 0; /* clear tick timer 1 counter */
lcsr->board_ctl |= 7; /* start tick timer 1, reset-on-compare, */
/* and clear overflow counter */
lcsr->intr_ena |= 0x01000000; /* enable tick timer 1 interrupt */
lcsr->vector_base |= MASK_INT; /* unmask VMEchip2 interrupts */
}
#define AVG_OVERHEAD 3UL /* It typically takes 3.0 microseconds */
/* (3 countdowns) to start/stop the timer. */
#define LEAST_VALID 3UL /* Don't trust a value lower than this */
/*
* This routine reads the Tick Timer 1 on the MVME167 board.
*
* Input parameters: NONE
*
* Output parameters: time in microseconds
*
* AVG_OVEREHAD is the overhead for starting and stopping the timer. It
* is usually deducted from the number returned.
*
* LEAST_VALID is the lowest number this routine should trust. Numbers
* below this are "noise" and zero is returned.
*/
benchmark_timer_t benchmark_timer_read(void)
{
uint32_t total;
total = (Ttimer_val * TICK_INTERVAL) + lcsr->timer_cnt_1;
if ( benchmark_timer_find_average_overhead )
return total; /* in one microsecond units */
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
return total - AVG_OVERHEAD;
}
/*
* This routine sets the benchmark_timer_find_average_overhead flag in this
* module.
*
* Input parameters: NONE
*
* Output parameters: time in microseconds
*/
void benchmark_timer_disable_subtracting_average_overhead(
bool find_flag
)
{
benchmark_timer_find_average_overhead = find_flag;
}

50
bsps/m68k/mvme167/btimer/timerisr.S
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/**
* @file
*
* This ISR is used to bump a count of interval "overflow" interrupts which
* have occurred since the timer was started. The number of overflows is taken
* into account in the benchmark_timer_read() routine.
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modifications of respective RTEMS file: COPYRIGHT (c) 1994.
* Copyright (c) 1998, National Research Council of Canada
*/
#include <rtems/asm.h>
BEGIN_CODE
.set INTR_CLEAR_REG, 0xfff40074 | interrupt clear register
.set T1_CNTRL_REG, 0xfff40060 | tick timer 1 control register
.set CLEAR_INT, 0x01000000 | clear tick 1 interrupt
.set CLEAR_OVF, 0x00000004 | clear tick 1 overflow counter
PUBLIC (Ttimer_val)
PUBLIC (timerisr)
SYM (timerisr):
move.l a0, -(a7) | save a0
move.l d0, -(a7) | save d0
move.w sr, -(a7) | save ccr
movea.l #INTR_CLEAR_REG, a0 | a0 = addr of intr clr reg
ori.l #CLEAR_INT, (a0) | clear tick timer 1 intr
movea.l #T1_CNTRL_REG, a0 | a0 = addr of t1 cntrl reg
move.l (a0), d0 | read overflow counter
lsr.l #4, d0 | put overflow in low order bits
andi.l #0xF, d0 | keep only overflow
add.l d0, SYM (Ttimer_val) | increment timer value
ori.l #CLEAR_OVF, (a0) | clear overflow counter
move.w (a7)+, sr | restore ccr
move.l (a7)+, d0 | restore d0
move.l (a7)+, a0 | restore a0
rte
END_CODE
END

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bsps/m68k/mvme167/clock/ckinit.c
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/*
* This port does not allow the application to select which timer on the
* MVME167 to use for the clock, nor does it allow the application to
* configure the clock. The clock uses the VMEchip2 Tick Timer #2. This
* timer is set up to raise a MC680x0 level-6 interrupt every 1 ms. The
* interrupt vector is 0x69.
*
* All page references are to the MVME166/MVME167/MVME187 Single Board
* Computer Programmer's Reference Guide (MVME187PG/D2) with the April
* 1993 supplements/addenda (MVME187PG/D2A1).
*/
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modifications of respective RTEMS files:
* Copyright (c) 1998, National Research Council of Canada
*/
#include <stdlib.h>
#include <bsp.h>
#include <rtems/clockdrv.h>
#define MS_COUNT 1000 /* T2's countdown constant (1 ms) */
#define CLOCK_INT_LEVEL 6 /* T2's interrupt level */
#define CLOCK_VECTOR (VBR0 * 0x10 + 0x9) /* T2 is vector $X9 (p. 2-71)*/
/*
* Clock_driver_ticks is a monotonically increasing counter of the number of
* VMEchip2 timer #2 ticks since the driver was initialized.
*/
volatile uint32_t Clock_driver_ticks;
/*
* Clock_isrs is the number of clock ISRs until the next invocation of the
* RTEMS clock tick routine. This clock tick device driver gets an interrupt
* once a millisecond and counts down until the length of time between the
* user configured microseconds per tick has passed. This allows the clock
* device to "tick" faster than the kernel clock. Of course, the kernel clock
* cannot tick faster than the hardware clock. Therefore, the kernel clock
* ticks cannot occur more frequently than every 1 millisecond.
*/
uint32_t Clock_isrs;
/*
* Records the previous clock ISR (should be NULL)
*/
rtems_isr_entry Old_ticker;
/*
* Called when the kernel exits.
*/
void clock_exit( void );
/*
* VMEchip2_T2_isr
*
* C ISR Handler. Increment the number of internal ticks. If it is time for a
* kernel clock tick (if Clock_isrs == 1), call rtems_clock_tick() to signal
* the event and reset the Clock_isrs counter; else, just decrement it.
*/
static rtems_isr VMEchip2_T2_isr(
rtems_vector_number vector
)
{
char overflow; /* Content of overflow counter */
long i;
long ct; /* Number of T2 ticks per RTEMS ticks */
ct = rtems_configuration_get_microseconds_per_tick() / 1000;
/*
* May have missed interrupts, so should look at the overflow counter.
*/
lcsr->intr_clear |= 0x02000000; /* Clear the interrupt */
overflow = (lcsr->board_ctl >> 12) & 0xF;
lcsr->board_ctl |= 0x400; /* Reset overflow counter */
/* Attempt to protect against one more period */
if ( overflow == 0 )
overflow = 16;
Clock_driver_ticks += overflow; /* One or more internal ticks */
if ( Clock_isrs <= overflow ) {
/* If its time for kernel clock ticks, signal the events to RTEMS */
for( i = overflow - Clock_isrs; i >= 0; i -= ct ) {
rtems_clock_tick();
}
/* Reset the counter */
Clock_isrs = (uint32_t)-i;
}
else
Clock_isrs -= overflow;
}
/*
* VMEchip2_T2_initialize
*
* Initialize the VMEchip2 Tick Timer #2.
*
* THE VMECHIP2 PRESCALER REGISTER IS ASSUMED TO BE SET!
* The prescaler is used by all VMEchip2 timers, including the VMEbus grant
* timeout counter, the DMAC time off timer, the DMAC timer on timer, and the
* VMEbus global timeout timer. The prescaler value is normally set by the
* boot ROM to provide a 1 MHz clock to the timers. For a 25 MHz MVME167, the
* prescaler value should be 0xE7 (page 2-63).
*/
static void VMEchip2_T2_initialize( void )
{
Clock_driver_ticks = 0;
Clock_isrs = rtems_configuration_get_microseconds_per_tick() / 1000;
lcsr->intr_ena &= 0xFDFFFFFF; /* Disable tick timer 2 interrupt */
lcsr->intr_clear = 0x02000000; /* Clear tick timer 2 interrupt */
lcsr->intr_level[0] = /* Set tick timer 2 interrupt level */
(lcsr->intr_level[0] & 0xFFFFFF0F ) | (CLOCK_INT_LEVEL << 4);
lcsr->timer_cmp_2 = MS_COUNT; /* Period in compare register */
lcsr->timer_cnt_2 = 0; /* Clear tick timer 2 counter */
Old_ticker = /* Install C ISR */
(rtems_isr_entry) set_vector( VMEchip2_T2_isr, CLOCK_VECTOR, 1 );
lcsr->board_ctl |= 0x700; /* Start tick timer 2, reset-on-compare, */
/* and clear tick timer 2 overflow counter */
lcsr->intr_ena |= 0x02000000; /* Enable tick timer 2 interrupt */
lcsr->vector_base |= 0x00800000;/* Unmask VMEchip2 interrupts */
atexit( clock_exit ); /* Turn off T2 interrupts when we exit */
}
/*
* This routine stops the VMEchip2 T2 timer, disables its interrupt, and
* re-install the old interrupt vectors.
*/
void clock_exit( void )
{
lcsr->board_ctl &= 0xFFFFFEFF; /* Stop tick timer 2 */
lcsr->intr_ena &= 0xFDFFFFFF; /* Disable tick timer 2 interrupt */
lcsr->intr_clear = 0x02000000; /* Clear tick timer 2 interrupt */
set_vector( Old_ticker, CLOCK_VECTOR, 1 );
}
void _Clock_Initialize( void )
{
VMEchip2_T2_initialize();
}

42
bsps/m68k/mvme167/config/mvme167.cfg
View File

@@ -1,42 +0,0 @@
#
# Config file for the mvme167 BSP
#
# THIS BSP USES ELF IMAGES. IT WILL NOT WORK WITH COFF UNLESS CHANGES
# ARE MADE TO THE LINKCMDS FILE.
RTEMS_CPU=m68k
include $(RTEMS_ROOT)/make/custom/default.cfg
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it. We also specify the BSP during compilation.
# This should really get its own flag, but it works here.
#
CPU_CFLAGS = -mcpu=68040
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g -fno-omit-frame-pointer
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections
# We use TFTP to transfer files to the MVME167. We generate binary files
# rather than S-records. We skip the header during downloads.
# The MC68040 does not implement all MC68881/MC68882 instructions, so use
# either the gcc floating-point software support (msoft-float libraries), or
# use the Motorola FPSP floating-point emulator in
# rtems/c/src/lib/libcpu/m68k/m68040/fpsp
# The default is to use the FPSP.
# To use the msoft-float libraries, uncomment the three lines below.
# You then should comment the M68KFPSPInstallExceptionHandlers() statement
# in rtems/c/src/lib/libbsp/m68k/mvme167/startup/bststart.c in bsp_start().
# Floating-point support will then be limited. See the mvme167 README file
# for more details.
define bsp-post-link
$(default-bsp-post-link)
$(OBJCOPY) -O binary -R .comment -S $(basename $@)$(EXEEXT) $(basename $@)$(DOWNEXT)
endef

572
bsps/m68k/mvme167/console/console-recording.h
View File

@@ -1,572 +0,0 @@
/*
* Copyright (c) 2000, National Research Council of Canada
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
/* CD2401 CONSOLE DRIVER DEBUG INFO RECORDING */
#ifdef CD2401_RECORD_DEBUG_INFO
/* Control individual recording here. That way, we don't clutter console.c */
#define CD2401_RECORD_WRITE
#define CD2401_RECORD_TX_ISR
#define CD2401_RECORD_RX_ISR
#define CD2401_RECORD_RE_ISR
#define CD2401_RECORD_MODEM_ISR
#define CD2401_RECORD_SET_ATTRIBUTE
#define CD2401_RECORD_FIRST_OPEN
#define CD2401_RECORD_LAST_CLOSE
#define CD2401_RECORD_START_REMOTE_TX
#define CD2401_RECORD_STOP_REMOTE_TX
#define CD2401_RECORD_DRAIN_OUTPUT
#define CD2401_RECORD_DELAY
/* Call the data recording functions */
#ifdef CD2401_RECORD_WRITE
#define CD2401_RECORD_WRITE_INFO( args ) cd2401_record_write_info args
#else
#define CD2401_RECORD_WRITE_INFO( args )
#endif
#ifdef CD2401_RECORD_TX_ISR
#define CD2401_RECORD_TX_ISR_INFO( args ) cd2401_record_tx_isr_info args
#define CD2401_RECORD_TX_ISR_SPURIOUS_INFO( args ) cd2401_record_tx_isr_spurious_info args
#define CD2401_RECORD_TX_ISR_BUSERR_INFO( args ) cd2401_record_tx_isr_buserr_info args
#else
#define CD2401_RECORD_TX_ISR_INFO( args )
#define CD2401_RECORD_TX_ISR_SPURIOUS_INFO( args )
#define CD2401_RECORD_TX_ISR_BUSERR_INFO( args )
#endif
#ifdef CD2401_RECORD_RX_ISR
#define CD2401_RECORD_RX_ISR_INFO( args ) cd2401_record_rx_isr_info args
#define CD2401_RECORD_RX_ISR_SPURIOUS_INFO( args ) cd2401_record_rx_isr_spurious_info args
#else
#define CD2401_RECORD_RX_ISR_INFO( args )
#define CD2401_RECORD_RX_ISR_SPURIOUS_INFO( args )
#endif
#ifdef CD2401_RECORD_RE_ISR
#define CD2401_RECORD_RE_ISR_SPURIOUS_INFO( args ) cd2401_record_re_isr_spurious_info args
#else
#define CD2401_RECORD_RE_ISR_SPURIOUS_INFO( args )
#endif
#ifdef CD2401_RECORD_MODEM_ISR
#define CD2401_RECORD_MODEM_ISR_SPURIOUS_INFO( args ) cd2401_record_modem_isr_spurious_info args
#else
#define CD2401_RECORD_MODEM_ISR_SPURIOUS_INFO( args )
#endif
#ifdef CD2401_RECORD_SET_ATTRIBUTES
#define CD2401_RECORD_SET_ATTRIBUTES_INFO( args ) cd2401_record_set_attributes_info args
#else
#define CD2401_RECORD_SET_ATTRIBUTES_INFO( args )
#endif
#ifdef CD2401_RECORD_FIRST_OPEN
#define CD2401_RECORD_FIRST_OPEN_INFO( args ) cd2401_record_first_open_info args
#else
#define CD2401_RECORD_FIRST_OPEN_INFO( args )
#endif
#ifdef CD2401_RECORD_LAST_CLOSE
#define CD2401_RECORD_LAST_CLOSE_INFO( args ) cd2401_record_last_close_info args
#else
#define CD2401_RECORD_LAST_CLOSE_INFO( args )
#endif
#ifdef CD2401_RECORD_START_REMOTE_TX
#define CD2401_RECORD_START_REMOTE_TX_INFO( args ) cd2401_record_start_remote_tx_info args
#else
#define CD2401_RECORD_START_REMOTE_TX_INFO( args )
#endif
#ifdef CD2401_RECORD_STOP_REMOTE_TX
#define CD2401_RECORD_STOP_REMOTE_TX_INFO( args ) cd2401_record_stop_remote_tx_info args
#else
#define CD2401_RECORD_STOP_REMOTE_TX_INFO( args )
#endif
#ifdef CD2401_RECORD_DRAIN_OUTPUT
#define CD2401_RECORD_DRAIN_OUTPUT_INFO( args ) cd2401_record_drain_output_info args
#else
#define CD2401_RECORD_DRAIN_OUTPUT_INFO( args )
#endif
#ifdef CD2401_RECORD_DELAY
#define CD2401_RECORD_DELAY_INFO( args ) cd2401_record_delay_info args
#else
#define CD2401_RECORD_DELAY_INFO( args )
#endif
/* Define the data and the recording functions */
#define CD2401_DEBUG_BUFFER_SIZE 256
#define CD2401_DEBUG_CHAR_BUFSIZE 64
#define CD2401_WRITE_INFO 1
#define CD2401_TX_ISR_INFO 2
#define CD2401_TX_ISR_SPURIOUS_INFO 3
#define CD2401_TX_ISR_BUSERR_INFO 4
#define CD2401_RX_ISR_INFO 5
#define CD2401_RX_ISR_SPURIOUS_INFO 6
#define CD2401_RE_ISR_SPURIOUS_INFO 7
#define CD2401_MODEM_ISR_SPURIOUS_INFO 8
#define CD2401_FIRST_OPEN_INFO 9
#define CD2401_LAST_CLOSE_INFO 10
#define CD2401_START_REMOTE_TX_INFO 11
#define CD2401_STOP_REMOTE_TX_INFO 12
#define CD2401_SET_ATTRIBUTE_INFO 13
#define CD2401_DRAIN_OUTPUT_INFO 14
#define CD2401_DELAY_INFO 15
struct cd2401_debug_info {
short discriminant;
short record_size;
union {
struct cd2401_write_info {
int length;
char buffer[CD2401_DEBUG_CHAR_BUFSIZE];
char dmabuf;
} write_info;
struct cd2401_tx_isr_info {
unsigned char channel;
unsigned char status;
unsigned char initial_ier;
unsigned char final_ier;
uint8_t txEmpty;
} tx_isr_info;
struct cd2401_tx_isr_spurious_info {
unsigned char channel;
unsigned char status;
unsigned char initial_ier;
unsigned char final_ier;
unsigned long spurdev;
unsigned long spurcount;
} tx_isr_spurious_info;
struct cd2401_tx_isr_buserr_info {
unsigned char channel;
unsigned char status;
unsigned char initial_ier;
unsigned char buserr;
unsigned long type;
unsigned long addr;
} tx_isr_buserr_info;
struct cd2401_rx_isr_info {
unsigned char channel;
int length;
char buffer[CD2401_DEBUG_CHAR_BUFSIZE];
} rx_isr_info;
struct cd2401_rx_isr_spurious_info {
unsigned char channel;
unsigned char status;
unsigned long spurdev;
unsigned long spurcount;
} rx_isr_spurious_info;
struct cd2401_re_isr_spurious_info {
unsigned char channel;
unsigned long spurdev;
unsigned long spurcount;
} re_isr_spurious_info;
struct cd2401_modem_isr_spurious_info {
unsigned char channel;
unsigned long spurdev;
unsigned long spurcount;
} modem_isr_spurious_info;
struct cd2401_first_open_info {
unsigned char channel;
uint8_t init_count;
} first_open_info;
struct cd2401_last_close_info {
unsigned char channel;
uint8_t init_count;
} last_close_info;
struct cd2401_start_remote_tx_info {
unsigned char channel;
} start_remote_tx_info;
struct cd2401_stop_remote_tx_info {
unsigned char channel;
} stop_remote_tx_info;
struct cd2401_set_attribute_info {
int minor;
uint8_t need_reinit;
uint8_t txEmpty;
uint8_t csize;
uint8_t cstopb;
uint8_t parodd;
uint8_t parenb;
uint8_t ignpar;
uint8_t inpck;
uint8_t hw_flow_ctl;
uint8_t sw_flow_ctl;
uint8_t extra_flow_ctl;
uint8_t icrnl;
uint8_t igncr;
uint8_t inlcr;
uint8_t brkint;
uint8_t ignbrk;
uint8_t parmrk;
uint8_t istrip;
uint16_t tx_period;
uint16_t rx_period;
uint32_t out_baud;
uint32_t in_baud;
} set_attribute_info;
struct cd2401_drain_output_info {
uint8_t txEmpty;
uint8_t own_buf_A;
uint8_t own_buf_B;
} drain_output_info;
struct cd2401_delay_info {
rtems_interval start;
rtems_interval end;
rtems_interval current;
unsigned long loop_count;
} delay_info;
} u;
};
struct cd2401_debug_info cd2401_debug_buffer[CD2401_DEBUG_BUFFER_SIZE];
int cd2401_debug_index = 0;
#include <string.h>
int cd2401_get_record_size(
int size
)
{
/* Not the best way to do this */
return size + 4;
}
void cd2401_record_write_info(
int len,
const char * buf,
char dmabuf
)
{
int max_length;
max_length = (len < CD2401_DEBUG_CHAR_BUFSIZE ) ? len : CD2401_DEBUG_CHAR_BUFSIZE;
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_WRITE_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_write_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.write_info.length = len;
memcpy ( &(cd2401_debug_buffer[cd2401_debug_index].u.write_info.buffer), buf, max_length );
cd2401_debug_buffer[cd2401_debug_index].u.write_info.dmabuf = dmabuf;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_tx_isr_info(
unsigned char ch,
unsigned char status,
unsigned char initial_ier,
unsigned char final_ier,
uint8_t txEmpty
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_TX_ISR_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_tx_isr_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_info.channel = ch;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_info.status = status;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_info.initial_ier = initial_ier;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_info.final_ier = final_ier;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_info.txEmpty = txEmpty;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_tx_isr_spurious_info(
unsigned char ch,
unsigned char status,
unsigned char initial_ier,
unsigned char final_ier,
unsigned char spur_dev,
unsigned char spur_cnt
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_TX_ISR_SPURIOUS_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_tx_isr_spurious_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_spurious_info.channel = ch;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_spurious_info.status = status;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_spurious_info.initial_ier = initial_ier;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_spurious_info.final_ier = final_ier;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_spurious_info.spurdev = spur_dev;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_spurious_info.spurcount = spur_cnt;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_tx_isr_buserr_info(
unsigned char ch,
unsigned char status,
unsigned char initial_ier,
unsigned char buserr,
unsigned long buserr_type,
unsigned long buserr_addr
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_TX_ISR_BUSERR_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_tx_isr_buserr_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_buserr_info.channel = ch;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_buserr_info.status = status;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_buserr_info.initial_ier = initial_ier;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_buserr_info.buserr = buserr;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_buserr_info.type = buserr_type;
cd2401_debug_buffer[cd2401_debug_index].u.tx_isr_buserr_info.addr = buserr_addr;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_rx_isr_info(
unsigned char ch,
unsigned char total,
char * buffer
)
{
int max_length;
max_length = (total < CD2401_DEBUG_CHAR_BUFSIZE ) ? total : CD2401_DEBUG_CHAR_BUFSIZE;
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_RX_ISR_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_rx_isr_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.rx_isr_info.length = max_length;
memcpy ( &(cd2401_debug_buffer[cd2401_debug_index].u.rx_isr_info.buffer), buffer, max_length );
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_rx_isr_spurious_info(
unsigned char ch,
unsigned char status,
uint32_t spur_dev,
uint32_t spur_cnt
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_RX_ISR_SPURIOUS_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_rx_isr_spurious_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.rx_isr_spurious_info.channel = ch;
cd2401_debug_buffer[cd2401_debug_index].u.rx_isr_spurious_info.status = status;
cd2401_debug_buffer[cd2401_debug_index].u.rx_isr_spurious_info.spurdev = spur_dev;
cd2401_debug_buffer[cd2401_debug_index].u.rx_isr_spurious_info.spurcount = spur_cnt;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_re_isr_spurious_info(
unsigned char ch,
uint32_t spur_dev,
uint32_t spur_cnt
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_RE_ISR_SPURIOUS_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_re_isr_spurious_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.re_isr_spurious_info.channel = ch;
cd2401_debug_buffer[cd2401_debug_index].u.re_isr_spurious_info.spurdev = spur_dev;
cd2401_debug_buffer[cd2401_debug_index].u.re_isr_spurious_info.spurcount = spur_cnt;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_modem_isr_spurious_info(
unsigned char ch,
uint32_t spur_dev,
uint32_t spur_cnt
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_MODEM_ISR_SPURIOUS_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_modem_isr_spurious_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.modem_isr_spurious_info.channel = ch;
cd2401_debug_buffer[cd2401_debug_index].u.modem_isr_spurious_info.spurdev = spur_dev;
cd2401_debug_buffer[cd2401_debug_index].u.modem_isr_spurious_info.spurcount = spur_cnt;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_first_open_info(
unsigned char ch,
uint8_t init_count
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_FIRST_OPEN_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_first_open_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.first_open_info.channel = ch;
cd2401_debug_buffer[cd2401_debug_index].u.first_open_info.init_count = init_count;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_last_close_info(
unsigned char ch,
uint8_t init_count
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_LAST_CLOSE_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_last_close_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.last_close_info.channel = ch;
cd2401_debug_buffer[cd2401_debug_index].u.last_close_info.init_count = init_count;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_start_remote_tx_info(
unsigned char ch
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_START_REMOTE_TX_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_start_remote_tx_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.start_remote_tx_info.channel = ch;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_stop_remote_tx_info(
unsigned char ch
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_STOP_REMOTE_TX_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_stop_remote_tx_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.stop_remote_tx_info.channel = ch;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_set_attributes_info(
int minor,
uint8_t need_reinit,
uint8_t csize,
uint8_t cstopb,
uint8_t parodd,
uint8_t parenb,
uint8_t ignpar,
uint8_t inpck,
uint8_t hw_flow_ctl,
uint8_t sw_flow_ctl,
uint8_t extra_flow_ctl,
uint8_t icrnl,
uint8_t igncr,
uint8_t inlcr,
uint8_t brkint,
uint8_t ignbrk,
uint8_t parmrk,
uint8_t istrip,
uint16_t tx_period,
uint16_t rx_period,
uint32_t out_baud,
uint32_t in_baud
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_SET_ATTRIBUTE_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_set_attribute_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.minor = minor;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.need_reinit = need_reinit;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.txEmpty = CD2401_Channel_Info[minor].txEmpty;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.csize = csize;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.cstopb = cstopb;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.parodd = parodd;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.parenb = parenb;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.ignpar = ignpar;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.inpck = inpck;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.hw_flow_ctl = hw_flow_ctl;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.sw_flow_ctl = sw_flow_ctl;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.extra_flow_ctl = extra_flow_ctl;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.icrnl = icrnl;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.igncr = igncr;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.inlcr = inlcr;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.brkint = brkint;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.ignbrk = ignbrk;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.parmrk = parmrk;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.istrip = istrip;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.tx_period = tx_period;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.rx_period = rx_period;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.out_baud = out_baud;
cd2401_debug_buffer[cd2401_debug_index].u.set_attribute_info.in_baud = in_baud;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_drain_output_info(
uint8_t txEmpty,
uint8_t own_buf_A,
uint8_t own_buf_B
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_DRAIN_OUTPUT_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_drain_output_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.drain_output_info.txEmpty = txEmpty;
cd2401_debug_buffer[cd2401_debug_index].u.drain_output_info.own_buf_A = own_buf_A;
cd2401_debug_buffer[cd2401_debug_index].u.drain_output_info.own_buf_B = own_buf_B;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
void cd2401_record_delay_info(
rtems_interval start,
rtems_interval end,
rtems_interval current,
unsigned long loop_count
)
{
memset( &(cd2401_debug_buffer[cd2401_debug_index]), '\0', sizeof( struct cd2401_debug_info ) );
cd2401_debug_buffer[cd2401_debug_index].discriminant = CD2401_DELAY_INFO;
cd2401_debug_buffer[cd2401_debug_index].record_size =
cd2401_get_record_size( sizeof( struct cd2401_delay_info ) );
cd2401_debug_buffer[cd2401_debug_index].u.delay_info.start = start;
cd2401_debug_buffer[cd2401_debug_index].u.delay_info.end = end;
cd2401_debug_buffer[cd2401_debug_index].u.delay_info.current = current;
cd2401_debug_buffer[cd2401_debug_index].u.delay_info.loop_count = loop_count;
cd2401_debug_index = (cd2401_debug_index + 1 ) % CD2401_DEBUG_BUFFER_SIZE;
}
#else
/* Do not call the data recording functions */
#define CD2401_RECORD_WRITE_INFO( args )
#define CD2401_RECORD_TX_ISR_INFO( args )
#define CD2401_RECORD_TX_ISR_SPURIOUS_INFO( args )
#define CD2401_RECORD_TX_ISR_BUSERR_INFO( args )
#define CD2401_RECORD_RX_ISR_INFO( args )
#define CD2401_RECORD_RX_ISR_SPURIOUS_INFO( args )
#define CD2401_RECORD_RE_ISR_SPURIOUS_INFO( args )
#define CD2401_RECORD_MODEM_ISR_SPURIOUS_INFO( args )
#define CD2401_RECORD_FIRST_OPEN_INFO( args )
#define CD2401_RECORD_LAST_CLOSE_INFO( args )
#define CD2401_RECORD_START_REMOTE_TX_INFO( args )
#define CD2401_RECORD_STOP_REMOTE_TX_INFO( args )
#define CD2401_RECORD_SET_ATTRIBUTES_INFO( args )
#define CD2401_RECORD_DRAIN_OUTPUT_INFO( args )
#define CD2401_RECORD_DELAY_INFO( args )
#endif

1676
bsps/m68k/mvme167/console/console.c
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File diff suppressed because it is too large Load Diff

329
bsps/m68k/mvme167/include/bsp.h
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@@ -1,329 +0,0 @@
/**
* @file
*
* @ingroup RTEMSBSPsM68kMVME167
*
* @brief Global BSP definitions.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modifications of respective RTEMS file:
* Copyright (c) 1998, National Research Council of Canada
*/
#ifndef LIBBSP_M68K_MVME167_BSP_H
#define LIBBSP_M68K_MVME167_BSP_H
/**
* @defgroup RTEMSBSPsM68kMVME162 MVME167
*
* @ingroup RTEMSBSPsM68k
*
* @brief MVME167 Board Support Package.
*
* @{
*/
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#include <rtems.h>
#include <rtems/bspIo.h>
#include <mvme16x_hw.h>
#ifdef __cplusplus
extern "C" {
#endif
/* GCSR is in mvme16x_hw.h */
/* LCSR is in mvme16x_hw.h */
/* i82596 is in mvme16x_hw.h */
/* NVRAM is in mvme16x_hw.h */
#if 0
/*
* Representation of the PCCchip2
*/
typedef volatile struct pccchip2_regs_ {
unsigned char chip_id; /* 0xFFF42000 */
unsigned char chip_revision; /* 0xFFF42001 */
unsigned char gen_control; /* 0xFFF42002 */
unsigned char vector_base; /* 0xFFF42003 */
unsigned long timer_cmp_1; /* 0xFFF42004 */
unsigned long timer_cnt_1; /* 0xFFF42008 */
unsigned long timer_cmp_2; /* 0xFFF4200C */
unsigned long timer_cnt_2; /* 0xFFF42010 */
unsigned char LSB_prescaler_count;/* 0xFFF42014 */
unsigned char prescaler_clock_adjust; /* 0xFFF42015 */
unsigned char timer_ctl_2; /* 0xFFF42016 */
unsigned char timer_ctl_1; /* 0xFFF42017 */
unsigned char gpi_int_ctl; /* 0xFFF42018 */
unsigned char gpio_ctl; /* 0xFFF42019 */
unsigned char timer_int_ctl_2; /* 0xFFF4201A */
unsigned char timer_int_ctl_1; /* 0xFFF4201B */
unsigned char SCC_error; /* 0xFFF4201C */
unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */
unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */
unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */
unsigned char reserved1[3];
unsigned char modem_piack; /* 0xFFF42023 */
unsigned char reserved2;
unsigned char tx_piack; /* 0xFFF42025 */
unsigned char reserved3;
unsigned char rx_piack; /* 0xFFF42027 */
unsigned char LANC_error; /* 0xFFF42028 */
unsigned char reserved4;
unsigned char LANC_int_ctl; /* 0xFFF4202A */
unsigned char LANC_berr_ctl; /* 0xFFF4202B */
unsigned char SCSI_error; /* 0xFFF4202C */
unsigned char reserved5[2];
unsigned char SCSI_int_ctl; /* 0xFFF4202F */
unsigned char print_ack_int_ctl; /* 0xFFF42030 */
unsigned char print_fault_int_ctl;/* 0xFFF42031 */
unsigned char print_sel_int_ctl; /* 0xFFF42032 */
unsigned char print_pe_int_ctl; /* 0xFFF42033 */
unsigned char print_busy_int_ctl; /* 0xFFF42034 */
unsigned char reserved6;
unsigned char print_input_status; /* 0xFFF42036 */
unsigned char print_ctl; /* 0xFFF42037 */
unsigned char chip_speed; /* 0xFFF42038 */
unsigned char reserved7;
unsigned char print_data; /* 0xFFF4203A */
unsigned char reserved8[3];
unsigned char int_level; /* 0xFFF4203E */
unsigned char int_mask; /* 0xFFF4203F */
} pccchip2_regs;
/*
* Base address of the PCCchip2.
* This is not configurable in the MVME167.
*/
#define pccchip2 ((pccchip2_regs * const) 0xFFF42000)
#endif
/*
* The MVME167 is equiped with one or two MEMC040 memory controllers at
* 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
* were initialized by 167Bug.
*/
typedef volatile struct memc040_regs_ {
unsigned char chip_id; /* 0xFFF43000/0xFFF43100 */
unsigned char reserved1[3];
unsigned char chip_revision; /* 0xFFF43004/0xFFF43104 */
unsigned char reserved2[3];
unsigned char mem_config; /* 0xFFF43008/0xFFF43108 */
unsigned char reserved3[3];
unsigned char alt_status; /* 0xFFF4300C/0xFFF4310C */
unsigned char reserved4[3];
unsigned char alt_ctl; /* 0xFFF43010/0xFFF43110 */
unsigned char reserved5[3];
unsigned char base_addr; /* 0xFFF43014/0xFFF43114 */
unsigned char reserved6[3];
unsigned char ram_ctl; /* 0xFFF43018/0xFFF43118 */
unsigned char reserved7[3];
unsigned char bus_clk; /* 0xFFF4301C/0xFFF4311C */
} memc040_regs;
/*
* Base address of the MEMC040s.
* This is not configurable in the MVME167.
*/
#define memc040_1 ((memc040_regs * const) 0xFFF43000)
#define memc040_2 ((memc040_regs * const) 0xFFF43100)
/*
* The MVME167 may be equiped with error-correcting RAM cards. In this case,
* each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
* assumes that these controllers, if present, are initialized by 167Bug.
* They do not appear to hold information of interest at this time, so they
* are not described. However, each MCECC pair lives at the same address as
* the MEMC040 is replaces. The first eight registers of the MCECC are
* nearly identical to the ones of the MEMC040, and the memc040_X structures
* can be used to read those first eight registers.
*/
/*
* Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
*/
typedef volatile struct cd2401_regs_ {
unsigned char reserved1[7];
unsigned char cor7; /* 0xFFF45007 - Channel Option 7 */
unsigned char reserved2;
unsigned char livr; /* 0xFFF45009 - Local Interrupt Vector */
unsigned char reserved3[6];
unsigned char cor1; /* 0xFFF45010 - Channel Option 1 */
unsigned char ier; /* 0xFFF45011 - Interrupt Enable */
unsigned char stcr; /* 0xFFF45012 - Special Transmit Command */
unsigned char ccr; /* 0xFFF45013 - Channel Command */
unsigned char cor5; /* 0xFFF45014 - Channel Option 5 */
unsigned char cor4; /* 0xFFF45015 - Channel Option 4 */
unsigned char cor3; /* 0xFFF45016 - Channel Option 3 */
unsigned char cor2; /* 0xFFF45017 - Channel Option 2 */
unsigned char cor6; /* 0xFFF45018 - Channel Option 6 */
unsigned char dmabsts; /* 0xFFF45019 - DMA Buffer Status */
unsigned char csr; /* 0xFFF4501A - Channel Status */
unsigned char cmr; /* 0xFFF4501B - Channel Mode */
union {
struct {
unsigned char schr4; /* 0xFFF4501C - Special Character 4 */
unsigned char schr3; /* 0xFFF4501D - Special Character 3 */
unsigned char schr2; /* 0xFFF4501E - Special Character 2 */
unsigned char schr1; /* 0xFFF4501F - Special Character 1 */
} async;
struct {
unsigned char rfar4; /* 0xFFF4501C - Receive Frame Address 4 */
unsigned char rfar3; /* 0xFFF4501D - Receive Frame Address 3 */
unsigned char rfar2; /* 0xFFF4501E - Receive Frame Address 2 */
unsigned char rfar1; /* 0xFFF4501F - Receive Frame Address 1 */
} sync;
} u1;
unsigned char reserved4[2];
unsigned char scrh; /* 0xFFF45022 - Special Character Range High */
unsigned char scrl; /* 0xFFF45023 - Special Character Range Low */
union {
struct {
unsigned short rtpr; /* 0xFFF45024 - Receive Timeout Period */
} w;
struct {
unsigned char rtprh; /* 0xFFF45024 - Receive Timeout Period High */
unsigned char rtprl; /* 0xFFF45025 - Receive Timeout Period Low */
} b;
} u2;
unsigned char licr; /* 0xFFF45026 - Local Interrupt Channel */
unsigned char reserved5[2];
union {
struct {
unsigned char ttr; /* 0xFFF45029 - Transmit Timer */
} async;
struct {
unsigned char gt2; /* 0xFFF45029 - General Timer 2 */
} sync;
} u3;
union {
struct {
unsigned short gt1; /* 0xFFF4502A - General Timer 1 */
} w;
struct {
unsigned char gt1h; /* 0xFFF4502A - General Timer 2 High */
unsigned char gt1l; /* 0xFFF4502B - General Timer 1 Low */
} b;
} u4;
unsigned char reserved6[2];
unsigned char lnxt; /* 0xFF4502E - LNext Character */
unsigned char reserved7;
unsigned char rfoc; /* 0xFFF45030 - Receive FIFO Output Count */
unsigned char reserved8[7];
unsigned short tcbadru; /* 0xFF45038 - Transmit Current Buffer Address Upper */
unsigned short tcbadrl; /* 0xFF4503A - Transmit Current Buffer Address Lower */
unsigned short rcbadru; /* 0xFF4503C - Receive Current Buffer Address Upper */
unsigned short rcbadrl; /* 0xFF4503E - Receive Current Buffer Address Lower */
unsigned short arbadru; /* 0xFF45040 - A Receive Buffer Address Upper */
unsigned short arbardl; /* 0xFF45042 - A Receive Buffer Address Lower */
unsigned short brbadru; /* 0xFF45044 - B Receive Buffer Address Upper */
unsigned short brbadrl; /* 0xFF45046 - B Receive Buffer Address Lower */
unsigned short brbcnt; /* 0xFF45048 - B Receive Buffer Byte Count */
unsigned short arbcnt; /* 0xFF4504A - A Receive Buffer Byte Count */
unsigned short reserved9;
unsigned char brbsts; /* 0xFF4504E - B Receive Buffer Status */
unsigned char arbsts; /* 0xFF4504F - A Receive Buffer Status */
unsigned short atbadru; /* 0xFF45050 - A Transmit Buffer Address Upper */
unsigned short atbadrl; /* 0xFF45052 - A Transmit Buffer Address Lower */
unsigned short btbadru; /* 0xFF45054 - B Transmit Buffer Address Upper */
unsigned short btbadrl; /* 0xFF45056 - B Transmit Buffer Address Lower */
unsigned short btbcnt; /* 0xFF45058 - B Transmit Buffer Byte Count */
unsigned short atbcnt; /* 0xFF4505A - A Transmit Buffer Byte Count */
unsigned short reserved10;
unsigned char btbsts; /* 0xFF4505E - B Transmit Buffer Status */
unsigned char atbsts; /* 0xFF4505F - A Transmit Buffer Status */
unsigned char reserved11[32];
unsigned char tftc; /* 0xFFF45080 - Transmit FIFO Transfer Count */
unsigned char gfrcr; /* 0xFFF45081 - Global Firmware Revision Code */
unsigned char reserved12[2];
unsigned char reoir; /* 0xFFF45084 - Receive End Of Interrupt */
unsigned char teoir; /* 0xFFF45085 - Transmit End Of Interrupt */
unsigned char meoir; /* 0xFFF45086 - Modem End Of Interrupt */
union {
struct {
unsigned short risr; /* 0xFFF45088 - Receive Interrupt Status */
} w;
struct {
unsigned char risrh; /* 0xFFF45088 - Receive Interrupt Status High */
unsigned char risrl; /* 0xFFF45089 - Receive Interrupt Status Low */
} b;
} u5;
unsigned char tisr; /* 0xFFF4508A - Transmit Interrupt Status */
unsigned char misr; /* 0xFFF4508B - Modem/Timer Interrupt Status */
unsigned char reserved13[2];
unsigned char bercnt; /* 0xFFF4508E - Bus Error Retry Count */
unsigned char reserved14[49];
unsigned char tcor; /* 0xFFF450C0 - Transmit Clock Option */
unsigned char reserved15[2];
unsigned char tbpr; /* 0xFFF450C3 - Transmit Baud Rate Period */
unsigned char reserved16[4];
unsigned char rcor; /* 0xFFF450C8 - Receive Clock Option */
unsigned char reserved17[2];
unsigned char rbpr; /* 0xFFF450CB - Receive Baud Rate Period */
unsigned char reserved18[10];
unsigned char cpsr; /* 0xFFF450D6 - CRC Polynomial Select */
unsigned char reserved19[3];
unsigned char tpr; /* 0xFFF450DA - Timer Period */
unsigned char reserved20[3];
unsigned char msvr_rts; /* 0xFFF450DE - Modem Signal Value - RTS */
unsigned char msvr_dtr; /* 0xFFF450DF - Modem Signal Value - DTR */
unsigned char tpilr; /* 0xFFF450E0 - Transmit Priority Interrupt Level */
unsigned char rpilr; /* 0xFFF450E1 - Receive Priority Interrupt Level */
unsigned char stk; /* 0xFFF450E2 - Stack */
unsigned char mpilr; /* 0xFFF450E3 - Modem Priority Interrupt Level */
unsigned char reserved21[8];
unsigned char tir; /* 0xFFF450EC - Transmit Interrupt */
unsigned char rir; /* 0xFFF450ED - Receive Interrupt */
unsigned char car; /* 0xFFF450EE - Channel Access */
unsigned char mir; /* 0xFFF450EF - Model Interrupt */
unsigned char reserved22[6];
unsigned char dmr; /* 0xFFF450F6 - DMA Mode */
unsigned char reserved23;
unsigned char dr; /* 0xFFF450F8 - Receive/Transmit Data */
} cd2401_regs;
/*
* Base address of the CD2401.
* This is not configurable in the MVME167.
*/
#define cd2401 ((cd2401_regs * const) 0xFFF45000)
/* CD2401 is clocked at 20 MHz */
#define CD2401_CLK_RATE 20000000
/* BSP-wide functions */
rtems_isr_entry set_vector(
rtems_isr_entry handler,
rtems_vector_number vector,
int type
);
#ifdef M167_INIT
#undef EXTERN
#define EXTERN
#else
#undef EXTERN
#define EXTERN extern
#endif
extern void *M68Kvec[]; /* vector table address */
#ifdef __cplusplus
}
#endif
/** @} */
#endif

1
bsps/m68k/mvme167/include/bsp/irq.h
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@@ -1 +0,0 @@
#include <bsp/irq-default.h>

43
bsps/m68k/mvme167/include/page_table.h
View File

@@ -1,43 +0,0 @@
/* page_table.h
*
* This file was submitted by Eric Vaitl <vaitl@viasat.com> and
* supports page table initialization.
*
* For now, we only use the transparent translation registers. Page tables
* may be set up in the future.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modifications of respective RTEMS files:
* Copyright (c) 1998, National Research Council of Canada
*/
#ifndef __PAGE_TABLE_H
#define __PAGE_TABLE_H
#include <rtems.h>
void page_table_teardown( void );
void page_table_init( void );
enum {
CACHE_WRITE_THROUGH,
CACHE_COPYBACK,
CACHE_NONE_SERIALIZED,
CACHE_NONE
};
enum {
PTM_SUCCESS,
PTM_BAD_ADDR,
PTM_BAD_SIZE,
PTM_BAD_CACHE,
PTM_NO_TABLE_SPACE
};
#endif

40
bsps/m68k/mvme167/include/tm27.h
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@@ -1,40 +0,0 @@
/*
* @file
* @ingroup m68k_mvme167
* @brief Implementations for interrupt mechanisms for Time Test 27
*/
/*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Define the interrupt mechanism for Time Test 27
*
* NOTE: We use software interrupt 0
*/
#define MUST_WAIT_FOR_INTERRUPT 0
#define TM27_USE_VECTOR_HANDLER
#define Install_tm27_vector( handler ) \
set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \
lcsr->intr_level[2] |= 3; \
lcsr->intr_ena |= 0x100
#define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100
#define Clear_tm27_intr() lcsr->intr_clear |= 0x100
#define Lower_tm27_intr() /* empty */
#endif

70
bsps/m68k/mvme167/start/bspclean.c
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@@ -1,70 +0,0 @@
/**
* @file
*
* These routines return control to 167Bug after a normal exit from the
* application.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modifications of respective RTEMS files:
* Copyright (c) 1998, National Research Council of Canada
*/
#include <bsp.h>
#include <bsp/bootcard.h>
#include <page_table.h>
extern void start( void );
extern void page_table_teardown( void );
/**
* @brief bsp_return_to_monitor_trap
*
* Switch the VBR back to ROM and make a .RETURN syscall to return control to
* 167 Bug. If 167Bug ever returns, restart the application.
*/
static void bsp_return_to_monitor_trap( void )
{
register volatile void *start_addr;
page_table_teardown();
lcsr->intr_ena = 0; /* disable interrupts */
m68k_set_vbr(0xFFE00000); /* restore 167Bug vectors */
__asm__ volatile( "trap #15\n\t" /* trap to 167Bug */
".short 0x63" ); /* return to 167Bug (.RETURN) */
/* restart program */
start_addr = start;
__asm__ volatile( "jmp %0@" : "=a" (start_addr) : "0" (start_addr) );
}
/*
* This code was copied from other MC680x0 MVME BSPs.
* Our guess is that someone was concerned about the CPU no longer being in
* supervisor mode when they got here. This function forces the CPU back to
* supervisor mode so the VBR may be changed. It places the address of the
* function that makes a 167Bug .RETURN syscall in the trap 13 entry in the
* exception vector, and then issues a trap 13 call. It is also possible that
* the code was copied from some other OS that does run tasks in user mode.
* In any case, it appears to be a bit of paranoia, and could lead to
* problems if 167Bug is invoked before we get to switch the VBR back to
* 167Bug because trap 13 is documented as being reserved for the internal
* use of the debugger.
*/
void bsp_reset( rtems_fatal_source source, rtems_fatal_code code )
{
(void) source;
(void) code;
M68Kvec[ 45 ] = bsp_return_to_monitor_trap;
__asm__ volatile( "trap #13" );
RTEMS_UNREACHABLE();
}

80
bsps/m68k/mvme167/start/bspstart.c
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@@ -1,80 +0,0 @@
/**
* @file
*
* Board-specific initialization code. Called from the generic boot_card()
* function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
* does some of the board independent initialization. It is called from the
* generic MC680x0 entry point _start() defined in
* rtems/c/src/lib/start/m68k/start.s
*
* _start() has set up a stack, has zeroed the .bss section, has turned off
* interrupts, and placed the processor in the supervisor mode. boot_card()
* has left the processor in that state when bsp_start() was called.
*
* RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF!
* ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL
* ADDRESSES. Software-controlled address translation would be required
* otherwise.
*
* ASSUMES THAT 167BUG IS PRESENT TO CATCH ANY EXCEPTIONS DURING
* INITIALIZATION.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modifications of respective RTEMS files:
* Copyright (c) 1998, National Research Council of Canada
*/
#include <bsp.h>
#include <bsp/bootcard.h>
#include <page_table.h>
void M68KFPSPInstallExceptionHandlers (void);
void bsp_start( void )
{
void **rom_monitor_vector_table;
int index;
/*
* 167Bug Vectors are at 0xFFE00000
*/
rom_monitor_vector_table = (void **)0xFFE00000;
m68k_set_vbr( rom_monitor_vector_table );
/*
* Copy 167Bug Bus Error handler into our exception vector. All 167Bug
* exception vectors are the same and point to the generalized exception
* handler. The bus error handler is the one that Motorola says to copy
* (p. 2-13, Debugging Package for Motorola 68K CISC CPUs User's Manual
* 68KBUG/D1A3, October 1993).
*/
for ( index=2 ; index<=255 ; index++ )
M68Kvec[ index ] = rom_monitor_vector_table[ 2 ];
/* Any exceptions during initialization should be trapped by 167Bug */
m68k_set_vbr( &M68Kvec );
/* Install the 68040 FPSP here */
M68KFPSPInstallExceptionHandlers();
/*
* You may wish to make the VME arbitration round-robin here, currently
* we leave it as it is.
*/
/* Set the Interrupt Base Vectors */
lcsr->vector_base = (VBR0 << 28) | (VBR1 << 24);
/*
* Initialize address translation
*/
page_table_init();
}

36
bsps/m68k/mvme167/start/linkcmds
View File

@@ -1,36 +0,0 @@
/*
* This file contains directives for the GNU linker which are specific
* to the Motorola MVME167 board.
*
* Copyright (c) 1999, National Research Council of Canada.
* Some of this material was copied from binutils-2.9.4 linker scripts,
* and is therefore likely to be copyrighted by the Free Software
* Foundation, even though explicit copyright notices did not appear in
* those files.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
RamBase = DEFINED(RamBase) ? RamBase : 0x00800000;
RamSize = DEFINED(RamSize) ? RamSize : 4M;
RamEnd = RamBase + RamSize;
MEMORY
{
/* The location of RAM is the address space is configurable.
This is where we put one board. The base address should be
passed as a parameter when building multiprocessor images
where each board resides at a different address. */
ram : org = RamBase, l = RamSize
rom : org = 0xFF800000, l = 4M
sram : org = 0xFFE00000, l = 128K
}
REGION_ALIAS ("REGION_TEXT", ram);
REGION_ALIAS ("REGION_TEXT_LOAD", ram);
REGION_ALIAS ("REGION_DATA", ram);
REGION_ALIAS ("REGION_DATA_LOAD", ram);
INCLUDE linkcmds.base

149
bsps/m68k/mvme167/start/page_table.c
View File

@@ -1,149 +0,0 @@
/* page_table.c
*
* The code submitted by Eric Vaitl <vaitl@viasat.com> for the MVME162 appears
* to be for a uniprocessor implementation. The function that sets up the
* page tables, page_table_init(), is not data driven. For all processors, it
* sets up page tables to map virtual addresses from 0x20000 to 0x3FFFFF to
* physical addresses 0x20000 to 0x3FFFFF. This presumably maps a subset of
* a local 4 MB space, which is probably the amount of RAM on Eric Vailt's
* MVME162.
*
* It is possible to set up the various bus bridges in the MVME167s to create
* a flat physical address space across multiple boards, i.e., it is possible
* for each MVME167 in a multiprocessor system to access a given memory
* location using the same physical address, whether that location is in local
* or VME space. Addres translation can be set up so that each virtual address
* maps to its corresponding physical address, e.g. virtual address 0x12345678
* is mapped to physical address 0x12345678. With this mapping, the MMU is
* only used to control the caching modes for the various regions of memory.
* Mapping the virtual addresses to their corresponding physical address makes
* it unnecessary to map addresses under software control during the
* initialization of RTEMS, before address translation is turned on.
*
* With the above approach, address translation may be set up either with the
* transparent address translation registers, or with page tables. If page
* tables are used, a more efficient use of page table space can be achieved
* by sharing the page tables between processors. The entire page table tree
* can be shared, or each processor can hold a private copy of the top nodes
* which point to leaf nodes stored on individual processors.
*
* In this port, only the transparent address translation registers are used.
* We map the entire virtual range from 0x0 to 0x7FFFFFFF to the identical
* physical range 0x0 to 0x7FFFFFFF. We rely on the hardware to signal bus
* errors if we address non-existent memory within this range. Our two
* MVME167s are configured to exist at physical addresses 0x00800000 to
* 0x00BFFFFF and 0x00C00000 to 0x00FFFFFF respectively. If jumper J1-4 is
* installed, memory and cache control can be done by providing parameters
* in NVRAM and jumpers J1-[5-7] are ignored. See the README for details.
* If J1-4 is removed, behaviour defaults to the following. We map the space
* from 0x0 to 0x7FFFFFFF as copyback, unless jumper J1-5 is removed, in which
* case we map as writethrough. If jumper J1-7 is removed, the data cache is
* NOT enabled. If jumper J1-6 is removed, the instruction cache is not enabled.
*
* Copyright (c) 1998, National Research Council of Canada
*/
#include <bsp.h>
#include <page_table.h> /* Nothing in here for us */
/*
* page_table_init
*
* Map the virtual range 0x00000000--0x7FFFFFFF to the physical range
* 0x00000000--0x7FFFFFFF. Rely on the hardware to raise exceptions when
* addressing non-existent memory. Use only the transparent translation
* registers (for now).
*
* On all processors, the local virtual address range 0xFF000000--0xFFFFFFFF
* is mapped to the physical address range 0xFF000000--0xFFFFFFFF as
* caching disabled, serialized access.
*
* Output parameters: NONE
*
* Return values: NONE
*/
void page_table_init( void )
{
unsigned char j1; /* State of J1 jumpers */
register unsigned long dtt0; /* Content of dtt0 */
register unsigned long cacr; /* Content of cacr */
/*
* Logical base addr = 0x00 map starting at 0x00000000
* Logical address mask = 0x7F map up to 0x7FFFFFFF
* E = 0b1 enable address translation
* S-Field = 0b1X ignore FC2 when matching
* U1, U0 = 0b00 user page attributes not used
* CM = 0b01 cachable, copyback
* W = 0b0 read/write access allowed
*/
dtt0 = 0x007FC020;
cacr = 0x00000000; /* Data and instruction cache off */
/* Read the J1 header */
j1 = (unsigned char)(lcsr->vector_base & 0xFF);
if ( !(j1 & 0x10) ) {
/* Jumper J1-4 is on, configure from NVRAM */
if ( nvram->cache_mode & 0x01 )
cacr |= 0x80000000;
if ( nvram->cache_mode & 0x02 )
cacr |= 0x00008000;
if ( nvram->cache_mode )
dtt0 = ((nvram->cache_mode & 0x0C) << 3) | (dtt0 & 0xFFFFFF9F);
}
else {
/* Configure according to other jumper settings */
if ( !(j1 & 0x80) )
/* Jumper J1-7 if on, enable data caching */
cacr |= 0x80000000;
if ( !(j1 & 0x40) )
/* Jumper J1-6 if on, enable instruction caching */
cacr |= 0x00008000;
if ( j1 & 0x20 )
/* Jumper J1-5 is off, enable writethrough caching */
dtt0 &= 0xFFFFFF9F;
}
/* do it ! */
__asm__ volatile("movec %0, %%tc\n\t" /* turn off paged address translation */
"movec %0, %%cacr\n\t" /* disable both caches */
"cinva %%bc\n\t" /* clear both caches */
"movec %1,%%dtt0\n\t" /* block address translation on */
"movec %1,%%itt0\n\t"
"movec %2,%%dtt1\n\t"
"movec %2,%%itt1\n\t"
"movec %3,%%cacr" /* data cache on */
:: "d" (0), "d" (dtt0), "d" (0xFF00C040), "d" (cacr));
}
/*
* page_table_teardown
*
* Turn off paging. Turn off the cache. Flush the cache. Tear down
* the transparent translations.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
void page_table_teardown( void )
{
__asm__ volatile ("movec %0,%%tc\n\t"
"movec %0,%%cacr\n\t"
"cpusha %%bc\n\t"
"movec %0,%%dtt0\n\t"
"movec %0,%%itt0\n\t"
"movec %0,%%dtt1\n\t"
"movec %0,%%itt1"
:: "d" (0) );
}

18
spec/build/bsps/m68k/mvme167/abi.yml
View File

@@ -1,18 +0,0 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-string: null
- split: null
- env-append: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: true
value:
- -mcpu=68040
description: |
ABI flags
enabled-by: true
links: []
name: ABI_FLAGS
type: build

70
spec/build/bsps/m68k/mvme167/bspmvme167.yml
View File

@@ -1,70 +0,0 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
arch: m68k
bsp: mvme167
build-type: bsp
cflags: []
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
cppflags: []
enabled-by: true
family: mvme167
includes: []
install:
- destination: ${BSP_INCLUDEDIR}
source:
- bsps/m68k/mvme167/include/bsp.h
- bsps/m68k/mvme167/include/page_table.h
- destination: ${BSP_INCLUDEDIR}/bsp
source:
- bsps/m68k/mvme167/include/bsp/irq.h
- destination: ${BSP_LIBDIR}
source:
- bsps/m68k/mvme167/start/linkcmds
- bsps/m68k/shared/start/linkcmds.base
links:
- role: build-dependency
uid: ../grp
- role: build-dependency
uid: abi
- role: build-dependency
uid: optconminor
- role: build-dependency
uid: optintlvl
- role: build-dependency
uid: optiomode
- role: build-dependency
uid: optmvme167
- role: build-dependency
uid: optprintkminor
- role: build-dependency
uid: optuseterm
- role: build-dependency
uid: ../objfpsp
- role: build-dependency
uid: ../start
- role: build-dependency
uid: ../../obj
- role: build-dependency
uid: ../../objirqdflt
- role: build-dependency
uid: ../../objmem
- role: build-dependency
uid: ../../opto2
- role: build-dependency
uid: ../../bspopts
source:
- bsps/m68k/mvme167/btimer/btimer.c
- bsps/m68k/mvme167/btimer/timerisr.S
- bsps/m68k/mvme167/clock/ckinit.c
- bsps/m68k/mvme167/console/console.c
- bsps/m68k/mvme167/start/bspclean.c
- bsps/m68k/mvme167/start/bspstart.c
- bsps/m68k/mvme167/start/page_table.c
- bsps/m68k/shared/cache/cache.c
- bsps/m68k/shared/m68kidle.c
- bsps/m68k/shared/memProbe.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/start/gettargethash-default.c
- bsps/shared/start/sbrk.c
- bsps/shared/start/setvec.c
type: build

16
spec/build/bsps/m68k/mvme167/optconminor.yml
View File

@@ -1,16 +0,0 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-boolean: null
- define-condition: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: true
value: true
description: |
Port to use for the RTEMS console. 0 - /dev/tty0, Serial Port 1/Console on the MVME712M. 1 - /dev/tty1, Serial Port 2/TTY01 on the MVME712M. 2 - /dev/tty2, Serial Port 3 on the MVME712M. 3 - /dev/tty3, Serial Port 4 on the MVME712M.
enabled-by: true
links: []
name: CONSOLE_MINOR
type: build

16
spec/build/bsps/m68k/mvme167/optintlvl.yml
View File

@@ -1,16 +0,0 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-boolean: null
- define-condition: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: true
value: true
description: |
Interrupt level for the CD2401(when CD2401_IO_MODE == 1).
enabled-by: true
links: []
name: CD2401_INT_LEVEL
type: build

16
spec/build/bsps/m68k/mvme167/optiomode.yml
View File

@@ -1,16 +0,0 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-boolean: null
- define-condition: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: true
value: false
description: |
0 for polled I/O, 1 for interrupt-driven.
enabled-by: true
links: []
name: CD2401_IO_MODE
type: build

13
spec/build/bsps/m68k/mvme167/optmvme167.yml
View File

@@ -1,13 +0,0 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- set-value: true
- define-condition: mvme167
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default: []
description: |
Defines mvme167 in <bspopts.h>.
enabled-by: true
links: []
type: build

17
spec/build/bsps/m68k/mvme167/optprintkminor.yml
View File

@@ -1,17 +0,0 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-integer: null
- define: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: true
value: 1
description: |
Port to use for printk debugging output. 0 - /dev/tty0, Serial Port 1/Console on the MVME712M. 1 - /dev/tty1, Serial Port 2/TTY01 on the MVME712M. 2 - /dev/tty2, Serial Port 3 on the MVME712M. 3 - /dev/tty3, Serial Port 4 on the MVME712M.
enabled-by: true
format: '{}'
links: []
name: PRINTK_MINOR
type: build

16
spec/build/bsps/m68k/mvme167/optuseterm.yml
View File

@@ -1,16 +0,0 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-boolean: null
- define-condition: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: true
value: false
description: |
1 for using termios based console.
enabled-by: true
links: []
name: CD2401_USE_TERMIOS
type: build