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2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org>

Browse Source 
* clock/ckinit.c, console/console.c, console/debugputs.c,
	erc32sonic/erc32sonic.c, include/bsp.h, include/erc32.h,
	startup/setvec.c, startup/spurious.c, timer/timer.c: Convert to
	using c99 fixed size types.
This commit is contained in:
Ralf Corsepius
2004-03-31 05:17:45 +00:00
parent cdf41b07a5
commit 1be1e91356
10 changed files with 90 additions and 83 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
c/src/lib/libbsp/sparc/erc32/ChangeLog
View File

@@ -1,3 +1,10 @@
2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org>
* clock/ckinit.c, console/console.c, console/debugputs.c,
erc32sonic/erc32sonic.c, include/bsp.h, include/erc32.h,
startup/setvec.c, startup/spurious.c, timer/timer.c: Convert to
using c99 fixed size types.
2004-02-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect changes to bsp.am.

6
c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
View File

@@ -39,7 +39,7 @@
* Clock ticks since initialization
*/
volatile rtems_unsigned32 Clock_driver_ticks;
volatile uint32_t Clock_driver_ticks;
/*
* This is the value programmed into the count down timer. It
@@ -48,7 +48,7 @@ volatile rtems_unsigned32 Clock_driver_ticks;
* the simulator.
*/
extern rtems_unsigned32 CPU_SPARC_CLICKS_PER_TICK;
extern uint32_t CPU_SPARC_CLICKS_PER_TICK;
rtems_isr_entry Old_ticker;
@@ -229,7 +229,7 @@ rtems_device_driver Clock_control(
void *pargp
)
{
rtems_unsigned32 isrlevel;
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args == 0)

10
c/src/lib/libbsp/sparc/erc32/console/console.c
View File

@@ -108,7 +108,7 @@ rtems_isr console_isr_a(
if ( ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA ) {
if ( !Ring_buffer_Is_empty( &TX_Buffer[ 0 ] ) ) {
Ring_buffer_Remove_character( &TX_Buffer[ 0 ], ch );
ERC32_MEC.UART_Channel_A = (unsigned32) ch;
ERC32_MEC.UART_Channel_A = (uint32_t) ch;
} else
Is_TX_active[ 0 ] = FALSE;
}
@@ -149,7 +149,7 @@ rtems_isr console_isr_b(
if ( ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB ) {
if ( !Ring_buffer_Is_empty( &TX_Buffer[ 1 ] ) ) {
Ring_buffer_Remove_character( &TX_Buffer[ 1 ], ch );
ERC32_MEC.UART_Channel_B = (unsigned32) ch;
ERC32_MEC.UART_Channel_B = (uint32_t) ch;
} else
Is_TX_active[ 1 ] = FALSE;
}
@@ -172,8 +172,8 @@ rtems_isr console_isr_b(
void console_exit()
{
rtems_unsigned32 port;
rtems_unsigned32 ch;
uint32_t port;
uint32_t ch;
/*
* Although the interrupts for the UART are unmasked, the PIL is set to
@@ -220,7 +220,7 @@ void console_exit()
*/
#ifdef RDB_BREAK_IN
extern unsigned32 trap_table[];
extern uint32_t trap_table[];
#endif
void console_initialize_interrupts( void )

2
c/src/lib/libbsp/sparc/erc32/console/debugputs.c
View File

@@ -101,7 +101,7 @@ void DEBUG_puts(
)
{
char *s;
unsigned32 old_level;
uint32_t old_level;
ERC32_Disable_interrupt( ERC32_INTERRUPT_UART_A_RX_TX, old_level );
for ( s = string ; *s ; s++ )

14
c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
View File

@@ -17,11 +17,11 @@
void erc32_sonic_write_register(
void *base,
unsigned32 regno,
unsigned32 value
uint32_t regno,
uint32_t value
)
{
volatile unsigned32 *p = base;
volatile uint32_t *p = base;
#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
printf( "%p Write 0x%04x to %s (0x%02x)\n",
@@ -31,13 +31,13 @@ void erc32_sonic_write_register(
p[regno] = 0x0ffff & value;
}
unsigned32 erc32_sonic_read_register(
uint32_t erc32_sonic_read_register(
void *base,
unsigned32 regno
uint32_t regno
)
{
volatile unsigned32 *p = base;
unsigned32 value;
volatile uint32_t *p = base;
uint32_t value;
value = p[regno];
#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)

2
c/src/lib/libbsp/sparc/erc32/include/bsp.h
View File

@@ -131,7 +131,7 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
* This is very dependent on the clock speed of the target.
*/
extern void Clock_delay(rtems_unsigned32 microseconds);
extern void Clock_delay(uint32_t microseconds);
#define delay( microseconds ) Clock_delay(microseconds)

116
c/src/lib/libbsp/sparc/erc32/include/erc32.h
View File

@@ -98,51 +98,51 @@ extern "C" {
*/
typedef struct {
volatile unsigned32 Control; /* offset 0x00 */
volatile unsigned32 Software_Reset; /* offset 0x04 */
volatile unsigned32 Power_Down; /* offset 0x08 */
volatile unsigned32 Unimplemented_0; /* offset 0x0c */
volatile unsigned32 Memory_Configuration; /* offset 0x10 */
volatile unsigned32 IO_Configuration; /* offset 0x14 */
volatile unsigned32 Wait_State_Configuration; /* offset 0x18 */
volatile unsigned32 Unimplemented_1; /* offset 0x1c */
volatile unsigned32 Memory_Access_0; /* offset 0x20 */
volatile unsigned32 Memory_Access_1; /* offset 0x24 */
volatile unsigned32 Unimplemented_2[ 7 ]; /* offset 0x28 */
volatile unsigned32 Interrupt_Shape; /* offset 0x44 */
volatile unsigned32 Interrupt_Pending; /* offset 0x48 */
volatile unsigned32 Interrupt_Mask; /* offset 0x4c */
volatile unsigned32 Interrupt_Clear; /* offset 0x50 */
volatile unsigned32 Interrupt_Force; /* offset 0x54 */
volatile unsigned32 Unimplemented_3[ 2 ]; /* offset 0x58 */
volatile uint32_t Control; /* offset 0x00 */
volatile uint32_t Software_Reset; /* offset 0x04 */
volatile uint32_t Power_Down; /* offset 0x08 */
volatile uint32_t Unimplemented_0; /* offset 0x0c */
volatile uint32_t Memory_Configuration; /* offset 0x10 */
volatile uint32_t IO_Configuration; /* offset 0x14 */
volatile uint32_t Wait_State_Configuration; /* offset 0x18 */
volatile uint32_t Unimplemented_1; /* offset 0x1c */
volatile uint32_t Memory_Access_0; /* offset 0x20 */
volatile uint32_t Memory_Access_1; /* offset 0x24 */
volatile uint32_t Unimplemented_2[ 7 ]; /* offset 0x28 */
volatile uint32_t Interrupt_Shape; /* offset 0x44 */
volatile uint32_t Interrupt_Pending; /* offset 0x48 */
volatile uint32_t Interrupt_Mask; /* offset 0x4c */
volatile uint32_t Interrupt_Clear; /* offset 0x50 */
volatile uint32_t Interrupt_Force; /* offset 0x54 */
volatile uint32_t Unimplemented_3[ 2 ]; /* offset 0x58 */
/* offset 0x60 */
volatile unsigned32 Watchdog_Program_and_Timeout_Acknowledge;
volatile unsigned32 Watchdog_Trap_Door_Set; /* offset 0x64 */
volatile unsigned32 Unimplemented_4[ 6 ]; /* offset 0x68 */
volatile unsigned32 Real_Time_Clock_Counter; /* offset 0x80 */
volatile unsigned32 Real_Time_Clock_Scalar; /* offset 0x84 */
volatile unsigned32 General_Purpose_Timer_Counter; /* offset 0x88 */
volatile unsigned32 General_Purpose_Timer_Scalar; /* offset 0x8c */
volatile unsigned32 Unimplemented_5[ 2 ]; /* offset 0x90 */
volatile unsigned32 Timer_Control; /* offset 0x98 */
volatile unsigned32 Unimplemented_6; /* offset 0x9c */
volatile unsigned32 System_Fault_Status; /* offset 0xa0 */
volatile unsigned32 First_Failing_Address; /* offset 0xa4 */
volatile unsigned32 First_Failing_Data; /* offset 0xa8 */
volatile unsigned32 First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
volatile unsigned32 Error_and_Reset_Status; /* offset 0xb0 */
volatile unsigned32 Error_Mask; /* offset 0xb4 */
volatile unsigned32 Unimplemented_7[ 2 ]; /* offset 0xb8 */
volatile unsigned32 Debug_Control; /* offset 0xc0 */
volatile unsigned32 Breakpoint; /* offset 0xc4 */
volatile unsigned32 Watchpoint; /* offset 0xc8 */
volatile unsigned32 Unimplemented_8; /* offset 0xcc */
volatile unsigned32 Test_Control; /* offset 0xd0 */
volatile unsigned32 Test_Data; /* offset 0xd4 */
volatile unsigned32 Unimplemented_9[ 2 ]; /* offset 0xd8 */
volatile unsigned32 UART_Channel_A; /* offset 0xe0 */
volatile unsigned32 UART_Channel_B; /* offset 0xe4 */
volatile unsigned32 UART_Status; /* offset 0xe8 */
volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge;
volatile uint32_t Watchdog_Trap_Door_Set; /* offset 0x64 */
volatile uint32_t Unimplemented_4[ 6 ]; /* offset 0x68 */
volatile uint32_t Real_Time_Clock_Counter; /* offset 0x80 */
volatile uint32_t Real_Time_Clock_Scalar; /* offset 0x84 */
volatile uint32_t General_Purpose_Timer_Counter; /* offset 0x88 */
volatile uint32_t General_Purpose_Timer_Scalar; /* offset 0x8c */
volatile uint32_t Unimplemented_5[ 2 ]; /* offset 0x90 */
volatile uint32_t Timer_Control; /* offset 0x98 */
volatile uint32_t Unimplemented_6; /* offset 0x9c */
volatile uint32_t System_Fault_Status; /* offset 0xa0 */
volatile uint32_t First_Failing_Address; /* offset 0xa4 */
volatile uint32_t First_Failing_Data; /* offset 0xa8 */
volatile uint32_t First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
volatile uint32_t Error_and_Reset_Status; /* offset 0xb0 */
volatile uint32_t Error_Mask; /* offset 0xb4 */
volatile uint32_t Unimplemented_7[ 2 ]; /* offset 0xb8 */
volatile uint32_t Debug_Control; /* offset 0xc0 */
volatile uint32_t Breakpoint; /* offset 0xc4 */
volatile uint32_t Watchpoint; /* offset 0xc8 */
volatile uint32_t Unimplemented_8; /* offset 0xcc */
volatile uint32_t Test_Control; /* offset 0xd0 */
volatile uint32_t Test_Data; /* offset 0xd4 */
volatile uint32_t Unimplemented_9[ 2 ]; /* offset 0xd8 */
volatile uint32_t UART_Channel_A; /* offset 0xe0 */
volatile uint32_t UART_Channel_B; /* offset 0xe4 */
volatile uint32_t UART_Status; /* offset 0xe8 */
} ERC32_Register_Map;
#endif
@@ -342,7 +342,7 @@ extern ERC32_Register_Map ERC32_MEC;
#define ERC32_Force_interrupt( _source ) \
do { \
unsigned32 _level; \
uint32_t _level; \
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
@@ -358,7 +358,7 @@ extern ERC32_Register_Map ERC32_MEC;
#define ERC32_Mask_interrupt( _source ) \
do { \
unsigned32 _level; \
uint32_t _level; \
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
@@ -367,7 +367,7 @@ extern ERC32_Register_Map ERC32_MEC;
#define ERC32_Unmask_interrupt( _source ) \
do { \
unsigned32 _level; \
uint32_t _level; \
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
@@ -376,8 +376,8 @@ extern ERC32_Register_Map ERC32_MEC;
#define ERC32_Disable_interrupt( _source, _previous ) \
do { \
unsigned32 _level; \
unsigned32 _mask = 1 << (_source); \
uint32_t _level; \
uint32_t _mask = 1 << (_source); \
\
_level = sparc_disable_interrupts(); \
(_previous) = ERC32_MEC.Interrupt_Mask; \
@@ -388,8 +388,8 @@ extern ERC32_Register_Map ERC32_MEC;
#define ERC32_Restore_interrupt( _source, _previous ) \
do { \
unsigned32 _level; \
unsigned32 _mask = 1 << (_source); \
uint32_t _level; \
uint32_t _mask = 1 << (_source); \
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Interrupt_Mask = \
@@ -448,7 +448,7 @@ extern ERC32_Register_Map ERC32_MEC;
#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F
#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005
extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
extern uint32_t _ERC32_MEC_Timer_Control_Mirror;
/*
* This macros manipulate the General Purpose Timer portion of the
@@ -458,9 +458,9 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
do { \
unsigned32 _level; \
unsigned32 _control; \
unsigned32 __value; \
uint32_t _level; \
uint32_t _control; \
uint32_t __value; \
\
__value = ((_value) & 0x0f); \
_level = sparc_disable_interrupts(); \
@@ -487,9 +487,9 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
do { \
unsigned32 _level; \
unsigned32 _control; \
unsigned32 __value; \
uint32_t _level; \
uint32_t _control; \
uint32_t __value; \
\
__value = ((_value) & 0x0f) << 8; \
_level = sparc_disable_interrupts(); \

4
c/src/lib/libbsp/sparc/erc32/startup/setvec.c
View File

@@ -39,8 +39,8 @@ rtems_isr_entry set_vector( /* returns old vector */
)
{
rtems_isr_entry previous_isr;
unsigned32 real_trap;
unsigned32 source;
uint32_t real_trap;
uint32_t source;
if ( type )
rtems_interrupt_catch( handler, vector, &previous_isr );

10
c/src/lib/libbsp/sparc/erc32/startup/spurious.c
View File

@@ -23,7 +23,7 @@ static const char digits[16] = "0123456789abcdef";
/* Simple integer-to-string conversion */
void itos(unsigned32 u, char *s)
void itos(uint32_t u, char *s)
{
int i;
@@ -44,7 +44,7 @@ rtems_isr bsp_spurious_handler(
)
{
char line[ 80 ];
rtems_unsigned32 real_trap;
uint32_t real_trap;
real_trap = SPARC_REAL_TRAP_NUMBER(trap);
@@ -161,9 +161,9 @@ rtems_isr bsp_spurious_handler(
void bsp_spurious_initialize()
{
rtems_unsigned32 trap;
unsigned32 level = 15;
unsigned32 mask;
uint32_t trap;
uint32_t level = 15;
uint32_t mask;
sparc_disable_interrupts(level);
mask = ERC32_MEC.Interrupt_Mask;

2
c/src/lib/libbsp/sparc/erc32/timer/timer.c
View File

@@ -60,7 +60,7 @@ void Timer_initialize()
int Read_timer()
{
rtems_unsigned32 total;
uint32_t total;
total = ERC32_MEC.General_Purpose_Timer_Counter;