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bsp/gen83xx: Support cache BSP options

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This commit is contained in:
Sebastian Huber
2012-04-02 11:06:34 +02:00
parent a3db5ff4ac
commit 1bb72a9487
2 changed files with 6 additions and 3 deletions
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7
c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c
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@@ -96,11 +96,11 @@ void bsp_start( void)
* Enable instruction and data caches. Do not force writethrough mode. * Enable instruction and data caches. Do not force writethrough mode.
*/ */
#if BSP_INSTRUCTION_CACHE_ENABLED #ifdef BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction(); rtems_cache_enable_instruction();
#endif #endif
#if BSP_DATA_CACHE_ENABLED #ifdef BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data(); rtems_cache_enable_data();
#endif #endif
@@ -130,6 +130,9 @@ void bsp_start( void)
} }
/* Initialize exception handler */ /* Initialize exception handler */
#ifndef BSP_DATA_CACHE_ENABLED
ppc_exc_cache_wb_check = 0;
#endif
sc = ppc_exc_initialize( sc = ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT, PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
interrupt_stack_start, interrupt_stack_start,

2
c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
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@@ -149,7 +149,7 @@ void cpu_init( void)
clear_mmu_regs(); clear_mmu_regs();
/* Clear caches */ /* Clear caches */
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ILOCK | HID0_DLOCK); PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ILOCK | HID0_DLOCK | HID0_ICE | HID0_DCE);
PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI); PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI); PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);