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2005-11-02 straumanatslacdotstanford.edu

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* mpc6xx/mmu/pte121.c, mpc6xx/mmu/pte121.h: enhancements to mpc6xx page
	table support - PTEs can now be modified even if the page table is
	already active; bugfix: address range crossing 256MB boundary was not
	handled correctly
This commit is contained in:
Till Straumann
2005-11-03 02:26:08 +00:00
parent ec58ea04af
commit 1b1b43ccc1
3 changed files with 814 additions and 557 deletions
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7
c/src/lib/libcpu/powerpc/ChangeLog
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@@ -1,3 +1,10 @@
2005-11-02 straumanatslacdotstanford.edu
* mpc6xx/mmu/pte121.c, mpc6xx/mmu/pte121.h: enhancements to mpc6xx page
table support - PTEs can now be modified even if the page table is
already active; bugfix: address range crossing 256MB boundary was not
handled correctly
2005-11-02 straumanatslacdotstanford.edu
* mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S: moved

1213
c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
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File diff suppressed because it is too large Load Diff

151
c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h
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@@ -13,19 +13,34 @@
* 1) allow write-protection of text/read-only data areas
* 2) provide more effective-address space in case
* the BATs are not enough
* 3) allow 'alias' mappings. Such aliases can only use
* the upper bits of the VSID since VSID & 0xf and the
* PI are always mapped 1:1 to the RPN.
* LIMITATIONS:
* - once activated, the page table cannot be changed
* - no PTE replacement (makes no sense in a real-time
* environment, anyway) -> the page table just MUST
* be big enough!.
* - only one page table supported.
* - no locking implemented. If multiple threads modify
* the page table, it is the user's responsibility to
* implement exclusive access.
*/
/* Author: Till Straumann <strauman@slac.stanford.edu>, 4/2002 */
/* Author: Till Straumann <strauman@slac.stanford.edu>, 4/2002 - 2004 */
/* I don't include mmu.h here because it says it's derived from linux
* and I want to avoid licensing problems
*/
/* Abstract handle for a page table */
typedef struct Triv121PgTblRec_ *Triv121PgTbl;
/* A PTE entry */
typedef struct PTERec_ {
volatile unsigned long v:1, vsid:24, h:1, api: 6;
volatile unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2;
} PTERec, *APte;
/* Initialize a trivial page table
* using 2^ldSize bytes of memory starting at
* 'base'.
@@ -41,8 +56,8 @@ typedef struct Triv121PgTblRec_ *Triv121PgTbl;
* the CPU from overwriting the page table,
* it can still be corrupted by PCI bus masters
* (like DMA engines, [VME] bridges etc.) and
* even by this CPU if either the MMU is off
* or if there is a DBAT mapping granting write
* even by this CPU if either the MMU is off
* or if there is a DBAT mapping granting write
* access...
*/
Triv121PgTbl
@@ -56,8 +71,8 @@ triv121PgTblInit(unsigned long base, unsigned ldSize);
* be allocated at the top of the available
* memory (assuming 'memsize' is a power of two):
*
* ldSize = triv121PgTblLdMinSize(memsize);
* memsize -= (1<<ldSize); / * reduce memory available to RTEMS * /
* ldSize = triv121PgTblLdMinSize(memsize);
* memsize -= (1<<ldSize); / * reduce memory available to RTEMS * /
* pgTbl = triv121PgTblInit(memsize,ldSize);
*
*/
@@ -81,55 +96,56 @@ triv121PgTblLdMinSize(unsigned long size);
*/
long
triv121PgTblMap(
Triv121PgTbl pgTbl, /* handle, returned by Init or Get */
Triv121PgTbl pgTbl, /* handle, returned by Init or Get */
long vsid, /* vsid for this mapping (contains topmost 4 bits of EA);
*
* NOTE: it is allowed to pass a VSID < 0 to tell this
* routine it should use a VSID corresponding to a
* 1:1:1 effective - virtual - physical mapping
*/
long vsid, /* vsid for this mapping (contains topmost 4 bits of EA);
*
* NOTE: it is allowed to pass a VSID < 0 to tell this
* routine it should use a VSID corresponding to a
* 1:1:1 effective - virtual - physical mapping
*/
unsigned long start, /* segment offset (lowermost 28 bits of EA) of address range
*
* NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter-
* preted as an effective address (EA), i.e. all 32
* bits are used - the most significant four going into
* to the VSID...
*/
unsigned long start, /* segment offset (lowermost 28 bits of EA) of address range
*
* NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter-
* preted as an effective address (EA), i.e. all 32
* bits are used - the most significant four going into
* to the VSID...
*/
unsigned long numPages, /* number of pages to map */
unsigned long numPages, /* number of pages to map */
unsigned wimgAttr, /* 'wimg' attributes
* (Write thru, cache Inhibit, coherent Memory,
* Guarded memory)
*/
unsigned wimgAttr, /* 'wimg' attributes
* (Write thru, cache Inhibit, coherent Memory,
* Guarded memory)
*/
unsigned protection /* 'pp' access protection: Super User
*
* 0 r/w none
* 1 r/w ro
* 2 r/w r/w
* 3 ro ro
*/
);
unsigned protection /* 'pp' access protection: Super User
*
* 0 r/w none
* 1 r/w ro
* 2 r/w r/w
* 3 ro ro
*/
);
#define TRIV121_ATTR_W 8
#define TRIV121_ATTR_I 4
#define TRIV121_ATTR_M 2
#define TRIV121_ATTR_G 1
#define TRIV121_ATTR_W 8
#define TRIV121_ATTR_I 4
#define TRIV121_ATTR_M 2
#define TRIV121_ATTR_G 1
/* for I/O pages (e.g. PCI, VME addresses) use cache inhibited
* and guarded pages. RTM about the 'eieio' instruction!
*/
#define TRIV121_ATTR_IO_PAGE (TRIV121_ATTR_I|TRIV121_ATTR_G)
#define TRIV121_ATTR_IO_PAGE (TRIV121_ATTR_I|TRIV121_ATTR_G)
#define TRIV121_PP_RO_PAGE (3) /* read-only for everyone */
#define TRIV121_PP_RW_PAGE (2) /* read-write for everyone */
#define TRIV121_PP_RO_PAGE (1) /* read-only for key = 1, unlocked by key=0 */
#define TRIV121_PP_RW_PAGE (2) /* read-write for key = 1/0 */
#define TRIV121_121_VSID (-1) /* use 1:1 effective<->virtual address mapping */
#define TRIV121_121_VSID (-1) /* use 1:1 effective<->virtual address mapping */
#define TRIV121_SEG_VSID (-2) /* lookup VSID in the segment register */
#define TRIV121_MAP_SUCCESS (-1) /* triv121PgTblMap() returns this on SUCCESS */
#define TRIV121_MAP_SUCCESS (-1) /* triv121PgTblMap() returns this on SUCCESS */
/* get a handle to the one and only page table
* (must have been initialized/allocated)
@@ -148,7 +164,7 @@ triv121PgTblSDR1(Triv121PgTbl pgTbl);
/*
* Activate the page table:
* - set up the segment registers for a 1:1 effective <-> virtual address mapping,
* - set up the segment registers for a 1:1 effective <-> virtual address mapping,
* give user and supervisor keys.
* - set up the SDR1 register
* - flush all tlbs
@@ -162,4 +178,53 @@ triv121PgTblSDR1(Triv121PgTbl pgTbl);
void
triv121PgTblActivate(Triv121PgTbl pgTbl);
/* Find the PTE for a EA and print its contents to stdout
* RETURNS: pte for EA or NULL if no entry was found.
*/
APte
triv121DumpEa(unsigned long ea);
/* Find and return a PTE for a vsid/pi combination
* RETURNS: pte or NULL if no entry was found
*/
APte
triv121FindPte(unsigned long vsid, unsigned long pi);
/*
* Unmap an effective address
*
* RETURNS: pte that mapped the ea or NULL if no
* mapping existed.
*/
APte
triv121UnmapEa(unsigned long ea);
/*
* Change the WIMG and PP attributes of the page containing 'ea'
*
* NOTES: The 'wimg' and 'pp' may be <0 to indicate that no
* change is desired.
*
* RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped.
*/
APte
triv121ChangeEaAttributes(unsigned long ea, int wimg, int pp);
/* Make the whole page table writable
* NOTES: If the page table has not been initialized yet,
* this routine has no effect (i.e., after
* initialization the page table will still be read-only).
*/
void
triv121MakePgTblRW();
/* Make the whole page table read-only
*/
void
triv121MakePgTblRO();
/* Dump a pte to stdout */
long
triv121DumpPte(APte pte);
#endif