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minor updates .. mostly version

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This commit is contained in:
Joel Sherrill
1998-01-23 16:57:29 +00:00
parent 1d01241029
commit 173c59c841
20 changed files with 110 additions and 106 deletions
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9
doc/supplements/hppa1_1/hppa1_1.texi
View File

@@ -35,9 +35,10 @@ END-INFO-DIR-ENTRY
@c Title Page Stuff
@c
@set edition 4.2.0-beta1
@set update-date 1 June 1997
@set update-month June 1997
@set edition 970904
@set version 970904
@set update-date 4 September 1997
@set update-month September 1997
@c
@c I don't really like having a short title page. --joel
@@ -50,7 +51,7 @@ END-INFO-DIR-ENTRY
@finalout
@title RTEMS Hewlett Packard PA-RISC Applications Supplement
@subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
@subtitle Edition @value{edition}, for RTEMS @value{version}
@sp 1
@subtitle @value{update-month}
@author On-Line Applications Research Corporation

17
doc/supplements/i386/i386.texi
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@@ -1,11 +1,3 @@
@c
@c COPYRIGHT (c) 1988-1997.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c $Id$
@c
\input ../texinfo/texinfo @c -*-texinfo-*-
@c %**start of header
@setfilename c_i386
@@ -43,9 +35,10 @@ END-INFO-DIR-ENTRY
@c Title Page Stuff
@c
@set edition 4.2.0-beta1
@set update-date 1 June 1997
@set update-month June 1997
@set edition 970904
@set version 970904
@set update-date 4 September 1997
@set update-month September 1997
@c
@c I don't really like having a short title page. --joel
@@ -58,7 +51,7 @@ END-INFO-DIR-ENTRY
@finalout
@title RTEMS Intel i386 Applications Supplement
@subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
@subtitle Edition @value{edition}, for RTEMS @value{version}
@sp 1
@subtitle @value{update-month}
@author On-Line Applications Research Corporation

9
doc/supplements/i960/i960.texi
View File

@@ -35,9 +35,10 @@ END-INFO-DIR-ENTRY
@c Title Page Stuff
@c
@set edition 4.2.0-beta1
@set update-date 1 June 1997
@set update-month June 1997
@set edition 970904
@set version 970904
@set update-date 4 September 1997
@set update-month September 1997
@c
@c I don't really like having a short title page. --joel
@@ -50,7 +51,7 @@ END-INFO-DIR-ENTRY
@finalout
@title RTEMS Intel i960 Applications Supplement
@subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
@subtitle Edition @value{edition}, for RTEMS @value{version}
@sp 1
@subtitle @value{update-month}
@author On-Line Applications Research Corporation

9
doc/supplements/m68k/m68k.texi
View File

@@ -35,9 +35,10 @@ END-INFO-DIR-ENTRY
@c Title Page Stuff
@c
@set edition 4.2.0-beta1
@set update-date 1 June 1997
@set update-month June 1997
@set edition 970904
@set version 970904
@set update-date 4 September 1997
@set update-month September 1997
@c
@c I don't really like having a short title page. --joel
@@ -50,7 +51,7 @@ END-INFO-DIR-ENTRY
@finalout
@title RTEMS Motorola MC68xxx Applications Supplement
@subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
@subtitle Edition @value{edition}, for RTEMS @value{version}
@sp 1
@subtitle @value{update-month}
@author On-Line Applications Research Corporation

2
doc/supplements/powerpc/bsp.t
View File

@@ -87,7 +87,7 @@ rtems_initialize executive, the PowrePC version has the following
specific requirements:
@itemize @bullet
@item Must leave the PR bit of the machine state register set so that
@item Must leave the PR bit of the machine state register set so that
the PowerPC remains in the supervisor state.
@item Must set stack pointer (sp) such that a minimum stack

2
doc/supplements/powerpc/bsp.texi
View File

@@ -87,7 +87,7 @@ rtems_initialize executive, the PowrePC version has the following
specific requirements:
@itemize @bullet
@item Must leave the PR bit of the machine state register set so that
@item Must leave the PR bit of the machine state register set so that
the PowerPC remains in the supervisor state.
@item Must set stack pointer (sp) such that a minimum stack

43
doc/supplements/powerpc/callconv.t
View File

@@ -153,25 +153,17 @@ The following table describes the role of each of these registers:
@end ifinfo
@subsection Floating Point Registers
The SPARC V7 architecture includes thirty-two,
thirty-two bit registers. These registers may be viewed as
follows:
The PowerPC architecture includes thirty-two,
sixty-four bit registers. All PowwerPC floating point instructions
interprete these registers as 32 double precision floating point registers,
regardless of whether the processor has 64-bit or 32-bit implementation.
@itemize @bullet
@item 32 single precision floating point or integer registers
(f0, f1, ... f31)
@item 16 double precision floating point registers (f0, f2,
f4, ... f30)
@item 8 extended precision floating point registers (f0, f4,
f8, ... f28)
@end itemize
The floating point status register (fpsr) specifies
the behavior of the floating point unit for rounding, contains
its condition codes, version specification, and trap information.
The floating point status and control register (fpscr) records exceptions
and the type of result generated by floating-point operations.
Additionally, it controls the rounding mode of operations and allows the
reporting of floating exceptions to be enabled or disabled.
XXXXXX
A queue of the floating point instructions which have
started execution but not yet completed is maintained. This
queue is needed to support the multiple cycle nature of floating
@@ -183,22 +175,29 @@ It is emptied normally when the floating point completes all
outstanding instructions and by floating point exception
handlers with the store double floating point queue (stdfq)
instruction.
XXX
@ifinfo
@node Special Registers, Calling Conventions Register Windows, Floating Point Registers, Calling Conventions Programming Model
@end ifinfo
@subsection Special Registers
The SPARC architecture includes two special registers
which are critical to the programming model: the Processor State
Register (psr) and the Window Invalid Mask (wim). The psr
contains the condition codes, processor interrupt level, trap
The PowerPC architecture includes XXX special registers
which are critical to the programming model: the Machine State
Register (msr) and XXX the Window Invalid Mask (wim) XXX. The msr
contains the processor mode, power management mode, endian mode, exception
information, privlige level, floating point available and floating point
excepiton mode, address translation information and the exception prefix.
XXX
condition codes, processor interrupt level, trap
enable bit, supervisor mode and previous supervisor mode bits,
version information, floating point unit and coprocessor enable
bits, and the current window pointer (cwp). The cwp field of
the psr and wim register are used to manage the register windows
in the SPARC architecture. The register windows are discussed
in more detail below.
XXX
@ifinfo
@node Calling Conventions Register Windows, Calling Conventions Call and Return Mechanism, Special Registers, Calling Conventions
@@ -369,3 +368,5 @@ All user-provided routines invoked by RTEMS, such as
user extensions, device drivers, and MPCI routines, must also
adhere to these calling conventions.

43
doc/supplements/powerpc/callconv.texi
View File

@@ -153,25 +153,17 @@ The following table describes the role of each of these registers:
@end ifinfo
@subsection Floating Point Registers
The SPARC V7 architecture includes thirty-two,
thirty-two bit registers. These registers may be viewed as
follows:
The PowerPC architecture includes thirty-two,
sixty-four bit registers. All PowwerPC floating point instructions
interprete these registers as 32 double precision floating point registers,
regardless of whether the processor has 64-bit or 32-bit implementation.
@itemize @bullet
@item 32 single precision floating point or integer registers
(f0, f1, ... f31)
@item 16 double precision floating point registers (f0, f2,
f4, ... f30)
@item 8 extended precision floating point registers (f0, f4,
f8, ... f28)
@end itemize
The floating point status register (fpsr) specifies
the behavior of the floating point unit for rounding, contains
its condition codes, version specification, and trap information.
The floating point status and control register (fpscr) records exceptions
and the type of result generated by floating-point operations.
Additionally, it controls the rounding mode of operations and allows the
reporting of floating exceptions to be enabled or disabled.
XXXXXX
A queue of the floating point instructions which have
started execution but not yet completed is maintained. This
queue is needed to support the multiple cycle nature of floating
@@ -183,22 +175,29 @@ It is emptied normally when the floating point completes all
outstanding instructions and by floating point exception
handlers with the store double floating point queue (stdfq)
instruction.
XXX
@ifinfo
@node Special Registers, Calling Conventions Register Windows, Floating Point Registers, Calling Conventions Programming Model
@end ifinfo
@subsection Special Registers
The SPARC architecture includes two special registers
which are critical to the programming model: the Processor State
Register (psr) and the Window Invalid Mask (wim). The psr
contains the condition codes, processor interrupt level, trap
The PowerPC architecture includes XXX special registers
which are critical to the programming model: the Machine State
Register (msr) and XXX the Window Invalid Mask (wim) XXX. The msr
contains the processor mode, power management mode, endian mode, exception
information, privlige level, floating point available and floating point
excepiton mode, address translation information and the exception prefix.
XXX
condition codes, processor interrupt level, trap
enable bit, supervisor mode and previous supervisor mode bits,
version information, floating point unit and coprocessor enable
bits, and the current window pointer (cwp). The cwp field of
the psr and wim register are used to manage the register windows
in the SPARC architecture. The register windows are discussed
in more detail below.
XXX
@ifinfo
@node Calling Conventions Register Windows, Calling Conventions Call and Return Mechanism, Special Registers, Calling Conventions
@@ -369,3 +368,5 @@ All user-provided routines invoked by RTEMS, such as
user extensions, device drivers, and MPCI routines, must also
adhere to these calling conventions.

9
doc/supplements/powerpc/powerpc.texi
View File

@@ -35,9 +35,10 @@ END-INFO-DIR-ENTRY
@c Title Page Stuff
@c
@set edition 4.2.0-beta1
@set update-date 1 June 1997
@set update-month June 1997
@set edition 970904
@set version 970904
@set update-date 4 September 1997
@set update-month September 1997
@c
@c I don't really like having a short title page. --joel
@@ -50,7 +51,7 @@ END-INFO-DIR-ENTRY
@finalout
@title RTEMS PowerPC Applications Supplement
@subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
@subtitle Edition @value{edition}, for RTEMS @value{version}
@sp 1
@subtitle @value{update-month}
@author On-Line Applications Research Corporation

9
doc/supplements/sparc/sparc.texi
View File

@@ -35,9 +35,10 @@ END-INFO-DIR-ENTRY
@c Title Page Stuff
@c
@set edition 4.2.0-beta1
@set update-date 1 June 1997
@set update-month June 1997
@set edition 970904
@set version 970904
@set update-date 4 September 1997
@set update-month September 1997
@c
@c I don't really like having a short title page. --joel
@@ -50,7 +51,7 @@ END-INFO-DIR-ENTRY
@finalout
@title RTEMS SPARC Applications Supplement
@subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
@subtitle Edition @value{edition}, for RTEMS @value{version}
@sp 1
@subtitle @value{update-month}
@author On-Line Applications Research Corporation