forked from Imagelibrary/rtems
2006-08-15 Kolja Waschk <kawk@telos.de>
* linkcmds.c, linkcmds.h, memory.c, memory.h, sample.ptf: New files. * bridges.c: corrected detection of bridged connections * clocks.c: removed a printf * linkcmds.[ch] new files, added output of linker script * Makefile.am: added new files * memory.[ch]: new files, detection of memory in SOPC configuration * nios2gen.c: updated command line parsing and output control * output.[ch]: improved output of BSP header file * ptf.[ch]: added ptf_dump_ptf_item and small fixes * sample.ptf: new file, sample configuration for nios2gen * README: updated
This commit is contained in:
Joel Sherrill
462
tools/cpu/nios2/sample.ptf
Normal file
462
tools/cpu/nios2/sample.ptf
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@@ -0,0 +1,462 @@
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N2GCOMM = "=============== Header output settings ===========================";
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BSPHEADER
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{
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LEADTEXT =
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"/* Autogenerated by nios2gen, (C) 2006 K. Waschk rtemsdev/ixo.de */
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#ifndef __SOPC_H
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#define __SOPC_H 1
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CLOCK_FREQ_REF(clock) clock ## _FREQ
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#define CLOCK_FREQ(x) CLOCK_FREQ_REF(x)
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";
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EPILOG =
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"
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#ifdef __cplusplus
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}
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#endif
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#endif
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";
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}
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N2GCOMM = "=============== Class templates ==================================";
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CLASS altera_nios2
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{
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N2G_DEFINE_IS_AVAILABLE = "1";
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SYSTEM_BUILDER_INFO
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{
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Clock_Source = "N2G_CLOCKREF_CLOCK";
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}
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SLAVE jtag_debug_module
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{
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SYSTEM_BUILDER_INFO { Base_Address = "BASE_ADDR"; }
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}
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WIZARD_SCRIPT_ARGUMENTS
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{
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cache_has_dcache = "HAS_DCACHE";
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cache_has_icache = "HAS_ICACHE";
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cache_dcache_size = "DCACHE_SIZE";
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cache_icache_size = "ICACHE_SIZE";
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cache_dcache_line_size = "DCACHE_LINE_SIZE";
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cache_icache_line_size = "ICACHE_LINE_SIZE";
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cache_dcache_bursts = "DCACHE_BURSTS";
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cache_icache_burst_type = "ICACHE_BURST_TYPE";
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hardware_multiply_present = "HAS_HWMULT";
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}
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}
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CLASS altera_avalon_onchip_memory2
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{
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N2G_DEFINE_IS_AVAILABLE = "1";
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WIZARD_SCRIPT_ARGUMENTS
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{
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Writeable = "WRITEABLE";
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dual_port = "DUAL_PORT";
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Size_Value = "SIZE_VALUE";
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Size_Multiple = "SIZE_MULTIPLE";
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}
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SYSTEM_BUILDER_INFO
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{
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Clock_Source = "N2G_CLOCKREF_CLOCK";
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}
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SLAVE s1
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{
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N2G_DEFINE_CONNECTED_PORT = "S1";
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SYSTEM_BUILDER_INFO
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{
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Base_Address = "S1_BASE_ADDR";
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Data_Width = "S1_DATA_WIDTH";
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Address_Width = "S1_ADDR_WIDTH";
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Address_Span = "S1_ADDR_SPAN";
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}
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}
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SLAVE s2
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{
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N2G_DEFINE_CONNECTED_PORT = "S2";
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SYSTEM_BUILDER_INFO
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{
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Base_Address = "S2_BASE_ADDR";
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Data_Width = "S2_DATA_WIDTH";
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Address_Width = "S2_ADDR_WIDTH";
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Address_Span = "S2_ADDR_SPAN";
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}
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}
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}
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CLASS sram_256k_x_16_bit
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{
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N2G_DEFINE_IS_AVAILABLE = "1";
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SLAVE sram
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{
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SYSTEM_BUILDER_INFO
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{
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Base_Address = "BASE_ADDR";
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Data_Width = "DATA_WIDTH";
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Address_Width = "ADDR_WIDTH";
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Address_Span = "ADDR_SPAN";
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}
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}
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}
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CLASS altera_avalon_sysid
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{
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N2G_DEFINE_IS_AVAILABLE = "1";
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SLAVE control_slave
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{
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SYSTEM_BUILDER_INFO
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{
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Base_Address = "BASE_ADDR";
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}
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}
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WIZARD_SCRIPT_ARGUMENTS
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{
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id = "ID";
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timestamp = "TIMESTAMP";
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}
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}
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CLASS altera_avalon_timer
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{
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N2G_DEFINE_IS_AVAILABLE = "1";
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SLAVE s1
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{
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SYSTEM_BUILDER_INFO
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{
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Base_Address = "BASE_ADDR";
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IRQ_MASTER { IRQ_Number = "IRQ"; }
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}
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}
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WIZARD_SCRIPT_ARGUMENTS
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{
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snapshot = "SNAPSHOT";
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always_run = "ALWAYS_RUN";
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mult = "MULT";
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period = "PERIOD";
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period_units = "PERIOD_UNITS";
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fixed_period = "FIXED_PERIOD";
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}
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SYSTEM_BUILDER_INFO
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{
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Clock_Source = "N2G_CLOCKREF_CLOCK";
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}
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}
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CLASS altera_avalon_uart
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{
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N2G_DEFINE_IS_AVAILABLE = "1";
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SYSTEM_BUILDER_INFO
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{
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Clock_Source = "N2G_CLOCKREF_CLOCK";
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}
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WIZARD_SCRIPT_ARGUMENTS
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{
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use_cts_rts = "USE_CTS_RTS";
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use_eop_register = "USE_EOP_REG";
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}
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SLAVE s1
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{
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SYSTEM_BUILDER_INFO
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{
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Base_Address = "BASE_ADDR";
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IRQ_MASTER { IRQ_Number = "IRQ"; }
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}
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}
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}
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CLASS altera_avalon_jtag_uart
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{
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N2G_DEFINE_IS_AVAILABLE = "1";
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SLAVE avalon_jtag_slave
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{
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SYSTEM_BUILDER_INFO
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{
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Base_Address = "BASE_ADDR";
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IRQ_MASTER { IRQ_Number = "IRQ"; }
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}
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}
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}
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CLASS altera_avalon_pio
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{
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N2G_DEFINE_IS_AVAILABLE = "1";
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SYSTEM_BUILDER_INFO
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{
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Clock_Source = "N2G_CLOCKREF_CLOCK";
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}
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SLAVE
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{
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SYSTEM_BUILDER_INFO
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{
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Base_Address = "BASE_ADDR";
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IRQ_MASTER { IRQ_Number = "IRQ"; }
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}
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}
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}
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N2GCOMM = "=============== Linkcmds output settings =========================";
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LINKCMDS
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{
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LEADTEXT = "
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OUTPUT_FORMAT( "elf32-littlenios2",
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"elf32-littlenios2",
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"elf32-littlenios2" )
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OUTPUT_ARCH( nios2 )
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ENTRY( _start )
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"
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SECTION entry
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{
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COMMANDS =
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" KEEP (*(.entry))
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";
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}
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SECTION exceptions
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{
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COMMANDS =
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" PROVIDE (__ram_exceptions_start = ABSOLUTE(.));
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. = ALIGN(0x20);
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*(.irq)
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KEEP (*(.exceptions.entry.label));
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KEEP (*(.exceptions.entry.user));
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KEEP (*(.exceptions.entry));
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KEEP (*(.exceptions.irqtest.user));
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KEEP (*(.exceptions.irqtest));
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KEEP (*(.exceptions.irqhandler.user));
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KEEP (*(.exceptions.irqhandler));
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KEEP (*(.exceptions.irqreturn.user));
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KEEP (*(.exceptions.irqreturn));
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KEEP (*(.exceptions.notirq.label));
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KEEP (*(.exceptions.notirq.user));
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KEEP (*(.exceptions.notirq));
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KEEP (*(.exceptions.soft.user));
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KEEP (*(.exceptions.soft));
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KEEP (*(.exceptions.unknown.user));
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KEEP (*(.exceptions.unknown));
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KEEP (*(.exceptions.exit.label));
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KEEP (*(.exceptions.exit.user));
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KEEP (*(.exceptions.exit));
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KEEP (*(.exceptions));
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PROVIDE (__ram_exceptions_end = ABSOLUTE(.));
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";
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}
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SECTION text
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{
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LOCATION = "SDRAM";
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COMMANDS =
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" PROVIDE (stext = ABSOLUTE(.));
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*(.interp)
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*(.hash)
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*(.dynsym)
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*(.dynstr)
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*(.gnu.version)
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*(.gnu.version_d)
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*(.gnu.version_r)
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*(.rel.init)
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*(.rela.init)
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*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
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*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
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*(.rel.fini)
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*(.rela.fini)
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*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
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*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
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*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
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*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
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*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
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*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
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*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
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*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
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*(.rel.ctors)
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*(.rela.ctors)
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*(.rel.dtors)
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*(.rela.dtors)
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*(.rel.got)
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*(.rela.got)
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*(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
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*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
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*(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
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*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
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*(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
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*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
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*(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
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*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
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*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
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*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
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*(.rel.plt)
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*(.rela.plt)
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KEEP (*(.init))
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*(.plt)
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*(.text .stub .text.* .gnu.linkonce.t.*)
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/* Special FreeBSD sysctl sections. */
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. = ALIGN (16);
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__start_set_sysctl_set = .;
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*(set_sysctl_*);
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__stop_set_sysctl_set = ABSOLUTE(.);
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*(set_domain_*);
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*(set_pseudo_*);
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*(.gnu.warning.*)
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KEEP (*(.fini))
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PROVIDE (__etext = ABSOLUTE(.));
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PROVIDE (_etext = ABSOLUTE(.));
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PROVIDE (etext = ABSOLUTE(.));
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*(.eh_frame_hdr)
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/* Ensure the __preinit_array_start label is properly aligned. We
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could instead move the label definition inside the section, but
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the linker would then create the section even if it turns out to
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be empty, which isn't pretty. */
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. = ALIGN(32 / 8);
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PROVIDE (__preinit_array_start = ABSOLUTE(.));
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*(.preinit_array)
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PROVIDE (__preinit_array_end = ABSOLUTE(.));
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PROVIDE (__init_array_start = ABSOLUTE(.));
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*(.init_array)
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PROVIDE (__init_array_end = ABSOLUTE(.));
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PROVIDE (__fini_array_start = ABSOLUTE(.));
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*(.fini_array)
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PROVIDE (__fini_array_end = ABSOLUTE(.));
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SORT(CONSTRUCTORS)
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KEEP (*(.eh_frame))
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*(.gcc_except_table)
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*(.dynamic)
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PROVIDE (__CTOR_LIST__ = ABSOLUTE(.));
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KEEP (*(.ctors))
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KEEP (*(SORT(.ctors.*)))
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PROVIDE (__CTOR_END__ = ABSOLUTE(.));
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PROVIDE (__DTOR_LIST__ = ABSOLUTE(.));
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KEEP (*(.dtors))
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KEEP (*(SORT(.dtors.*)))
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PROVIDE (__DTOR_END__ = ABSOLUTE(.));
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KEEP (*(.jcr))
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. = ALIGN(32 / 8);
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";
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}
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SECTION rodata
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{
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LOCATION = "SDRAM";
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COMMANDS =
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" PROVIDE (__ram_rodata_start = ABSOLUTE(.));
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. = ALIGN(32 / 8);
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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*(.rodata1)
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. = ALIGN(32 / 8);
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PROVIDE (__ram_rodata_end = ABSOLUTE(.));
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";
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}
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SECTION rwdata
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{
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LOCATION = "SDRAM";
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COMMANDS =
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" PROVIDE (__ram_rwdata_start = ABSOLUTE(.));
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. = ALIGN(32 / 8);
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||||
*(.got.plt) *(.got)
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||||
*(.data1)
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||||
*(.data .data.* .gnu.linkonce.d.*)
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||||
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||||
_gp = ABSOLUTE(. + 0x8000);
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||||
PROVIDE(gp = _gp);
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||||
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||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
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||||
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
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||||
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||||
. = ALIGN(32 / 8);
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||||
_edata = ABSOLUTE(.);
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||||
PROVIDE (edata = ABSOLUTE(.));
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||||
PROVIDE (__ram_rwdata_end = ABSOLUTE(.));
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||||
";
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||||
}
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||||
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||||
SECTION bss
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||||
{
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||||
LOCATION = "SDRAM";
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||||
COMMANDS =
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||||
" __bss_start = ABSOLUTE(.);
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||||
PROVIDE (__sbss_start = ABSOLUTE(.));
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||||
PROVIDE (___sbss_start = ABSOLUTE(.));
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||||
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||||
*(.dynsbss)
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||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
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||||
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
|
||||
*(.scommon)
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||||
|
||||
PROVIDE (__sbss_end = ABSOLUTE(.));
|
||||
PROVIDE (___sbss_end = ABSOLUTE(.));
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||||
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||||
*(.dynbss)
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||||
*(.bss .bss.* .gnu.linkonce.b.*)
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||||
*(COMMON)
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||||
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||||
. = ALIGN(32 / 8);
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||||
__bss_end = ABSOLUTE(.);
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||||
";
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||||
}
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||||
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||||
STABS =
|
||||
" .stab 0 : { *(.stab) }
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||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
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||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
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||||
.comment 0 : { *(.comment) }
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||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
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||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
/* Altera debug extensions */
|
||||
.debug_alt_sim_info 0 : { *(.debug_alt_sim_info) }
|
||||
";
|
||||
|
||||
HEAP = "SDRAM";
|
||||
STACK = "SDRAM";
|
||||
}
|
||||
|
||||
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