forked from Imagelibrary/rtems
bsp/mpc55xxevb: Change early MMU settings
Add internal SRAM sections with cache enabled to early MMU settings. The internal SRAM initialization will use the early MMU settings. This allows applications to use cache inhibited areas in the internal SRAM.
This commit is contained in:
@@ -7,7 +7,7 @@
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*/
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*/
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/*
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/*
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* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
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* Copyright (c) 2011-2012 embedded brains GmbH. All rights reserved.
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*
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*
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* embedded brains GmbH
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* Obere Lagerstr. 30
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@@ -25,14 +25,25 @@
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BSP_START_TEXT_SECTION const struct MMU_tag
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BSP_START_TEXT_SECTION const struct MMU_tag
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mpc55xx_start_config_mmu_early [] = {
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mpc55xx_start_config_mmu_early [] = {
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#if MPC55XX_CHIP_TYPE / 10 == 564
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#if MPC55XX_CHIP_TYPE / 10 == 555
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/* Internal SRAM 96k */
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MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 1, 1, 1, 0),
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#elif MPC55XX_CHIP_TYPE / 10 == 556
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/* Internal SRAM 128k */
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MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 1, 1, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(5, 0x40010000, MPC55XX_MMU_64K, 0, 1, 1, 0),
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#elif MPC55XX_CHIP_TYPE / 10 == 564
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/* Internal flash 1M */
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/* Internal flash 1M */
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MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 1),
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MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 1),
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/* IO */
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/* IO */
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MPC55XX_MMU_TAG_INITIALIZER(1, 0xffe00000, MPC55XX_MMU_2M, 0, 1, 1, 1),
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MPC55XX_MMU_TAG_INITIALIZER(1, 0xffe00000, MPC55XX_MMU_2M, 0, 1, 1, 1),
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MPC55XX_MMU_TAG_INITIALIZER(2, 0xc3f00000, MPC55XX_MMU_1M, 0, 1, 1, 1),
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MPC55XX_MMU_TAG_INITIALIZER(2, 0xc3f00000, MPC55XX_MMU_1M, 0, 1, 1, 1),
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/* Internal SRAM 64k */
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/* Internal SRAM 64k + 64k */
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MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 1, 1, 1, 1)
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MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 1, 1, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(4, 0x50000000, MPC55XX_MMU_64K, 0, 1, 1, 0)
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#elif MPC55XX_CHIP_TYPE / 10 == 567
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/* Internal SRAM 256k */
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MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 1, 1, 1, 0)
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#endif
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#endif
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};
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};
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@@ -7,7 +7,7 @@
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*/
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*/
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/*
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/*
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* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
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* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
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*
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*
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* embedded brains GmbH
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* Obere Lagerstr. 30
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@@ -86,20 +86,20 @@ BSP_START_TEXT_SECTION const struct MMU_tag
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#elif defined(MPC55XX_BOARD_MPC5566EVB)
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#elif defined(MPC55XX_BOARD_MPC5566EVB)
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/* Internal flash 3M */
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/* Internal flash 3M */
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MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(6, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_64K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(7, 0x00020000, MPC55XX_MMU_64K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(7, 0x00030000, MPC55XX_MMU_64K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(8, 0x00030000, MPC55XX_MMU_64K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(8, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(9, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(9, 0x00080000, MPC55XX_MMU_256K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(10, 0x00080000, MPC55XX_MMU_256K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(10, 0x000c0000, MPC55XX_MMU_256K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(11, 0x000c0000, MPC55XX_MMU_256K, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(11, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(12, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(12, 0x00200000, MPC55XX_MMU_1M, 1, 0, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(13, 0x00200000, MPC55XX_MMU_1M, 1, 0, 1, 0),
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/* External SRAM 512k */
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/* External SRAM 512k */
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MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(13, 0x20040000, MPC55XX_MMU_256K, 0, 1, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(14, 0x20040000, MPC55XX_MMU_256K, 0, 1, 1, 0),
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/* Internal SRAM 128k */
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/* Internal SRAM 128k */
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MPC55XX_MMU_TAG_INITIALIZER(3, 0x40010000, MPC55XX_MMU_64K, 0, 1, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(14, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
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MPC55XX_MMU_TAG_INITIALIZER(5, 0x40010000, MPC55XX_MMU_64K, 0, 1, 1, 0),
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/* External Ethernet Controller 64k */
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/* External Ethernet Controller 64k */
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MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
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MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
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#elif defined(MPC55XX_BOARD_MPC5674FEVB)
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#elif defined(MPC55XX_BOARD_MPC5674FEVB)
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@@ -166,8 +166,8 @@ BSP_START_TEXT_SECTION void mpc55xx_start_early(void)
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#if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
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#if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
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mpc55xx_start_cache();
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mpc55xx_start_cache();
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#endif
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#endif
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mpc55xx_start_mmu();
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mpc55xx_start_internal_ram();
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mpc55xx_start_internal_ram();
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mpc55xx_start_mmu();
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mpc55xx_start_mode_change();
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mpc55xx_start_mode_change();
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mpc55xx_start_siu();
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mpc55xx_start_siu();
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mpc55xx_start_ebi_chip_select();
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mpc55xx_start_ebi_chip_select();
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