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Initial submission of gen68340 BSP (should run on a 68349) from

Browse Source 
Geoffroy Montel <g_montel@yahoo.com>.
This commit is contained in:
Joel Sherrill
1998-07-01 22:03:20 +00:00
parent a05de51283
commit 132f19405b
30 changed files with 5826 additions and 0 deletions
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25
c/src/lib/libbsp/m68k/gen68340/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SRCS=README
# someday ...
## We only build the ka9q device driver if HAS_KA9Q was defined
#KA9Q_DRIVER_yes_V = network
#KA9Q_DRIVER = $(KA9Q_DRIVER_$(HAS_KA9Q)_V)
all: $(SRCS)
# wrapup is the one that actually builds and installs the library
# from the individual .rel files built in other directories
SUB_DIRS=include start340 startup clock console timer $(KA9Q_DRIVER) wrapup

83
c/src/lib/libbsp/m68k/gen68340/README Normal file
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#
# $Id$
#
#
# This package requires a version of GCC that supports the `-mcpu32' option.
#
#
# Please send any comments, improvements, or bug reports to:
# Geoffroy Montel
# g_montel@yahoo.com
#
#
# This board support package works both MC68340 and MC68349 systems.
#
# Special console features:
# - support of polled and interrupts mode (both MC68340 and MC68349)
# - support of FIFO FULL mode (only for MC68340, the MC68349 doesn't have any timer, so
# you may write your own timer driver if you have an external one)
#
# The type of the board is automatically recognised in the initialization sequence.
#
# WARNING: there's still no KA9Q driver! I hope it will come in the next RTEMS version!
#
BSP NAME: gen68340
BOARD: Generic 68360 as described in Motorola MC68340 User's Manual
BOARD: Home made MC68340 board
BOARD: Home made MC68349 board
BUS: none
CPU FAMILY: Motorola CPU32
COPROCESSORS: none
MODE: not applicable
DEBUG MONITOR: none (Hardware provides BDM)
PERIPHERALS
===========
TIMERS: two timers
RESOLUTION: one microsecond
SERIAL PORTS: 2 channel on the UART
REAL-TIME CLOCK: yes
DMA: yes
VIDEO: none
SCSI: none
NETWORKING: Ethernet on SCC1.
DRIVER INFORMATION
==================
CLOCK DRIVER:
IOSUPP DRIVER:
SHMSUPP: none
TIMER DRIVER: Timer 1 for timing test suites
Timer 2 for console's FIFO FULL mode
STDIO
=====
PORT: 1
ELECTRICAL:
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
Board description
-----------------
clock rate: 25 MHz
bus width: 16-bit PROM, 32-bit DRAM
ROM: To 1 MByte, 60 nsec (0 wait states), chip select 0
RAM: 1 to 16 MByte DRAM SIMM, 60 nsec (0 wait states), parity or nonparity
Host System
-----------
Cygwin 32
Verification (Standalone 68360)
-------------------------------
Single processor tests: Passed
Multi-processort tests: not applicable

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c/src/lib/libbsp/m68k/gen68340/bsp_specs Normal file
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%rename cpp old_cpp
%rename lib old_lib
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*cpp:
%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded)
*lib:
%{!qrtems: %(old_lib)} %{qrtems: --start-group \
%{!qrtems_debug: -lrtemsall} %{qrtems_debug: -lrtemsall_g} \
-lc -lgcc --end-group \
%{!qnolinkcmds: -T linkcmds%s}}
*startfile:
%{!qrtems: %(old_startfile)} %{qrtems: \
%{!qrtems_debug: start340.o%s} \
%{qrtems_debug: start340_g.o%s}}
*link:
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e start}

54
c/src/lib/libbsp/m68k/gen68340/clock/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGM=${ARCH}/clock.rel
# C source names, if any, go here -- minus the .c
C_PIECES=ckinit
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
SRCS=$(C_FILES) $(H_FILES)
OBJS=$(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${SRCS} ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(PGM)
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
install: all

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c/src/lib/libbsp/m68k/gen68340/clock/ckinit.c Normal file
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/*
* This routine initializes the MC68340/349 Periodic Interval Timer
*
* Based on the `gen68360' board support package, and covered by the
* original distribution terms.
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* $Id$
*/
/*
* Input parameters: NONE
*
* Output parameters: NONE
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*/
#include <stdlib.h> /* for atexit() */
#include <bsp.h>
#include <rtems/libio.h>
#include <m68340.h>
#define CLOCK_VECTOR 120 /* clock isr routine vector in the vbr */
#define CLOCK_IRQ_LEVEL 6 /* clock isr level */
/*
* Clock_driver_ticks is a monotonically increasing counter of the
* number of clock ticks since the driver was initialized.
*/
volatile rtems_unsigned32 Clock_driver_ticks;
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
/*
* Periodic interval timer interrupt handler
*/
/******************************************************
Name: Clock_isr
Input parameters: irq vector
Output parameters: none
Description: update # of clock ticks
*****************************************************/
rtems_isr
Clock_isr (rtems_vector_number vector)
{
/*
* Announce the clock tick
*/
Clock_driver_ticks++;
rtems_clock_tick();
}
/******************************************************
Name: clock_exit
Input parameters: -
Output parameters: -
Description: turn off periodic time at shutdown
*****************************************************/
void
Clock_exit (void)
{
if (BSP_Configuration.ticks_per_timeslice ) {
/*
* Turn off periodic interval timer
*/
SIMPITR = 0;
}
}
/******************************************************
Name: Install_clock
Input parameters: the Clock Interrupt Subroutine
Output parameters: -
Description: initialize the periodic interval ticker
called by Clock_Initialize
*****************************************************/
static void
Install_clock (rtems_isr_entry clock_isr)
{
unsigned32 pitr_tmp;
Clock_driver_ticks = 0;
if ( BSP_Configuration.ticks_per_timeslice ) {
set_vector (clock_isr, CLOCK_VECTOR, 1);
/* sets the Periodic Interrupt Control Register PICR */
/* voir a quoi correspond exactement le Clock Vector */
SIMPICR = ( CLOCK_IRQ_LEVEL << 8 ) | ( CLOCK_VECTOR );
/* sets the PITR count value */
/* this assumes a 32.765 kHz crystal */
/* find out whether prescaler should be enabled or not */
if ( BSP_Configuration.microseconds_per_tick <= 31128 ) {
pitr_tmp = ( BSP_Configuration.microseconds_per_tick * 8192 ) / 1000000 ;
}
else {
pitr_tmp = ( BSP_Configuration.microseconds_per_tick / 1000000 ) * 16;
/* enable it */
pitr_tmp |= 0x100;
}
SIMPITR = (unsigned char) pitr_tmp;
atexit (Clock_exit);
}
}
/******************************************************
Name: Clock_initialize
Input parameters: major & minor numbers
Output parameters: -
Description: main entry for clock initialization
calls the bsp dependant routine
*****************************************************/
rtems_device_driver
Clock_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
Install_clock (Clock_isr);
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
/******************************************************
Name: Clock_control
Input parameters: major & minor number
Output parameters:
Description:
*****************************************************/
rtems_device_driver Clock_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
rtems_unsigned32 isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args) {
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' ')) {
Clock_isr( CLOCK_VECTOR);
}
else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) {
rtems_interrupt_disable( isrlevel );
(void) set_vector( args->buffer, CLOCK_VECTOR, 1 );
rtems_interrupt_enable( isrlevel );
}
}
return RTEMS_SUCCESSFUL;
}

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c/src/lib/libbsp/m68k/gen68340/console/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGM=${ARCH}/console.rel
# C source names, if any, go here -- minus the .c
C_PIECES=console m340uart
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
# Assembly source names, if any, go here -- minus the .s
S_PIECES=Modif_cpu_asm
S_FILES=$(S_PIECES:%=%.s)
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
SRCS=$(C_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${SRCS} ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(PGM)
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
install: all

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c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s Normal file
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/* cpu_asm.s
*
* This file contains all assembly code for the MC68020 implementation
* of RTEMS.
*
* ATTENTION: Modified for benchmarks
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <asm.h>
.text
/*PAGE
* void _Debug_ISR_Handler_Console()
*
* This routine provides the RTEMS interrupt management.
*
* NOTE:
* Upon entry, the master stack will contain an interrupt stack frame
* back to the interrupted thread and the interrupt stack will contain
* a throwaway interrupt stack frame. If dispatching is enabled, this
* is the outer most interrupt, and (a context switch is necessary or
* the current thread has signals), then set up the master stack to
* transfer control to the interrupt dispatcher.
* NOTE:
* USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE
* CS5 - CS8 are linked to an oscilloscope so that you can mesure
* RTEMS overhead (BTW it's very short :) )
*/
/*
* With this approach, lower priority interrupts may
* execute twice if a higher priority interrupt is
* acknowledged before _Thread_Dispatch_disable is
* increamented and the higher priority interrupt
* preforms a context switch after executing. The lower
* priority intterrupt will execute (1) at the end of the
* higher priority interrupt in the new context if
* permitted by the new interrupt level mask, and (2) when
* the original context regains the cpu.
*/
#if ( M68K_HAS_VBR == 1)
.set SR_OFFSET, 0 | Status register offset
.set PC_OFFSET, 2 | Program Counter offset
.set FVO_OFFSET, 6 | Format/vector offset
#else
.set SR_OFFSET, 2 | Status register offset
.set PC_OFFSET, 4 | Program Counter offset
.set FVO_OFFSET, 0 | Format/vector offset placed in the stack
#endif /* M68K_HAS_VBR */
.set SAVED, 16 | space for saved registers
.align 4
.global SYM (_Debug_ISR_Handler_Console)
SYM (_Debug_ISR_Handler_Console):
|
tst.w 0x14000000 | ALLUME CS5
|
addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1
movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
andl #0x0fff,d0 | d0 = vector offset in vbr
#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
movew sr,d1 | Save status register
oriw #0x700,sr | Disable interrupts
tstl SYM (_ISR_Nest_level) | Interrupting an interrupt handler?
bne 1f | Yes, just skip over stack switch code
movel SYM(_CPU_Interrupt_stack_high),a0 | End of interrupt stack
movel a7,a0@- | Save task stack pointer
movel a0,a7 | Switch to interrupt stack
1:
addql #1,SYM(_ISR_Nest_level) | one nest level deeper
movew d1,sr | Restore status register
#else
addql #1,SYM (_ISR_Nest_level) | one nest level deeper
#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
#if ( M68K_HAS_PREINDEXING == 1 )
movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
#else
movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table
addal d0,a0 | a0 = address of vector
movel (a0),a0 | a0 = address of user routine
#endif
lsrl #2,d0 | d0 = vector number
movel d0,a7@- | push vector number
|
tst.w 0x18000000 | ALLUME CS6
|
jbsr a0@ | invoke the user ISR
|
tst.w 0x18000000 | ALLUME CS6
|
addql #4,a7 | remove vector number
#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
movew sr,d0 | Save status register
oriw #0x700,sr | Disable interrupts
subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count
bne 1f | Skip if return to interrupt
movel (a7),a7 | Restore task stack pointer
1:
movew d0,sr | Restore status register
#else
subql #1,SYM (_ISR_Nest_level) | one less nest level
#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
subql #1,SYM (_Thread_Dispatch_disable_level)
| unnest multitasking
bne Debug_exit | If dispatch disabled, Debug_exit
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
movew #0xf000,d0 | isolate format nibble
andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO
cmpiw #0x1000,d0 | is it a throwaway isf?
bne Debug_exit | NOT outer level, so branch
#endif
tstl SYM (_Context_Switch_necessary)
| Is thread switch necessary?
bne bframe | Yes, invoke dispatcher
tstl SYM (_ISR_Signals_to_thread_executing)
| signals sent to Run_thread
| while in interrupt handler?
beq Debug_exit | No, then Debug_exit
bframe: clrl SYM (_ISR_Signals_to_thread_executing)
| If sent, will be processed
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
movec msp,a0 | a0 = master stack pointer
movew #0,a0@- | push format word
movel # SYM (_ISR_Dispatch),a0@- | push return addr
| filter out the trace bit to stop single step debugging breaking
movew a0@(6+SR_OFFSET),d0
andw #0x7FFF,d0
movew d0,a0@- | push thread sr
movec a0,msp | set master stack pointer
#else
| filter out the trace bit to stop single step debugging breaking
movew a7@(16+SR_OFFSET),d0
andw #0x7FFF,d0
movew d0,sr
jsr SYM (_Thread_Dispatch)
#endif
Debug_exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1
#if ( M68K_HAS_VBR == 0 )
addql #2,a7 | pop format/id
#endif /* M68K_HAS_VBR */
|
tst.w 0x1C000000 | ALLUME CS7
|
rte | return to thread
| OR _Isr_dispatch

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c/src/lib/libbsp/m68k/gen68340/console/console.c Normal file
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/*
* 68340/68349 console serial I/O.
*
* Author:
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <termios.h>
#include <bsp.h>
#include <rtems/libio.h>
#include <m68340.h>
#include <m340uart.h>
#include <m340timer.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
#define CONSOLE_VECTOR 121
#define CONSOLE_IRQ_LEVEL 3
#define CONSOLE_INTERRUPT_ARBITRATION 2
static void *ttypA; /* to remember which tty has been opened on channel A
used when interrupts are enabled */
static void *ttypB; /* to remember which tty has been opened on channel B
used when interrupts are enabled */
unsigned char DUIER_mirror = 0 ; /* reflects the state of IER register, which is Write Only */
unsigned char Error_Status_A = 0; /* error status on Channel A */
unsigned char Error_Status_B = 0; /* error status on Channel A */
/*
* Device-specific routines
*/
#define USE_INTERRUPTS_A (m340_uart_config[UART_CHANNEL_A].mode==UART_INTERRUPTS)
#define USE_INTERRUPTS_B (m340_uart_config[UART_CHANNEL_B].mode==UART_INTERRUPTS)
#define CHANNEL_ENABLED_A m340_uart_config[UART_CHANNEL_A].enable
#define CHANNEL_ENABLED_B m340_uart_config[UART_CHANNEL_B].enable
#define set_DUIER(a) DUIER_mirror |= (a); DUIER = DUIER_mirror
#define unset_DUIER(a) DUIER_mirror &= ~(a); DUIER = DUIER_mirror
#define Enable_Interrupts_Tx_A if (USE_INTERRUPTS_A) set_DUIER(m340_TxRDYA)
#define Disable_Interrupts_Tx_A if (USE_INTERRUPTS_A) unset_DUIER(m340_TxRDYA)
#define Enable_Interrupts_Tx_B if (USE_INTERRUPTS_B) set_DUIER(m340_TxRDYB)
#define Disable_Interrupts_Tx_B if (USE_INTERRUPTS_B) unset_DUIER(m340_TxRDYB)
/******************************************************
Name: erreur
Input parameters: string
Output parameters: -
Description: small error routine :)
*****************************************************/
static void erreur (char * string)
{
fprintf(stderr, string);
}
/******************************************************
Name: InterruptHandler
Input parameters: vector number
Output parameters: -
Description: UART ISR Routine, called by _RTEMS_ISR
*****************************************************/
rtems_isr
InterruptHandler (rtems_vector_number v)
{
char ch;
/*****************************************************************************
** CHANNEL A **
*****************************************************************************/
/* check Received Break*/
if (DUSRA & m340_RB) {
Error_Status_A |= m340_RB;
/* reset error status */
DUCRA = m340_Reset_Error_Status;
}
/* buffer received ? */
if (DUSRA & m340_Rx_RDY) {
do {
/* error encountered? */
if (DUSRA & (m340_OE | m340_PE | m340_FE | m340_RB)) {
Error_Status_A |= DUSRA;
/* reset error status */
DUCRA = m340_Reset_Error_Status;
/* all the characters in the queue may not be good */
while (DUSRA & m340_Rx_RDY)
/* push them in a trash */
ch = DURBA;
}
else {
/* this is necessary, otherwise it blocks when FIFO is full */
ch = DURBA;
rtems_termios_enqueue_raw_characters(ttypA,&ch,1);
}
} while (DUSRA & m340_Rx_RDY);
Restart_Fifo_Full_A_Timer(); /* only if necessary (pointer to a fake function if
not in FIFO full mode) */
}
else /* if no character has been received */
Restart_Check_A_Timer(); /* same remark */
/* ready to accept a character ? */
if (DUISR & DUIER_mirror & m340_TxRDYA) {
Disable_Interrupts_Tx_A;
/* one character has been transmitted */
rtems_termios_dequeue_characters(ttypA,1);
}
/*****************************************************************************
** CHANNEL B **
*****************************************************************************/
/* check Received Break*/
if (DUSRB & m340_RB) {
Error_Status_B |= m340_RB;
/* reset error status */
DUCRB = m340_Reset_Error_Status;
}
/* buffer received ? */
if (DUSRB & m340_Rx_RDY) {
do {
if (DUSRB & (m340_OE | m340_PE | m340_FE | m340_RB)) {
Error_Status_B |= DUSRB;
/* reset error status */
DUCRB = m340_Reset_Error_Status;
/* all the characters in the queue may not be good */
while (DUSRB & m340_Rx_RDY)
/* push them in a trash */
ch = DURBB;
}
else {
ch = DURBB;
rtems_termios_enqueue_raw_characters(ttypB,&ch,1);
}
} while (DUSRB & m340_Rx_RDY);
Restart_Fifo_Full_B_Timer();
}
else /* if no character has been received */
Restart_Check_B_Timer();
/* ready to accept a character ? */
if (DUISR & DUIER_mirror & m340_TxRDYB) {
Disable_Interrupts_Tx_B;
/* one character has been transmitted */
rtems_termios_dequeue_characters(ttypB,1);
}
}
/******************************************************
Name: InterruptWrite
Input parameters: minor = channel, pointer to buffer,
and length of buffer to transmit
Output parameters: -
Description: write the first character of buf only
may be called by either console_write
or rtems_termios_enqueue_raw_characters
*****************************************************/
static int
InterruptWrite (int minor, const char *buf, int len)
{
if (minor==UART_CHANNEL_A) {
if (len>0) (char)DUTBA=*buf;
Enable_Interrupts_Tx_A;
}
else if (minor==UART_CHANNEL_B) {
if (len>0) (char)DUTBB=*buf;
Enable_Interrupts_Tx_B;
}
return 0;
}
/******************************************************
Name: dbug_out_char
Input parameters: channel, character to emit
Output parameters: -
Description: wait for the UART to be ready to emit
a character and send it
*****************************************************/
void dbug_out_char( int minor, int ch )
{
if (minor==UART_CHANNEL_A) {
while (!(DUSRA & m340_Tx_RDY)) continue;
DUTBA=ch;
}
else if (minor==UART_CHANNEL_B) {
while (!(DUSRB & m340_Tx_RDY)) continue;
DUTBB=ch;
}
}
/******************************************************
Name: dbug_in_char
Input parameters: -
Output parameters: received character
Description: return the character in the UART
*****************************************************/
int dbug_in_char( int minor )
{
if (minor==UART_CHANNEL_A) {
return DURBA;
}
else if (minor==UART_CHANNEL_B) {
return DURBB;
}
return 0;
}
/******************************************************
Name: dbug_char_present
Input parameters: channel #
Output parameters: TRUE or FALSE
Description: return whether there's a character
in the receive buffer
*****************************************************/
int dbug_char_present( int minor )
{
if (minor==UART_CHANNEL_A) {
return (DUSRA & m340_Rx_RDY);
}
else if (minor==UART_CHANNEL_B) {
return (DUSRB & m340_Rx_RDY);
}
return 0;
}
/******************************************************
Name: dbugInitialise
Input parameters: -
Output parameters: -
Description: Init the UART
*****************************************************/
static void
dbugInitialise ()
{
t_baud_speed_table uart_config; /* configuration of UARTS */
/*
* Reset Receiver
*/
DUCRA = m340_Reset_Receiver;
DUCRB = m340_Reset_Receiver;
/*
* Reset Transmitter
*/
DUCRA = m340_Reset_Transmitter;
DUCRB = m340_Reset_Transmitter;
/*
* Enable serial module for normal operation, ignore FREEZE, select the crystal clock,
* supervisor/user serial registers unrestricted
* interrupt arbitration at priority CONSOLE_INTERRUPT_ARBITRATION
* WARNING : 8 bits access only on this UART!
*/
DUMCRH = 0x00;
DUMCRL = CONSOLE_INTERRUPT_ARBITRATION;
/*
* Interrupt level register
*/
DUILR = CONSOLE_IRQ_LEVEL;
/* sets the IVR */
DUIVR = CONSOLE_VECTOR;
/* search for a correct m340 uart configuration */
uart_config = Find_Right_m340_UART_Config(m340_uart_config[UART_CHANNEL_A].rx_baudrate,
m340_uart_config[UART_CHANNEL_A].tx_baudrate,
CHANNEL_ENABLED_A,
m340_uart_config[UART_CHANNEL_B].rx_baudrate,
m340_uart_config[UART_CHANNEL_B].tx_baudrate,
CHANNEL_ENABLED_B);
/*****************************************************************************
** CHANNEL A **
*****************************************************************************/
if (CHANNEL_ENABLED_A) {
if (USE_INTERRUPTS_A) {
rtems_isr_entry old_handler;
rtems_status_code sc;
proc_ptr ignored;
extern void _Debug_ISR_Handler_Console(void);
sc = rtems_interrupt_catch (InterruptHandler,
CONSOLE_VECTOR,
&old_handler);
/* uncomment this if you want to pass control to your own ISR handler
it may be usefull to do so to check for performances with an oscilloscope */
/*
_CPU_ISR_install_raw_handler( CONSOLE_VECTOR, _Debug_ISR_Handler_Console, &ignored );
*/
/*
* Interrupt Enable Register
* Enable Interrupts on Channel A Receiver Ready
*/
set_DUIER(m340_RxRDYA);
}
else {
/*
* Disable Interrupts on channel A
*/
unset_DUIER(m340_RxRDYA&m340_TxRDYA);
}
/*
* Change set of baud speeds
* disable input control
*/
/* no good uart configuration ? */
if (uart_config.nb<1) rtems_fatal_error_occurred (-1);
if (uart_config.baud_speed_table[UART_CHANNEL_A].set==1)
DUACR = m340_BRG_Set1;
else
DUACR = m340_BRG_Set2;
/*
* make OPCR an auxiliary function serving the communication channels
*/
DUOPCR = m340_OPCR_Aux;
/* poll the XTAL_RDY bit until it is cleared to ensure that an unstable crystal
input is not applied to the baud rate generator */
while (DUISR & m340_XTAL_RDY) continue;
/*
* Serial Channel Baud Speed
*/
DUCSRA = (uart_config.baud_speed_table[UART_CHANNEL_A].rcs << 4)
| (uart_config.baud_speed_table[UART_CHANNEL_A].tcs);
/*
* Serial Channel Configuration
*/
DUMR1A = m340_uart_config[UART_CHANNEL_A].parity_mode
| m340_uart_config[UART_CHANNEL_A].bits_per_char
| m340_RxRTS;
if (m340_uart_config[UART_CHANNEL_A].rx_mode==UART_FIFO_FULL) DUMR1A |= m340_R_F | m340_ERR;
/*
* Serial Channel Configuration 2
*/
DUMR2A |= m340_normal;
/*
* Enable Channel A: transmitter and receiver
*/
DUCRA = m340_Transmitter_Enable | m340_Receiver_Enable;
} /* channel A enabled */
/*****************************************************************************
** CHANNEL B **
*****************************************************************************/
if (CHANNEL_ENABLED_B) {
/* we mustn't set the console vector twice! */
if ((USE_INTERRUPTS_B && !(CHANNEL_ENABLED_A))
|| (USE_INTERRUPTS_B && CHANNEL_ENABLED_A && !USE_INTERRUPTS_A)) {
rtems_isr_entry old_handler;
rtems_status_code sc;
proc_ptr ignored;
extern void _Debug_ISR_Handler_Console(void);
sc = rtems_interrupt_catch (InterruptHandler,
CONSOLE_VECTOR,
&old_handler);
/* uncomment this if you want to pass control to your own ISR handler
it may be usefull to do so to check for performances with an oscilloscope */
/*
_CPU_ISR_install_raw_handler( CONSOLE_VECTOR, _Debug_ISR_Handler_Console, &ignored );
*/
/*
* Interrupt Enable Register
* Enable Interrupts on Channel A Receiver Ready
*/
set_DUIER(m340_RxRDYB);
}
else {
/*
* Disable Interrupts on channel B
*/
unset_DUIER(m340_RxRDYB&m340_TxRDYB);
}
/*
* Change set of baud speeds
* disable input control
*/
/* no good uart configuration ? */
if (uart_config.nb<2) rtems_fatal_error_occurred (-1);
/* don't set DUACR twice! */
if (!CHANNEL_ENABLED_A)
if (uart_config.baud_speed_table[UART_CHANNEL_B].set==1) DUACR = m340_BRG_Set1;
else DUACR = m340_BRG_Set2;
/*
* make OPCR an auxiliary function serving the communication channels
*/
if (!CHANNEL_ENABLED_A) DUOPCR = m340_OPCR_Aux;
/* poll the XTAL_RDY bit until it is cleared to ensure that an unstable crystal
input is not applied to the baud rate generator */
while (DUISR & m340_XTAL_RDY) continue;
/*
* Serial Channel Baud Speed
*/
DUCSRB = (uart_config.baud_speed_table[UART_CHANNEL_B].rcs << 4)
| (uart_config.baud_speed_table[UART_CHANNEL_B].tcs);
/*
* Serial Channel Configuration
*/
DUMR1B = m340_uart_config[UART_CHANNEL_B].parity_mode
| m340_uart_config[UART_CHANNEL_B].bits_per_char
| m340_RxRTS;
if (m340_uart_config[UART_CHANNEL_B].rx_mode==UART_FIFO_FULL) DUMR1B |= m340_R_F | m340_ERR;
/*
* Serial Channel Configuration 2
*/
DUMR2B |= m340_normal;
/*
* Enable Channel A: transmitter and receiver
*/
DUCRB = m340_Transmitter_Enable | m340_Receiver_Enable;
} /* channel B enabled */
}
/******************************************************
Name: SetAttributes
Input parameters: termios structure, channel
Output parameters: -
Description: return whether there's a character
in the receive buffer
TO DO: add the channel # to check for!!
*****************************************************/
static void
SetAttributes (struct termios *t, int minor)
{
rtems_interrupt_level level;
float ispeed, ospeed;
int isp, osp;
/* output speed */
if (t->c_cflag & CBAUDEX)
osp = (t->c_cflag & CBAUD) + CBAUD + 1;
else
osp = t->c_cflag & CBAUD;
/* input speed */
isp = (t->c_cflag / (CIBAUD / CBAUD)) & CBAUD;
/* convert it */
ispeed = termios_baud_rates_equivalence(isp);
ospeed = termios_baud_rates_equivalence(osp);
if (ispeed || ospeed) {
/* update config table */
m340_uart_config[UART_CHANNEL_A].rx_baudrate = ((minor==UART_CHANNEL_A)&&(ispeed!=0)) ? ispeed : m340_uart_config[UART_CHANNEL_A].rx_baudrate;
m340_uart_config[UART_CHANNEL_A].tx_baudrate = ((minor==UART_CHANNEL_A)&&(ospeed!=0)) ? ospeed : m340_uart_config[UART_CHANNEL_A].tx_baudrate;
m340_uart_config[UART_CHANNEL_B].rx_baudrate = ((minor==UART_CHANNEL_B)&&(ispeed!=0)) ? ispeed : m340_uart_config[UART_CHANNEL_B].rx_baudrate;
m340_uart_config[UART_CHANNEL_B].tx_baudrate = ((minor==UART_CHANNEL_B)&&(ospeed!=0)) ? ospeed : m340_uart_config[UART_CHANNEL_B].tx_baudrate;
}
/* change parity */
if (t->c_cflag & PARENB) {
if (t->c_cflag & PARODD) m340_uart_config[minor].parity_mode = m340_Odd_Parity;
else m340_uart_config[minor].parity_mode = m340_Even_Parity;
}
/* change bits per character */
if (t->c_cflag & CSIZE) {
switch (t->c_cflag & CSIZE) {
default: break;
case CS5: m340_uart_config[minor].bits_per_char = m340_5bpc; break;
case CS6: m340_uart_config[minor].bits_per_char = m340_6bpc; break;
case CS7: m340_uart_config[minor].bits_per_char = m340_7bpc; break;
case CS8: m340_uart_config[minor].bits_per_char = m340_8bpc; break;
}
}
/* if serial module configuration has been changed */
if (t->c_cflag & (CBAUD | CIBAUD | CSIZE | PARENB)) {
rtems_interrupt_disable(level);
/* reinit the UART */
dbugInitialise();
rtems_interrupt_enable (level);
}
}
/******************************************************
Name: console_atexit
Input parameters: -
Output parameters: -
Description: called at program termination.
TO DO: add a TERMIOS routine to wait for all the
characters to be transmitted
*****************************************************/
void console_atexit(void)
{
if ((CHANNEL_ENABLED_A && USE_INTERRUPTS_A) || (CHANNEL_ENABLED_B && USE_INTERRUPTS_B))
{
/* should do a drain output but the function is static
and we do not have a table holding all the file descriptors */
/* just loop, I don't mind not to shutdown the executive */
while (1) continue;
}
}
/******************************************************
Name: console_reserve_resources
Input parameters: -
Output parameters: -
Description: Reserve resources consumed by this driver
*****************************************************/
void console_reserve_resources(
rtems_configuration_table *configuration
)
{
rtems_termios_reserve_resources (configuration, 1);
}
/******************************************************
Name: console_initialize
Input parameters: MAJOR # of console_driver,
minor is always 0,
args are always NULL
Output parameters: -
Description: Reserve resources consumed by this driver
TODO: We should pass m340_uart_config table in arg
*****************************************************/
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code status;
int i;
/*
* Set up console driver needs for program termination
*/
atexit(console_atexit);
/*
* Set up TERMIOS
*/
rtems_termios_initialize ();
/*
* Do device-specific initialization
*/
Init_UART_Table();
dbugInitialise ();
Fifo_Full_Timer_initialize();
/*
* Register the devices
*/
for (i=0; i<UART_NUMBER_OF_CHANNELS; i++) {
if (m340_uart_config[i].enable) {
status = rtems_io_register_name (m340_uart_config[i].name, major, i);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred (status);
}
}
return RTEMS_SUCCESSFUL;
}
/******************************************************
Name: console_open
Input parameters: channel #, arg
Output parameters: -
Description: open the device
*****************************************************/
rtems_device_driver console_open(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
rtems_status_code sc = 0;
static const rtems_termios_callbacks intrCallbacks = {
NULL, /* firstOpen */
NULL, /* lastClose */
NULL, /* pollRead */
InterruptWrite, /* write */
SetAttributes, /* setAttributes */
NULL, /* stopRemoteTx */
NULL, /* startRemoteTx */
1 /* outputUsesInterrupts */
};
static const rtems_termios_callbacks pollCallbacks = {
NULL, /* firstOpen */
NULL, /* lastClose */
dbugRead, /* pollRead */
dbugWrite, /* write */
SetAttributes, /* setAttributes */
NULL, /* stopRemoteTx */
NULL, /* startRemoteTx */
0 /* outputUsesInterrupts */
};
if (minor==UART_CHANNEL_A) {
if (USE_INTERRUPTS_A) {
rtems_libio_open_close_args_t *args = arg;
sc |= rtems_termios_open (major, minor, arg, &intrCallbacks);
ttypA = args->iop->data1;
}
else {
sc |= rtems_termios_open (major, minor, arg, &pollCallbacks);
}
}
else if (minor==UART_CHANNEL_B) {
if (USE_INTERRUPTS_B) {
rtems_libio_open_close_args_t *args = arg;
sc |= rtems_termios_open (major, minor, arg, &intrCallbacks);
ttypB = args->iop->data1;
}
else {
sc |= rtems_termios_open (major, minor, arg, &pollCallbacks);
}
}
else return RTEMS_INVALID_NUMBER;
return sc;
}
/******************************************************
Name: console_close
Input parameters: channel #, termios args
Output parameters: -
Description: close the device
*****************************************************/
rtems_device_driver console_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_close (arg);
}
/******************************************************
Name: console_read
Input parameters: channel #, termios args
Output parameters: -
Description: read the device
*****************************************************/
rtems_device_driver console_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_read (arg);
}
/******************************************************
Name: console_write
Input parameters: channel #, termios args
Output parameters: -
Description: write to the device
*****************************************************/
rtems_device_driver console_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_write (arg);
}
/******************************************************
Name: console_control
Input parameters: channel #, termios args
Output parameters: -
Description: Handle ioctl request
*****************************************************/
rtems_device_driver console_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
rtems_libio_ioctl_args_t *args = arg;
if (args->command == RTEMS_IO_SET_ATTRIBUTES)
SetAttributes ((struct termios *)args->buffer, minor);
return rtems_termios_ioctl (arg);
}

409
c/src/lib/libbsp/m68k/gen68340/console/m340uart.c Normal file
View File

@@ -0,0 +1,409 @@
/*
* M68340/349 uart management tools
*
* Author:
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <termios.h>
#include <bsp.h>
#include <rtems/libio.h>
#include <m68340.h>
#include <m340uart.h>
#include <stdarg.h>
/* this table shows compatible speed configurations for the MC68340:
the first row shows baud rates for baud speed set 1
the second row shows baud rates for baud speed set 2
look at Motorola's MC68340 Integrated Processor User's Manual
page 7-30 for more infos */
float m340_Baud_Rates_Table[16][2] = {\
{ 50, 75 }, \
{ 110, 110 }, \
{ 134.5, 134.5 }, \
{ 200, 150 }, \
{ 300, 300 }, \
{ 600, 600 }, \
{ 1200, 1200 }, \
{ 1050, 2000 }, \
{ 2400, 2400 }, \
{ 4800, 4800 }, \
{ 7200, 1800 }, \
{ 9600, 9600 }, \
{ 38400, 19200 }, \
{ 76800, 38400 }, \
{ SCLK/16, SCLK/16}, \
{ SCLK, SCLK }, \
};
/* config on both 340 channels */
uart_channel_config m340_uart_config[UART_NUMBER_OF_CHANNELS];
/*
* Init UART table
*/
#define NOT_IMPLEMENTED_YET 0
/******************************************************
Name: Init_UART_Table
Input parameters: -
Output parameters: -
Description: Init the m340_uart_config
THIS SHOULD NOT BE HERE!
Its aim was to let the user configure
UARTs for each application.
As we can't pass args to the console
driver initialisation routine at the
moment, this was not done.
ATTENTION: TERMIOS init presupposes that the channel
baud rates is 9600/9600.
-> risks when using IOCTL
*****************************************************/
void Init_UART_Table(void)
{
m340_uart_config[UART_CHANNEL_A].enable = TRUE;
strcpy(m340_uart_config[UART_CHANNEL_A].name, UART_CONSOLE_NAME);
m340_uart_config[UART_CHANNEL_A].parity_mode = m340_No_Parity;
m340_uart_config[UART_CHANNEL_A].bits_per_char = m340_8bpc;
m340_uart_config[UART_CHANNEL_A].rx_baudrate = 9600;
m340_uart_config[UART_CHANNEL_A].tx_baudrate = 9600;
m340_uart_config[UART_CHANNEL_A].rx_mode = UART_CRR;
m340_uart_config[UART_CHANNEL_A].mode = UART_POLLING;
m340_uart_config[UART_CHANNEL_A].termios.enable = TRUE;
m340_uart_config[UART_CHANNEL_A].termios.rx_buffer_size = NOT_IMPLEMENTED_YET;
m340_uart_config[UART_CHANNEL_A].termios.tx_buffer_size = NOT_IMPLEMENTED_YET;
m340_uart_config[UART_CHANNEL_B].enable = FALSE;
strcpy(m340_uart_config[UART_CHANNEL_B].name, UART_RAW_IO_NAME);
m340_uart_config[UART_CHANNEL_B].parity_mode = m340_No_Parity;
m340_uart_config[UART_CHANNEL_B].bits_per_char = m340_8bpc;
m340_uart_config[UART_CHANNEL_B].rx_baudrate = 38400;
m340_uart_config[UART_CHANNEL_B].tx_baudrate = 38400;
m340_uart_config[UART_CHANNEL_B].rx_mode = UART_CRR;
m340_uart_config[UART_CHANNEL_B].mode = UART_INTERRUPTS;
m340_uart_config[UART_CHANNEL_B].termios.enable = TRUE;
m340_uart_config[UART_CHANNEL_B].termios.rx_buffer_size = NOT_IMPLEMENTED_YET;
m340_uart_config[UART_CHANNEL_B].termios.tx_buffer_size = NOT_IMPLEMENTED_YET;
}
/******************************************************
Name: Find_Right_m340_UART_Channel_Config
Input parameters: Send/Receive baud rates for a
given channel
Output parameters: UART compatible configs for this
channel
Description: returns which uart configurations fit
Receiver Baud Rate and Transmitter Baud
Rate for a given channel
For instance, according to the
m340_Baud_Rates_Table:
- Output Speed = 50, Input Speed = 75
is not a correct config, because
50 bauds implies set 1 and 75 bauds
implies set 2
- Output Speed = 9600, Input Speed = 9600
two correct configs for this:
RCS=11, TCS=11, Set=1 or 2
*****************************************************/
t_baud_speed_table
Find_Right_m340_UART_Channel_Config(float ReceiverBaudRate, float TransmitterBaudRate)
{
t_baud_speed_table return_value;
struct {
int cs;
int set;
} Receiver[2], Transmitter[2];
int Receiver_nb_of_config = 0;
int Transmitter_nb_of_config = 0;
int i,j;
/* Receiver and Transmitter baud rates must be compatible, ie in the same set */
/* search for configurations for ReceiverBaudRate - there can't be more than two (only two sets) */
for (i=0;i<16;i++)
for (j=0;j<2;j++)
if (m340_Baud_Rates_Table[i][j]==ReceiverBaudRate) {
Receiver[Receiver_nb_of_config].cs=i;
Receiver[Receiver_nb_of_config].set=j;
Receiver_nb_of_config++;
}
/* search for configurations for TransmitterBaudRate - there can't be more than two (only two sets) */
for (i=0;i<16;i++)
for (j=0;j<2;j++)
if (m340_Baud_Rates_Table[i][j]==TransmitterBaudRate) {
Transmitter[Transmitter_nb_of_config].cs=i;
Transmitter[Transmitter_nb_of_config].set=j;
Transmitter_nb_of_config++;
}
/* now check if there's a compatible config */
return_value.nb=0;
for (i=0; i<Receiver_nb_of_config; i++)
for (j=0;j<Transmitter_nb_of_config;j++)
if (Receiver[i].set == Transmitter[j].set) {
return_value.baud_speed_table[return_value.nb].set = Receiver[i].set + 1; /* we want set 1 or set 2, not 0 or 1 */
return_value.baud_speed_table[return_value.nb].rcs = Receiver[i].cs;
return_value.baud_speed_table[return_value.nb].tcs = Transmitter[j].cs;
return_value.nb++;
}
return return_value;
}
/******************************************************
Name: Find_Right_m340_UART_Config
Input parameters: Send/Receive baud rates for both
channels
Output parameters: UART compatible configs for
BOTH channels
Description: returns which uart configurations fit
Receiver Baud Rate and Transmitter Baud
Rate for both channels
For instance, if we want 9600/38400 on
channel A and 9600/19200 on channel B,
this is not a good m340 uart config
(channel A needs set 1 and channel B
needs set 2)
*****************************************************/
t_baud_speed_table
Find_Right_m340_UART_Config(float ChannelA_ReceiverBaudRate, float ChannelA_TransmitterBaudRate, rtems_unsigned8 enableA,
float ChannelB_ReceiverBaudRate, float ChannelB_TransmitterBaudRate, rtems_unsigned8 enableB)
{
t_baud_speed_table tableA, tableB;
t_baud_speed_table return_value, tmp;
int i,j;
return_value.nb=0;
if (enableA && enableB) {
tableA = Find_Right_m340_UART_Channel_Config(ChannelA_ReceiverBaudRate, ChannelA_TransmitterBaudRate);
tableB = Find_Right_m340_UART_Channel_Config(ChannelB_ReceiverBaudRate, ChannelB_TransmitterBaudRate);
for (i=0;i<tableA.nb;i++)
for (j=0;j<tableB.nb;j++)
if (tableA.baud_speed_table[i].set==tableB.baud_speed_table[j].set) {
return_value.baud_speed_table[UART_CHANNEL_A].set=tableA.baud_speed_table[i].set;
return_value.baud_speed_table[UART_CHANNEL_A].rcs=tableA.baud_speed_table[i].rcs;
return_value.baud_speed_table[UART_CHANNEL_A].tcs=tableA.baud_speed_table[i].tcs;
return_value.baud_speed_table[UART_CHANNEL_B].set=tableB.baud_speed_table[j].set;
return_value.baud_speed_table[UART_CHANNEL_B].rcs=tableB.baud_speed_table[j].rcs;
return_value.baud_speed_table[UART_CHANNEL_B].tcs=tableB.baud_speed_table[j].tcs;
return_value.nb=2;
break;
}
return return_value;
}
if (enableA) {
return_value = Find_Right_m340_UART_Channel_Config(ChannelA_ReceiverBaudRate, ChannelA_TransmitterBaudRate);
return return_value;
}
if (enableB) {
tmp = Find_Right_m340_UART_Channel_Config(ChannelB_ReceiverBaudRate, ChannelB_TransmitterBaudRate);
if (tmp.nb!=0) {
return_value.nb = 2;
return_value.baud_speed_table[1].set = tmp.baud_speed_table[0].set;
return_value.baud_speed_table[1].rcs = tmp.baud_speed_table[0].rcs;
return_value.baud_speed_table[1].tcs = tmp.baud_speed_table[0].tcs;
}
}
return return_value;
}
/******************************************************
Name: termios_baud_rates_equivalence
Input parameters: Termios coded speed
Output parameters: explicit speed
Description: ioctl calls return termios coded speed
we need to know real speed in order
to use the functions above
*****************************************************/
float termios_baud_rates_equivalence ( int speed )
{
switch (speed) {
default: return 0; break;
case B50: return 50; break;
case B75: return 75; break;
case B110: return 110; break;
case B134: return 134; break;
case B150: return 150; break;
case B200: return 200; break;
case B300: return 300; break;
case B600: return 600; break;
case B1200: return 1200; break;
case B1800: return 1800; break;
case B2400: return 2400; break;
case B4800: return 4800; break;
case B9600: return 9600; break;
case B19200: return 19200; break;
case B38400: return 38400; break;
case B57600: return 57600; break;
case B115200: return 115200; break;
case B230400: return 230400; break;
case B460800: return 460800; break;
}
return 0;
}
/****************************************************************************************************/
/*
* very low level fmted output
*/
extern void dbug_out_char( int minor, int ch );
extern int dbug_in_char( int minor );
extern int dbug_char_present( int minor );
/******************************************************
Name: dbugRead
Input parameters: channel
Output parameters: char read
Description: polled read
*****************************************************/
int dbugRead (int minor)
{
if (dbug_char_present(minor) == 0)
return -1;
return dbug_in_char(minor);
}
/******************************************************
Name: dbugWrite
Input parameters: channel, buffer and its length
Output parameters: always successfull
Description: polled write
*****************************************************/
int dbugWrite (int minor, const char *buf, int len)
{
static char txBuf;
while (len--) {
txBuf = *buf++;
dbug_out_char( minor, (int)txBuf );
}
return 0;
}
static void fmt_num( int minor, unsigned long, unsigned );
static void fmt_str( int minor, const char* );
/******************************************************
Name: RAW_GETC
Input parameters: channel, buffer and its length
Output parameters:
Description: a light blocking "getc"
*****************************************************/
char RAW_GETC(int minor)
{
while (!dbug_char_present(minor)) continue;
return dbug_in_char(minor);
}
/******************************************************
Name: RAW_FMT
Input parameters: channel, buffer and its length
Output parameters: always successfull
Description: a light polled "printf"
useful when there's a serious pb and
there are no more interrupts
*****************************************************/
void RAW_FMT( int minor, const char* fmt, ... )
{
int ch;
va_list va;
va_start( va, fmt );
while( (ch = *fmt++) )
if( ch != '%' || (ch = *fmt++) == '%' )
{
if( ch == '\n' )
dbug_out_char( minor, '\r' );
dbug_out_char( minor, ch );
}
else switch( ch )
{
case 'c':
dbug_out_char( minor, va_arg( va, int ) );
continue;
case 's':
fmt_str( minor, va_arg( va, char* ) );
continue;
case 'd':
ch = va_arg( va, int );
if( ch >= 0 )
fmt_num( minor, ch, 10 );
else
{
dbug_out_char( minor, '-' );
fmt_num( minor, -ch, 10 );
}
continue;
case 'u':
fmt_num( minor, va_arg( va, unsigned ), 10 );
continue;
case 'o':
fmt_num( minor, va_arg( va, unsigned ), 8 );
continue;
case 'x':
case 'p':
fmt_num( minor, va_arg( va, unsigned ), 16 );
continue;
default: continue;
return;
}
va_end( va );
}
static void fmt_num( int minor, unsigned long num, unsigned base )
{
char buf[33];
int ib = sizeof(buf);
buf[--ib] = 0;
do
{
buf[--ib] = "0123456789ABCDEF"[num%base];
num /= base;
}
while( num != 0 );
fmt_str( minor, buf+ib );
}
static void fmt_str( int minor, const char* str )
{
if( str )
while( *str )
dbug_out_char( minor, *str++ );
}

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
H_FILES = $(srcdir)/bsp.h $(srcdir)/coverhd.h $(srcdir)/m340uart.h $(srcdir)/m340timer.h $(srcdir)/m68340.h $(srcdir)/m68340.inc $(srcdir)/m68349.inc
#
# Equate files are for including from assembly preprocessed by
# gm4 or gasp. No examples are provided except for those for
# other CPUs. The best way to generate them would be to
# provide a program which generates the constants used based
# on the C equivalents.
#
EQ_FILES =
SRCS=$(H_FILES) $(EQ_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: $(SRCS)
$(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE)
$(INSTALL) -m 444 $(EQ_FILES) $(PROJECT_INCLUDE)

123
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/*
* Board Support Package for `Generic' Motorola MC68340
*
* Based on the `gen68360' board support package, and covered by the
* original distribution terms.
*
* $Id$
*/
/* bsp.h
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*/
#ifndef __GEN68340_BSP_h
#define __GEN68340_BSP_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems.h>
#include <console.h>
#include <iosupp.h>
#include <clockdrv.h>
/*
* Define the time limits for RTEMS Test Suite test durations.
* Long test and short test duration limits are provided. These
* values are in seconds and need to be converted to ticks for the
* application.
*
*/
#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */
#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */
/*
* Stuff for Time Test 27
* Don't bother with hardware -- just use a software-interrupt
*/
#define MUST_WAIT_FOR_INTERRUPT 0
#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 )
#define Cause_tm27_intr() /* asm volatile ("trap #2"); */
#define Clear_tm27_intr()
#define Lower_tm27_intr()
/*
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*/
#define delay( microseconds ) \
{ register rtems_unsigned32 _delay=(microseconds); \
register rtems_unsigned32 _tmp=123; \
asm volatile( "0: \
nbcd %0 ; \
nbcd %0 ; \
dbf %1,0b" \
: "=d" (_tmp), "=d" (_delay) \
: "0" (_tmp), "1" (_delay) ); \
}
/* Constants */
/* Structures */
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
/*
* How many libio files we want
*/
#define BSP_LIBIO_MAX_FDS 20
/* miscellaneous stuff assumed to exist */
extern rtems_configuration_table BSP_Configuration;
extern m68k_isr_entry M68Kvec[]; /* vector table address */
/* functions */
void bsp_cleanup( void );
m68k_isr_entry set_vector(
rtems_isr_entry handler,
rtems_vector_number vector,
int type
);
/*
* Values assigned by link editor
*/
extern void *_RomBase, *_RamBase;
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/*
* This file was machine-generated from the tmoverhd.exe output
*
* $Id$
*/
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4
#define CALLING_OVERHEAD_TASK_CREATE 8
#define CALLING_OVERHEAD_TASK_IDENT 6
#define CALLING_OVERHEAD_TASK_START 6
#define CALLING_OVERHEAD_TASK_RESTART 5
#define CALLING_OVERHEAD_TASK_DELETE 4
#define CALLING_OVERHEAD_TASK_SUSPEND 4
#define CALLING_OVERHEAD_TASK_RESUME 4
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 6
#define CALLING_OVERHEAD_TASK_MODE 6
#define CALLING_OVERHEAD_TASK_GET_NOTE 6
#define CALLING_OVERHEAD_TASK_SET_NOTE 6
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 12
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4
#define CALLING_OVERHEAD_INTERRUPT_CATCH 6
#define CALLING_OVERHEAD_CLOCK_GET 12
#define CALLING_OVERHEAD_CLOCK_SET 12
#define CALLING_OVERHEAD_CLOCK_TICK 3
#define CALLING_OVERHEAD_TIMER_CREATE 5
#define CALLING_OVERHEAD_TIMER_DELETE 4
#define CALLING_OVERHEAD_TIMER_IDENT 5
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 14
#define CALLING_OVERHEAD_TIMER_RESET 4
#define CALLING_OVERHEAD_TIMER_CANCEL 4
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 7
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 6
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 6
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 6
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 6
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 6
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 6
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 5
#define CALLING_OVERHEAD_EVENT_SEND 6
#define CALLING_OVERHEAD_EVENT_RECEIVE 6
#define CALLING_OVERHEAD_SIGNAL_CATCH 5
#define CALLING_OVERHEAD_SIGNAL_SEND 5
#define CALLING_OVERHEAD_PARTITION_CREATE 8
#define CALLING_OVERHEAD_PARTITION_IDENT 6
#define CALLING_OVERHEAD_PARTITION_DELETE 5
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 6
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 6
#define CALLING_OVERHEAD_REGION_CREATE 8
#define CALLING_OVERHEAD_REGION_IDENT 5
#define CALLING_OVERHEAD_REGION_DELETE 4
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 7
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 6
#define CALLING_OVERHEAD_PORT_CREATE 7
#define CALLING_OVERHEAD_PORT_IDENT 5
#define CALLING_OVERHEAD_PORT_DELETE 5
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 6
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 6
#define CALLING_OVERHEAD_IO_INITIALIZE 6
#define CALLING_OVERHEAD_IO_OPEN 6
#define CALLING_OVERHEAD_IO_CLOSE 6
#define CALLING_OVERHEAD_IO_READ 6
#define CALLING_OVERHEAD_IO_WRITE 6
#define CALLING_OVERHEAD_IO_CONTROL 6
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 5
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 5
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 5
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 5
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3

82
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/*
* Header file for timer driver
* defines for accessing M68340 timer registers
*
* Author:
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __m340timer_H__
#define __m340timer_H__
extern void Fifo_Full_Timer_initialize (void);
extern void (*Restart_Fifo_Full_A_Timer)();
extern void (*Restart_Check_A_Timer)();
extern void (*Restart_Fifo_Full_B_Timer)();
extern void (*Restart_Check_B_Timer)();
/* CR */
#define m340_SWR (1<<15)
#define m340_Polling_Mode (0<<12)
#define m340_TC_Enabled (1<<12)
#define m340_TG_Enabled (2<<12)
#define m340_TG_TC_Enabled (3<<12)
#define m340_TO_Enabled (4<<12)
#define m340_TO_TC_Enabled (5<<12)
#define m340_TG_TG_Enabled (6<<12)
#define m340_TO_TG_TG_Enabled (7<<12)
#define m340_TGE (1<<11)
#define m340_PSE (1<<10)
#define m340_CPE (1<<9)
#define m340_CLK (1<<8)
#define m340_Divide_by_2 (1<<5)
#define m340_Divide_by_4 (2<<5)
#define m340_Divide_by_8 (3<<5)
#define m340_Divide_by_16 (4<<5)
#define m340_Divide_by_32 (5<<5)
#define m340_Divide_by_64 (6<<5)
#define m340_Divide_by_128 (7<<5)
#define m340_Divide_by_256 (0<<5)
#define m340_ICOC (0<<2)
#define m340_SWG (1<<2)
#define m340_VDCSWG (2<<2)
#define m340_VWSSPG (3<<2)
#define m340_PWM (4<<2)
#define m340_PM (5<<2)
#define m340_EC (6<<2)
#define m340_TB (7<<2)
#define m340_Disabled 0
#define m340_Toggle_Mode 1
#define m340_Zero_Mode 2
#define m340_One_Mode 3
/* SR */
#define m340_IRQ (1<<15)
#define m340_TO (1<<14)
#define m340_TG (1<<13)
#define m340_TC (1<<12)
#define m340_TGL (1<<11)
#define m340_ON (1<<10)
#define m340_OUT (1<<9)
#define m340_COM (1<<8)
#endif

159
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/*
* Header file for console driver
* defines for accessing M68340/68349 UART registers
*
* Author:
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __m340uart_H__
#define __m340uart_H__
/* UART initialisation */
#define UART_CHANNEL_A 0
#define UART_CHANNEL_B 1
#define UART_NUMBER_OF_CHANNELS 2
#define UART_CONSOLE_NAME "/dev/console"
#define UART_RAW_IO_NAME "/dev/tty1"
#define UART_FIFO_FULL 0
#define UART_CRR 1
#define UART_INTERRUPTS 0
#define UART_POLLING 1
#define UART_TERMIOS_CONSOLE 0
#define UART_TERMIOS_RAW 1
#define UART_TERMIOS_MIN_DEFAULT 1
#define UART_TERMIOS_TIME_DEFAULT 0
void Init_UART_Table(void);
typedef struct {
rtems_unsigned8 enable;
rtems_unsigned16 rx_buffer_size; /* NOT IMPLEMENTED */
rtems_unsigned16 tx_buffer_size; /* NOT IMPLEMENTED */
} uart_termios_config;
typedef struct { /* for one channel */
rtems_unsigned8 enable; /* use this channel */
char name[64]; /* use UART_CONSOLE_NAME for console purpose */
rtems_unsigned8 parity_mode; /* parity mode, see MR1 section for defines */
rtems_unsigned8 bits_per_char; /* bits per character, see MR1 section for defines */
float rx_baudrate; /* Rx baudrate */
float tx_baudrate; /* Tx baudrate */
rtems_unsigned8 rx_mode; /* FIFO Full (UART_FIFO_FULL) or ChannelReceiverReady (UART_CRR) */
rtems_unsigned8 mode; /* use interrupts (UART_INTERRUPTS) or polling (UART_POLLING) */
uart_termios_config termios;
} uart_channel_config;
extern uart_channel_config m340_uart_config[UART_NUMBER_OF_CHANNELS];
typedef struct {
int set; /* number of the m340 baud speed set */
int rcs; /* RCS for the needed baud set */
int tcs; /* TCS for the needed baud set */
} t_baud_speed;
typedef struct {
t_baud_speed baud_speed_table[2];
short nb;
} t_baud_speed_table;
extern t_baud_speed_table
Find_Right_m340_UART_Config(float ChannelA_ReceiverBaudRate, float ChannelA_TransmitterBaudRate, rtems_unsigned8 enableA,
float ChannelB_ReceiverBaudRate, float ChannelB_TransmitterBaudRate, rtems_unsigned8 enableB);
extern rtems_isr InterruptHandler (rtems_vector_number v);
extern float termios_baud_rates_equivalence ( int speed ) ;
extern int dbugRead (int minor);
extern int dbugWrite (int minor, const char *buf, int len);
extern float m340_Baud_Rates_Table[16][2];
/* SR */
#define m340_Rx_RDY 1
#define m340_FFULL (1<<1)
#define m340_Tx_RDY (1<<2)
#define m340_TxEMP (1<<3)
#define m340_OE (1<<4)
#define m340_PE (1<<5)
#define m340_FE (1<<6)
#define m340_RB (1<<7)
/* IER */
#define m340_TxRDYA 1
#define m340_RxRDYA (1<<1)
#define m340_TxRxRDYA 0x3
#define m340_TxRDYB (1<<4)
#define m340_RxRDYB (1<<5)
#define m340_TxRxRDYB 0x30
/* CR */
#define m340_Reset_Error_Status 0x40
#define m340_Reset_Receiver 0x20
#define m340_Reset_Transmitter 0x30
#define m340_Transmitter_Enable (1<<2)
#define m340_Receiver_Enable 1
#define m340_Transmitter_Disable (2<<2)
#define m340_Receiver_Disable 2
/* ACR */
#define m340_BRG_Set1 0
#define m340_BRG_Set2 (1<<7)
/* OPCR */
#define m340_OPCR_Gal 0x0
#define m340_OPCR_Aux 0xFF
/* ISR */
#define m340_COS (1<<7)
#define m340_DBB (1<<6)
#define m340_XTAL_RDY (1<<3)
#define m340_DBA (1<<2)
/* MR1 */
#define m340_RxRTS (1<<7)
#define m340_R_F (1<<6) /* character or block mode */
#define m340_ERR (1<<5)
#define m340_RxRTX (1<<7)
#define m340_Even_Parity 0
#define m340_Odd_Parity (1<<2)
#define m340_Low_Parity (2<<2)
#define m340_High_Parity (3<<2)
#define m340_No_Parity (4<<2)
#define m340_Data_Character (6<<2)
#define m340_Address_Character (7<<2)
#define m340_5bpc 0x0
#define m340_6bpc 0x1
#define m340_7bpc 0x2
#define m340_8bpc 0x3
/* MR2 */
#define m340_normal (0<<6)
#define m340_automatic_echo (1<<6)
#define m340_local_loopback (2<<6)
#define m340_remote_loopback (3<<6)
#define m340_TxRTS (1<<5)
#define m340_TxCTS (1<<4)
/* Baud rates for Transmitter/Receiver */
#define SCLK 1 /* put your own SCLK value here */
#endif

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/**********************************************************************
* MC68340 C Header File *
* *
* Developed by : Motorola *
* High Performance Embedded Systems Division *
* Austin, TX *
* Rectified by : Geoffroy Montel
* g_montel@yahoo.com *
* *
**********************************************************************/
typedef volatile unsigned char * portb; /* 8-bit port */
typedef volatile unsigned short * portw; /* 16-bit port */
typedef volatile unsigned int * portl; /* 32-bit port */
#define MBASE 0xEFFFF000 /* Module Base Address */
/* not EFFFF000 due to a 68349
hardware incompatibility */
#define MBAR (*(portb) 0x0003FF00) /* Module Base Addr Reg */
#define MBAR1 (*(portb) 0x0003FF00) /* Module Base Addr Reg 1 (MSW) */
#define MBAR2 (*(portb) 0x0003FF02) /* Module Base Addr Reg 2 (LSW) */
/* System Integration Module */
#define SIMMCR (*(portw) (MBASE+0x0000)) /* SIM Module Config Reg */
#define SIMSYNCR (*(portw) (MBASE+0x0004)) /* SIM Clock Synth Cont Reg */
#define SIMAVR (*(portb) (MBASE+0x0006)) /* SIM Autovector Reg */
#define SIMRSR (*(portb) (MBASE+0x0007)) /* SIM Reset Status Reg */
#define SIMPORTA (*(portb) (MBASE+0x0011)) /* SIM Port A Data Reg */
#define SIMDDRA (*(portb) (MBASE+0x0013)) /* SIM Port A Data Dir Reg */
#define SIMPPRA1 (*(portb) (MBASE+0x0015)) /* SIM Port A Pin Asm 1 Reg */
#define SIMPPRA2 (*(portb) (MBASE+0x0017)) /* SIM Port A Pin Asm 2 Reg */
#define SIMPORTB (*(portb) (MBASE+0x0019)) /* SIM Port B Data Reg */
#define SIMPORTB1 (*(portb) (MBASE+0x001B)) /* SIM Port B Data Reg */
#define SIMDDRB (*(portb) (MBASE+0x001D)) /* SIM Port B Data Dir Reg */
#define SIMPPARB (*(portb) (MBASE+0x001F)) /* SIM Port B Pin Asm Reg */
#define SIMSWIV (*(portb) (MBASE+0x0020)) /* SIM SW Interrupt Vector */
#define SIMSYPCR (*(portb) (MBASE+0x0021)) /* SIM System Prot Cont Reg */
#define SIMPICR (*(portw) (MBASE+0x0022)) /* SIM Period Intr Cont Reg */
#define SIMPITR (*(portw) (MBASE+0x0024)) /* SIM Period Intr Tmg Reg */
#define SIMSWSR (*(portb) (MBASE+0x0027)) /* SIM Software Service Reg */
#define SIMCS0AM (*(portl) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk */
#define SIMCS0AM1 (*(portw) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk 1 */
#define SIMCS0AM2 (*(portw) (MBASE+0x0042)) /* SIM Chp Sel 0 Addr Msk 2 */
#define SIMCS0BA (*(portl) (MBASE+0x0044)) /* SIM Chp Sel 0 Base Addr */
#define SIMCS0BA1 (*(portw) (MBASE+0x0044)) /* SIM Chp Sel 0 Bas Addr 1 */
#define SIMCS0BA2 (*(portw) (MBASE+0x0046)) /* SIM Chp Sel 0 Bas Addr 2 */
#define SIMCS1AM (*(portl) (MBASE+0x0048)) /* SIM Chp Sel 1 Adress Msk */
#define SIMCS1AM1 (*(portw) (MBASE+0x0048)) /* SIM Chp Sel 1 Addr Msk 1 */
#define SIMCS1AM2 (*(portw) (MBASE+0x004A)) /* SIM Chp Sel 1 Addr Msk 2 */
#define SIMCS1BA (*(portl) (MBASE+0x004C)) /* SIM Chp Sel 1 Base Addr */
#define SIMCS1BA1 (*(portw) (MBASE+0x004C)) /* SIM Chp Sel 1 Bas Addr 1 */
#define SIMCS1BA2 (*(portw) (MBASE+0x004E)) /* SIM Chp Sel 1 Bas Addr 2 */
#define SIMCS2AM (*(portl) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk */
#define SIMCS2AM1 (*(portw) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk 1 */
#define SIMCS2AM2 (*(portw) (MBASE+0x0052)) /* SIM Chp Sel 2 Addr Msk 2 */
#define SIMCS2BA (*(portl) (MBASE+0x0054)) /* SIM Chp Sel 2 Base Addr */
#define SIMCS2BA1 (*(portw) (MBASE+0x0054)) /* SIM Chp Sel 2 Bas Addr 1 */
#define SIMCS2BA2 (*(portw) (MBASE+0x0056)) /* SIM Chp Sel 2 Bas Addr 2 */
#define SIMCS3AM (*(portl) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk */
#define SIMCS3AM1 (*(portw) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk 1 */
#define SIMCS3AM2 (*(portw) (MBASE+0x005A)) /* SIM Chp Sel 3 Addr Msk 2 */
#define SIMCS3BA (*(portl) (MBASE+0x005C)) /* SIM Chp Sel 3 Base Addr */
#define SIMCS3BA1 (*(portw) (MBASE+0x005C)) /* SIM Chp Sel 3 Bas Addr 1 */
#define SIMCS3BA2 (*(portw) (MBASE+0x005E)) /* SIM Chp Sel 3 Bas Addr 2 */
/* Dynamic Memory Access (DMA) Module */
#define DMAMCR1 (*(portw) (MBASE+0x0780)) /* DMA Module Config Reg 1 */
#define DMAINTR1 (*(portw) (MBASE+0x0784)) /* DMA Interrupt Reg 1 */
#define DMACCR1 (*(portw) (MBASE+0x0788)) /* DMA Channel Cont Reg 1 */
#define DMACSR1 (*(portb) (MBASE+0x078A)) /* DMA Channel Status Reg 1 */
#define DMAFCR1 (*(portb) (MBASE+0x078B)) /* DMA Function Code Reg 1 */
#define DMASAR1 (*(portl) (MBASE+0x078C)) /* DMA DMA Src Addr Reg 1 */
#define DMADAR1 (*(portl) (MBASE+0x0790)) /* DMA Dest Addr Reg 1 */
#define DMABTC1 (*(portb) (MBASE+0x079l)) /* DMA Byte Trans Cnt Reg 1 */
#define DMAMCR2 (*(portw) (MBASE+0x07A0)) /* DMA Module Config Reg 2 */
#define DMAINTR2 (*(portw) (MBASE+0x07A4)) /* DMA Interrupt Reg 2 */
#define DMACCR2 (*(portw) (MBASE+0x07A8)) /* DMA Channel Cont Reg 2 */
#define DMACSR2 (*(portb) (MBASE+0x07AA)) /* DMA Channel Status Reg 2 */
#define DMAFCR2 (*(portb) (MBASE+0x07AB)) /* DMA Function Code Reg 1 */
#define DMASAR2 (*(portl) (MBASE+0x07AC)) /* DMA Source Addr Reg 2 */
#define DMADAR2 (*(portl) (MBASE+0x07B0)) /* DMA Dest Addr Reg 2 */
#define DMABTC2 (*(portb) (MBASE+0x07B4)) /* DMA Byte Trans Cnt Reg 2 */
/* Dual Serial Module */
#define DUMCRH (*(portb) (MBASE+0x0700)) /* DUART Module Config Reg */
#define DUMCRL (*(portb) (MBASE+0x0701)) /* DUART Module Config Reg */
#define DUILR (*(portb) (MBASE+0x0704)) /* DUART Interrupt Level */
#define DUIVR (*(portb) (MBASE+0x0705)) /* DUART Interrupt Vector */
#define DUMR1A (*(portb) (MBASE+0x0710)) /* DUART Mode Reg 1A */
#define DUSRA (*(portb) (MBASE+0x0711)) /* DUART Status Reg A */
#define DUCSRA (*(portb) (MBASE+0x0711)) /* DUART Clock Sel Reg A */
#define DUCRA (*(portb) (MBASE+0x0712)) /* DUART Command Reg A */
#define DURBA (*(portb) (MBASE+0x0713)) /* DUART Receiver Buffer A */
#define DUTBA (*(portb) (MBASE+0x0713)) /* DUART Transmitter Buff A */
#define DUIPCR (*(portb) (MBASE+0x0714)) /* DUART Input Port Chg Reg */
#define DUACR (*(portb) (MBASE+0x0714)) /* DUART Auxiliary Cont Reg */
#define DUISR (*(portb) (MBASE+0x0715)) /* DUART Interrupt Stat Reg */
#define DUIER (*(portb) (MBASE+0x0715)) /* DUART Interrupt Enb Reg */
#define DUMR1B (*(portb) (MBASE+0x0718)) /* DUART Mode Reg 1B */
#define DUSRB (*(portb) (MBASE+0x0719)) /* DUART Status Reg B */
#define DUCSRB (*(portb) (MBASE+0x0719)) /* DUART Clock Sel Reg B */
#define DUCRB (*(portb) (MBASE+0x071A)) /* DUART Command Reg B */
#define DURBB (*(portb) (MBASE+0x071B)) /* DUART Receiver Buffer B */
#define DUTBB (*(portb) (MBASE+0x071B)) /* DUART Transmitter Buff B */
#define DUIP (*(portb) (MBASE+0x071D)) /* DUART Input Port Reg */
#define DUOPCR (*(portb) (MBASE+0x071D)) /* DUART Outp Port Cnt Reg */
#define DUOPBS (*(portb) (MBASE+0x071E)) /* DUART Outp Port Bit Set */
#define DUOPBR (*(portb) (MBASE+0x071F)) /* DUART Outp Port Bit Rst */
#define DUMR2A (*(portb) (MBASE+0x0720)) /* DUART Mode Reg 2A */
#define DUMR2B (*(portb) (MBASE+0x0721)) /* DUART Mode Reg 2B */
/* Dual Timer Module */
#define TMCR1 (*(portw) (MBASE+0x0600)) /* Timer Module Config Reg 1 */
#define TIR1 (*(portw) (MBASE+0x0604)) /* Timer Interrupt Reg 1 */
#define TCR1 (*(portw) (MBASE+0x0606)) /* Timer Control Reg 1 */
#define TSR1 (*(portw) (MBASE+0x0608)) /* Timer Status Reg 1 */
#define TCNTR1 (*(portw) (MBASE+0x060A)) /* Timer Counter Reg 1 */
#define WPREL11 (*(portw) (MBASE+0x060C)) /* Timer Preload 1 Reg 1 */
#define WPREL21 (*(portw) (MBASE+0x060E)) /* Timer Preload 2 Reg 1 */
#define TCOM1 (*(portw) (MBASE+0x0610)) /* Timer Compare Reg 1 */
#define TMCR2 (*(portw) (MBASE+0x0640)) /* Timer Module Config Reg 2 */
#define TIR2 (*(portw) (MBASE+0x0644)) /* Timer Interrupt Reg 2 */
#define TCR2 (*(portw) (MBASE+0x0646)) /* Timer Control Reg 2 */
#define TSR2 (*(portw) (MBASE+0x0648)) /* Timer Status Reg 2 */
#define TCNTR2 (*(portw) (MBASE+0x064A)) /* Timer Counter Reg 2 */
#define WPREL12 (*(portw) (MBASE+0x064C)) /* Timer Preload 1 Reg 2 */
#define WPREL22 (*(portw) (MBASE+0x064E)) /* Timer Preload 2 Reg 2 */
#define TCOM2 (*(portw) (MBASE+0x0650)) /* Timer Compare Reg 2 */

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/*----------------------------------------------------------------------------
* file name: M68340.INC JC RAHUEL CNET/DSM/TAM/CAT
*
* MC68340 BCC Board Support Package
*
* date: 1/12/1993
*
* Copyright 1989, Ready Systems FRANCE
*
* Supports: VRTX32 and RTscope
*
* Related Board: MOTOROLA BCC M68340
*
* Description: EQUATES FOR 68340 DEVICES
*
* Changes:
* - Geoffroy Montel (g_montel@yahoo.com) :
* changed EQU syntax for GNU as
*
*----------------------------------------------------------------------------*/
/************************************************
* ATTENTION: must match defs. in C header file *
************************************************/
/* -- SIM equates -- system integration module */
.equ BASE_REG, 0x3FF00
.equ BASE_SIM, 0xEFFFF000
.equ SIM_MCR, 0x000 /* module configuration register */
.equ SIM_SYNCR, 0x004 /* clock synthesizer control register */
.equ SIM_AVR, 0x006 /* autovector register */
.equ SIM_RSR, 0x007 /* reset status register */
/* -- Port A -- */
.equ SIM_PORTA, 0x011 /* port A data */
.equ SIM_DDRA, 0x013 /* port A direction data */
.equ SIM_PPRA1, 0x015 /* Port A pin assignement 1 */
.equ SIM_PPRA2, 0x017 /* Port A pin assignement 2 */
/* -- Port B -- */
.equ SIM_PORTB, 0x019 /* port B data */
.equ SIM_PORTB1, 0x01B /* port B data auxiliary */
.equ SIM_DDRB, 0x01D /* port B direction data */
.equ SIM_PPRB, 0x01F /* Port B pin assignement */
.equ SIM_SWIV, 0x020 /* SW interrupt vector */
.equ SIM_SYPCR, 0x021 /* System protection control register */
.equ SIM_PICR, 0x022 /* Periodic interrupt control register */
.equ SIM_PITR, 0x024 /* Periodic interrupt timing register */
.equ SIM_SWSR, 0x027 /* Sofware service */
/* -- Chip select -- */
.equ SIM_MASKH0, 0x040 /* mask register CS0 */
.equ SIM_MASKL0, 0x042 /* mask register CS0 */
.equ SIM_ADDRH0, 0x044 /* base address CS0 */
.equ SIM_ADDRL0, 0x046 /* base address CS0 */
.equ SIM_MASKH1, 0x048 /* mask register CS1 */
.equ SIM_MASKL1, 0x04A /* mask register CS1 */
.equ SIM_ADDRH1, 0x04C /* base address CS1 */
.equ SIM_ADDRL1, 0x04E /* base address CS1 */
.equ SIM_MASKH2, 0x050 /* mask register CS2 */
.equ SIM_MASKL2, 0x052 /* mask register CS2 */
.equ SIM_ADDRH2, 0x054 /* base address CS2 */
.equ SIM_ADDRL2, 0x056 /* base address CS2 */
.equ SIM_MASKH3, 0x058 /* mask register CS3 */
.equ SIM_MASKL3, 0x05A /* mask register CS3 */
.equ SIM_ADDRH3, 0x05C /* base address CS3 */
.equ SIM_ADDRL3, 0x05E /* base address CS3 */
/* -- TIMERS equates -- */
/* __ TIMER 0 */
.equ TIM_MCR0, 0x600 /* Module configuration register */
.equ TIM_IR0, 0x604 /* interrupt register */
.equ TIM_CR0, 0x606 /* controle register */
.equ TIM_SR0, 0x608 /* Status/prescaler register */
.equ TIM_CNTR0, 0x60A /* counter register */
.equ TIM_PREL10, 0x60C /* Preload register 1 */
.equ TIM_PREL20, 0x60E /* Preload register 2 */
.equ TIM_COM0, 0x610 /* Compare register */
/* __ TIMER 1 */
.equ TIM_MCR1, 0x640 /* Module configuration register */
.equ TIM_IR1, 0x644 /* interrupt register */
.equ TIM_CR1, 0x646 /* controle register */
.equ TIM_SR1, 0x648 /* Status/prescaler register */
.equ TIM_CNTR1, 0x64A /* counter register */
.equ TIM_PREL11, 0x64C /* Preload register 1 */
.equ TIM_PREL21, 0x64E /* Preload register 2 */
.equ TIM_COM1, 0x650 /* Compare register */
/* -- U.A.R.T. equates -- */
.equ UA_MCRH, 0x700 /* module configuration register */
.equ UA_MCRL, 0x701 /* module configuration register */
.equ UA_ILR, 0x704 /* Interrupt level */
.equ UA_IVR, 0x705 /* Interrupt vector */
.equ UA_MR1A, 0x710 /* Mode register 1 A */
.equ UA_MR2A, 0x720 /* Mode register 2 A*/
.equ UA_CSRA, 0x711 /* Clock_select register A */
.equ UA_SRA, 0x711 /* status register A */
.equ UA_CRA, 0x712 /* command register A */
.equ UA_RBA, 0x713 /* receive buffer A */
.equ UA_TBA, 0x713 /* transmit buffer A */
.equ UA_IPCR, 0x714 /* input port change register */
.equ UA_ACR, 0x714 /* auxiliary control register */
.equ UA_ISR, 0x715 /* interrupt status register */
.equ UA_IER, 0x715 /* interrupt enable register */
.equ UA_MR1B, 0x718 /* Mode register 1 B */
.equ UA_MR2B, 0x721 /* Mode register 2 B */
.equ UA_CSRB, 0x719 /* Clock_select register B */
.equ UA_SRB, 0x719 /* status register B */
.equ UA_CRB, 0x71A /* command register A */
.equ UA_RBB, 0x71B /* receive buffer A */
.equ UA_TBB, 0x71B /* transmit buffer A */
.equ UA_IP, 0x71D /* Input port register */
.equ UA_OPCR, 0x71D /* output port control register */
.equ UA_OPS, 0x71E /* output port bit set */
.equ UA_OPR, 0x71F /* output port bit reset */
.equ TX_A_EN, 0x01 /* Tx A irq enable */
.equ TX_B_EN, 0x10 /* Tx B irq enable */
.equ TX_A_DIS, 0xFE /* Tx A irq enable */
.equ TX_B_DIS, 0xEF /* Tx B irq enable */
.equ TX_AB_DIS, 0x22
/* -- DMA equates -- */
.equ DMA_MCR0, 0x780 /* module configuration register */
.equ DMA_IR0, 0x784 /* Interrupt register */
.equ DMA_CCR0, 0x788 /* Channel control register */
.equ DMA_CSR0, 0x78A /* Channel status register */
.equ DMA_FCR0, 0x78B /* Function code register */
.equ DMA_SARH0, 0x78C /* Source adresse register */
.equ DMA_SARL0, 0x78E /* Source adresse register */
.equ DMA_DARH0, 0x790 /* destination adresse register */
.equ DMA_DARL0, 0x792 /* destination adresse register */
.equ DMA_BTCH0, 0x794 /* byte transfer register */
.equ DMA_BTCL0, 0x796 /* byte transfer register */
.equ DMA_MCR1, 0x7A0 /* module configuration register */
.equ DMA_IR1, 0x7A4 /* Interrupt register */
.equ DMA_CCR1, 0x7A8 /* Channel control register */
.equ DMA_CSR1, 0x7AA /* Channel status register */
.equ DMA_FCR1, 0x7AB /* Function code register */
.equ DMA_SARH1, 0x7AC /* Source adresse register */
.equ DMA_SARL1, 0x7AE /* Source adresse register */
.equ DMA_DARH1, 0x7B0 /* destination adresse register */
.equ DMA_DARL1, 0x7B2 /* destination adresse register */
.equ DMA_BTCH1, 0x7B4 /* byte transfer register */
.equ DMA_BTCL1, 0x7B6 /* byte transfer register */

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/*----------------------------------------------------------------------------
* file name: M68349.INC P. CADIC CNET/DSM/TAM/CAT
*
* MC68349 BCC Board Support Package
*
* date: 31/07/97
*
* Description: EQUATES FOR 68349 DEVICES
*
* Modifications:
* - adapted for GNU CC by G.Montel 26/05/98
*----------------------------------------------------------------------------*/
| -- SIM equates --
.equ BASE_REG, 0x3FF00
.equ BASE_SIM, 0xEFFFF000 | pour correction du bug 68349 sur IACK
.equ SIM_MCR, 0x000 | module configuration register
.equ SIM_IDR, 0x002 | processor identification register
.equ SIM_SYNCR, 0x004 | clock synthesizer control register
.equ SIM_AVR, 0x006 | autovector register
.equ SIM_RSR, 0x007 | reset status register
| -- Port A
.equ SIM_PORTA, 0x011 | port A data
.equ SIM_DDRA, 0x013 | port A direction data
.equ SIM_PPRA1, 0x015 | Port A pin assignement 1
.equ SIM_PPRA2, 0x017 | Port A pin assignement 2
| -- Port B
.equ SIM_PORTB, 0x019 | port B data
.equ SIM_PORTB1, 0x01B | port B data auxiliary
.equ SIM_DDRB, 0x01D | port B direction data
.equ SIM_PPRB, 0x01F | Port B pin assignement
.equ SIM_SWIV, 0x020 | SW interrupt vector
.equ SIM_SYPCR, 0x021 | System protection control register
.equ SIM_PICR, 0x022 | Periodic interrupt control register
.equ SIM_PITR, 0x024 | Periodic interrupt timing register
.equ SIM_SWSR, 0x027 | Sofware service
| -- Chip select
.equ SIM_MASKH0, 0x040 | mask register CS0
.equ SIM_MASKL0, 0x042 | mask register CS0
.equ SIM_ADDRH0, 0x044 | base address CS0
.equ SIM_ADDRL0, 0x046 | base address CS0
.equ SIM_MASKH1, 0x048 | mask register CS1
.equ SIM_MASKL1, 0x04A | mask register CS1
.equ SIM_ADDRH1, 0x04C | base address CS1
.equ SIM_ADDRL1, 0x04E | base address CS1
.equ SIM_MASKH2, 0x050 | mask register CS2
.equ SIM_MASKL2, 0x052 | mask register CS2
.equ SIM_ADDRH2, 0x054 | base address CS2
.equ SIM_ADDRL2, 0x056 | base address CS2
.equ SIM_MASKH3, 0x058 | mask register CS3
.equ SIM_MASKL3, 0x05A | mask register CS3
.equ SIM_ADDRH3, 0x05C | base address CS3
.equ SIM_ADDRL3, 0x05E | base address CS3
| -- TIMERS equates --
| __ TIMER 0
.equ TIM_MCR0, 0x600 | Module configuration register
.equ TIM_IR0, 0x604 | interrupt register
.equ TIM_CR0, 0x606 | controle register
.equ TIM_SR0, 0x608 | Status/prescaler register
.equ TIM_CNTR0, 0x60A | counter register
.equ TIM_PREL10, 0x60C | Preload register 1
.equ TIM_PREL20, 0x60E | Preload register 2
.equ TIM_COM0, 0x610 | Compare register
| __ TIMER 1
.equ TIM_MCR1, 0x640 | Module configuration register
.equ TIM_IR1, 0x644 | interrupt register
.equ TIM_CR1, 0x646 | controle register
.equ TIM_SR1, 0x648 | Status/prescaler register
.equ TIM_CNTR1, 0x64A | counter register
.equ TIM_PREL11, 0x64C | Preload register 1
.equ TIM_PREL21, 0x64E | Preload register 2
.equ TIM_COM1, 0x650 | Compare register
| -- U.A.R.T. equates --
.equ UA_MCRH, 0x700 | module configuration register
.equ UA_MCRL, 0x701 | module configuration register
.equ UA_ILR, 0x704 | Interrupt level
.equ UA_IVR, 0x705 | Interrupt vector
.equ UA_MR1A, 0x710 | Mode register 1 A
.equ UA_MR2A, 0x720 | Mode register 2 A
.equ UA_CSRA, 0x711 | Clock_select regiter A
.equ UA_SRA, 0x711 | status register A
.equ UA_CRA, 0x712 | command register A
.equ UA_RBA, 0x713 | receive buffer A
.equ UA_TBA, 0x713 | transmit buffer A
.equ UA_IPCR, 0x714 | input port change register
.equ UA_ACR, 0x714 | auxiliary control register
.equ UA_ISR, 0x715 | interrupt status register
.equ UA_IER, 0x715 | interrupt enable register
.equ UA_MR1B, 0x718 | Mode register 1 B
.equ UA_MR2B, 0x721 | Mode register 2 B
.equ UA_CSRB, 0x719 | Clock_select regiter B
.equ UA_SRB, 0x719 | status register B
.equ UA_CRB, 0x71A | command register A
.equ UA_RBB, 0x71B | receive buffer A
.equ UA_TBB, 0x71B | transmit buffer A
.equ UA_IP, 0x71D | Input port register
.equ UA_OPCR, 0x71D | output port control register
.equ UA_OPS, 0x71E | output port bit set
.equ UA_OPR, 0x71F | output port bit reset
.equ TX_A_EN, 0x01 | Tx A irq enable
.equ TX_B_EN, 0x10 | Tx B irq enable
.equ TX_A_DIS, 0xFE | Tx A irq enable
.equ TX_B_DIS, 0xEF | Tx B irq enable
.equ TX_AB_DIS, 0x22
| -- DMA equates
.equ DMA_MCR0, 0x780 | module configuration register
.equ DMA_IR0, 0x784 | Interrupt register
.equ DMA_CCR0, 0x788 | Channel control register
.equ DMA_CSR0, 0x78A | Channel status register
.equ DMA_FCR0, 0x78B | Function code register
.equ DMA_SARH0, 0x78C | Source adresse register
.equ DMA_SARL0, 0x78E | Source adresse register
.equ DMA_DARH0, 0x790 | destination adresse register
.equ DMA_DARL0, 0x792 | destination adresse register
.equ DMA_BTCH0, 0x794 | byte transfer register
.equ DMA_BTCL0, 0x796 | byte transfer register
.equ DMA_MCR1, 0x7A0 | module configuration register
.equ DMA_IR1, 0x7A4 | Interrupt register
.equ DMA_CCR1, 0x7A8 | Channel control register
.equ DMA_CSR1, 0x7AA | Channel status register
.equ DMA_FCR1, 0x7AB | Function code register
.equ DMA_SARH1, 0x7AC | Source adresse register
.equ DMA_SARL1, 0x7AE | Source adresse register
.equ DMA_DARH1, 0x7B0 | destination adresse register
.equ DMA_DARL1, 0x7B2 | destination adresse register
.equ DMA_BTCH1, 0x7B4 | byte transfer register
.equ DMA_BTCL1, 0x7B6 | byte transfer register
| -- cache equates
.equ CACHE_MCR, 0xFC0 | cache config reg. (long)
| -- quad data memory module (QDMM) equates
.equ QDMM_MCR, 0xC00 | QDMM config reg (long)
.equ QDMM_QBAR0, 0xC10 | QDMM base 0 (long)
.equ QDMM_QBAR1, 0xC14 | QDMM base 1 (long)
.equ QDMM_QBAR2, 0xC18 | QDMM base 2 (long)
.equ QDMM_QBAR3, 0xC1C | QDMM base 3 (long)
|-----------------------------------------------------
| AST68349 internal registers
|-----------------------------------------------------
.equ EPLD_SPACE, 3 | "reserved user" space
.equ CPU_SPACE, 7 | "CPU" space
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| GLUE EPLD
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
.equ GLUE_EPLD, 0xB0000000
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| configuration of /CS0 :
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena|val|wid| ws|b31|b30|b29|b28|
| +---+---+---+---+---+---+---+---+
|
| b[31..28] : base address for decoding /CS[3..0]
| the decoding is as follow :
|
| +----------+------------+------+
| | a[31..28] | a[27..26] | /CS |
| +-----------+-----------+------+
| | b[31..28] | 00 | /CS0 | each /CS decodes 64 Mbytes
| | b[31..28] | 01 | /CS1 |
| | b[31..28] | 10 | /CS2 |
| | b[31..28] | 11 | /CS3 |
| +-----------------------+------+
|
| after /RESET, /CS0 is validated for every cycle, until programmed
|
| ws : number of wait-states : 0 => 0 ws
| 1 => external /dsackx
| wid : width of chip-select : 0 => 16 bits
| 1 => 32 bits
| ena : enable chip-select : 0 => disabled
| 1 => enabled
|
| val : automatic validation. set after reset
| cleared when /CS0 is configured
|
.equ REG_CS0, 0
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| configuration of /CS1 to /CS3:
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena| x |wid| ws| x | x | x | x |
| +---+---+---+---+---+---+---+---+
|
| ws : number of wait-states : 0 => 0 ws
| 1 => external /dsackx
| wid : width of chip-select : 0 => 16 bits
| 1 => 32 bits
| ena : enable chip-select : 0 => disabled
| 1 => enabled
.equ REG_CS1, 1
.equ REG_CS2, 2
.equ REG_CS3, 3
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| I2C register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+----+
| | x | x | x | x | x | x |clk|data|
| +---+---+---+---+---+---+---+----+
| bidirecionnal pin, open drain output.
| set bit to 1 to read external state of pin
|
.equ REG_I2C, 4
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| PDCS register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |s12|s11|s14|pd5|pd4|pd3|pd2|pd1|
| +---+---+---+---+---+---+---+---+
| pd[5..1] : value read on the DRAM module
| S12, S11 and S14 : "user reserved" configuration switch
|
.equ REG_PDCS, 5
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| timer1 register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena| x | x | x | x | x | d1| d0|
| +---+---+---+---+---+---+---+---+
|
| the timer clock is the 1000Hz clock of the ASTECC platform
| the timer is reloaded on each write to the register, or if the input
| TIN1 is set to 0.
| on overflow, the open drain output TOUT1 is set to 0
| the timer must be disabled to return TOUT1 to the inactive state
|
.equ REG_TIMER1, 6
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| timer2 register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena| x | x | x | x | x | d1| d0|
| +---+---+---+---+---+---+---+---+
| the timer clock is the 1000Hz clock of the ASTECC platform
| the timer is reloaded on each write to the register, or if the input
| TIN2 is set to 0.
| on overflow, the open drain output TOUT2 is set to 0
| the timer must be disabled to return TOUT2 to the inactive state
|
.equ REG_TIMER2, 7
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| baudrate generator register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x | x | x | d2| d1| d0|
| +---+---+---+---+---+---+---+---+
|
| d[2..0] : divider of a 3.6864 Mhz clock
|
| d[2..0] : 0 1 2 3 4 5 6 7
| divides by : 2 4 6 8 10 12 14 16
| SCLK (Mhz) : 1.8432 0.9216 0.6144 0.4608 x 0.3072 x 0.2304
| baudrate : 115200 57600 38400 28800 x 19200 x 14400
|
.equ REG_BAUDRATE, 8
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| IO register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x |io4|io3|io2|io1|io0|
| +---+---+---+---+---+---+---+---+
|
| io[4..0] : data written to port
|
| maximum current load is about 5 mA per pin
|
.equ REG_IO, 9
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| IO port
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x |io4|io3|io2|io1|io0|
| +---+---+---+---+---+---+---+---+
|
| io[4..0] : data read from port
|
.equ REG_IO_PORT, 10
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| IO direction register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x | x | x |dr2|dr1|dr0|
| +---+---+---+---+---+---+---+---+
|
| dr0 : 0 => io port 0 is configured as input (default after /RESET)
| 1 => io port 0 is configured as output
|
| dr1 : 0 => io port 1 is configured as input (default after /RESET)
| 1 => io port 1 is configured as output
|
| dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET)
| 1 => io ports 2 to 4 are configured as output
|
.equ REG_DIR_IO, 11
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DRAM EPLD
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
.equ DRAM_EPLD, 0xA0000000
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| number of wait-state for DRAM
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x | x | x | x |ws1|ws0|
| +---+---+---+---+---+---+---+---+
|
| ws[1..0] : 0 1 2 3
| wait states : 0 1 2 3
|
.equ REG_WS, 0
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| configuration of refresh for DRAM
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena| x | x | x | x | x |rf1|rf0|
| +---+---+---+---+---+---+---+---+
|
| rf[1..0] : 0 1 2 3
| refresh : 5<EFBFBD>s 10<EFBFBD>s 15<EFBFBD>s 20<EFBFBD>s
|
| ena == 0 : refresh disabled
| ena == 1 : refresh enabled
|
.equ REG_REFRESH, 1
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| configuration of DRAM module size
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x | x | x |sz2|sz1|sz0|
| +---+---+---+---+---+---+---+---+
|
| sz[2..0] : 0 1 2 3 4 5 6 7
| size (Mbytes): 4 8 16 32 64 128 0 0
|
.equ REG_CONFIG, 2
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| bus width of /CS0 during reset bw[1..0] : 0 1 2 3
| bus width : 32 16 8 ext. /dsackx
|
| state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
| : sel == 1 => EPLD chip_selects (/CS[3..0])
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |bw1|bw0| x | x | x | x | x |sel|
| +---+---+---+---+---+---+---+---+
|
.equ REG_BUSWIDTH, 3

57
c/src/lib/libbsp/m68k/gen68340/start/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGMS=${ARCH}/start340.o
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
# Assembly source names, if any, go here -- minus the .s
S_PIECES=start340
S_FILES=$(S_PIECES:%=%.s)
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
SRCS=$(C_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 555 ${PGMS} ${PROJECT_RELEASE}/lib
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)

874
c/src/lib/libbsp/m68k/gen68340/start/start340.s Normal file
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/*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Based on the `gen68360' board support package, and covered by the
* original distribution terms.
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* $Id$
*/
#include "asm.h"
#include <m68349.inc>
#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */
BEGIN_CODE
/*
* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
*/
Entry:
.long SYM(m340)+1024 | 0: Initial SSP
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_uhoh) | 64: User defined vectors (192)
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
.long SYM(_uhoh) | 162:
.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
.long SYM(_uhoh) | 189:
.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
.long SYM(_uhoh) | 192:
.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
.long SYM(_uhoh) | 198:
.long SYM(_uhoh) | 199:
.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
.long SYM(_uhoh) | 203:
.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
PUBLIC (_uhoh)
SYM(_uhoh): nop | Leave spot for breakpoint
/* stop #0x2700 | Stop with interrupts disabled */
move.w #0x2700,sr
move.w (a7),_boot_panic_registers+4 | SR
move.l 2(a7),_boot_panic_registers | PC
move.w 6(a7),_boot_panic_registers+6 | format & vector
movem.l d0-d7/a0-a7, _boot_panic_registers+8
movec sfc, d0
movem.l d0, _boot_panic_registers+72
movec dfc, d0
movem.l d0, _boot_panic_registers+76
movec vbr, d0
movem.l d0, _boot_panic_registers+80
jmp SYM(_dbug_dumpanic)
bra.s _crt0_cold_start
/*
* Log, but otherwise ignore, spurious interrupts
*/
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/*
* Place the low-order 3 octets of the board's ethernet address at
* a `well-known' fixed location relative to the startup location.
*/
.align 2
.word 0 | Padding
ethernet_address_buffer:
.word 0x08F3 | Default address
.word 0xDEAD
.word 0xCAFE
BEGIN_DATA
/* equates */
.equ _CPU340, 0x0
.equ _CPU349, 0x31
#ifdef _OLD_ASTECC /* old addresses for AST68340 only */
.equ _EPLD_CS_BASE, 0x1
.equ _PROM_Start, 0x01000000 /* CS0 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x0c000000 /* CS3 */
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
.equ _ExtRam_Start, 0x10000000 /* SRAM */
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
#else /* new addresses for AST68349 and 68340 */
.equ _EPLD_CS_BASE, 0x5
.equ _PROM_Start, 0x50000000 /* CS0 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x0c000000 /* CS3 */
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
.equ _ExtRam_Start, 0x80000000 /* DRAM */
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
#endif
.equ _SPEED349, 0xD680 /* 24 Mhz */
.equ _SPEED340, 0xD700 /* 25 Mhz */
/* .equ _SPEED340, 0xCE00 16 Mhz */
#define crt0_boot_type d0 /* cold/warm start (must be D0) */
#define crt0_temp d1
#define crt0_cpu_type d2
#define crt0_csswitch d3
#define crt0_buswidth d4
#define crt0_pdcs d5
#define crt0_spare6 d6
#define crt0_spare7 d7
#define crt0_sim_base a0
#define crt0_glue a1
#define crt0_dram a2
#define crt0_ptr3 a3
#define crt0_ptr4 a4
#define crt0_ptr5 a5
#define crt0_ptr6 a6
/* -- PDCS buffer equates -- */
.equ pdcs_mask, 0x1F /* DRAM configuration */
.equ pdcs_sw12, 7 /* switch 12 */
.equ pdcs_sw11, 6 /* switch 11 */
.equ pdcs_sw14, 5 /* switch 14 */
.equ bit_cache, pdcs_sw12 /* enable cache if on */
.equ bit_meminit, pdcs_sw11 /* init memory if on */
/* -- Initialization stack and vars -- */
_AsteccBusWidth: ds.b 1
_AsteccCsSwitch: ds.b 1
_AsteccCpuName: ds.l 1
.align 4
_crt0_init_stack:
ds.l 500
_crt0_init_stktop:
/* -- Initialization code -- */
BEGIN_CODE
.align 4
dc.l _crt0_init_stktop /* reset SP */
dc.l _crt0_cold_start /* reset PC */
dc.l _crt0_warm_start
.ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards"
dc.w 0
.align 4
.globl start
start:
_crt0_cold_start:
moveq.l #0,crt0_boot_type | signal cold reset
bra.s _crt0_common_start
_crt0_warm_start:
moveq.l #1,crt0_boot_type | signal warm reset
_crt0_common_start:
move.w #0x2700,sr | disable interrupts and switch to interrupt mode
movea.l #_crt0_init_stktop,sp | set up initialization stack
move.l #Entry,crt0_temp | VBR initialization
movec.l crt0_temp,vbr |
moveq.l #0x07,crt0_temp
movec.l crt0_temp,dfc | prepare access in CPU space
move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES
moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795)
movea.l #BASE_SIM,crt0_sim_base
/* -- disable Bus Monitor -- */
move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register
/* -- enable A31-A24 -- */
clr.b SIM_PPRA1(crt0_sim_base)
/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
move.w #0x427F,SIM_MCR(crt0_sim_base)
/* -- enable /IRQ3, 5, 6, 7 -- */
move.b #0xE8,SIM_PPRB(crt0_sim_base)
/* -- enable autovector on /IRQ7 -- */
move.b #0x80,SIM_AVR(crt0_sim_base)
/* -- test CPU type -- */
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne cpu_is_68340
/*-------------------------------------------------------------------------------------------*/
cpu_is_68349:
/* -- set cpu clock -- */
move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock
sync_wait349:
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
beq sync_wait349
/* to allow access to the EPLD internal registers, it is necessary
to disable the global chip-select /CS0 (which decodes every external
cycles). To do that, we initialize the 68349 internal RAM,
copy a part of the initialization code in it, and jump there.
from that moment, /CS0 is not used, therefore it can be initialized
with its default value. Its width may be incorrect, but it will be
adjusted later. The goal is to avoid any conflict with
the accesses to the EPLD registers.
When this is done, we read the RESET parameters (boot prom width
and chip-select switch) and proceed with the initialization
when all is done, we jump back to the boot prom now
decoded with a properly configured /CS0 */
/*-------------------------------------*/
/* -- configure internal SRAM banks -- */
move.l #0x00000000,QDMM_MCR(crt0_sim_base)
move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)
/*--------------------------------------------------------*/
/* -- copy to address of the 68349 initialization code -- */
lea.l _copy_start(%pc),crt0_ptr3
lea.l _copy_end(%pc),crt0_ptr4
move.l crt0_ptr4,crt0_temp
sub.l crt0_ptr3,crt0_temp
add.l #3,crt0_temp | adjust to next long word
lsr.l #2,crt0_temp
move.l #_FastRam_Start,crt0_ptr4
_copy_loop:
move.l (crt0_ptr3)+,(crt0_ptr4)+
subq.l #1,crt0_temp
bne.s _copy_loop
bra.l _FastRam_Start | jump to code in internal RAM
/*------------------------------------*/
/* -- start of initialization code -- */
_copy_start:
bra.l _begin_68349_init
/*----------------------------------------------------------*/
/* Astecc 68349 board : chip-select initialization values */
_table_csepld:
dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws
dc.b 0x80 | 16 bits, 0 ws
dc.b 0x90 | 16 bits, ext /dsack
dc.b 0x90 | 16 bits, ext /dsack
_table_cs349:
dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS)
dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0
dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS)
dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1
dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes)
dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2
dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes)
dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3
/*-------------------------------------------------*/
_begin_68349_init:
/*-------------------------------------------------*/
/* 68349 chip select initialization
at this stage, the width of /CS0 may be incorrect
it will be corrected later
*/
_cs68349_init:
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
moveq.l #0x07,crt0_temp
_cs349_init2:
move.l (crt0_ptr3)+,(crt0_ptr4)+
dbra crt0_temp,_cs349_init2
/*-----------------------------------------------*/
/* -- prepare access to the internal registers --*/
moveq.l #EPLD_SPACE,crt0_temp
movec.l crt0_temp,dfc
movec.l crt0_temp,sfc
move.l #GLUE_EPLD,crt0_glue
move.l #DRAM_EPLD,crt0_dram
/*-------------------------------------------*/
/* EPLD generated /CS[3..0] must be disabled */
_csepld_clear:
move.l crt0_glue,crt0_ptr4
move.w #3,crt0_spare6
clr.b crt0_temp
_csepld_clear1:
moves.b crt0_temp,(crt0_ptr4)+
dbra crt0_spare6,_csepld_clear1
/*---------------------------------------------------------*/
/* -- get width of boot PROM, and active chip-select set --*/
moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch
move.b crt0_csswitch,crt0_buswidth
/* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
: sel == 1 => EPLD chip_selects (/CS[3..0]) */
and.b #1,crt0_csswitch
/* bus width of /CS0 during reset bw[1..0] : 0 1 2 3
bus width : 32 16 8 ext./dsackx */
rol.b #2,crt0_buswidth
and.b #3,crt0_buswidth
/*----------------------------------------------------*/
/* -- configure chip select 0 with boot prom width -- */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
move.l (crt0_ptr3)+,crt0_temp
and.b #0xFC,crt0_temp | clear PS0 & PS1
or.b crt0_buswidth,crt0_temp | set boot PROM bus width
move.l crt0_temp,(crt0_ptr4)+
/*------------------------*/
/* -- read PDCS buffer -- */
moves.b REG_PDCS(crt0_glue),crt0_pdcs
/* move.b #0x3F,crt0_pdcs pour test */
/*---------------------------------------*/
/* -- EPLD chip-select initialization -- */
/*---------------------------------------*/
btst.b #0,crt0_csswitch
beq _cs_init_end
/*--------------------------------------------*/
/* 68349 generated /CS[3..0] must be disabled */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
moveq.l #0x03,crt0_temp
_cs349_clear:
move.l (crt0_ptr3)+,(crt0_ptr4)+
move.l (crt0_ptr3)+,crt0_spare6
and.b #0xFE,crt0_spare6 | disable chip-select
move.l crt0_spare6,(crt0_ptr4)+
dbra crt0_temp,_cs349_clear
/*---------------------------------------------*/
/* EPLD generated /CS[3..0] must be configured */
_csepld_init:
move.l crt0_glue,crt0_ptr4
lea.l _table_csepld(%pc),crt0_ptr3
move.b (crt0_ptr3)+,crt0_temp
or.b #0x20,crt0_temp | default width is 32 bits
tst.b crt0_buswidth | is boot PROM bus width 32 bits ?
beq _csepld1 | if not
and.b #0xDF,crt0_temp | set width to 16 bits
_csepld1:
moves.b crt0_temp,(crt0_ptr4)+
moveq.l #0x02,crt0_spare6
_csepld2:
move.b (crt0_ptr3)+,crt0_temp
moves.b crt0_temp,(crt0_ptr4)+
dbra crt0_spare6,_csepld2
_cs_init_end:
/*--------------------------------------*/
/* -- DRAM controller initialization -- */
_dram_init:
move.w #15,crt0_temp
move.l #_ExtRam_Start,crt0_ptr3
_dram_init1:
clr.l (crt0_ptr3)+ | must access DRAM
dbra crt0_temp,_dram_init1 | prior to init refresh
_dram_init2:
move.b #3,crt0_temp
moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states
move.b #0x81,crt0_temp
moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10<EFBFBD>s
move.b #0,crt0_temp
moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes
/*-----------------------*/
/* -- configure cache -- */
_init_cache:
move.l #0x000001E0,CACHE_MCR(crt0_sim_base)
btst.b #bit_cache,crt0_pdcs
bne _init_cache_end
or.l #0x00000001,CACHE_MCR(crt0_sim_base)
_init_cache_end:
/*-----------------------------*/
/* -- timers initialization -- */
clr.b crt0_temp
moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1
moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2
/*--------------------------*/
/* -- I2C initialization -- */
move.b #3,crt0_temp
moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports
/*-----------------------------------------*/
/* -- baudrate generator initialization -- */
move.b #2,crt0_temp
moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400
/*-------------------------------*/
/* -- IO port initialization -- */
clr.b crt0_temp
moves.b crt0_temp,REG_IO(crt0_glue) | set port as input
/* -- */
move.l #68349,crt0_cpu_type
/* -- jump back to PROM -- */
jmp.l (_fill_test) | must be absolute long
_copy_end:
/*-------------------------------------------------
initialization code for the 68340 board
-------------------------------------------------*/
/* Astecc 68340 board : chip-select initialization values */
_table_cs340:
dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */
dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */
dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */
dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */
cpu_is_68340:
/* -- set cpu clock -- */
move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock
sync_wait340:
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
beq sync_wait340
/* -- chip select initialization -- */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs340(%pc),crt0_ptr3
moveq.l #0x07,crt0_temp
_b_cs340:
move.l (crt0_ptr3)+,crt0_ptr5
move.l crt0_ptr5,(crt0_ptr4)+ | pour test
dbra crt0_temp,_b_cs340
move.l #68340,crt0_cpu_type
move.b #0,crt0_csswitch | CPU
move.b #1,crt0_buswidth | 16 bits
/*-------------------------------------------------
fill RAM if COLDSTART
-------------------------------------------------*/
_fill_test:
tst.l crt0_boot_type
bne _dont_fill
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne _fill
btst.b #bit_meminit,crt0_pdcs
bne _dont_fill
/* fill main memory */
_fill:
move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars
move.l #_ExtRam_Start,crt0_temp
sub.l #_crt0_init_stack,crt0_temp
add.l #_ExtRam_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_fill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _fill_loop
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne _fill_bccram
/* fill QDMM memory */
movea.l #_FastRam_Start,crt0_ptr3 | get start
move.l #_FastRam_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_QDMMfill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _QDMMfill_loop
bra _dont_fill
/* fill BCC memory */
_fill_bccram:
movea.l #_BCCram_Start,crt0_ptr3 | get start
move.l #_BCCram_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_BCCfill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _BCCfill_loop
*-------------------------------------------------*/
_dont_fill:
move.b crt0_csswitch,_AsteccCsSwitch
move.b crt0_buswidth,_AsteccBusWidth
move.l crt0_cpu_type,_AsteccCpuName
jmp SYM(_Init68340) | Start C code (which never returns)
/*
* Copy DATA segment, clear BSS segment, set up real stack,
* initialize heap, start C program.
* Assume that DATA and BSS sizes are multiples of 4.
*/
PUBLIC (_CopyDataClearBSSAndStart)
SYM(_CopyDataClearBSSAndStart):
lea copy_start,a0 | Get start of DATA in RAM
lea SYM(etext),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea copy_end,a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea clear_start,a0 | Get start of BSS
lea clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
movel #stack_init,a7 | set master stack pointer
movel d0,a7@- | environp
movel d0,a7@- | argv
movel d0,a7@- | argc
jsr SYM(boot_card) | Call C main
PUBLIC (_mainDone)
SYM(_mainDone):
nop | Leave spot for breakpoint
movew #1,a7 | Force a double bus error
movel d0,a7@- | This should cause a RESET
/* stop #0x2700 | Stop with interrupts disabled */
move.w #0x2700,sr
bra.s SYM(_mainDone) | Stuck forever
.align 2
PUBLIC (_HeapSize)
SYM (_HeapSize):
.long HeapSize
PUBLIC (_StackSize)
SYM (_StackSize):
.long StackSize
END_CODE
BEGIN_DATA_DCL
.align 2
PUBLIC (environ)
SYM (environ):
.long 0
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END

57
c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGMS=${ARCH}/start340.o
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
# Assembly source names, if any, go here -- minus the .s
S_PIECES=start340
S_FILES=$(S_PIECES:%=%.s)
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
SRCS=$(C_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 555 ${PGMS} ${PROJECT_RELEASE}/lib
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)

874
c/src/lib/libbsp/m68k/gen68340/start340/start340.s Normal file
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/*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Based on the `gen68360' board support package, and covered by the
* original distribution terms.
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* $Id$
*/
#include "asm.h"
#include <m68349.inc>
#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */
BEGIN_CODE
/*
* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
*/
Entry:
.long SYM(m340)+1024 | 0: Initial SSP
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_uhoh) | 64: User defined vectors (192)
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
.long SYM(_uhoh) | 162:
.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
.long SYM(_uhoh) | 189:
.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
.long SYM(_uhoh) | 192:
.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
.long SYM(_uhoh) | 198:
.long SYM(_uhoh) | 199:
.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
.long SYM(_uhoh) | 203:
.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
PUBLIC (_uhoh)
SYM(_uhoh): nop | Leave spot for breakpoint
/* stop #0x2700 | Stop with interrupts disabled */
move.w #0x2700,sr
move.w (a7),_boot_panic_registers+4 | SR
move.l 2(a7),_boot_panic_registers | PC
move.w 6(a7),_boot_panic_registers+6 | format & vector
movem.l d0-d7/a0-a7, _boot_panic_registers+8
movec sfc, d0
movem.l d0, _boot_panic_registers+72
movec dfc, d0
movem.l d0, _boot_panic_registers+76
movec vbr, d0
movem.l d0, _boot_panic_registers+80
jmp SYM(_dbug_dumpanic)
bra.s _crt0_cold_start
/*
* Log, but otherwise ignore, spurious interrupts
*/
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/*
* Place the low-order 3 octets of the board's ethernet address at
* a `well-known' fixed location relative to the startup location.
*/
.align 2
.word 0 | Padding
ethernet_address_buffer:
.word 0x08F3 | Default address
.word 0xDEAD
.word 0xCAFE
BEGIN_DATA
/* equates */
.equ _CPU340, 0x0
.equ _CPU349, 0x31
#ifdef _OLD_ASTECC /* old addresses for AST68340 only */
.equ _EPLD_CS_BASE, 0x1
.equ _PROM_Start, 0x01000000 /* CS0 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x0c000000 /* CS3 */
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
.equ _ExtRam_Start, 0x10000000 /* SRAM */
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
#else /* new addresses for AST68349 and 68340 */
.equ _EPLD_CS_BASE, 0x5
.equ _PROM_Start, 0x50000000 /* CS0 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x0c000000 /* CS3 */
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
.equ _ExtRam_Start, 0x80000000 /* DRAM */
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
#endif
.equ _SPEED349, 0xD680 /* 24 Mhz */
.equ _SPEED340, 0xD700 /* 25 Mhz */
/* .equ _SPEED340, 0xCE00 16 Mhz */
#define crt0_boot_type d0 /* cold/warm start (must be D0) */
#define crt0_temp d1
#define crt0_cpu_type d2
#define crt0_csswitch d3
#define crt0_buswidth d4
#define crt0_pdcs d5
#define crt0_spare6 d6
#define crt0_spare7 d7
#define crt0_sim_base a0
#define crt0_glue a1
#define crt0_dram a2
#define crt0_ptr3 a3
#define crt0_ptr4 a4
#define crt0_ptr5 a5
#define crt0_ptr6 a6
/* -- PDCS buffer equates -- */
.equ pdcs_mask, 0x1F /* DRAM configuration */
.equ pdcs_sw12, 7 /* switch 12 */
.equ pdcs_sw11, 6 /* switch 11 */
.equ pdcs_sw14, 5 /* switch 14 */
.equ bit_cache, pdcs_sw12 /* enable cache if on */
.equ bit_meminit, pdcs_sw11 /* init memory if on */
/* -- Initialization stack and vars -- */
_AsteccBusWidth: ds.b 1
_AsteccCsSwitch: ds.b 1
_AsteccCpuName: ds.l 1
.align 4
_crt0_init_stack:
ds.l 500
_crt0_init_stktop:
/* -- Initialization code -- */
BEGIN_CODE
.align 4
dc.l _crt0_init_stktop /* reset SP */
dc.l _crt0_cold_start /* reset PC */
dc.l _crt0_warm_start
.ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards"
dc.w 0
.align 4
.globl start
start:
_crt0_cold_start:
moveq.l #0,crt0_boot_type | signal cold reset
bra.s _crt0_common_start
_crt0_warm_start:
moveq.l #1,crt0_boot_type | signal warm reset
_crt0_common_start:
move.w #0x2700,sr | disable interrupts and switch to interrupt mode
movea.l #_crt0_init_stktop,sp | set up initialization stack
move.l #Entry,crt0_temp | VBR initialization
movec.l crt0_temp,vbr |
moveq.l #0x07,crt0_temp
movec.l crt0_temp,dfc | prepare access in CPU space
move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES
moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795)
movea.l #BASE_SIM,crt0_sim_base
/* -- disable Bus Monitor -- */
move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register
/* -- enable A31-A24 -- */
clr.b SIM_PPRA1(crt0_sim_base)
/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
move.w #0x427F,SIM_MCR(crt0_sim_base)
/* -- enable /IRQ3, 5, 6, 7 -- */
move.b #0xE8,SIM_PPRB(crt0_sim_base)
/* -- enable autovector on /IRQ7 -- */
move.b #0x80,SIM_AVR(crt0_sim_base)
/* -- test CPU type -- */
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne cpu_is_68340
/*-------------------------------------------------------------------------------------------*/
cpu_is_68349:
/* -- set cpu clock -- */
move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock
sync_wait349:
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
beq sync_wait349
/* to allow access to the EPLD internal registers, it is necessary
to disable the global chip-select /CS0 (which decodes every external
cycles). To do that, we initialize the 68349 internal RAM,
copy a part of the initialization code in it, and jump there.
from that moment, /CS0 is not used, therefore it can be initialized
with its default value. Its width may be incorrect, but it will be
adjusted later. The goal is to avoid any conflict with
the accesses to the EPLD registers.
When this is done, we read the RESET parameters (boot prom width
and chip-select switch) and proceed with the initialization
when all is done, we jump back to the boot prom now
decoded with a properly configured /CS0 */
/*-------------------------------------*/
/* -- configure internal SRAM banks -- */
move.l #0x00000000,QDMM_MCR(crt0_sim_base)
move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)
/*--------------------------------------------------------*/
/* -- copy to address of the 68349 initialization code -- */
lea.l _copy_start(%pc),crt0_ptr3
lea.l _copy_end(%pc),crt0_ptr4
move.l crt0_ptr4,crt0_temp
sub.l crt0_ptr3,crt0_temp
add.l #3,crt0_temp | adjust to next long word
lsr.l #2,crt0_temp
move.l #_FastRam_Start,crt0_ptr4
_copy_loop:
move.l (crt0_ptr3)+,(crt0_ptr4)+
subq.l #1,crt0_temp
bne.s _copy_loop
bra.l _FastRam_Start | jump to code in internal RAM
/*------------------------------------*/
/* -- start of initialization code -- */
_copy_start:
bra.l _begin_68349_init
/*----------------------------------------------------------*/
/* Astecc 68349 board : chip-select initialization values */
_table_csepld:
dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws
dc.b 0x80 | 16 bits, 0 ws
dc.b 0x90 | 16 bits, ext /dsack
dc.b 0x90 | 16 bits, ext /dsack
_table_cs349:
dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS)
dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0
dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS)
dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1
dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes)
dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2
dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes)
dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3
/*-------------------------------------------------*/
_begin_68349_init:
/*-------------------------------------------------*/
/* 68349 chip select initialization
at this stage, the width of /CS0 may be incorrect
it will be corrected later
*/
_cs68349_init:
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
moveq.l #0x07,crt0_temp
_cs349_init2:
move.l (crt0_ptr3)+,(crt0_ptr4)+
dbra crt0_temp,_cs349_init2
/*-----------------------------------------------*/
/* -- prepare access to the internal registers --*/
moveq.l #EPLD_SPACE,crt0_temp
movec.l crt0_temp,dfc
movec.l crt0_temp,sfc
move.l #GLUE_EPLD,crt0_glue
move.l #DRAM_EPLD,crt0_dram
/*-------------------------------------------*/
/* EPLD generated /CS[3..0] must be disabled */
_csepld_clear:
move.l crt0_glue,crt0_ptr4
move.w #3,crt0_spare6
clr.b crt0_temp
_csepld_clear1:
moves.b crt0_temp,(crt0_ptr4)+
dbra crt0_spare6,_csepld_clear1
/*---------------------------------------------------------*/
/* -- get width of boot PROM, and active chip-select set --*/
moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch
move.b crt0_csswitch,crt0_buswidth
/* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
: sel == 1 => EPLD chip_selects (/CS[3..0]) */
and.b #1,crt0_csswitch
/* bus width of /CS0 during reset bw[1..0] : 0 1 2 3
bus width : 32 16 8 ext./dsackx */
rol.b #2,crt0_buswidth
and.b #3,crt0_buswidth
/*----------------------------------------------------*/
/* -- configure chip select 0 with boot prom width -- */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
move.l (crt0_ptr3)+,crt0_temp
and.b #0xFC,crt0_temp | clear PS0 & PS1
or.b crt0_buswidth,crt0_temp | set boot PROM bus width
move.l crt0_temp,(crt0_ptr4)+
/*------------------------*/
/* -- read PDCS buffer -- */
moves.b REG_PDCS(crt0_glue),crt0_pdcs
/* move.b #0x3F,crt0_pdcs pour test */
/*---------------------------------------*/
/* -- EPLD chip-select initialization -- */
/*---------------------------------------*/
btst.b #0,crt0_csswitch
beq _cs_init_end
/*--------------------------------------------*/
/* 68349 generated /CS[3..0] must be disabled */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
moveq.l #0x03,crt0_temp
_cs349_clear:
move.l (crt0_ptr3)+,(crt0_ptr4)+
move.l (crt0_ptr3)+,crt0_spare6
and.b #0xFE,crt0_spare6 | disable chip-select
move.l crt0_spare6,(crt0_ptr4)+
dbra crt0_temp,_cs349_clear
/*---------------------------------------------*/
/* EPLD generated /CS[3..0] must be configured */
_csepld_init:
move.l crt0_glue,crt0_ptr4
lea.l _table_csepld(%pc),crt0_ptr3
move.b (crt0_ptr3)+,crt0_temp
or.b #0x20,crt0_temp | default width is 32 bits
tst.b crt0_buswidth | is boot PROM bus width 32 bits ?
beq _csepld1 | if not
and.b #0xDF,crt0_temp | set width to 16 bits
_csepld1:
moves.b crt0_temp,(crt0_ptr4)+
moveq.l #0x02,crt0_spare6
_csepld2:
move.b (crt0_ptr3)+,crt0_temp
moves.b crt0_temp,(crt0_ptr4)+
dbra crt0_spare6,_csepld2
_cs_init_end:
/*--------------------------------------*/
/* -- DRAM controller initialization -- */
_dram_init:
move.w #15,crt0_temp
move.l #_ExtRam_Start,crt0_ptr3
_dram_init1:
clr.l (crt0_ptr3)+ | must access DRAM
dbra crt0_temp,_dram_init1 | prior to init refresh
_dram_init2:
move.b #3,crt0_temp
moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states
move.b #0x81,crt0_temp
moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10<EFBFBD>s
move.b #0,crt0_temp
moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes
/*-----------------------*/
/* -- configure cache -- */
_init_cache:
move.l #0x000001E0,CACHE_MCR(crt0_sim_base)
btst.b #bit_cache,crt0_pdcs
bne _init_cache_end
or.l #0x00000001,CACHE_MCR(crt0_sim_base)
_init_cache_end:
/*-----------------------------*/
/* -- timers initialization -- */
clr.b crt0_temp
moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1
moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2
/*--------------------------*/
/* -- I2C initialization -- */
move.b #3,crt0_temp
moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports
/*-----------------------------------------*/
/* -- baudrate generator initialization -- */
move.b #2,crt0_temp
moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400
/*-------------------------------*/
/* -- IO port initialization -- */
clr.b crt0_temp
moves.b crt0_temp,REG_IO(crt0_glue) | set port as input
/* -- */
move.l #68349,crt0_cpu_type
/* -- jump back to PROM -- */
jmp.l (_fill_test) | must be absolute long
_copy_end:
/*-------------------------------------------------
initialization code for the 68340 board
-------------------------------------------------*/
/* Astecc 68340 board : chip-select initialization values */
_table_cs340:
dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */
dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */
dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */
dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */
cpu_is_68340:
/* -- set cpu clock -- */
move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock
sync_wait340:
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
beq sync_wait340
/* -- chip select initialization -- */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs340(%pc),crt0_ptr3
moveq.l #0x07,crt0_temp
_b_cs340:
move.l (crt0_ptr3)+,crt0_ptr5
move.l crt0_ptr5,(crt0_ptr4)+ | pour test
dbra crt0_temp,_b_cs340
move.l #68340,crt0_cpu_type
move.b #0,crt0_csswitch | CPU
move.b #1,crt0_buswidth | 16 bits
/*-------------------------------------------------
fill RAM if COLDSTART
-------------------------------------------------*/
_fill_test:
tst.l crt0_boot_type
bne _dont_fill
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne _fill
btst.b #bit_meminit,crt0_pdcs
bne _dont_fill
/* fill main memory */
_fill:
move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars
move.l #_ExtRam_Start,crt0_temp
sub.l #_crt0_init_stack,crt0_temp
add.l #_ExtRam_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_fill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _fill_loop
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne _fill_bccram
/* fill QDMM memory */
movea.l #_FastRam_Start,crt0_ptr3 | get start
move.l #_FastRam_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_QDMMfill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _QDMMfill_loop
bra _dont_fill
/* fill BCC memory */
_fill_bccram:
movea.l #_BCCram_Start,crt0_ptr3 | get start
move.l #_BCCram_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_BCCfill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _BCCfill_loop
*-------------------------------------------------*/
_dont_fill:
move.b crt0_csswitch,_AsteccCsSwitch
move.b crt0_buswidth,_AsteccBusWidth
move.l crt0_cpu_type,_AsteccCpuName
jmp SYM(_Init68340) | Start C code (which never returns)
/*
* Copy DATA segment, clear BSS segment, set up real stack,
* initialize heap, start C program.
* Assume that DATA and BSS sizes are multiples of 4.
*/
PUBLIC (_CopyDataClearBSSAndStart)
SYM(_CopyDataClearBSSAndStart):
lea copy_start,a0 | Get start of DATA in RAM
lea SYM(etext),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea copy_end,a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea clear_start,a0 | Get start of BSS
lea clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
movel #stack_init,a7 | set master stack pointer
movel d0,a7@- | environp
movel d0,a7@- | argv
movel d0,a7@- | argc
jsr SYM(boot_card) | Call C main
PUBLIC (_mainDone)
SYM(_mainDone):
nop | Leave spot for breakpoint
movew #1,a7 | Force a double bus error
movel d0,a7@- | This should cause a RESET
/* stop #0x2700 | Stop with interrupts disabled */
move.w #0x2700,sr
bra.s SYM(_mainDone) | Stuck forever
.align 2
PUBLIC (_HeapSize)
SYM (_HeapSize):
.long HeapSize
PUBLIC (_StackSize)
SYM (_StackSize):
.long StackSize
END_CODE
BEGIN_DATA_DCL
.align 2
PUBLIC (environ)
SYM (environ):
.long 0
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END

56
c/src/lib/libbsp/m68k/gen68340/startup/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGM=${ARCH}/startup.rel
# C source names, if any, go here -- minus the .c
C_PIECES=bspclean bsplibc bsppost bspstart init68340 main sbrk setvec dumpanic
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
SRCS=$(srcdir)/linkcmds \
$(C_FILES) $(H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${SRCS} ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(PGM)
$(INSTALL) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile

27
c/src/lib/libbsp/m68k/gen68340/startup/bspclean.c Normal file
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/* bsp_cleanup()
*
* This routine normally is part of start.s and usually returns
* control to a monitor.
*
* INPUT: NONE
*
* OUTPUT: NONE
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
void bsp_cleanup( void )
{
/* Cause double bus fault to force reset? */
}

118
c/src/lib/libbsp/m68k/gen68340/startup/bspstart.c Normal file
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/* bsp_start()
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*
* INPUT: NONE
*
* OUTPUT: NONE
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/libio.h>
#include <libcsupport.h>
#include <string.h>
/*
* The original table from the application and our copy of it with
* some changes.
*/
extern rtems_configuration_table Configuration;
rtems_configuration_table BSP_Configuration;
rtems_cpu_table Cpu_table;
char *rtems_progname;
/* Initialize whatever libc we are using
* called from postdriver hook
*/
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, unsigned32, int );
/*
* Function: bsp_pretasking_hook
* Created: 95/03/10
*
* Description:
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*
* NOTES:
* Must not use libc (to do io) from here, since drivers are
* not yet initialized.
*
*/
void bsp_pretasking_hook(void)
{
extern void *_HeapStart;
extern rtems_unsigned32 _HeapSize;
bsp_libc_init(&_HeapStart, _HeapSize, 0);
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
extern void *_WorkspaceBase;
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
#if 0
Cpu_table.interrupt_vector_table = (mc68000_isr *) 0/*&M68Kvec*/;
#endif
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
BSP_Configuration.work_space_start = (void *)&_WorkspaceBase;
/*
* Account for the console's resources
*/
console_reserve_resources( &BSP_Configuration );
/*
* initialize the CPU table for this BSP
*/
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.postdriver_hook = bsp_postdriver_hook;
Cpu_table.do_zero_of_workspace = TRUE;
Cpu_table.interrupt_stack_size = 4096;
}

193
c/src/lib/libbsp/m68k/gen68340/startup/dumpanic.c Normal file
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/*
* M68340/349 registers and stack dump if an exception is raised
*
* Author:
* Pascal Cadic
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <stdio.h>
const char *exceptionName[] =
{
"INITIAL STACK POINTER",
"INITIAL PROGRAM COUNTER",
"BUS ERROR",
"ADDRESS ERROR",
"ILLEGAL INSTRUCTION",
"DIVISION BY ZERO",
"CHK, CHK2",
"TRAPcc, TRAPv",
"PRIVILEGE VIOLATION",
"TRACE",
"LINE A EMULATOR",
"LINE F EMULATOR",
"HARDWARE BREAK",
"COPROCESSOR PROTOCOL VIOLATION",
"FORMAT ERROR",
"UNINITIALIZED INTERRUPT",
"RESERVED 16",
"RESERVED 17",
"RESERVED 18",
"RESERVED 19",
"RESERVED 20",
"RESERVED 21",
"RESERVED 22",
"RESERVED 23",
"SPURIOUS INTERRUPT",
"LEVEL 1 AUTOVECTOR",
"LEVEL 2 AUTOVECTOR",
"LEVEL 3 AUTOVECTOR",
"LEVEL 4 AUTOVECTOR",
"LEVEL 5 AUTOVECTOR",
"LEVEL 6 AUTOVECTOR",
"LEVEL 7 AUTOVECTOR",
"TRAP 1",
"TRAP 2",
"TRAP 3",
"TRAP 4",
"TRAP 5",
"TRAP 6",
"TRAP 7",
"TRAP 8",
"TRAP 9",
"TRAP 10",
"TRAP 11",
"TRAP 12",
"TRAP 13",
"TRAP 14",
"TRAP 15",
"VECTOR 48",
"VECTOR 49",
"VECTOR 50",
"VECTOR 51",
"VECTOR 52",
"VECTOR 53",
"VECTOR 54",
"VECTOR 55",
"VECTOR 56",
"VECTOR 57",
"VECTOR 58",
"VECTOR 59",
"VECTOR 60",
"VECTOR 61",
"VECTOR 62",
"VECTOR 63",
};
typedef struct {
unsigned long pc;
unsigned short sr;
unsigned short format_id;
unsigned long d0, d1, d2, d3, d4, d5, d6, d7;
unsigned long a0, a1, a2, a3, a4, a5, a6, a7;
unsigned long sfc, dfc, vbr;
} boot_panic_registers_t;
boot_panic_registers_t _boot_panic_registers;
extern void RAW_FMT( int minor, const char* fmt, ... );
extern char RAW_GETC(int minor);
/******************************************************
Name: _dbug_dump
Input parameters: sr, pc, stack pointer,
size to display
Output parameters: -
Description: display the supervisor stack
*****************************************************/
void _dbug_dump(unsigned short sr, void* pc, unsigned short *stack, int size)
{
int i;
RAW_FMT(0,"%x : %x \t%x",0,sr,(unsigned short)(((unsigned)pc)>>16));
for (i=2; i<size; i++) {
if ((i%8)==0) RAW_FMT(0,"\n%x :",i/8);
RAW_FMT(0," %x\t",stack[i-2]);
}
RAW_FMT(0,"\n");
}
/******************************************************
Name: _dbug_dump
Input parameters: -
Output parameters: -
Description: display microcontroler state. Registers
values are stored in _boot_panic_registers
which is filled in _uhoh ASM routine
*****************************************************/
void _dbug_dumpanic(void)
{
int c;
void *faultedAddr, *pc;
unsigned short vector, status;
unsigned char frametype, *stack;
#define ESCAPE 27
stack = (unsigned char*)(_boot_panic_registers.a7);
do {
status = _boot_panic_registers.sr;
pc = (void*)_boot_panic_registers.pc;
faultedAddr = *(void**)(stack+4);
vector = (_boot_panic_registers.format_id&0x0FFF)>>2;
frametype = (_boot_panic_registers.format_id&0xF000)>>12;
RAW_FMT(0,"\n---------------------------------------------\n");
if (vector<64)
RAW_FMT(0,"%s",exceptionName[vector]);
else {
RAW_FMT(0,"RESERVED USER");
}
RAW_FMT(0," exception (vector %x, type %x)\n",vector,frametype);
RAW_FMT(0,"---------------------------------------------\n");
RAW_FMT(0,"PC : 0x%x ",pc);
RAW_FMT(0,"A7 : 0x%x ",_boot_panic_registers.a7);
RAW_FMT(0,"SR : 0x%x\n",status);
if (frametype==0x0c) {
RAW_FMT(0,"\nfaulted address = 0x%x\n",faultedAddr);
}
RAW_FMT(0,"---------------------------------------------\n");
RAW_FMT(0," panic regs\n");
RAW_FMT(0,"---------------------------------------------\n");
RAW_FMT(0,"D[0..3] : %x \t%x \t%x \t%x\n",
_boot_panic_registers.d0,_boot_panic_registers.d1,
_boot_panic_registers.d2,_boot_panic_registers.d3);
RAW_FMT(0,"D[4..7] : %x \t%x \t%x \t%x\n",
_boot_panic_registers.d4,_boot_panic_registers.d5,
_boot_panic_registers.d6,_boot_panic_registers.d7);
RAW_FMT(0,"A[0..3] : %x \t%x \t%x \t%x\n",
_boot_panic_registers.a0,_boot_panic_registers.a1,
_boot_panic_registers.a2,_boot_panic_registers.a3);
RAW_FMT(0,"A[4..7] : %x \t%x \t%x \t%x\n",
_boot_panic_registers.a4,_boot_panic_registers.a5,
_boot_panic_registers.a6,_boot_panic_registers.a7);
RAW_FMT(0," SFC : %x",_boot_panic_registers.sfc);
RAW_FMT(0," DFC : %x\n",_boot_panic_registers.dfc);
RAW_FMT(0," VBR : %x\n",_boot_panic_registers.vbr);
RAW_FMT(0,"---------------------------------------------\n");
RAW_FMT(0," panic stack\n");
RAW_FMT(0,"---------------------------------------------\n");
_dbug_dump(status, pc, (unsigned short*)stack,64*2);
RAW_FMT(0,"---------------------------------------------\n");
RAW_FMT(0,"press escape to reboot\n");
} while ((c=RAW_GETC(0))!=ESCAPE); /* cgets ne marche pas si les IT sont bloqu<71>es */
}

39
c/src/lib/libbsp/m68k/gen68340/startup/init68340.c Normal file
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/*
* MC68340/349 support routines
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
/*
* Initialize MC68340
*/
void _Init68340 (void)
{
extern void _CopyDataClearBSSAndStart (void);
m68k_isr_entry *vbr;
int i;
/*
* Copy the exception vector table to system RAM
*/
m68k_get_vbr (vbr);
for (i = 0; i < 256; ++i)
M68Kvec[i] = vbr[i];
m68k_set_vbr (M68Kvec);
/*
* Copy data, clear BSS, switch stacks and call main()
*/
_CopyDataClearBSSAndStart ();
}

155
c/src/lib/libbsp/m68k/gen68340/startup/linkcmds Normal file
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/*
* This file contains GNU linker directives for a generic MC68340/349 board.
* Variations in hardware type and dynamic memory size can be made
* by overriding some values with linker command-line arguments.
*
* ATTENTION: RAM and ROM placement must accord those in start340.S!!
* (next time I'll use some shared variables :) )
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* $Id$
*/
/*
* a.out format doesn't handle prom images very well
*/
OUTPUT_FORMAT(coff-m68k)
/*
* Declare some sizes.
* XXX: The assignment of ". += XyzSize;" fails in older gld's if the
* number used there is not constant. If this happens to you, edit
* the lines marked XXX below to use a constant value.
*/
RamSize = DEFINED(RamSize) ? RamSize : 4M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x10000;
StackSize = DEFINED(StackSize) ? StackSize : 0x1000;
/*
* Declare on-board memory.
* It would be nice if the ram length could be given as
* LENGTH=RamSize, but gld doesn't allow non-constant
* values in the LENGTH expression.
*/
MEMORY {
ram : ORIGIN = 0x10000000, LENGTH = 4M
rom : ORIGIN = 0x01000000, LENGTH = 4M
/* dpram : ORIGIN = 0xFE000000, LENGTH = 8k */
}
/*
* Declare low-order three octets of Ethernet address.
*/
ETHERNET_ADDRESS = DEFINED(ETHERNET_ADDRESS) ? ETHERNET_ADDRESS : 0xDEAD12;
/*
* Load objects
*/
SECTIONS {
/*
* Hardware variations
*/
_RamSize = RamSize;
__RamSize = RamSize;
/*
* Boot PROM
*/
rom : {
_RomBase = .;
__RomBase = .;
} >rom
/*
* Dynamic RAM
*/
ram : {
_RamBase = .;
__RamBase = .;
} >ram
/*
* Text, data and bss segments
*/
.text : {
CREATE_OBJECT_SYMBOLS
*(.text)
. = ALIGN (16);
/*
* C++ constructors
*/
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
*(.ctors)
LONG(0)
__CTOR_END__ = .;
__DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
*(.dtors)
LONG(0)
__DTOR_END__ = .;
etext = .;
_etext = .;
} >rom
.eh_fram : {
. = ALIGN (16);
*(.eh_fram)
} >ram
.gcc_exc : {
. = ALIGN (16);
*(.gcc_exc)
} >ram
/*
* On-chip memory/peripherals
*
*/
dpram : {
m340 = .;
_m340 = .;
. += (8 * 1024);
} >ram
.data : {
copy_start = .;
*(.data)
. = ALIGN (16);
_edata = .;
copy_end = .;
} >ram
.bss : {
M68Kvec = .;
_M68Kvec = .;
. += (256 * 4);
clear_start = .;
*(.bss)
*(COMMON)
. = ALIGN (16);
_end = .;
_HeapStart = .;
__HeapStart = .;
. += HeapSize; /* XXX -- Old gld can't handle this */
. += StackSize; /* XXX -- Old gld can't handle this */
/* . += 0x10000; */ /* HeapSize for old gld */
/* . += 0x1000; */ /* StackSize for old gld */
. = ALIGN (16);
stack_init = .;
clear_end = .;
_WorkspaceBase = .;
__WorkspaceBase = .;
} >ram
}

54
c/src/lib/libbsp/m68k/gen68340/timer/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGM=${ARCH}/timer.rel
# C source names, if any, go here -- minus the .c
C_PIECES=timer
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
SRCS=$(C_FILES) $(H_FILES)
OBJS=$(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${SRCS} ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(PGM)
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
install: all

287
c/src/lib/libbsp/m68k/gen68340/timer/timer.c Normal file
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/*
* Timer_init()
*
* ATTENTION: AS MC68349 has no built-in Timer, the following code doesn't work
* in a MC68349. You can't use FIFO full mode for the moment, but
* it should be easy to fix this by using an external timer
*
* Use TIMER 1 for TIMEOUT when using FIFO FULL mode in UART driver
* Use TIMER 2 for timing test suites
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* $Id$
*/
/*
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* NOTE: It is important that the timer start/stop overhead be
* determined when porting or modifying this code.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*/
#include <rtems.h>
#include <bsp.h>
#include <m340uart.h>
#include <m340timer.h>
#include <m68340.h>
#define TIMER1_VECTOR 122
#define TIMER1_IRQ_LEVEL 5
#define TIMER1_INTERRUPT_ARBITRATION 5
#define TIMER2_VECTOR 123
#define TIMER2_IRQ_LEVEL 4
#define TIMER2_INTERRUPT_ARBITRATION 4
#define CLOCK_SPEED 25 /* in Mhz */
#define max(a,b) (((a)>(b)) ? (a) : (b))
void (*Restart_Fifo_Full_A_Timer)();
void (*Restart_Check_A_Timer)();
void (*Restart_Fifo_Full_B_Timer)();
void (*Restart_Check_B_Timer)();
int preload = 0;
/******************************************************
Name: __Restart_Fifo_Full_Timer
Input parameters: -
Output parameters: -
Description: when a character is received, sets
the TIMER to raise an interrupt at
TIMEOUT.
It's necessary to prevent from not
getting n-1 characters (with n the
Uart Fifo size)
*****************************************************/
void __Restart_Fifo_Full_Timer (void)
{
TSR1 |= m340_TO;
TCR1 &= ~m340_CPE;
WPREL11 = preload;
TCR1 |= m340_CPE;
}
/******************************************************
Name: __Restart_Fifo_Full_Timer
Input parameters: -
Output parameters: -
Description: when no character has been received
recently, check now and then if whether
a there's a character in the FIFO
*****************************************************/
void __Restart_Check_Timer (void)
{
TSR1 |= m340_TO;
TCR1 &= ~m340_CPE;
WPREL11 = 0xFFFF;
TCR1 |= m340_CPE;
}
/******************************************************
Name: __do_nothing
Input parameters: -
Output parameters: -
Description: we always restart the fifo full timer
with a call to Restart_*_Timer
if we do not use FIFO full, Restart_*_Timer
are set to do __do_nothing
*****************************************************/
void __do_nothing (void)
{
}
#define Fifo_Full_on_A (m340_uart_config[UART_CHANNEL_A].rx_mode==UART_FIFO_FULL && m340_uart_config[UART_CHANNEL_A].enable && m340_uart_config[UART_CHANNEL_A].mode==UART_INTERRUPTS)
#define Fifo_Full_on_B (m340_uart_config[UART_CHANNEL_B].rx_mode==UART_FIFO_FULL && m340_uart_config[UART_CHANNEL_B].enable && m340_uart_config[UART_CHANNEL_B].mode==UART_INTERRUPTS)
/******************************************************
Name: Fifo_Full_Timer_initialize
Input parameters: -
Output parameters: -
Description: initialize Timer 1 for FIFO full mode
*****************************************************/
void Fifo_Full_Timer_initialize (void)
{
float max_baud_rate;
int prescaler_output_tap = -1;
int nb_of_clock_ticks = 0;
/*
* USE TIMER 1 for UART FIFO FULL mode
*/
if ( Fifo_Full_on_A || Fifo_Full_on_B )
{
/* Disable the timer */
TCR1 &= ~m340_SWR;
/* Reset the interrupts */
TSR1 &= ~(m340_TO | m340_TG | m340_TC);
/* Init the stop bit for normal operation, ignore FREEZE, user privileges,
set interrupt arbitration */
TMCR1 = TIMER1_INTERRUPT_ARBITRATION;
/* interrupt priority level and interrupt vector */
TIR1 = TIMER1_VECTOR | (TIMER1_IRQ_LEVEL << 8);
/* compute prescaler */
if ( Fifo_Full_on_A && Fifo_Full_on_B)
max_baud_rate = max(m340_uart_config[UART_CHANNEL_A].rx_baudrate, m340_uart_config[UART_CHANNEL_B].rx_baudrate);
else if ( Fifo_Full_on_A )
max_baud_rate = m340_uart_config[UART_CHANNEL_A].rx_baudrate;
else max_baud_rate = m340_uart_config[UART_CHANNEL_B].rx_baudrate;
/* find out config */
nb_of_clock_ticks = (10/max_baud_rate)*(CLOCK_SPEED*1000000)*1.2;
if (nb_of_clock_ticks < 0xFFFF) {
preload = nb_of_clock_ticks;
prescaler_output_tap = -1;
} else if (nb_of_clock_ticks/2 < 0xFFFF) {
preload = nb_of_clock_ticks/2;
prescaler_output_tap = m340_Divide_by_2;
} else if (nb_of_clock_ticks/4 < 0xFFFF) {
preload = nb_of_clock_ticks/4;
prescaler_output_tap = m340_Divide_by_4;
} else if (nb_of_clock_ticks/8 < 0xFFFF) {
preload = nb_of_clock_ticks/8;
prescaler_output_tap = m340_Divide_by_16;
} else if (nb_of_clock_ticks/16 < 0xFFFF) {
preload = nb_of_clock_ticks/16;
prescaler_output_tap = m340_Divide_by_16;
} else if (nb_of_clock_ticks/32 < 0xFFFF) {
preload = nb_of_clock_ticks/32;
prescaler_output_tap = m340_Divide_by_32;
} else if (nb_of_clock_ticks/64 < 0xFFFF) {
preload = nb_of_clock_ticks/64;
prescaler_output_tap = m340_Divide_by_64;
} else if (nb_of_clock_ticks/128 < 0xFFFF) {
preload = nb_of_clock_ticks/128;
prescaler_output_tap = m340_Divide_by_128;
} else if (nb_of_clock_ticks/256 < 0xFFFF) {
preload = nb_of_clock_ticks/256;
prescaler_output_tap = m340_Divide_by_256;
}
/* Input Capture/Output Compare (ICOC) */
TCR1 = m340_SWR | m340_TO_Enabled | m340_ICOC;
if (prescaler_output_tap!=-1) TCR1 |= prescaler_output_tap | m340_PSE;
/* install interrupt vector */
{
rtems_isr_entry old_handler;
rtems_status_code sc;
proc_ptr ignored;
extern void _Debug_ISR_Handler_Console(void);
sc = rtems_interrupt_catch (InterruptHandler,
TIMER1_VECTOR,
&old_handler);
/* uncomment this if you want to pass control to your own ISR handler
it may be usefull to do so to check for performances with an oscilloscope */
/*
_CPU_ISR_install_raw_handler( TIMER1_VECTOR, _Debug_ISR_Handler_Console, &ignored );
*/
}
} /* fifo full mode on a uart */
/* install routines */
Restart_Check_A_Timer = Fifo_Full_on_A ? __Restart_Check_Timer : __do_nothing;
Restart_Fifo_Full_A_Timer = Fifo_Full_on_A ? __Restart_Fifo_Full_Timer : __do_nothing;
Restart_Check_B_Timer = Fifo_Full_on_B ? __Restart_Check_Timer : __do_nothing;
Restart_Fifo_Full_B_Timer = Fifo_Full_on_B ? __Restart_Fifo_Full_Timer : __do_nothing;
/* start checking timer */
Restart_Check_A_Timer();
Restart_Check_B_Timer();
}
/******************************************************
Name: Timer_initialize
Input parameters: -
Output parameters: -
Description: init Timer for timing test suites
*****************************************************/
void Timer_initialize (void)
{
/* Disable the timer */
TCR2 &= ~m340_SWR;
/* Reset the interrupts */
TSR2 &= ~(m340_TO | m340_TG | m340_TC);
/* Init the stop bit for normal operation, ignore FREEZE, user privileges,
set interrupt arbitration */
TMCR1 = TIMER2_INTERRUPT_ARBITRATION;
/* interrupt priority level and interrupt vector */
TIR1 = TIMER2_VECTOR | (TIMER2_IRQ_LEVEL << 8);
/* Init the stop bit for normal operation, ignore FREEZE, user privileges,
set interrupt arbitration */
TMCR2 = TIMER2_INTERRUPT_ARBITRATION;
/* Preload register 1 */
WPREL21 = 0xFFFF;
/* Input Capture/Output Compare (ICOC) */
TCR2 = m340_SWR | m340_ICOC | m340_PSE | m340_Divide_by_16 | m340_CPE;
}
/******************************************************
Name: Read_timer
Input parameters: -
Output parameters: -
Description: Return timer value in microsecond units
*****************************************************/
int
Read_timer (void)
{
/* there's CLOCK_SPEED / 16 micro seconds between two timer register decrement */
return (((0xFFFF - TCNTR2) * CLOCK_SPEED) / 16);
}
/******************************************************
Name: Empty_function
Input parameters: -
Output parameters: -
Description: Empty function call used in loops to
measure basic cost of looping
in Timing Test Suite.
*****************************************************/
rtems_status_code
Empty_function (void)
{
return RTEMS_SUCCESSFUL;
}
/******************************************************
Name: Set_find_average_overhead
Input parameters: -
Output parameters: -
Description: -
*****************************************************/
void
Set_find_average_overhead(rtems_boolean find_flag)
{
}