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bsp/arm: Correct L2 cache enable method

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This commit is contained in:
Ralf Kirchner
2014-04-17 11:22:53 +02:00
committed by Sebastian Huber
parent 62fa1ea25e
commit 127634c358
1 changed files with 47 additions and 52 deletions
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15
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
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@@ -1275,9 +1275,12 @@ static inline void
cache_l2c_310_enable( void ) cache_l2c_310_enable( void )
{ {
volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE; volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
uint32_t cache_id = l2cc->cache_id & CACHE_L2C_310_L2CC_ID_PART_MASK;
int ways = 0;
/* Only enable if L2CC is currently disabled */
if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {
uint32_t cache_id =
l2cc->cache_id & CACHE_L2C_310_L2CC_ID_PART_MASK;
int ways = 0;
/* Do we actually have an L2C-310 cache controller? /* Do we actually have an L2C-310 cache controller?
* Has BSP_ARM_L2CC_BASE been configured correctly? */ * Has BSP_ARM_L2CC_BASE been configured correctly? */
@@ -1323,14 +1326,8 @@ cache_l2c_310_enable( void )
} }
if ( ways > 0 ) { if ( ways > 0 ) {
/* Only enable if L2CC is currently disabled */
if ( ways != 0
&& ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {
rtems_interrupt_level level;
uint32_t aux; uint32_t aux;
rtems_interrupt_disable( level );
/* Set up the way size */ /* Set up the way size */
aux = l2cc->aux_ctrl; aux = l2cc->aux_ctrl;
aux &= CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK; /* Set way_size to 0 */ aux &= CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK; /* Set way_size to 0 */
@@ -1362,8 +1359,6 @@ cache_l2c_310_enable( void )
/* Enable the L2CC */ /* Enable the L2CC */
l2cc->ctrl |= CACHE_L2C_310_L2CC_ENABLE_MASK; l2cc->ctrl |= CACHE_L2C_310_L2CC_ENABLE_MASK;
rtems_interrupt_enable( level );
} }
} }
} }