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2002-05-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>

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* rtems/score/ppc.h: Remove PPC_DEBUG_MODEL.
This commit is contained in:
Joel Sherrill
2002-05-14 18:31:37 +00:00
parent bd9265df54
commit 0fe89f6a5f
4 changed files with 8 additions and 92 deletions
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4
c/src/exec/score/cpu/powerpc/ChangeLog
View File

@@ -1,3 +1,7 @@
2002-05-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* rtems/score/ppc.h: Remove PPC_DEBUG_MODEL.
2001-05-14 Till Straumann <strauman@slac.stanford.edu> 2001-05-14 Till Straumann <strauman@slac.stanford.edu>
* rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add * rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add

46
c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
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@@ -64,7 +64,6 @@ extern "C" {
* The following architectural feature definitions are defaulted * The following architectural feature definitions are defaulted
* unless specifically set by the model definition: * unless specifically set by the model definition:
* *
* + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD
* + PPC_INTERRUPT_MAX - 16 * + PPC_INTERRUPT_MAX - 16
* + PPC_CACHE_ALIGNMENT - 32 * + PPC_CACHE_ALIGNMENT - 32
* + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE
@@ -75,18 +74,6 @@ extern "C" {
* + PPC_USE_MULTIPLE - 0 * + PPC_USE_MULTIPLE - 0
*/ */
/*
* Define the debugging assistance models found in the PPC family.
*
* Standard: single step and branch trace
* Single Step Only: single step only
* IBM 4xx: debug exception
*/
#define PPC_DEBUG_MODEL_STANDARD 1
#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
#define PPC_DEBUG_MODEL_IBM4xx 3
/* /*
* Define the low power mode models * Define the low power mode models
* *
@@ -125,7 +112,6 @@ extern "C" {
#define PPC_I_CACHE 2048 #define PPC_I_CACHE 2048
#define PPC_D_CACHE 1024 #define PPC_D_CACHE 1024
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx
#define PPC_HAS_EXCEPTION_PREFIX 0 #define PPC_HAS_EXCEPTION_PREFIX 0
#define PPC_HAS_EVPR 1 #define PPC_HAS_EVPR 1
@@ -169,8 +155,6 @@ extern "C" {
#define PPC_I_CACHE 0 #define PPC_I_CACHE 0
#define PPC_D_CACHE 32768 #define PPC_D_CACHE 32768
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
#elif defined(ppc602) #elif defined(ppc602)
/* /*
* Submitted with original port -- book checked only. * Submitted with original port -- book checked only.
@@ -372,15 +356,6 @@ extern "C" {
#define PPC_ASM PPC_ASM_ELF #define PPC_ASM PPC_ASM_ELF
#endif #endif
/*
* Use the default debug scheme defined in the architectural specification
* if another model has not been specified.
*/
#ifndef PPC_DEBUG_MODEL
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
#endif
/* /*
* If the maximum number of exception sources has not been defined, * If the maximum number of exception sources has not been defined,
* then default it to 16. * then default it to 16.
@@ -731,27 +706,6 @@ extern "C" {
#define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ #define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */
#endif #endif
/*
* Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
* Environments" and the manuals for various PPC models.
*/
#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */
#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */
#define PPC_MSR_SE 0x000000400 /* bit 21 - single step trace enable */
#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */
#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */
#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */
#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
#define PPC_MSR_DE 0x000000200 /* bit 22 - debug exception enable */
#define PPC_MSR_BE 0x000000000 /* bit 22 - branch trace enable */
#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */
#else
#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
#endif
#define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ #define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */
#define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ #define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */

4
cpukit/score/cpu/powerpc/ChangeLog
View File

@@ -1,3 +1,7 @@
2002-05-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* rtems/score/ppc.h: Remove PPC_DEBUG_MODEL.
2001-05-14 Till Straumann <strauman@slac.stanford.edu> 2001-05-14 Till Straumann <strauman@slac.stanford.edu>
* rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add * rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add

46
cpukit/score/cpu/powerpc/rtems/score/ppc.h
View File

@@ -64,7 +64,6 @@ extern "C" {
* The following architectural feature definitions are defaulted * The following architectural feature definitions are defaulted
* unless specifically set by the model definition: * unless specifically set by the model definition:
* *
* + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD
* + PPC_INTERRUPT_MAX - 16 * + PPC_INTERRUPT_MAX - 16
* + PPC_CACHE_ALIGNMENT - 32 * + PPC_CACHE_ALIGNMENT - 32
* + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE
@@ -75,18 +74,6 @@ extern "C" {
* + PPC_USE_MULTIPLE - 0 * + PPC_USE_MULTIPLE - 0
*/ */
/*
* Define the debugging assistance models found in the PPC family.
*
* Standard: single step and branch trace
* Single Step Only: single step only
* IBM 4xx: debug exception
*/
#define PPC_DEBUG_MODEL_STANDARD 1
#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
#define PPC_DEBUG_MODEL_IBM4xx 3
/* /*
* Define the low power mode models * Define the low power mode models
* *
@@ -125,7 +112,6 @@ extern "C" {
#define PPC_I_CACHE 2048 #define PPC_I_CACHE 2048
#define PPC_D_CACHE 1024 #define PPC_D_CACHE 1024
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx
#define PPC_HAS_EXCEPTION_PREFIX 0 #define PPC_HAS_EXCEPTION_PREFIX 0
#define PPC_HAS_EVPR 1 #define PPC_HAS_EVPR 1
@@ -169,8 +155,6 @@ extern "C" {
#define PPC_I_CACHE 0 #define PPC_I_CACHE 0
#define PPC_D_CACHE 32768 #define PPC_D_CACHE 32768
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
#elif defined(ppc602) #elif defined(ppc602)
/* /*
* Submitted with original port -- book checked only. * Submitted with original port -- book checked only.
@@ -372,15 +356,6 @@ extern "C" {
#define PPC_ASM PPC_ASM_ELF #define PPC_ASM PPC_ASM_ELF
#endif #endif
/*
* Use the default debug scheme defined in the architectural specification
* if another model has not been specified.
*/
#ifndef PPC_DEBUG_MODEL
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
#endif
/* /*
* If the maximum number of exception sources has not been defined, * If the maximum number of exception sources has not been defined,
* then default it to 16. * then default it to 16.
@@ -731,27 +706,6 @@ extern "C" {
#define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ #define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */
#endif #endif
/*
* Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
* Environments" and the manuals for various PPC models.
*/
#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */
#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */
#define PPC_MSR_SE 0x000000400 /* bit 21 - single step trace enable */
#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */
#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */
#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */
#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
#define PPC_MSR_DE 0x000000200 /* bit 22 - debug exception enable */
#define PPC_MSR_BE 0x000000000 /* bit 22 - branch trace enable */
#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */
#else
#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
#endif
#define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ #define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */
#define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ #define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */