diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index 9d2f8110c6..765b4ab280 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,3 +1,7 @@
+2011-12-09	Jennifer Averett
+
+	* cpu.c: Correct typo.
+
 2011-09-27	Sebastian Huber <sebastian.huber@embedded-brains.de>
 
 	PR 1914/cpukit
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index c4b8dce4a7..4e41c91013 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -195,7 +195,7 @@ void _CPU_ISR_install_raw_handler(
    *  table used by the CPU to dispatch interrupt handlers.
    *
    *  Because all interrupts are vectored through the same exception handler
-   *  this is not necessary on thi sport.
+   *  this is not necessary on this port.
    */
 }