From 0f55591fd6c4a12fa4e7319a79c384e036e5aaa0 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 28 Aug 2024 04:19:39 +0200 Subject: [PATCH] bsps: Option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM GIC support. Enable this option for arm/altera-cyclone-v and arm/xilinx-zynq BSPs by default. --- bsps/arm/altera-cyclone-v/include/bsp.h | 2 -- bsps/shared/dev/irq/arm-gicv2.c | 14 ++++----- spec/build/bsps/dev/irq/objarmgicv2.yml | 2 ++ spec/build/bsps/dev/irq/objarmgicv3.yml | 2 ++ .../irq/optarmgic-enable-fiq-for-group-0.yml | 31 +++++++++++++++++++ 5 files changed, 42 insertions(+), 9 deletions(-) create mode 100644 spec/build/bsps/dev/irq/optarmgic-enable-fiq-for-group-0.yml diff --git a/bsps/arm/altera-cyclone-v/include/bsp.h b/bsps/arm/altera-cyclone-v/include/bsp.h index 6bea17ed20..65bcd28b05 100644 --- a/bsps/arm/altera-cyclone-v/include/bsp.h +++ b/bsps/arm/altera-cyclone-v/include/bsp.h @@ -60,8 +60,6 @@ extern "C" { #define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000 -#define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 - #define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 ) #define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 ) diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c index fa1ac48ab3..577ec162c1 100644 --- a/bsps/shared/dev/irq/arm-gicv2.c +++ b/bsps/shared/dev/irq/arm-gicv2.c @@ -56,18 +56,18 @@ /* * The following variants * - * - GICv1 with Security Extensions, - * - GICv2 without Security Extensions, or - * - within Secure processor mode + * - GICv1 with Security Extensions, + * - GICv2 without Security Extensions, and + * - GICv2 with Security Extensions and in Secure processor mode * * have the ability to assign group 0 or 1 to individual interrupts. Group * 0 interrupts can be configured to raise an FIQ exception. This enables * the use of NMIs with respect to RTEMS. * - * BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 - * define. Use arm_gic_irq_set_group() to change the group of an - * interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is - * defined). + * Use arm_gic_irq_set_group() to change the group of an interrupt (default + * group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined). To use FIQ + * interrupts, you have to install an FIQ exception handler and enable FIQs in + * the Current Program Status Register (CPSR). */ #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 #define DIST_ICDDCR (GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE) diff --git a/spec/build/bsps/dev/irq/objarmgicv2.yml b/spec/build/bsps/dev/irq/objarmgicv2.yml index d63626c919..74621c42cc 100644 --- a/spec/build/bsps/dev/irq/objarmgicv2.yml +++ b/spec/build/bsps/dev/irq/objarmgicv2.yml @@ -15,6 +15,8 @@ install: - bsps/include/dev/irq/arm-gic-regs.h - bsps/include/dev/irq/arm-gic-tm27.h links: +- role: build-dependency + uid: optarmgic-enable-fiq-for-group-0 - role: build-dependency uid: grpaarch64gic - role: build-dependency diff --git a/spec/build/bsps/dev/irq/objarmgicv3.yml b/spec/build/bsps/dev/irq/objarmgicv3.yml index 3ef283407f..371caef820 100644 --- a/spec/build/bsps/dev/irq/objarmgicv3.yml +++ b/spec/build/bsps/dev/irq/objarmgicv3.yml @@ -16,6 +16,8 @@ install: - bsps/include/dev/irq/arm-gic-tm27.h - bsps/include/dev/irq/arm-gicv3.h links: +- role: build-dependency + uid: optarmgic-enable-fiq-for-group-0 - role: build-dependency uid: optarmgic-icc-bpr0 - role: build-dependency diff --git a/spec/build/bsps/dev/irq/optarmgic-enable-fiq-for-group-0.yml b/spec/build/bsps/dev/irq/optarmgic-enable-fiq-for-group-0.yml new file mode 100644 index 0000000000..faab8385b4 --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-enable-fiq-for-group-0.yml @@ -0,0 +1,31 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: + - bsps/arm/altera-cyclone-v + - bsps/arm/xilinx-zynq + value: true +- enabled-by: true + value: false +description: | + This option enables the use FIQ interrupts for GIC group 0 interrupts. The + ARM Generic Interrupt Controller (GIC) variants GICv1 with Security + Extensions, GICv2 without Security Extensions, GICv2 with Security Extensions + and in Secure processor mode, GICv3 and GICv4 in Secure processor mode, GICv3 + and GICv4 with GICD_CTLR.DS == 1 have the ability to assign group 0 or 1 to + individual interrupts. Group 0 interrupts can be configured to raise an FIQ + exception. This enables the use of NMIs with respect to RTEMS. Use + arm_gic_irq_set_group() to change the group of an interrupt (default group is + 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined). To use FIQ interrupts, + you have to install an FIQ exception handler and enable FIQs in the Current + Program Status Register (CPSR). +enabled-by: true +format: '{}' +links: [] +name: BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 +type: build