PR 1993 - Convert MIPS to PIC IRQ model

c/src/lib/libbsp/mips/ChangeLog

@@ -1,3 +1,28 @@
+2012-03-07	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* shared/irq/irq.c: Fixed unhandled interrupts to print
+	the registers and shutdown. This prevents a loop of 
+	unusable information from occuring.
+
+2012-03-06	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* shared/clock/clockdrv.c, shared/irq/vectorexceptions.c,
+	../shared/clockdrv_shell.h: Changed interrupt call, removed warnings
+	and did cleanup.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* shared/irq/interruptmask.c, 
+	shared/irq/interruptmask_TX49.c,
+	shared/irq/irq.c, shared/irq/maxvectors.c,
+	shared/irq/vectorexceptions.c:
+	Mips conversion to PIC IRQ model.
+	* shared/irq/interruptmask.c, 
+	shared/irq/interruptmask_TX49.c, 
+	shared/irq/irq.c: New files.
+
 2011-02-02	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* configure.ac: Require autoconf-2.68, automake-1.11.1.

c/src/lib/libbsp/mips/csb350/ChangeLog

@@ -1,3 +1,23 @@
+2012-03-08	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
+
+2012-03-06	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* clock/clockdrv.c, include/bsp.h, include/irq.h,
+	irq/vectorisrs.c, startup/bspstart.c:
+	Changed interrupt call, removed warnings and did cleanup.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* Makefile.am, clock/clockdrv.c, include/irq.h,
+	irq/vectorisrs.c,network/network.c,
+	preinstall.am, startup/bspstart.c:
+	Mips conversion to PIC IRQ model.
+	* include/irq.h, irq/vectorisrs.c: New files.
+
 2011-12-14	Joel Sherrill <joel.sherrilL@OARcorp.com>
 
 	* Makefile.am: Change to one file per line. Clean up.

c/src/lib/libbsp/mips/csb350/Makefile.am

@@ -13,6 +13,10 @@ dist_project_lib_DATA = bsp_specs
 include_HEADERS = include/bsp.h
 include_HEADERS += include/tm27.h
 include_bsp_HEADERS = ../shared/liblnk/regs.h
+#isr
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += include/irq.h
 
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -41,8 +45,6 @@ libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
 libbsp_a_SOURCES += startup/bspstart.c
 libbsp_a_SOURCES += ../../shared/bootcard.c
 libbsp_a_SOURCES += ../../shared/sbrk.c
-libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
-libbsp_a_SOURCES += ../../shared/setvec.c
 # clock
 libbsp_a_SOURCES += clock/clockdrv.c
 libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
@@ -51,6 +53,17 @@ libbsp_a_SOURCES += console/console-io.c
 libbsp_a_SOURCES += ../../shared/console-polled.c
 # timer
 libbsp_a_SOURCES += timer/timer.c
+#isr
+libbsp_a_SOURCES += ../../shared/src/irq-generic.c
+libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
+libbsp_a_SOURCES += ../../shared/src/irq-info.c
+libbsp_a_SOURCES += ../../shared/src/irq-shell.c
+libbsp_a_SOURCES += ../../shared/src/irq-server.c
+libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
+libbsp_a_SOURCES += ../shared/irq/irq.c
+libbsp_a_SOURCES += ../shared/irq/maxvectors.c
+libbsp_a_SOURCES += irq/vectorisrs.c
+libbsp_a_SOURCES += ../shared/irq/interruptmask.c
 
 if HAS_NETWORKING
 network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
@@ -62,7 +75,7 @@ endif
 
 libbsp_a_LIBADD  = ../../../libcpu/mips/shared/cache.rel
 libbsp_a_LIBADD += ../../../libcpu/mips/shared/interrupts.rel
-libbsp_a_LIBADD += ../../../libcpu/mips/au1x00/vectorisrs.rel
+
 if HAS_NETWORKING
 libbsp_a_LIBADD += network.rel
 endif

c/src/lib/libbsp/mips/csb350/bsp_specs

@@ -4,7 +4,7 @@
 
 *startfile:
 %{!qrtems: %(old_startfile)} \
-%{!nostdlib: %{qrtems: start.o%s crtbegin.o%s -e _start}}
+%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}}
 
 *link:
 %(old_link) %{qrtems: -dc -dp -N}

c/src/lib/libbsp/mips/csb350/clock/clockdrv.c

@@ -1,8 +1,12 @@
-/*
+/**
+ *  @file
+ *  
  *  Instantiate the clock driver shell.
  *
  *  This uses the TOY (Time of Year) timer to implement the clock.
- *
+ */
+
+/*
  *  Copyright (c) 2005 by Cogent Computer Systems
  *  Written by Jay Monkman <jtm@lopingdog.com>
  *
@@ -15,12 +19,14 @@
 
 #include <rtems.h>
 #include <bsp.h>
-#include <libcpu/au1x00.h>
+#include <bsp/irq.h>
 #include <rtems/bspIo.h>
 
 uint32_t tick_interval;
 uint32_t last_match;
 
+void au1x00_clock_init(void);
+
 #define CLOCK_VECTOR AU1X00_IRQ_TOY_MATCH2
 
 #define Clock_driver_support_at_tick()                        \
@@ -34,7 +40,13 @@ uint32_t last_match;
 /* Set for rising edge interrupt */
 #define Clock_driver_support_install_isr( _new, _old )  \
   do {                                                  \
-        _old = set_vector( _new, AU1X00_IRQ_TOY_MATCH2, 1 );     \
+    rtems_interrupt_handler_install( \
+      CLOCK_VECTOR, \
+      "clock", \
+      0, \
+      _new, \
+      NULL \
+    ); \
     AU1X00_IC_MASKCLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
     AU1X00_IC_SRCSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
     AU1X00_IC_CFG0SET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \

c/src/lib/libbsp/mips/csb350/include/bsp.h

@@ -1,9 +1,12 @@
-/*  bsp.h
+/**
+ *  @file
  *  
  *  This include file contains some definitions specific to the
  *  Cogent CSB350 Board.
- *
+ */
- *  COPYRIGHT (c) 1989-2000.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -28,6 +31,8 @@ extern "C" {
 #include <rtems/clockdrv.h>
 #include <libcpu/au1x00.h>
 
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
 
 /*
  * Network driver configuration

c/src/lib/libbsp/mips/csb350/include/irq.h

@@ -0,0 +1,125 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#ifndef LIBBSP_MIPS_AU1X00_IRQ_H
+#define LIBBSP_MIPS_AU1X00_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ */
+/* MIPS_INTERRUPT_BASE should be 32 (0x20) */
+#define BSP_INTERRUPT_VECTOR_MIN      0
+#define AU1X00_IRQ_SW0                (MIPS_INTERRUPT_BASE + 0)
+#define AU1X00_IRQ_SW1                (MIPS_INTERRUPT_BASE + 1)
+#define AU1X00_IRQ_IC0_REQ0           (MIPS_INTERRUPT_BASE + 2)
+#define AU1X00_IRQ_IC0_REQ1           (MIPS_INTERRUPT_BASE + 3)
+#define AU1X00_IRQ_IC1_REQ0           (MIPS_INTERRUPT_BASE + 4)
+#define AU1X00_IRQ_IC1_REQ1           (MIPS_INTERRUPT_BASE + 5)
+#define AU1X00_IRQ_PERF               (MIPS_INTERRUPT_BASE + 6)
+#define AU1X00_IRQ_CNT                (MIPS_INTERRUPT_BASE + 7)
+
+#define AU1X00_IRQ_IC0_BASE           (MIPS_INTERRUPT_BASE + 8)
+#define AU1X00_IRQ_UART0              (MIPS_INTERRUPT_BASE + 8)
+#define AU1X00_IRQ_INTA               (MIPS_INTERRUPT_BASE + 9)
+#define AU1X00_IRQ_INTB               (MIPS_INTERRUPT_BASE + 10)
+#define AU1X00_IRQ_UART3              (MIPS_INTERRUPT_BASE + 11)
+#define AU1X00_IRQ_INTC               (MIPS_INTERRUPT_BASE + 12)
+#define AU1X00_IRQ_INTD               (MIPS_INTERRUPT_BASE + 13)
+#define AU1X00_IRQ_DMA0               (MIPS_INTERRUPT_BASE + 14)
+#define AU1X00_IRQ_DMA1               (MIPS_INTERRUPT_BASE + 15)
+#define AU1X00_IRQ_DMA2               (MIPS_INTERRUPT_BASE + 16)
+#define AU1X00_IRQ_DMA3               (MIPS_INTERRUPT_BASE + 17)
+#define AU1X00_IRQ_DMA4               (MIPS_INTERRUPT_BASE + 18)
+#define AU1X00_IRQ_DMA5               (MIPS_INTERRUPT_BASE + 19)
+#define AU1X00_IRQ_DMA6               (MIPS_INTERRUPT_BASE + 20)
+#define AU1X00_IRQ_DMA7               (MIPS_INTERRUPT_BASE + 21)
+#define AU1X00_IRQ_TOY_TICK           (MIPS_INTERRUPT_BASE + 22)
+#define AU1X00_IRQ_TOY_MATCH0         (MIPS_INTERRUPT_BASE + 23)
+#define AU1X00_IRQ_TOY_MATCH1         (MIPS_INTERRUPT_BASE + 24)
+#define AU1X00_IRQ_TOY_MATCH2         (MIPS_INTERRUPT_BASE + 25)
+#define AU1X00_IRQ_RTC_TICK           (MIPS_INTERRUPT_BASE + 26)
+#define AU1X00_IRQ_RTC_MATCH0         (MIPS_INTERRUPT_BASE + 27)
+#define AU1X00_IRQ_RTC_MATCH1         (MIPS_INTERRUPT_BASE + 28)
+#define AU1X00_IRQ_RTC_MATCH2         (MIPS_INTERRUPT_BASE + 29)
+#define AU1X00_IRQ_PCI_ERR            (MIPS_INTERRUPT_BASE + 30)
+#define AU1X00_IRQ_RSV0               (MIPS_INTERRUPT_BASE + 31)
+#define AU1X00_IRQ_USB_DEV            (MIPS_INTERRUPT_BASE + 32)
+#define AU1X00_IRQ_USB_SUSPEND        (MIPS_INTERRUPT_BASE + 33)
+#define AU1X00_IRQ_USB_HOST           (MIPS_INTERRUPT_BASE + 34)
+#define AU1X00_IRQ_AC97_ACSYNC        (MIPS_INTERRUPT_BASE + 35)
+#define AU1X00_IRQ_MAC0               (MIPS_INTERRUPT_BASE + 36)
+#define AU1X00_IRQ_MAC1               (MIPS_INTERRUPT_BASE + 37)
+#define AU1X00_IRQ_RSV1               (MIPS_INTERRUPT_BASE + 38)
+#define AU1X00_IRQ_AC97_CMD           (MIPS_INTERRUPT_BASE + 39)
+
+#define AU1X00_IRQ_IC1_BASE           (MIPS_INTERRUPT_BASE + 40)
+#define AU1X00_IRQ_GPIO0              (MIPS_INTERRUPT_BASE + 40)
+#define AU1X00_IRQ_GPIO1              (MIPS_INTERRUPT_BASE + 41)
+#define AU1X00_IRQ_GPIO2              (MIPS_INTERRUPT_BASE + 42)
+#define AU1X00_IRQ_GPIO3              (MIPS_INTERRUPT_BASE + 43)
+#define AU1X00_IRQ_GPIO4              (MIPS_INTERRUPT_BASE + 44)
+#define AU1X00_IRQ_GPIO5              (MIPS_INTERRUPT_BASE + 45)
+#define AU1X00_IRQ_GPIO6              (MIPS_INTERRUPT_BASE + 46)
+#define AU1X00_IRQ_GPIO7              (MIPS_INTERRUPT_BASE + 47)
+#define AU1X00_IRQ_GPIO8              (MIPS_INTERRUPT_BASE + 48)
+#define AU1X00_IRQ_GPIO9              (MIPS_INTERRUPT_BASE + 49)
+#define AU1X00_IRQ_GPIO10             (MIPS_INTERRUPT_BASE + 50)
+#define AU1X00_IRQ_GPIO11             (MIPS_INTERRUPT_BASE + 51)
+#define AU1X00_IRQ_GPIO12             (MIPS_INTERRUPT_BASE + 52)
+#define AU1X00_IRQ_GPIO13             (MIPS_INTERRUPT_BASE + 53)
+#define AU1X00_IRQ_GPIO14             (MIPS_INTERRUPT_BASE + 54)
+#define AU1X00_IRQ_GPIO15             (MIPS_INTERRUPT_BASE + 55)
+#define AU1X00_IRQ_GPIO200            (MIPS_INTERRUPT_BASE + 56)
+#define AU1X00_IRQ_GPIO201            (MIPS_INTERRUPT_BASE + 57)
+#define AU1X00_IRQ_GPIO202            (MIPS_INTERRUPT_BASE + 58)
+#define AU1X00_IRQ_GPIO203            (MIPS_INTERRUPT_BASE + 59)
+#define AU1X00_IRQ_GPIO20             (MIPS_INTERRUPT_BASE + 60)
+#define AU1X00_IRQ_GPIO204            (MIPS_INTERRUPT_BASE + 61)
+#define AU1X00_IRQ_GPIO205            (MIPS_INTERRUPT_BASE + 62)
+#define AU1X00_IRQ_GPIO23             (MIPS_INTERRUPT_BASE + 63)
+#define AU1X00_IRQ_GPIO24             (MIPS_INTERRUPT_BASE + 64)
+#define AU1X00_IRQ_GPIO25             (MIPS_INTERRUPT_BASE + 65)
+#define AU1X00_IRQ_GPIO26             (MIPS_INTERRUPT_BASE + 66)
+#define AU1X00_IRQ_GPIO27             (MIPS_INTERRUPT_BASE + 67)
+#define AU1X00_IRQ_GPIO28             (MIPS_INTERRUPT_BASE + 68)
+#define AU1X00_IRQ_GPIO206            (MIPS_INTERRUPT_BASE + 69)
+#define AU1X00_IRQ_GPIO207            (MIPS_INTERRUPT_BASE + 70)
+#define AU1X00_IRQ_GPIO208_215        (MIPS_INTERRUPT_BASE + 71)
+
+#define AU1X00_MAXIMUM_VECTORS        (MIPS_INTERRUPT_BASE + 72)
+
+#define BSP_INTERRUPT_VECTOR_MAX      AU1X00_MAXIMUM_VECTORS 
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_AU1X00_IRQ_H */

c/src/lib/libbsp/mips/csb350/irq/vectorisrs.c

@@ -0,0 +1,170 @@
+/**
+ *  @file
+ *  
+ *  Au1x00 Interrupt Vectoring
+ */
+
+/*
+ *  Copyright (c) 2005 by Cogent Computer Systems
+ *  Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/au1x00.h>
+#include <rtems/irq.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
+static void call_vectored_isr(CPU_Interrupt_frame *, uint32_t , void *);
+
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  cause &= (sr & SR_IMASK);
+  cause >>= CAUSE_IPSHIFT;
+
+  /* count/compare interrupt */
+  if ( cause & 0x80 ) {
+      unsigned long zero = 0;
+      /*
+       * I don't see a good way to disable the compare
+       * interrupt, so let's just ignore it.
+       */
+      __asm__ volatile ("mtc0 %0, $11\n" :: "r" (zero));
+  }
+
+  /* Performance counter */
+  if ( cause & 0x40 ) {
+      bsp_interrupt_handler_dispatch(AU1X00_IRQ_PERF);
+  }
+
+  /* Interrupt controller 0 */
+  if ( cause & 0x0c ) {
+      call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR);
+  }
+
+  /* Interrupt controller 1 */
+  if ( cause & 0x30 ) {
+      call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR);
+  }
+
+  /* SW[0] */
+  if ( cause & 0x01 )
+      bsp_interrupt_handler_dispatch( AU1X00_IRQ_SW0 );
+
+  /* SW[1] */
+  if ( cause & 0x02 )
+      bsp_interrupt_handler_dispatch( AU1X00_IRQ_SW1 );
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+  rtems_fatal_error_occurred(1);
+}
+
+static void call_vectored_isr(
+    CPU_Interrupt_frame *frame,
+    uint32_t cause,
+    void *ctrlr
+    )
+{
+    uint32_t src;
+    uint32_t mask;
+    int index;
+
+    /* get mask register */
+    mask = AU1X00_IC_MASKRD(ctrlr);
+
+    /* check request 0 */
+    src = AU1X00_IC_REQ0INT(ctrlr);
+    src = src & mask;
+    index = 0;
+    while (src) {
+        /* check LSB */
+        if (src & 1) {
+            /* clear rising/falling edge detects */
+            AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
+            AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
+            au_sync();
+            bsp_interrupt_handler_dispatch(AU1X00_IRQ_IC0_BASE + index);
+        }
+        index ++;
+
+        /* shift, and make sure MSB is clear */
+        src = (src >> 1) & 0x7fffffff;
+    }
+
+    /* check request 1 */
+    src = AU1X00_IC_REQ1INT(ctrlr);
+    src = src & mask;
+    index = 0;
+    while (src) {
+        /* check LSB */
+        if (src & 1) {
+            /* clear rising/falling edge detects */
+            AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
+            AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
+            au_sync();
+            bsp_interrupt_handler_dispatch(AU1X00_IRQ_IC0_BASE + index);
+        }
+        index ++;
+
+        /* shift, and make sure MSB is clear */
+        src = (src >> 1) & 0x7fffffff;
+    }
+}
+
+/* Generate a software interrupt */
+int assert_sw_irq(uint32_t irqnum)
+{
+    uint32_t cause;
+
+    if (irqnum <= 1) {
+        mips_get_cause(cause);
+        cause = cause | ((irqnum + 1) << CAUSE_IPSHIFT);
+        mips_set_cause(cause);
+
+        return irqnum;
+    } else {
+        return -1;
+    }
+}
+
+/* Clear a software interrupt */
+int negate_sw_irq(uint32_t irqnum)
+{
+    uint32_t cause;
+
+    if (irqnum <= 1) {
+        mips_get_cause(cause);
+        cause = cause & ~((irqnum + 1) << CAUSE_IPSHIFT);
+        mips_set_cause(cause);
+
+        return irqnum;
+    } else {
+        return -1;
+    }
+}

c/src/lib/libbsp/mips/csb350/network/network.c

@@ -1,6 +1,10 @@
-/*
+/**
- *  Au1x00 ethernet driver
+ *  @file
  *  
+ *  Au1x00 ethernet driver
+ */
+
+/*
  *  Copyright (c) 2005 by Cogent Computer Systems
  *  Written by Jay Monkman <jtm@lopingdog.com>
  *
@@ -16,6 +20,7 @@
 #include <bsp.h>
 #include <rtems/bspIo.h>
 #include <libcpu/au1x00.h>
+#include <bsp/irq.h>
 
 #include <stdio.h>
 #include <string.h>

c/src/lib/libbsp/mips/csb350/preinstall.am

@@ -49,6 +49,18 @@ $(PROJECT_INCLUDE)/bsp/regs.h: ../shared/liblnk/regs.h $(PROJECT_INCLUDE)/bsp/$(
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/regs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
 
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h

c/src/lib/libbsp/mips/csb350/startup/bspstart.c

@@ -1,10 +1,14 @@
-/*
+/**
+ *  @file
+ *  
  *  This routine starts the application.  It includes application,
  *  board, and monitor specific initialization and configuration.
  *  The generic CPU dependent initialization has been performed
  *  before this routine is invoked.
- *
+ */
- *  COPYRIGHT (c) 1989-2000.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -19,6 +23,9 @@
 #include <bsp.h>
 #include <libcpu/au1x00.h>
 #include <libcpu/isr_entries.h>
+#include <bsp/irq-generic.h>
+
+void bsp_start( void );
 
 au1x00_uart_t *uart0 = (au1x00_uart_t *)AU1X00_UART0_ADDR;
 au1x00_uart_t *uart3 = (au1x00_uart_t *)AU1X00_UART3_ADDR;
@@ -35,17 +42,5 @@ void bsp_start( void )
   mips_set_sr( 0x7f00 );  /* all interrupts unmasked but globally off */
                           /* depend on the IRC to take care of things */
   __asm__ volatile ("mtc0 %0, $11\n" :: "r" (compare));
-  mips_install_isr_entries();
+  bsp_interrupt_initialize();
-}
-
-
-/* These replace the ones in newlib. I'm not sure why the newlib ones
- * don't work.
- */
-void _init(void)
-{
-}
-
-void _fini(void)
-{
 }

c/src/lib/libbsp/mips/genmongoosev/ChangeLog

@@ -1,3 +1,24 @@
+2012-03-08	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
+
+2012-03-06	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* clock/clockdrv.c, include/bsp.h,
+	include/irq.h, irq/vectorisrs.c,
+	startup/bspstart.c, clock/ckinit.c:
+	Changed interrupt call, removed warnings and did cleanup.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* Makefile.am, clock/clockdrv.c, console/conscfg.c,
+	include/irq.h, irq/vectorisrs.c, preinstall.am,
+	startup/bspstart.c:
+	Mips conversion to PIC IRQ model.
+	* include/irq.h, irq/vectorisrs.c: New files.
+
 2011-10-18	Jennifer Averett <Jennifer.Averett@OARcorp.com>
 
 	PR 1917/bsps

c/src/lib/libbsp/mips/genmongoosev/Makefile.am

@@ -13,6 +13,10 @@ dist_project_lib_DATA = bsp_specs
 include_HEADERS = include/bsp.h
 include_HEADERS += include/tm27.h
 include_bsp_HEADERS = start/regs.h
+#isr
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += include/irq.h
 
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -22,7 +26,9 @@ noinst_PROGRAMS =
 nodist_include_HEADERS += ../../shared/include/coverhd.h
 
 noinst_LIBRARIES = libbspstart.a
-libbspstart_a_SOURCES = start/start.S start/regs.h start/mg5.h
+libbspstart_a_SOURCES  = start/start.S
+libbspstart_a_SOURCES += start/regs.h
+libbspstart_a_SOURCES += start/mg5.h
 project_lib_DATA = start.$(OBJEXT)
 
 dist_project_lib_DATA += startup/linkcmds
@@ -31,33 +37,50 @@ noinst_LIBRARIES += libbsp.a
 libbsp_a_SOURCES =
 
 # startup
-libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsppretaskinghook.c \
+libbsp_a_SOURCES += ../../shared/bspclean.c
-    ../../shared/bsppredriverhook.c ../../shared/bsplibc.c \
+libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
-    ../../shared/bsppost.c startup/bspstart.c ../../shared/bootcard.c \
+libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
-    ../../shared/sbrk.c ../../shared/gnatinstallhandler.c \
+libbsp_a_SOURCES += ../../shared/bsplibc.c
-    ../../shared/setvec.c ../../shared/bspgetworkarea.c
+libbsp_a_SOURCES += ../../shared/bsppost.c
+libbsp_a_SOURCES += startup/bspstart.c
+libbsp_a_SOURCES += ../../shared/bootcard.c
+libbsp_a_SOURCES += ../../shared/sbrk.c
+libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
 # clock
 libbsp_a_SOURCES += clock/clockdrv.c
 libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
 # console
-libbsp_a_SOURCES += console/conscfg.c ../../shared/console.c \
+libbsp_a_SOURCES += console/conscfg.c
-    ../../shared/console_select.c ../../shared/console_control.c \
+libbsp_a_SOURCES += ../../shared/console.c
-    ../../shared/console_read.c ../../shared/console_write.c
+libbsp_a_SOURCES += ../../shared/console_select.c
+libbsp_a_SOURCES += ../../shared/console_control.c
+libbsp_a_SOURCES += ../../shared/console_read.c
+libbsp_a_SOURCES += ../../shared/console_write.c
 # timer
 libbsp_a_SOURCES += timer/timer.c
+#isr
+libbsp_a_SOURCES += ../../shared/src/irq-generic.c
+libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
+libbsp_a_SOURCES += ../../shared/src/irq-info.c
+libbsp_a_SOURCES += ../../shared/src/irq-shell.c
+libbsp_a_SOURCES += ../../shared/src/irq-server.c
+libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
+libbsp_a_SOURCES += ../shared/irq/irq.c
+libbsp_a_SOURCES += ../shared/irq/maxvectors.c
+libbsp_a_SOURCES += irq/vectorisrs.c
+libbsp_a_SOURCES += ../shared/irq/interruptmask.c
 
 gdbstub_CPPFLAGS = -I$(srcdir)/../../mips/shared/gdbstub
 noinst_PROGRAMS += gdbstub.rel
-gdbstub_rel_SOURCES = ../../mips/shared/gdbstub/mips-stub.c \
+gdbstub_rel_SOURCES  = ../../mips/shared/gdbstub/mips-stub.c
-    startup/gdb-support.c ../../shared/gdbstub/rtems-stub-glue.c
+gdbstub_rel_SOURCES += startup/gdb-support.c
+gdbstub_rel_SOURCES += ../../shared/gdbstub/rtems-stub-glue.c
 gdbstub_rel_CPPFLAGS = $(AM_CPPFLAGS) $(gdbstub_CPPFLAGS)
 gdbstub_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 
-libbsp_a_LIBADD = \
+libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
+libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
-    ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel \
+libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mongoosev/duart.rel
-    ../../../libcpu/@RTEMS_CPU@/mongoosev/duart.rel \
-    ../../../libcpu/@RTEMS_CPU@/mongoosev/vectorisrs.rel
 
 include $(srcdir)/preinstall.am
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/mips/genmongoosev/clock/clockdrv.c

@@ -1,7 +1,11 @@
-/*
+/**
- *  Instantiate the clock driver shell for the Mongoose-V's on-CPU timer.
+ *  @file
  *  
- *  COPYRIGHT (c) 1989-2001.
+ *  Instantiate the clock driver shell for the Mongoose-V's on-CPU timer.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -12,7 +16,7 @@
  */
 
 #include <rtems.h>
-#include <libcpu/mongoose-v.h>
+#include <bsp/irq.h>
 #include <bsp.h>
 
 #if defined(USE_TIMER2_FOR_CLOCK)
@@ -33,7 +37,13 @@
 
 #define Clock_driver_support_install_isr( _new, _old ) \
   do { \
-    _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
+    rtems_interrupt_handler_install( \
+      CLOCK_VECTOR, \
+      "clock", \
+      0, \
+      _new, \
+      NULL \
+    ); \
   } while(0)
 
 #define Clock_driver_support_initialize_hardware() \

c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c

@@ -1,9 +1,13 @@
-/*
+/**
+ *  @file
+ *  
  *  This file contains the libchip configuration information
  *  to instantiate the libchip driver for the on-CPU DUART
  *  and any other serial ports in the system.
- *
+ */
- *  COPYRIGHT (c) 1989-2001.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -16,6 +20,7 @@
 #include <unistd.h> /* write */
 
 #include <bsp.h>
+#include <bsp/irq.h>
 
 #include <libchip/serial.h>
 #include <libchip/mg5uart.h>

c/src/lib/libbsp/mips/genmongoosev/include/bsp.h

@@ -1,9 +1,12 @@
-/*  bsp.h
+/**
+ *  @file
  *  
  *  This include file contains some definitions specific to a board
  *  based upon the generic capabilities of a Mongoose-V.
- *
+ */
- *  COPYRIGHT (c) 1989-2001.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -28,6 +31,9 @@ extern "C" {
 #include <rtems/clockdrv.h>
 #include <libcpu/mongoose-v.h>
 
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
 #ifndef CPU_CLOCK_RATE
 #define CLOCK_RATE	12000000
 #endif

c/src/lib/libbsp/mips/genmongoosev/include/irq.h

@@ -0,0 +1,97 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#ifndef LIBBSP_MIPS_MONGOOSEV_IRQ_H
+#define LIBBSP_MIPS_MONGOOSEV_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ *  NOTE: IRQ INT5 is logical or of peripheral cause register
+ *        per p. 5-22 of Mongoose-V manual.
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN              0
+#define MONGOOSEV_IRQ_INT0                    MIPS_INTERRUPT_BASE+0
+#define MONGOOSEV_IRQ_TIMER1                  MONGOOSEV_IRQ_INT0
+#define MONGOOSEV_IRQ_INT1                    MIPS_INTERRUPT_BASE+1
+#define MONGOOSEV_IRQ_TIMER2                  MONGOOSEV_IRQ_INT1
+#define MONGOOSEV_IRQ_INT2                    MIPS_INTERRUPT_BASE+2
+#define MONGOOSEV_IRQ_INT3                    MIPS_INTERRUPT_BASE+3
+#define MONGOOSEV_IRQ_FPU		      MONGOOSEV_IRQ_INT3
+
+#define MONGOOSEV_IRQ_INT4                    MIPS_INTERRUPT_BASE+4
+
+/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
+#define MONGOOSEV_IRQ_PERIPHERAL_BASE         MIPS_INTERRUPT_BASE+5
+#define MONGOOSEV_IRQ_XINT0                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 0
+#define MONGOOSEV_IRQ_XINT1                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 1
+#define MONGOOSEV_IRQ_XINT2                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 2
+#define MONGOOSEV_IRQ_XINT3                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 3
+#define MONGOOSEV_IRQ_XINT4                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 4
+#define MONGOOSEV_IRQ_XINT5                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 5
+#define MONGOOSEV_IRQ_XINT6                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 6
+#define MONGOOSEV_IRQ_XINT7                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 7
+#define MONGOOSEV_IRQ_XINT8                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 8
+#define MONGOOSEV_IRQ_XINT9                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 9
+#define MONGOOSEV_IRQ_RESERVED_BIT_10	     MONGOOSEV_IRQ_PERIPHERAL_BASE + 10
+#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR   MONGOOSEV_IRQ_PERIPHERAL_BASE + 11
+#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12
+#define MONGOOSEV_IRQ_UART0_TX_EMPTY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 13
+#define MONGOOSEV_IRQ_UART0_TX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 14
+#define MONGOOSEV_IRQ_UART0_RX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 15
+#define MONGOOSEV_IRQ_RESERVED_BIT_16        MONGOOSEV_IRQ_PERIPHERAL_BASE + 16
+#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR   MONGOOSEV_IRQ_PERIPHERAL_BASE + 17
+#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18
+#define MONGOOSEV_IRQ_UART1_TX_EMPTY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 19
+#define MONGOOSEV_IRQ_UART1_TX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 20
+#define MONGOOSEV_IRQ_UART1_RX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 21
+#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION  MONGOOSEV_IRQ_PERIPHERAL_BASE + 22
+#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23
+#define MONGOOSEV_IRQ_RESERVED_24            MONGOOSEV_IRQ_PERIPHERAL_BASE + 24
+#define MONGOOSEV_IRQ_RESERVED_25            MONGOOSEV_IRQ_PERIPHERAL_BASE + 25
+#define MONGOOSEV_IRQ_RESERVED_26            MONGOOSEV_IRQ_PERIPHERAL_BASE + 26
+#define MONGOOSEV_IRQ_RESERVED_27            MONGOOSEV_IRQ_PERIPHERAL_BASE + 27
+#define MONGOOSEV_IRQ_RESERVED_28            MONGOOSEV_IRQ_PERIPHERAL_BASE + 28
+#define MONGOOSEV_IRQ_RESERVED_29            MONGOOSEV_IRQ_PERIPHERAL_BASE + 29
+#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR    MONGOOSEV_IRQ_PERIPHERAL_BASE + 30
+#define MONGOOSEV_IRQ_CORRECTABLE_ERROR      MONGOOSEV_IRQ_PERIPHERAL_BASE + 31
+
+#define MONGOOSEV_IRQ_SOFTWARE_1             MIPS_INTERRUPT_BASE+37
+#define MONGOOSEV_IRQ_SOFTWARE_2             MIPS_INTERRUPT_BASE+38
+#define MONGOOSEV_MAXIMUM_VECTORS            MIPS_INTERRUPT_BASE+39
+
+#define BSP_INTERRUPT_VECTOR_MAX             MONGOOSEV_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_MONGOOSEV_IRQ_H */

c/src/lib/libbsp/mips/genmongoosev/irq/vectorisrs.c

@@ -0,0 +1,259 @@
+/**
+ *  @file
+ *  
+ *  ISR Vectoring support for the Synova Mongoose-V.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/mongoose-v.h>
+
+#include <rtems/mips/iregdef.h>
+#include <rtems/mips/idtcpu.h>
+#include <rtems/irq.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+
+#include <rtems/bspIo.h>  /* for printk */
+
+int mips_default_isr( int vector );
+int assertSoftwareInterrupt( uint32_t   n );
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
+
+int mips_default_isr( int vector )
+{
+  unsigned int sr, sr2;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  sr2 = sr & ~0xffff;
+  mips_set_sr(sr2);
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr );
+  rtems_fatal_error_occurred(1);
+  return 0;
+}
+
+/* userspace routine to assert either software interrupt */
+
+int assertSoftwareInterrupt( uint32_t   n )
+{
+   if( n<2 )
+   {
+      uint32_t   c;
+
+      mips_get_cause(c);
+      c = ((n+1) << CAUSE_IPSHIFT);
+      mips_set_cause(c);
+
+      return n;
+   }
+   else return -1;
+}
+
+
+/*
+ * Instrumentation tweaks for isr timing measurement, turning them off
+ * via this #if will remove the code entirely from the RTEMS kernel.
+ */
+
+#if 0
+#define SET_ISR_FLAG( offset )	*((uint32_t*)(0x8001e000+offset)) = 1;
+#define CLR_ISR_FLAG( offset )	*((uint32_t*)(0x8001e000+offset)) = 0;
+#else
+#define SET_ISR_FLAG( offset )
+#define CLR_ISR_FLAG( offset )
+#endif
+
+
+
+
+
+
+static volatile uint32_t   _ivcause, _ivsr;
+
+
+static uint32_t   READ_CAUSE(void)
+{
+   mips_get_cause( _ivcause );
+   _ivcause &= SR_IMASK;	/* mask off everything other than the interrupt bits */
+
+   return ((_ivcause & (_ivsr & SR_IMASK)) >> CAUSE_IPSHIFT);
+}
+
+
+
+/*
+ * This rather strangely coded routine enforces an interrupt priority
+ * scheme.  As it runs thru finding whichever interrupt caused it to get
+ * here, it test for other interrupts arriving in the meantime (maybe it
+ * occured while the vector code is executing for instance).  Each new
+ * interrupt will be served in order of its priority.  In an effort to
+ * minimize overhead, the cause register is only fetched after an
+ * interrupt is serviced.  Because of the intvect goto's, this routine
+ * will only exit when all interrupts have been serviced and no more
+ * have arrived, this improves interrupt latency at the cost of
+ * increasing scheduling jitter; though scheduling jitter should only
+ * become apparent in high interrupt load conditions.
+ */
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+   uint32_t  	cshifted;
+
+   /* mips_get_sr( sr ); */
+   _ivsr = frame->c0_sr;
+
+   cshifted = READ_CAUSE();
+
+  intvect:
+
+   if( cshifted & 0x3 )
+   {
+      /* making the software interrupt the highest priority is kind of
+       * stupid, but it makes the bit testing lots easier.  On the other
+       * hand, these ints are infrequently used and the testing overhead
+       * is minimal.  Who knows, high-priority software ints might be
+       * handy in some situation.
+       */
+
+      /* unset both software int cause bits */
+      mips_set_cause( _ivcause & ~(3 << CAUSE_IPSHIFT) );
+
+      if ( cshifted & 0x01 )       /* SW[0] */
+      {
+	 bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_SOFTWARE_1 );
+      }
+      if ( cshifted & 0x02 )       /* SW[1] */
+      {
+	 bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_SOFTWARE_2 );
+      }
+      cshifted = READ_CAUSE();
+   }
+
+
+   if ( cshifted & 0x04 )       /* IP[0] ==> INT0 == TIMER1 */
+   {
+      SET_ISR_FLAG( 0x4 );
+      bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_TIMER1 );
+      CLR_ISR_FLAG( 0x4 );
+      if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect;
+   }
+
+   if ( cshifted & 0x08 )       /* IP[1] ==> INT1 == TIMER2*/
+   {
+      SET_ISR_FLAG( 0x8 );
+      bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_TIMER2 );
+      CLR_ISR_FLAG( 0x8 );
+      if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect;
+   }
+
+   if ( cshifted & 0x10 )       /* IP[2] ==> INT2 */
+   {
+      SET_ISR_FLAG( 0x10 );
+      bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT2 );
+      CLR_ISR_FLAG( 0x10 );
+      if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect;
+   }
+
+   if ( cshifted & 0x20 )       /* IP[3] ==> INT3 == FPU interrupt */
+   {
+      SET_ISR_FLAG( 0x20 );
+      bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT3 );
+      CLR_ISR_FLAG( 0x20 );
+      if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect;
+   }
+
+   if ( cshifted & 0x40 )       /* IP[4] ==> INT4, external interrupt */
+   {
+      SET_ISR_FLAG( 0x40 );
+      bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT4 );
+      CLR_ISR_FLAG( 0x40 );
+      if( (cshifted = READ_CAUSE()) & 0x3f ) goto intvect;
+   }
+
+   if ( cshifted & 0x80 )       /* IP[5] ==> INT5, peripheral interrupt */
+   {
+      uint32_t    bit;
+      uint32_t    pf_icr, pf_mask, pf_reset = 0;
+      uint32_t    i, m;
+
+      pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
+
+/*
+      for (bit=0, pf_mask = 1;    bit < 32;     bit++, pf_mask <<= 1 )
+      {
+	 if ( pf_icr & pf_mask )
+	 {
+	    SET_ISR_FLAG( 0x80 + (bit*4) );
+	    bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit );
+	    CLR_ISR_FLAG( 0x80 + (bit*4) );
+	    pf_reset |= pf_mask;
+	    if( (cshifted = READ_CAUSE()) & 0xff ) break;
+	 }
+      }
+*/
+
+      /*
+       * iterate thru 32 bits in 4 chunks of 8 bits each.  This lets us
+       * quickly get past unasserted interrupts instead of flogging our
+       * way thru a full 32 bits.  pf_mask shifts left 8 bits at a time
+       * to serve as a interrupt cause test mask.
+       */
+      for( bit=0, pf_mask = 0xff;    (bit < 32 && pf_icr);     (bit+=8, pf_mask <<= 8) )
+      {
+	 if ( pf_icr & pf_mask )
+	 {
+	    /* one or more of the 8 bits we're testing is high */
+
+	    m = (1 << bit);
+
+	    /* iterate thru the 8 bits, servicing any of the interrupts */
+	    for(i=0; (i<8 && pf_icr); (i++, m <<= 1))
+	    {
+	       if( pf_icr & m )
+	       {
+		  SET_ISR_FLAG( 0x80 + ((bit + i) * 4) );
+		  bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit + i );
+		  CLR_ISR_FLAG( 0x80 + ((bit + i) * 4) );
+
+		  /* or each serviced interrupt into our interrupt clear mask */
+		  pf_reset |= m;
+
+		  /* xor off each int we service so we can immediately
+		   * exit once we get the last one
+                   */
+		  pf_icr   %= m;
+
+		  /* if another interrupt has arrived, jump out right
+		   * away but be sure to reset all the interrupts we've
+		   * already serviced
+                   */
+		  if( READ_CAUSE() & 0xff ) goto pfexit;
+	       }
+	    }
+	 }
+      }
+     pfexit:
+      MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, pf_reset );
+   }
+
+   /*
+    * this is a last ditch interrupt check, if an interrupt arrives
+    * after this step, servicing it will incur the entire interrupt
+    * overhead cost.
+    */
+   if( (cshifted = READ_CAUSE()) & 0xff ) goto intvect;
+}

c/src/lib/libbsp/mips/genmongoosev/preinstall.am

@@ -49,6 +49,18 @@ $(PROJECT_INCLUDE)/bsp/regs.h: start/regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/regs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
 
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h

c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c

@@ -1,10 +1,18 @@
-/*
+/**
+ *  @file
+ *  
  *  This routine starts the application.  It includes application,
  *  board, and monitor specific initialization and configuration.
  *  The generic CPU dependent initialization has been performed
  *  before this routine is invoked.
  *
- *  COPYRIGHT (c) 1989-2001.
+ *  Modification History:
+ *        12/10/01  A.Ferrer, NASA/GSFC, Code 582
+ *           Set interrupt mask to 0xAF00 (Line 139).
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -12,10 +20,6 @@
  *  http://www.rtems.com/license/LICENSE.
  * 
  *  $Id$
- *
- * Modification History:
- *        12/10/01  A.Ferrer, NASA/GSFC, Code 582
- *           Set interrupt mask to 0xAF00 (Line 139).
  */
  
 #include <string.h>
@@ -23,7 +27,10 @@
 #include <bsp.h>
 #include <libcpu/mongoose-v.h>
 #include <libcpu/isr_entries.h>
+#include <bsp/irq-generic.h>
 
+void bsp_start( void );
+void clear_cache( void );
 extern void _sys_exit(int);
 extern void mips_gdb_stub_install(void);
 
@@ -82,7 +89,7 @@ void bsp_start( void )
    */
   mips_set_sr( (SR_CU0 | 0x400) );
 
-  mips_install_isr_entries();
+  bsp_interrupt_initialize();
 }
 
 void clear_cache( void )

c/src/lib/libbsp/mips/hurricane/ChangeLog

@@ -1,3 +1,22 @@
+2012-03-08	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
+
+2012-03-06	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* include/bsp.h, include/irq.h,
+	irq/vectorisrs.c, startup/bspstart.c:
+	Changed interrupt call, removed warnings and did cleanup.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* Makefile.am, clock/ckinit.c, include/irq.h,
+	irq/vectorisrs.c, preinstall.am, startup/bspstart.c:
+	Mips conversion to PIC IRQ model.
+	* include/irq.h, irq/vectorisrs.c: New files.
+
 2011-02-02	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* configure.ac: Require autoconf-2.68, automake-1.11.1.

c/src/lib/libbsp/mips/hurricane/Makefile.am

@@ -14,6 +14,10 @@ include_HEADERS = include/bsp.h
 include_HEADERS += ../../shared/include/tm27.h
 include_HEADERS += include/usc.h
 include_bsp_HEADERS = ../shared/liblnk/regs.h
+#isr
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += include/irq.h
 
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -31,27 +35,45 @@ noinst_LIBRARIES += libbsp.a
 libbsp_a_SOURCES =
 
 # startup
-libbsp_a_SOURCES += ../../shared/bspclean.c \
+libbsp_a_SOURCES += ../../shared/bspclean.c
-    ../../shared/bsplibc.c ../../shared/bsppost.c \
+libbsp_a_SOURCES += ../../shared/bsplibc.c
-   ../../shared/bsppretaskinghook.c ../../shared/bspgetworkarea.c \
+libbsp_a_SOURCES += ../../shared/bsppost.c
-    ../../shared/bsppredriverhook.c startup/bspstart.c \
+libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
-    ../../shared/bootcard.c ../../shared/sbrk.c \
+libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
-    ../../shared/gnatinstallhandler.c ../../shared/setvec.c \
+libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
-    startup/inittlb.c ../shared/startup/idtmem.S ../shared/startup/idttlb.S \
+libbsp_a_SOURCES += startup/bspstart.c
-    ../shared/irq/exception.S startup/usc.S
+libbsp_a_SOURCES += ../../shared/bootcard.c
+libbsp_a_SOURCES += ../../shared/sbrk.c
+libbsp_a_SOURCES += startup/inittlb.c
+libbsp_a_SOURCES += ../shared/startup/idtmem.S
+libbsp_a_SOURCES += ../shared/startup/idttlb.S
+libbsp_a_SOURCES += ../shared/irq/exception.S
+libbsp_a_SOURCES += startup/usc.S
 # clock
 libbsp_a_SOURCES += clock/ckinit.c
+libbsp_a_SOURCES += clock/clock.h
+
 # console
 libbsp_a_SOURCES += console/console.c
 # liblnk
-libbsp_a_SOURCES += ../shared/liblnk/lnklib.S ../shared/liblnk/pmon.S \
+libbsp_a_SOURCES += ../shared/liblnk/lnklib.S
-    ../shared/liblnk/regs.h
+libbsp_a_SOURCES += ../shared/liblnk/pmon.S
+libbsp_a_SOURCES += ../shared/liblnk/regs.h
+#isr
+libbsp_a_SOURCES += ../../shared/src/irq-generic.c
+libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
+libbsp_a_SOURCES += ../../shared/src/irq-info.c
+libbsp_a_SOURCES += ../../shared/src/irq-shell.c
+libbsp_a_SOURCES += ../../shared/src/irq-server.c
+libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
+libbsp_a_SOURCES += ../shared/irq/irq.c
+libbsp_a_SOURCES += ../shared/irq/maxvectors.c
+libbsp_a_SOURCES += irq/vectorisrs.c
+libbsp_a_SOURCES += ../shared/irq/interruptmask.c
 
-libbsp_a_LIBADD = \
+libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
+libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
-    ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel \
+libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rm52xx/timer.rel
-    ../../../libcpu/@RTEMS_CPU@/rm52xx/timer.rel \
-    ../../../libcpu/@RTEMS_CPU@/rm52xx/vectorisrs.rel
 
 include $(srcdir)/preinstall.am
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/mips/hurricane/clock/ckinit.c

@@ -1,8 +1,10 @@
-
+/**
-/*  ckinit.c
+ *  @file
  *  
  *  This file contains the clock driver initialization for the Hurricane BSP.
- *
+ */
+
+/*
  *  Author:     Craig Lebakken <craigl@transition.com>
  *
  *  COPYRIGHT (c) 1996 by Transition Networks Inc.
@@ -18,9 +20,9 @@
  *      Transition Networks makes no representations about the suitability
  *      of this software for any purpose.
  *
- *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c:
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c
  *
- *  COPYRIGHT (c) 1989-1999.
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -41,6 +43,8 @@
 #include <stdlib.h>
 
 #include <rtems.h>
+#include <bsp.h>
+#include <bsp/irq.h>
 
 extern uint32_t bsp_clicks_per_microsecond;
 
@@ -48,10 +52,8 @@ extern uint32_t bsp_clicks_per_microsecond;
 
 #include "clock.h"
 
-/* to avoid including the bsp */
+rtems_isr USC_isr(void *unused);
-mips_isr_entry set_vector( rtems_isr_entry, rtems_vector_number, int );
 
-void USC_isr( void );
 void reset_wdt(void);
 void enable_wdi(void);
 void init_hbt(void);
@@ -60,6 +62,8 @@ void disable_hbi(void);
 
 void Clock_exit(void);
 rtems_isr Clock_isr(rtems_vector_number vector);
+rtems_isr User_Clock_isr(rtems_vector_number vector);
+void Install_clock(rtems_isr_entry clock_isr);
 
 
 /*
@@ -87,13 +91,6 @@ volatile uint32_t Clock_driver_ticks;
 
 uint32_t Clock_isrs;              /* ISRs until next tick */
 
-/*
- * These are set by clock driver during its init
- */
-
-rtems_device_major_number rtems_clock_major = ~0;
-rtems_device_minor_number rtems_clock_minor;
-
 /*
  *  The previous ISR on this clock tick interrupt vector.
  */
@@ -168,7 +165,13 @@ void Install_clock(
   disable_hbi();      /* Disable heartbeat interrupt in USC */
 
   /* Install interrupt handler */
-  Old_ticker = (rtems_isr_entry) set_vector( USC_isr, CLOCK_VECTOR, 1 );
+  rtems_interrupt_handler_install( 
+    CLOCK_VECTOR,
+    "clock",
+    0,
+    USC_isr,
+    NULL
+  );
 
   init_hbt();        /* Initialize heartbeat timer */
 
@@ -212,13 +215,6 @@ rtems_device_driver Clock_initialize(
 {
   Install_clock( Clock_isr );
 
-  /*
-   * make major/minor avail to others such as shared memory driver
-   */
-
-  rtems_clock_major = major;
-  rtems_clock_minor = minor;
-
   return RTEMS_SUCCESSFUL;
 }
 

c/src/lib/libbsp/mips/hurricane/include/bsp.h

@@ -1,5 +1,10 @@
+/**
+ *  @file
+ *  
+ */
+
 /*
- *  COPYRIGHT (c) 1989-2008.
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -28,6 +33,9 @@ extern void WriteDisplay( char * string );
 
 extern uint32_t mips_get_timer( void );
 
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
 #define CPU_CLOCK_RATE_MHZ     (200)
 #define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
 

c/src/lib/libbsp/mips/hurricane/include/irq.h

@@ -0,0 +1,42 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#ifndef LIBBSP_MIPS_XXX_IRQ_H
+#define LIBBSP_MIPS_XXX_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN    0
+#define RM5231_MAXIMUM_VECTORS      (MIPS_INTERRUPT_BASE+8)
+#define BSP_INTERRUPT_VECTOR_MAX    RM5231_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */

c/src/lib/libbsp/mips/hurricane/irq/vectorisrs.c

@@ -0,0 +1,60 @@
+/**
+ *  @file
+ *
+ *  RM5231 Interrupt Vectoring  
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/rm5231.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
+void mips_default_isr( int vector );
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int i;
+  unsigned int mask;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  cause &= (sr & SR_IMASK);
+  cause >>= CAUSE_IPSHIFT;
+
+  for ( i=1, mask=0x80 ; i<=8 ; i++, mask >>= 1 ) {
+    if ( cause & mask )
+      bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + 8 - i );
+  }
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+  rtems_fatal_error_occurred(1);
+}
+

c/src/lib/libbsp/mips/hurricane/preinstall.am

@@ -53,6 +53,18 @@ $(PROJECT_INCLUDE)/bsp/regs.h: ../shared/liblnk/regs.h $(PROJECT_INCLUDE)/bsp/$(
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/regs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
 
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h

c/src/lib/libbsp/mips/hurricane/startup/bspstart.c

@@ -1,10 +1,14 @@
-/*
+/**
+ *  @file
+ *  
  *  This routine starts the application.  It includes application,
  *  board, and monitor specific initialization and configuration.
  *  The generic CPU dependent initialization has been performed
  *  before this routine is invoked.
- *
+ */
- *  COPYRIGHT (c) 1989-1999.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -18,7 +22,9 @@
 
 #include <bsp.h>
 #include <libcpu/isr_entries.h>
+#include <bsp/irq-generic.h>
 
+void bsp_start( void );
 uint32_t bsp_clicks_per_microsecond;
 
 /*
@@ -31,5 +37,5 @@ void bsp_start( void )
 
   bsp_clicks_per_microsecond = CPU_CLOCK_RATE_MHZ;
 
-  mips_install_isr_entries(); /* Install generic MIPS exception handler */
+  bsp_interrupt_initialize();
 }

c/src/lib/libbsp/mips/jmr3904/ChangeLog

@@ -1,3 +1,22 @@
+2012-03-08	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
+
+2012-03-06	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* clock/clockdrv.c, include/bsp.h,
+	include/irq.h, irq/vectorisrs.c, startup/bspstart.c:
+	Changed interrupt call, removed warnings and did cleanup.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* Makefile.am, clock/clockdrv.c, include/irq.h,
+	irq/vectorisrs.c, preinstall.am, startup/bspstart.c:
+	Mips conversion to PIC IRQ model.
+	* include/irq.h, irq/vectorisrs.c: New files.
+
 2011-12-14	Joel Sherrill <joel.sherrilL@OARcorp.com>
 
 	* Makefile.am: Change to one file per line. Clean up.

c/src/lib/libbsp/mips/jmr3904/Makefile.am

@@ -13,6 +13,10 @@ dist_project_lib_DATA = bsp_specs
 include_HEADERS = include/bsp.h
 include_HEADERS += include/tm27.h
 include_bsp_HEADERS = ../shared/liblnk/regs.h
+#isr
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += include/irq.h
 
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -39,8 +43,6 @@ libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
 libbsp_a_SOURCES += startup/bspstart.c
 libbsp_a_SOURCES += ../../shared/bootcard.c
 libbsp_a_SOURCES += ../../shared/sbrk.c
-libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
-libbsp_a_SOURCES += ../../shared/setvec.c
 libbsp_a_SOURCES += ../../shared/bspreset.c
 # clock
 libbsp_a_SOURCES += clock/clockdrv.c
@@ -50,11 +52,20 @@ libbsp_a_SOURCES += ../../shared/console-polled.c
 libbsp_a_SOURCES += console/console-io.c
 # timer
 libbsp_a_SOURCES += timer/timer.c
+#isr
+libbsp_a_SOURCES += ../../shared/src/irq-generic.c
+libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
+libbsp_a_SOURCES += ../../shared/src/irq-info.c
+libbsp_a_SOURCES += ../../shared/src/irq-shell.c
+libbsp_a_SOURCES += ../../shared/src/irq-server.c
+libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
+libbsp_a_SOURCES += ../shared/irq/irq.c
+libbsp_a_SOURCES += ../shared/irq/maxvectors.c
+libbsp_a_SOURCES += irq/vectorisrs.c
+libbsp_a_SOURCES += ../shared/irq/interruptmask.c
 
 libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx39/vectorisrs.rel
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
 
 include $(srcdir)/preinstall.am
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/mips/jmr3904/clock/clockdrv.c

@@ -1,9 +1,13 @@
-/*
+/**
+ *  @file
+ *  
  *  Instantiate the clock driver shell.
  *
  *  The TX3904 simulator in gdb counts instructions.
- *
+ */
- *  COPYRIGHT (c) 1989-2009.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -14,7 +18,7 @@
  */
 
 #include <rtems.h>
-#include <libcpu/tx3904.h>
+#include <bsp/irq.h>
 #include <bsp.h>
 
 #define CLOCK_DRIVER_USE_FAST_IDLE
@@ -26,9 +30,16 @@
  */
 
 #define CLICKS 5000
+
 #define Clock_driver_support_install_isr( _new, _old ) \
   do { \
-    _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
+    rtems_interrupt_handler_install( \
+      CLOCK_VECTOR, \
+      "clock", \
+      0, \
+      _new, \
+      NULL \
+    ); \
  } while(0)
 
 #define Clock_driver_support_initialize_hardware() \

c/src/lib/libbsp/mips/jmr3904/include/bsp.h

@@ -1,9 +1,12 @@
-/*  bsp.h
+/**
+ *  @file
  *  
  *  This include file contains some definitions specific to the
  *  JMR3904 simulator in gdb.
- *
+ */
- *  COPYRIGHT (c) 1989-2000.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -28,6 +31,9 @@ extern "C" {
 #include <rtems/clockdrv.h>
 #include <libcpu/tx3904.h>
 
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
 /* functions */
 
 rtems_isr_entry set_vector(

c/src/lib/libbsp/mips/jmr3904/include/irq.h

@@ -0,0 +1,70 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief jmr3904 interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#ifndef LIBBSP_MIPS_JMR3904_IRQ_H
+#define LIBBSP_MIPS_JMR3904_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ *  NOTE: Numbers 0-15 directly map to levels on the IRC.
+ *        Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
+ */
+
+  #define TX3904_IRQ_INT1        MIPS_INTERRUPT_BASE+0
+  #define TX3904_IRQ_INT2        MIPS_INTERRUPT_BASE+1
+  #define TX3904_IRQ_INT3        MIPS_INTERRUPT_BASE+2
+  #define TX3904_IRQ_INT4        MIPS_INTERRUPT_BASE+3
+  #define TX3904_IRQ_INT5        MIPS_INTERRUPT_BASE+4
+  #define TX3904_IRQ_INT6        MIPS_INTERRUPT_BASE+5
+  #define TX3904_IRQ_INT7        MIPS_INTERRUPT_BASE+6
+  #define TX3904_IRQ_DMAC3       MIPS_INTERRUPT_BASE+7
+  #define TX3904_IRQ_DMAC2       MIPS_INTERRUPT_BASE+8
+  #define TX3904_IRQ_DMAC1       MIPS_INTERRUPT_BASE+9
+  #define TX3904_IRQ_DMAC0       MIPS_INTERRUPT_BASE+10
+  #define TX3904_IRQ_SIO0        MIPS_INTERRUPT_BASE+11
+  #define TX3904_IRQ_SIO1        MIPS_INTERRUPT_BASE+12
+  #define TX3904_IRQ_TMR0        MIPS_INTERRUPT_BASE+13
+  #define TX3904_IRQ_TMR1        MIPS_INTERRUPT_BASE+14
+  #define TX3904_IRQ_TMR2        MIPS_INTERRUPT_BASE+15
+  #define TX3904_IRQ_INT0        MIPS_INTERRUPT_BASE+16
+  #define TX3904_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+17
+  #define TX3904_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+18
+  #define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
+
+#define BSP_INTERRUPT_VECTOR_MAX TX3904_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */

c/src/lib/libbsp/mips/jmr3904/irq/vectorisrs.c

@@ -0,0 +1,50 @@
+/**
+ *  @file
+ *  
+ *  TX3904 Interrupt Vectoring
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <bsp/irq.h>
+#include <rtems/bspIo.h>  /* for printk */
+#include <bsp/irq-generic.h>
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  cause &= (sr & SR_IMASK);
+  cause >>= CAUSE_IPSHIFT;
+
+  if ( cause & 0x80 )       /* IP[5] ==> INT0 */
+    bsp_interrupt_handler_dispatch( TX3904_IRQ_INT0 );
+
+  if ( cause & 0x40 ) {     /* (IP[4] == 1) ==> IP[0-3] are valid */
+    unsigned int v = (cause >> 2) & 0x0f;
+    bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + v );
+  }
+
+  if ( cause & 0x02 )       /* SW[0] */
+    bsp_interrupt_handler_dispatch( TX3904_IRQ_SOFTWARE_1 );
+
+  if ( cause & 0x01 )       /* IP[1] */
+    bsp_interrupt_handler_dispatch( TX3904_IRQ_SOFTWARE_2 );
+}

c/src/lib/libbsp/mips/jmr3904/preinstall.am

@@ -49,6 +49,18 @@ $(PROJECT_INCLUDE)/bsp/regs.h: ../shared/liblnk/regs.h $(PROJECT_INCLUDE)/bsp/$(
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/regs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
 
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h

c/src/lib/libbsp/mips/jmr3904/startup/bspstart.c

@@ -1,10 +1,14 @@
-/*
+/**
+ *  @file
+ *  
  *  This routine starts the application.  It includes application,
  *  board, and monitor specific initialization and configuration.
  *  The generic CPU dependent initialization has been performed
  *  before this routine is invoked.
- *
+ */
- *  COPYRIGHT (c) 1989-2009.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -17,25 +21,9 @@
 #include <bsp.h>
 #include <libcpu/isr_entries.h>
 #include <bsp/bootcard.h>
-
+#include <bsp/irq-generic.h>
-/*
+#include <bsp/irq.h>
- *  bsp_start
+#include <bsp/irq-generic.h>
- *
- *  This routine does the bulk of the system initialization.
- */
-void bsp_start( void )
-{
-  mips_set_sr( 0xff00 );  /* all interrupts unmasked but globally off */
-                          /* depend on the IRC to take care of things */
-  mips_install_isr_entries();
-}
-
-/*
- *  Required routine by some gcc run-times.
- */
-void clear_cache( void *address, size_t n )
-{
-}
 
 /* Structure filled in by get_mem_info.  Only the size field is
  * actually used (to clear bss), so the others aren't even filled in.
@@ -47,6 +35,30 @@ struct s_mem
   unsigned int dcsize;
 };
 
+void bsp_start( void );
+void clear_cache( void *address, size_t n );
+void get_mem_info( struct s_mem *mem );
+
+/*
+ *  bsp_start
+ *
+ *  This routine does the bulk of the system initialization.
+ */
+void bsp_start( void )
+{
+  mips_set_sr( 0xff00 );  /* all interrupts unmasked but globally off */
+                          /* depend on the IRC to take care of things */
+  bsp_interrupt_initialize();
+}
+
+/*
+ *  Required routine by some gcc run-times.
+ */
+void clear_cache( void *address, size_t n )
+{
+}
+
+
 void get_mem_info(
   struct s_mem *mem
 )

c/src/lib/libbsp/mips/rbtx4925/ChangeLog

@@ -1,3 +1,22 @@
+2012-03-08	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
+
+2012-03-06	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* clock/clockdrv.c, include/bsp.h,
+	include/irq.h, irq/vectorisrs.c, startup/bspstart.c:
+	Changed interrupt call, removed warnings and did cleanup.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* Makefile.am, clock/clockdrv.c, include/irq.h,
+	irq/vectorisrs.c, preinstall.am, startup/bspstart.c:
+	Mips conversion to PIC IRQ model.
+	* include/irq.h, irq/vectorisrs.c: New files.
+
 2011-12-14	Joel Sherrill <joel.sherrilL@OARcorp.com>
 
 	* Makefile.am: Change to one file per line. Clean up.

c/src/lib/libbsp/mips/rbtx4925/Makefile.am

@@ -13,6 +13,10 @@ dist_project_lib_DATA = bsp_specs
 include_HEADERS = include/bsp.h
 include_HEADERS += ../../shared/include/tm27.h
 include_bsp_HEADERS = ../shared/liblnk/regs.h
+#isr
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += include/irq.h
 
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -41,8 +45,6 @@ libbsp_a_SOURCES += ../../shared/bsppost.c
 libbsp_a_SOURCES += startup/bspstart.c
 libbsp_a_SOURCES += ../../shared/bootcard.c
 libbsp_a_SOURCES += ../../shared/sbrk.c
-libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
-libbsp_a_SOURCES += ../../shared/setvec.c
 libbsp_a_SOURCES += startup/inittlb.c
 libbsp_a_SOURCES += ../shared/startup/idttlb.S
 libbsp_a_SOURCES += ../shared/startup/idtmem.S
@@ -56,11 +58,21 @@ libbsp_a_SOURCES += console/console-io.c
 libbsp_a_SOURCES += ../shared/liblnk/lnklib.S
 libbsp_a_SOURCES += ../shared/liblnk/pmon.S
 libbsp_a_SOURCES += ../shared/liblnk/regs.h
+#isr
+libbsp_a_SOURCES += ../../shared/src/irq-generic.c
+libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
+libbsp_a_SOURCES += ../../shared/src/irq-info.c
+libbsp_a_SOURCES += ../../shared/src/irq-shell.c
+libbsp_a_SOURCES += ../../shared/src/irq-server.c
+libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
+libbsp_a_SOURCES += ../shared/irq/irq.c
+libbsp_a_SOURCES += ../shared/irq/maxvectors.c
+libbsp_a_SOURCES += irq/vectorisrs.c
+libbsp_a_SOURCES += ../shared/irq/interruptmask_TX49.c
 
 libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/timer.rel
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/vectorisrs.rel
 
 include $(srcdir)/preinstall.am
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/mips/rbtx4925/clock/clockdrv.c

@@ -1,11 +1,22 @@
-/*
+/**
- *  Instantiate the clock driver shell.
+ *  @file
  *  
- *  clockdrv.c,v 1.5 2001/01/09 17:05:57 joel Exp
+ *  Instantiate the clock driver shell.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
  */
 
 #include <rtems.h>
-#include <libcpu/tx4925.h>
+#include <bsp/irq.h>
 #include <bsp.h>
 
 /* #define CLOCK_DRIVER_USE_FAST_IDLE */
@@ -31,7 +42,13 @@
 
 #define Clock_driver_support_install_isr( _new, _old ) \
   do { \
-    _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
+    rtems_interrupt_handler_install( \
+      CLOCK_VECTOR, \
+      "clock", \
+      0, \
+      _new, \
+      NULL \
+    ); \
  } while(0)
 
 

c/src/lib/libbsp/mips/rbtx4925/include/bsp.h

@@ -1,15 +1,18 @@
-/*  bsp.h
+/**
+ *  @file
  *  
  *  This include file contains some definitions specific to the RBTX4925.
- *
+ */
- *  COPYRIGHT (c) 1989-2000.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  bsp.h,v 1.7.6.1 2003/09/04 18:44:49 joel Exp
+ *  $Id$
  */
 
 #ifndef _BSP_H
@@ -27,6 +30,9 @@ extern "C" {
 #include <rtems/clockdrv.h>
 #include <libcpu/tx4925.h>
 
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
 /* functions */
 
 rtems_isr_entry set_vector(

c/src/lib/libbsp/mips/rbtx4925/include/irq.h

@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#ifndef LIBBSP_MIPS_TX4925_IRQ_H
+#define LIBBSP_MIPS_TX4925_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ */
+#define BSP_INTERRUPT_VECTOR_MIN   0
+#define TX4925_IRQ_RSV1        MIPS_INTERRUPT_BASE+0
+#define TX4925_IRQ_WTE         MIPS_INTERRUPT_BASE+1
+#define TX4925_IRQ_INT0        MIPS_INTERRUPT_BASE+2
+#define TX4925_IRQ_INT1        MIPS_INTERRUPT_BASE+3
+#define TX4925_IRQ_INT2        MIPS_INTERRUPT_BASE+4
+#define TX4925_IRQ_INT3        MIPS_INTERRUPT_BASE+5
+#define TX4925_IRQ_INT4        MIPS_INTERRUPT_BASE+6
+#define TX4925_IRQ_INT5        MIPS_INTERRUPT_BASE+7
+#define TX4925_IRQ_INT6        MIPS_INTERRUPT_BASE+8
+#define TX4925_IRQ_INT7        MIPS_INTERRUPT_BASE+9
+#define TX4925_IRQ_RSV2        MIPS_INTERRUPT_BASE+10
+#define TX4925_IRQ_NAND        MIPS_INTERRUPT_BASE+11
+#define TX4925_IRQ_SIO0        MIPS_INTERRUPT_BASE+12
+#define TX4925_IRQ_SIO1        MIPS_INTERRUPT_BASE+13
+#define TX4925_IRQ_DMAC0       MIPS_INTERRUPT_BASE+14
+#define TX4925_IRQ_DMAC1       MIPS_INTERRUPT_BASE+15
+#define TX4925_IRQ_DMAC2       MIPS_INTERRUPT_BASE+16
+#define TX4925_IRQ_DMAC3       MIPS_INTERRUPT_BASE+17
+#define TX4925_IRQ_IRC         MIPS_INTERRUPT_BASE+18
+#define TX4925_IRQ_PDMAC       MIPS_INTERRUPT_BASE+19
+#define TX4925_IRQ_PCIC        MIPS_INTERRUPT_BASE+20
+#define TX4925_IRQ_TMR0        MIPS_INTERRUPT_BASE+21
+#define TX4925_IRQ_TMR1        MIPS_INTERRUPT_BASE+22
+#define TX4925_IRQ_TMR2        MIPS_INTERRUPT_BASE+23
+#define TX4925_IRQ_SPI         MIPS_INTERRUPT_BASE+24
+#define TX4925_IRQ_RTC         MIPS_INTERRUPT_BASE+25
+#define TX4925_IRQ_ACLC        MIPS_INTERRUPT_BASE+26
+#define TX4925_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
+#define TX4925_IRQ_CHI         MIPS_INTERRUPT_BASE+28
+#define TX4925_IRQ_PCIERR      MIPS_INTERRUPT_BASE+29
+#define TX4925_IRQ_PCIPME      MIPS_INTERRUPT_BASE+30
+#define TX4925_IRQ_RSV3        MIPS_INTERRUPT_BASE+31
+
+#define TX4925_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
+#define TX4925_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
+#define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
+
+#define BSP_INTERRUPT_VECTOR_MAX TX4925_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_ TX4925_IRQ_H */

c/src/lib/libbsp/mips/rbtx4925/irq/vectorisrs.c

@@ -0,0 +1,66 @@
+/**
+ *  @file
+ *  
+ *  TX4925 Interrupt Vectoring
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/tx4925.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
+void mips_default_isr( int vector );
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int pending;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  pending = (cause & sr & 0x700) >> CAUSE_IPSHIFT;
+
+  if ( pending & 0x4 ) {     /* (IP[2] == 1) ==> IP[3-7] are valid */
+    unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f;
+    bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + v );
+  }
+
+  if ( pending & 0x01 )       /* IP[0] */
+    bsp_interrupt_handler_dispatch( TX4925_IRQ_SOFTWARE_1 );
+
+  if ( pending & 0x02 )       /* IP[1] */
+    bsp_interrupt_handler_dispatch( TX4925_IRQ_SOFTWARE_2 );
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+
+  while(1);	/* Lock it up */
+
+  rtems_fatal_error_occurred(1);
+}
+

c/src/lib/libbsp/mips/rbtx4925/preinstall.am

@@ -49,6 +49,18 @@ $(PROJECT_INCLUDE)/bsp/regs.h: ../shared/liblnk/regs.h $(PROJECT_INCLUDE)/bsp/$(
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/regs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
 
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h

c/src/lib/libbsp/mips/rbtx4925/startup/bspstart.c

@@ -1,21 +1,28 @@
-/*
+/**
+ *  @file
+ *  
  *  This routine starts the application.  It includes application,
  *  board, and monitor specific initialization and configuration.
  *  The generic CPU dependent initialization has been performed
  *  before this routine is invoked.
- *
+ */
- *  COPYRIGHT (c) 1989-2000.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  * 
- *  bspstart.c,v 1.4.2.1 2003/09/04 18:44:49 joel Exp
+ *  $Id$
  */
 
 #include <bsp.h>
 #include <libcpu/isr_entries.h>
+#include <bsp/irq-generic.h>
+
+void bsp_start( void );
 
 /*
  *  bsp_start
@@ -24,6 +31,6 @@
  */
 void bsp_start( void )
 {
-  mips_install_isr_entries();  /* Install generic MIPS exception handler */
+  bsp_interrupt_initialize();
 }
 

c/src/lib/libbsp/mips/rbtx4938/ChangeLog

@@ -1,3 +1,22 @@
+2012-03-08	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
+
+2012-03-06	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* clock/clockdrv.c, include/bsp.h, include/irq.h,
+	irq/vectorisrs.c, startup/bspstart.c:
+	Changed interrupt call, removed warnings and did cleanup.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* Makefile.am, clock/clockdrv.c, include/irq.h,
+	irq/vectorisrs.c, preinstall.am, startup/bspstart.c,
+	Mips conversion to PIC IRQ model.
+	* include/irq.h, irq/vectorisrs.c: New files.
+
 2011-12-14	Joel Sherrill <joel.sherrilL@OARcorp.com>
 
 	* Makefile.am: Change to one file per line. Clean up.

c/src/lib/libbsp/mips/rbtx4938/Makefile.am

@@ -13,6 +13,10 @@ dist_project_lib_DATA = bsp_specs
 include_HEADERS = include/bsp.h
 include_HEADERS += ../../shared/include/tm27.h
 include_bsp_HEADERS = ../shared/liblnk/regs.h
+#isr
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += include/irq.h
 
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -41,8 +45,6 @@ libbsp_a_SOURCES += ../../shared/bsppost.c
 libbsp_a_SOURCES += startup/bspstart.c
 libbsp_a_SOURCES += ../../shared/bootcard.c
 libbsp_a_SOURCES += ../../shared/sbrk.c
-libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
-libbsp_a_SOURCES += ../../shared/setvec.c
 libbsp_a_SOURCES += startup/inittlb.c
 libbsp_a_SOURCES += ../shared/startup/idttlb.S
 libbsp_a_SOURCES += ../shared/startup/idtmem.S
@@ -56,11 +58,21 @@ libbsp_a_SOURCES += console/console-io.c
 libbsp_a_SOURCES += ../shared/liblnk/lnklib.S
 libbsp_a_SOURCES += ../shared/liblnk/pmon.S
 libbsp_a_SOURCES += ../shared/liblnk/regs.h
+#isr
+libbsp_a_SOURCES += ../../shared/src/irq-generic.c
+libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
+libbsp_a_SOURCES += ../../shared/src/irq-info.c
+libbsp_a_SOURCES += ../../shared/src/irq-shell.c
+libbsp_a_SOURCES += ../../shared/src/irq-server.c
+libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
+libbsp_a_SOURCES += ../shared/irq/irq.c
+libbsp_a_SOURCES += ../shared/irq/maxvectors.c
+libbsp_a_SOURCES += irq/vectorisrs.c
+libbsp_a_SOURCES += ../shared/irq/interruptmask_TX49.c
 
 libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/timer.rel
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/vectorisrs.rel
 
 include $(srcdir)/preinstall.am
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/mips/rbtx4938/clock/clockdrv.c

@@ -1,11 +1,22 @@
-/*
+/**
- *  Instantiate the clock driver shell.
+ *  @file
  *  
- *  clockdrv.c,v 1.5 2001/01/09 17:05:57 joel Exp
+ *  Instantiate the clock driver shell.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
  */
 
 #include <rtems.h>
-#include <libcpu/tx4938.h>
+#include <bsp/irq.h>
 #include <bsp.h>
 
 #include <stdio.h>
@@ -30,6 +41,7 @@
 #error "Build Error: unsupported timer mode"
 #endif
 
+void new_brk_esr(void);
 
 t_yamon_retfunc esr_retfunc = 0;
 t_yamon_ref original_brk_esr = 0;
@@ -49,7 +61,13 @@ void new_brk_esr(void)
 
 #define Clock_driver_support_install_isr( _new, _old ) \
   do { \
-    _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
+    rtems_interrupt_handler_install( \
+      CLOCK_VECTOR, \
+      "clock", \
+      0, \
+      _new, \
+      NULL \
+    ); \
     YAMON_FUNC_REGISTER_IC_ISR(17,(t_yamon_isr)_new,0,&original_tmr0_isr); /* Call Yamon to enable interrupt */ \
   } while(0)
 

c/src/lib/libbsp/mips/rbtx4938/include/bsp.h

@@ -1,15 +1,18 @@
-/*  bsp.h
+/**
+ *  @file
  *  
  *  This include file contains some definitions specific to the RBTX4938.
- *
+ */
- *  COPYRIGHT (c) 1989-2000.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  bsp.h,v 1.7.6.1 2003/09/04 18:44:49 joel Exp
+ *  $Id$
  */
 
 #ifndef _BSP_H
@@ -27,6 +30,9 @@ extern "C" {
 #include <rtems/clockdrv.h>
 #include <libcpu/tx4938.h>
 
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
 /* functions */
 
 rtems_isr_entry set_vector(

c/src/lib/libbsp/mips/rbtx4938/include/irq.h

@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#ifndef LIBBSP_MIPS_TX4938_IRQ_H
+#define LIBBSP_MIPS_TX4938_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ */
+#define BSP_INTERRUPT_VECTOR_MIN   0
+#define TX4938_IRQ_ECC         MIPS_INTERRUPT_BASE+0
+#define TX4938_IRQ_WTE         MIPS_INTERRUPT_BASE+1
+#define TX4938_IRQ_INT0        MIPS_INTERRUPT_BASE+2
+#define TX4938_IRQ_INT1        MIPS_INTERRUPT_BASE+3
+#define TX4938_IRQ_INT2        MIPS_INTERRUPT_BASE+4
+#define TX4938_IRQ_INT3        MIPS_INTERRUPT_BASE+5
+#define TX4938_IRQ_INT4        MIPS_INTERRUPT_BASE+6
+#define TX4938_IRQ_INT5        MIPS_INTERRUPT_BASE+7
+#define TX4938_IRQ_SIO0        MIPS_INTERRUPT_BASE+8
+#define TX4938_IRQ_SIO1        MIPS_INTERRUPT_BASE+9
+#define TX4938_IRQ_DMAC00      MIPS_INTERRUPT_BASE+10
+#define TX4938_IRQ_DMAC01      MIPS_INTERRUPT_BASE+11
+#define TX4938_IRQ_DMAC02      MIPS_INTERRUPT_BASE+12
+#define TX4938_IRQ_DMAC03      MIPS_INTERRUPT_BASE+13
+#define TX4938_IRQ_IRC         MIPS_INTERRUPT_BASE+14
+#define TX4938_IRQ_PDMAC       MIPS_INTERRUPT_BASE+15
+#define TX4938_IRQ_PCIC        MIPS_INTERRUPT_BASE+16
+#define TX4938_IRQ_TMR0        MIPS_INTERRUPT_BASE+17
+#define TX4938_IRQ_TMR1        MIPS_INTERRUPT_BASE+18
+#define TX4938_IRQ_TMR2        MIPS_INTERRUPT_BASE+19
+#define TX4938_IRQ_RSV1        MIPS_INTERRUPT_BASE+20
+#define TX4938_IRQ_NDFMC       MIPS_INTERRUPT_BASE+21
+#define TX4938_IRQ_PCIERR      MIPS_INTERRUPT_BASE+22
+#define TX4938_IRQ_PCIPMC      MIPS_INTERRUPT_BASE+23
+#define TX4938_IRQ_ACLC        MIPS_INTERRUPT_BASE+24
+#define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+25
+#define TX4938_IRQ_PCIC1NT     MIPS_INTERRUPT_BASE+26
+#define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
+#define TX4938_IRQ_DMAC10      MIPS_INTERRUPT_BASE+28
+#define TX4938_IRQ_DMAC11      MIPS_INTERRUPT_BASE+29
+#define TX4938_IRQ_DMAC12      MIPS_INTERRUPT_BASE+30
+#define TX4938_IRQ_DMAC13      MIPS_INTERRUPT_BASE+31
+
+#define TX4938_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
+#define TX4938_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
+#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
+
+#define BSP_INTERRUPT_VECTOR_MAX TX4938_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */

c/src/lib/libbsp/mips/rbtx4938/irq/vectorisrs.c

@@ -0,0 +1,66 @@
+/**
+ *  @file
+ *  
+ *  TX4925 Interrupt Vectoring
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/tx4938.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
+void mips_default_isr( int vector );
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int pending;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  pending = (cause & sr & 0x700) >> CAUSE_IPSHIFT;
+
+  if ( pending & 0x4 ) {     /* (IP[2] == 1) ==> IP[3-7] are valid */
+    unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f;
+    bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + v );
+  }
+
+  if ( pending & 0x01 )       /* IP[0] */
+    bsp_interrupt_handler_dispatch( TX4938_IRQ_SOFTWARE_1 );
+
+  if ( pending & 0x02 )       /* IP[1] */
+    bsp_interrupt_handler_dispatch( TX4938_IRQ_SOFTWARE_2 );
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+
+  while(1);	/* Lock it up */
+
+  rtems_fatal_error_occurred(1);
+}
+

c/src/lib/libbsp/mips/rbtx4938/preinstall.am

@@ -49,6 +49,18 @@ $(PROJECT_INCLUDE)/bsp/regs.h: ../shared/liblnk/regs.h $(PROJECT_INCLUDE)/bsp/$(
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/regs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
 
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h

c/src/lib/libbsp/mips/rbtx4938/startup/bspstart.c

@@ -1,21 +1,28 @@
-/*
+/**
+ *  @file
+ *  
  *  This routine starts the application.  It includes application,
  *  board, and monitor specific initialization and configuration.
  *  The generic CPU dependent initialization has been performed
  *  before this routine is invoked.
- *
+ */
- *  COPYRIGHT (c) 1989-2000.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  * 
- *  bspstart.c,v 1.4.2.1 2003/09/04 18:44:49 joel Exp
+ *  $Id$
  */
 
 #include <bsp.h>
 #include <libcpu/isr_entries.h>
+#include <bsp/irq-generic.h>
+
+void bsp_start( void );
 
 /*
  *  bsp_start
@@ -24,5 +31,5 @@
  */
 void bsp_start( void )
 {
-  mips_install_isr_entries();  /* Install generic MIPS exception handler */
+  bsp_interrupt_initialize();
 }

c/src/lib/libbsp/mips/shared/clock/clockdrv.c

@@ -0,0 +1,62 @@
+/*
+ *  COPYRIGHT (c) 1989-2011.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id: clockdrv.c,v 1.2 2012/02/06 14:17:28 jennifer Exp $
+ */
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bspopts.h>
+
+/* XXX convert to macros? Move to score/cpu? */
+void mips_set_timer(uint32_t timer_clock_interval);
+uint32_t mips_get_timer(void);
+uint32_t bsp_clock_nanoseconds_since_last_tick(void);
+
+/* XXX move to BSP.h or irq.h?? */
+#define EXT_INT5             0x8000  /* external interrupt 5 */
+#define CLOCK_VECTOR_MASK    EXT_INT5
+#define CLOCK_VECTOR         (MIPS_INTERRUPT_BASE+0x7)
+
+extern uint32_t bsp_clicks_per_microsecond;
+
+static uint32_t   mips_timer_rate = 0;
+
+/* refresh the internal CPU timer */
+#define Clock_driver_support_at_tick() \
+  mips_set_timer( mips_timer_rate );
+
+#define Clock_driver_support_install_isr( _new, _old ) \
+  do { \
+    rtems_interrupt_handler_install(CLOCK_VECTOR, \
+      "PIT clock",0, _new, NULL); \
+   } while(0)
+
+#define Clock_driver_support_initialize_hardware() \
+  do { \
+    mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * \
+      bsp_clicks_per_microsecond; \
+    mips_set_timer( mips_timer_rate ); \
+    printk("Clock_mask: %x\n", CLOCK_VECTOR_MASK ); \
+    mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK); \
+  } while(0)
+
+uint32_t bsp_clock_nanoseconds_since_last_tick(void)
+{
+  return 0;
+}
+
+#define Clock_driver_nanoseconds_since_last_tick \
+  bsp_clock_nanoseconds_since_last_tick
+
+#define Clock_driver_support_shutdown_hardware() \
+  do { \
+    mips_disable_in_interrupt_mask(CLOCK_VECTOR_MASK); \
+  } while (0)
+
+#include "../../../shared/clockdrv_shell.h"

c/src/lib/libbsp/mips/shared/clock/mips_timer.S

@@ -0,0 +1,45 @@
+/*  clock.s
+ *
+ *  This file contains the assembly code for the IDT 4650 clock driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  $Id: mips_timer.S,v 1.1 2011/12/09 18:06:08 joel Exp $
+ */
+/* @(#)clock.S       08/20/96     1.2 */
+
+#include <rtems/mips/iregdef.h>
+#include <rtems/mips/idtcpu.h>
+#include <rtems/asm.h>
+
+FRAME(mips_set_timer,sp,0,ra)
+	.set noreorder
+        mfc0 t0,C0_COUNT
+        nop
+        addu t0,a0,t0
+        mtc0 t0,C0_COMPARE
+        j ra
+	nop
+	.set reorder
+ENDFRAME(mips_set_timer)
+
+FRAME(mips_get_timer,sp,0,ra)
+	.set noreorder
+        mfc0 v0,C0_COUNT
+        j ra
+	nop
+	.set reorder
+ENDFRAME(mips_get_timer)

c/src/lib/libbsp/mips/shared/irq/i8259.c

@@ -0,0 +1,331 @@
+/**
+ *  @file
+ *  
+ *  This file was based upon the powerpc and the i386.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ */
+
+/*
+ *  Copyright (C) 1998, 1999 valette@crf.canon.fr
+ */
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/i8259.h>
+#include <bsp/pci.h>
+#include <bsp/irq-generic.h>
+
+
+#define DEBUG_8259      1
+
+#define ValidateIrqLine( _irq ) \
+   if ( ((int)_irq < 0) ||((int)_irq > 16)) return 1;
+
+/*-------------------------------------------------------------------------+
+| Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register.
++--------------------------------------------------------------------------*/
+/*
+ * lower byte is interrupt mask on the master PIC.
+ * while upper bits are interrupt on the slave PIC.
+ */
+volatile rtems_i8259_masks i8259s_cache = 0xfffb;
+
+/*-------------------------------------------------------------------------+
+|         Function:  BSP_irq_disable_at_i8259s
+|      Description: Mask IRQ line in appropriate PIC chip.
+| Global Variables: i8259s_cache
+|        Arguments: vector_offset - number of IRQ line to mask.
+|          Returns: original state or -1 on error.
++--------------------------------------------------------------------------*/
+int BSP_irq_disable_at_i8259s    (const rtems_irq_number irqLine)
+{
+  unsigned short        mask;
+  rtems_interrupt_level level;
+  int                   rval;
+
+  ValidateIrqLine(irqLine);
+
+  rtems_interrupt_disable(level);
+
+  /* Recalculate the value */
+  mask = 1 << irqLine;
+  rval = i8259s_cache & mask ? 0 : 1;
+  i8259s_cache |= mask;
+
+  /* Determine which chip and write the value. */
+  if (irqLine < 8) {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_IMR_IO_PORT, 
+      i8259s_cache & 0xff
+    );
+  } else {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_SLAVE_IMR_IO_PORT, 
+      ((i8259s_cache & 0xff00) >> 8)
+    );
+  }
+
+  rtems_interrupt_enable(level);
+
+  return rval;
+}
+
+/*-------------------------------------------------------------------------+
+|         Function:  BSP_irq_enable_at_i8259s
+|      Description: Unmask IRQ line in appropriate PIC chip.
+| Global Variables: i8259s_cache
+|        Arguments: irqLine - number of IRQ line to mask.
+|          Returns: Nothing.
++--------------------------------------------------------------------------*/
+int BSP_irq_enable_at_i8259s    (const rtems_irq_number irqLine)
+{
+  unsigned short        mask;
+  rtems_interrupt_level level;
+  
+  ValidateIrqLine( irqLine );
+
+  rtems_interrupt_disable(level);
+
+  /* Calculate the value */
+  mask = ~(1 << irqLine);
+  i8259s_cache &= mask;
+
+  /* Determine which chip and write the value */
+  if (irqLine < 8) {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_IMR_IO_PORT, 
+      i8259s_cache & 0xff
+    );
+  } else {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_SLAVE_IMR_IO_PORT, 
+      ((i8259s_cache & 0xff00) >> 8)
+    );
+  }
+
+  rtems_interrupt_enable(level);
+
+  return 0;
+} /* mask_irq */
+
+
+int BSP_irq_enabled_at_i8259s(const rtems_irq_number irqLine)
+{
+  unsigned short mask;
+
+  ValidateIrqLine( irqLine );
+
+  mask = (1 << irqLine);
+
+  return  (~(i8259s_cache & mask));
+}
+
+/*-------------------------------------------------------------------------+
+|         Function: BSP_irq_ack_at_i8259s
+|      Description: Signal generic End Of Interrupt (EOI) to appropriate PIC.
+| Global Variables: None.
+|        Arguments: irqLine - number of IRQ line to acknowledge.
+|          Returns: Nothing.
++--------------------------------------------------------------------------*/
+int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine)
+{
+  if (irqLine >= 8) {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_COMMAND_IO_PORT, 
+      SLAVE_PIC_EOSI
+    );
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_SLAVE_COMMAND_IO_PORT, 
+      (PIC_EOSI | (irqLine - 8))
+    );
+  }else {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_COMMAND_IO_PORT, 
+      (PIC_EOSI | irqLine)
+    );
+  }
+
+  return 0;
+
+} /* ackIRQ */
+
+void BSP_i8259s_init(void)
+{
+  volatile uint32_t i;
+
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT, 0xff );
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT,  0xff );
+  
+
+  /*
+   * init master 8259 interrupt controller
+   */
+
+  /* Start init sequence */
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_COMMAND_IO_PORT, 
+    0x11
+  );
+  /* Vector base  = 0 */
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_IMR_IO_PORT, 
+    0x00
+  );
+
+  /* edge tiggered, Cascade (slave) on IRQ2 */
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_IMR_IO_PORT, 
+    0x04
+  );
+
+  /* Select 8086 mode */
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_IMR_IO_PORT, 
+    0x01
+  );
+
+  /*
+   * init slave  interrupt controller
+   */
+
+  /* Start init sequence */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_COMMAND_IO_PORT, 0x11); 
+
+  /* Vector base  = 8 */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0x08);
+
+  /* edge triggered, Cascade (slave) on IRQ2 */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0x02);
+
+  /* Select 8086 mode */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0x01); 
+
+  /* Mask all except cascade */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT, 0xFB); 
+
+  /* Mask all */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0xFF); 
+
+  /*
+   * Enable all interrupts in debug mode.
+   */
+
+  if ( DEBUG_8259 ) {
+     i8259s_cache = 0x0101;
+  }
+
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_IMR_IO_PORT, 
+    i8259s_cache & 0xff
+  );
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_SLAVE_IMR_IO_PORT, 
+    ((i8259s_cache & 0xff00) >> 8)
+  );
+
+  for (i=0; i<10000; i++);
+}
+
+#define PCI__GEN(bus, off, num)		(((off)^((bus) << 7))+((num) << 4))
+#define PCI_INTR_ACK(bus)		PCI__GEN(bus, 0x0c34, 0)
+
+volatile uint8_t  master;
+volatile uint8_t  slave;
+volatile uint8_t  temp;
+
+void bsp_show_interrupt_regs(void);
+void bsp_show_interrupt_regs() {
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int pending;
+
+  mips_get_sr( sr ); 
+  mips_get_cause( cause );
+  pending = (cause & sr & 0xff00) >> CAUSE_IPSHIFT;
+
+  master = simple_in_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_COMMAND_IO_PORT);
+  slave  = simple_in_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_COMMAND_IO_PORT);
+
+  printk("sr: 0x%x cause: 0x%x pending: 0x%x  master: 0x%x slave: 0x%x\n", 
+    sr, cause, pending, master, slave 
+  );
+}
+
+int BSP_i8259s_int_process()
+{
+  uint8_t           irq;
+  volatile uint32_t temp;
+
+  /* Get the Interrupt */
+  irq = simple_in_le32(BSP_PCI_BASE_ADDRESS, PCI_INTR_ACK(0) );
+
+  /*
+   *  Mask interrupts
+   *   + Mask all except cascade on master
+   *   + Mask all on slave
+   */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT, 0xFB);
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0xFF);
+
+  /* Call the Handler */
+  temp = irq + MALTA_SB_IRQ_0;
+  bsp_interrupt_handler_dispatch( temp );
+
+  /* Reset the interrupt on the 8259 either the master or the slave chip */
+  if (irq & 8) {
+    temp = simple_in_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT);
+
+    /* Mask all */
+    simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0xFF); 
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_SLAVE_COMMAND_IO_PORT, 
+      (PIC_EOSI + (irq&7))
+    );
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_COMMAND_IO_PORT, 
+      SLAVE_PIC_EOSI 
+    );
+  } else {
+    temp = simple_in_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT);
+    /* Mask all except cascade */
+    simple_out_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT, 0xFB);
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_COMMAND_IO_PORT, 
+      (PIC_EOSI+irq)
+    );
+  }
+
+  /* Restore the interrupts */
+  simple_out_8(BSP_8259_BASE_ADDRESS,PIC_MASTER_IMR_IO_PORT,i8259s_cache&0xff);
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_SLAVE_IMR_IO_PORT, 
+    ((i8259s_cache & 0xff00) >> 8)
+  );
+
+  return 0;
+}

c/src/lib/libbsp/mips/shared/irq/i8259.h

@@ -0,0 +1,205 @@
+/* irq.h
+ *
+ *  This include file describe the data structure and the functions implemented
+ *  by RTEMS to control the i8259 chip.
+ *
+ *  Copyright (C) 1999 valette@crf.canon.fr
+ *
+ *  This code is heavilly inspired by the public specification of STREAM V2
+ *  that can be found at :
+ *
+ *      <http://www.chorus.com/Documentation/index.html> by following
+ *  the STREAM API Specification Document link.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id: i8259.h,v 1.1 2012/02/06 14:19:07 jennifer Exp $
+ */
+
+#ifndef I8259_H
+#define I8259_H
+
+/*
+ * 8259 edge/level control definitions at VIA
+ */
+#if 1 
+#define ISA8259_M_ELCR 		0x4d0
+#define ISA8259_S_ELCR 		0x4d1
+#endif
+
+#define ELCRS_INT15_LVL         0x80
+#define ELCRS_INT14_LVL         0x40
+#define ELCRS_INT13_LVL         0x20
+#define ELCRS_INT12_LVL         0x10
+#define ELCRS_INT11_LVL         0x08
+#define ELCRS_INT10_LVL         0x04
+#define ELCRS_INT9_LVL          0x02
+#define ELCRS_INT8_LVL          0x01
+#define ELCRM_INT7_LVL          0x80
+#define ELCRM_INT6_LVL          0x40
+#define ELCRM_INT5_LVL          0x20
+#define ELCRM_INT4_LVL          0x10
+#define ELCRM_INT3_LVL          0x8
+#define ELCRM_INT2_LVL          0x4
+#define ELCRM_INT1_LVL          0x2
+#define ELCRM_INT0_LVL          0x1
+
+/* 
+ * PIC's command and mask registers 
+ */
+#define PIC_MASTER_COMMAND_IO_PORT		0x20	/* Master PIC command register */
+#define PIC_SLAVE_COMMAND_IO_PORT		0xa0	/* Slave PIC command register */
+#define PIC_MASTER_IMR_IO_PORT			0x21	/* Master PIC Interrupt Mask Register */
+#define PIC_SLAVE_IMR_IO_PORT		 	0xa1	/* Slave PIC Interrupt Mask Register */
+
+/* 
+ * Command for specific EOI (End Of Interrupt): Interrupt acknowledge 
+ */
+#define PIC_EOSI	0x60	/* End of Specific Interrupt (EOSI) */
+#define	SLAVE_PIC_EOSI  0x62	/* End of Specific Interrupt (EOSI) for cascade */
+#define PIC_EOI		0x20	/* Generic End of Interrupt (EOI) */
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * rtems_irq_number Definitions
+ */
+#if 0
+/*
+ * ISA IRQ handler related definitions
+ */
+#define BSP_ISA_IRQ_NUMBER		(16)
+#define BSP_ISA_IRQ_LOWEST_OFFSET	(0)
+#define BSP_ISA_IRQ_MAX_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
+
+#ifndef qemu
+#define BSP_PCI_IRQ_NUMBER		(16)
+#else
+#define BSP_PCI_IRQ_NUMBER		(0)
+#endif
+#define BSP_PCI_IRQ_LOWEST_OFFSET	(BSP_ISA_IRQ_NUMBER)
+#define BSP_PCI_IRQ_MAX_OFFSET		(BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
+
+/*
+ * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
+ * handler might be connected
+ */
+#define BSP_PROCESSOR_IRQ_NUMBER	(1)
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
+/* Misc vectors for OPENPIC irqs (IPI, timers)
+ */
+#ifndef qemu
+#define BSP_MISC_IRQ_NUMBER		(8)
+#else
+#define BSP_MISC_IRQ_NUMBER		(0)
+#endif
+
+#define BSP_MISC_IRQ_LOWEST_OFFSET	(BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
+#define BSP_MISC_IRQ_MAX_OFFSET		(BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
+/*
+ * Summary
+ */
+#define BSP_IRQ_NUMBER			(BSP_MISC_IRQ_MAX_OFFSET + 1)
+#define BSP_LOWEST_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET)
+#define BSP_MAX_OFFSET			(BSP_MISC_IRQ_MAX_OFFSET)
+/*
+ * Some ISA IRQ symbolic name definition
+ */
+#define BSP_ISA_PERIODIC_TIMER      	(0)
+#define BSP_ISA_KEYBOARD          	(1)
+#define BSP_ISA_UART_COM2_IRQ		(3)
+#define BSP_ISA_UART_COM1_IRQ		(4)
+#define BSP_ISA_RT_TIMER1	      	(8)
+#define BSP_ISA_RT_TIMER3		(10)
+/*
+ * Some PCI IRQ symbolic name definition
+ */
+#define BSP_PCI_IRQ0			(BSP_PCI_IRQ_LOWEST_OFFSET)
+#if     BSP_PCI_IRQ_NUMBER > 0
+#define BSP_PCI_ISA_BRIDGE_IRQ		(BSP_PCI_IRQ0)
+#endif
+
+#if defined(mvme2100)
+#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
+#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
+#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
+#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
+#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
+#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
+#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
+#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
+#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
+#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
+#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
+#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
+#else
+#define BSP_UART_COM1_IRQ		BSP_ISA_UART_COM1_IRQ
+#define BSP_UART_COM2_IRQ		BSP_ISA_UART_COM2_IRQ
+#endif
+
+/*
+ * Some Processor execption handled as RTEMS IRQ symbolic name definition
+ */
+#define BSP_DECREMENTER			(BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+#endif
+
+/*
+ * Type definition for RTEMS managed interrupts
+ */
+typedef unsigned short rtems_i8259_masks;
+extern  volatile rtems_i8259_masks i8259s_cache;
+
+/*-------------------------------------------------------------------------+
+| Function Prototypes.
++--------------------------------------------------------------------------*/
+/*
+ * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
+ */
+void BSP_i8259s_init(void);
+
+/*
+ * function to disable a particular irq at 8259 level. After calling
+ * this function, even if the device asserts the interrupt line it will
+ * not be propagated further to the processor
+ *
+ * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
+ *          a value < 0 on error.
+ */
+int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
+/*
+ * function to enable a particular irq at 8259 level. After calling
+ * this function, if the device asserts the interrupt line it will
+ * be propagated further to the processor
+ */
+int BSP_irq_enable_at_i8259s		(const rtems_irq_number irqLine);
+/*
+ * function to acknowledge a particular irq at 8259 level. After calling
+ * this function, if a device asserts an enabled interrupt line it will
+ * be propagated further to the processor. Mainly usefull for people
+ * writing raw handlers as this is automagically done for RTEMS managed
+ * handlers.
+ */
+int BSP_irq_ack_at_i8259s           	(const rtems_irq_number irqLine);
+/*
+ * function to check if a particular irq is enabled at 8259 level. After calling
+ */
+int BSP_irq_enabled_at_i8259s        	(const rtems_irq_number irqLine);
+
+int BSP_i8259s_int_process(void);
+
+extern void BSP_rtems_irq_mng_init(unsigned cpuId);
+extern void BSP_i8259s_init(void);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+#endif

c/src/lib/libbsp/mips/shared/irq/interruptmask.c

@@ -0,0 +1,31 @@
+/**
+ *  @file
+ *  
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+
+/*
+ *  This function returns a mask value which is used to select the bits
+ *  in the processor status register that can be set to enable interrupts.
+ *  The mask value should not include the 2 software interrupt enable bits.
+ */
+
+uint32_t mips_interrupt_mask( void )
+{
+  uint32_t interrupt_mask;
+
+  interrupt_mask = 0x0000fc00;
+  return(interrupt_mask);
+}

c/src/lib/libbsp/mips/shared/irq/interruptmask_TX49.c

@@ -0,0 +1,31 @@
+/**
+ *  @file
+ *  
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+
+/*
+ *  This function returns a mask value which is used to select the bits
+ *  in the processor status register that can be set to enable interrupts.
+ *  The mask value should not include the 2 software interrupt enable bits.
+ */
+
+uint32_t mips_interrupt_mask( void )
+{
+  uint32_t interrupt_mask;
+
+  interrupt_mask = 0x00000400;			/* Toshiba TX49 processors have a non-standard interrupt mask */
+  return(interrupt_mask);
+}

c/src/lib/libbsp/mips/shared/irq/irq.c

@@ -0,0 +1,100 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Interrupt support.
+ */
+
+/*
+ *  Copyright (c) 2005 by Cogent Computer Systems
+ *  Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <libcpu/isr_entries.h>
+
+static const char *const cause_strings[32] = {
+  /*  0 */ "Int",
+  /*  1 */ "TLB Mods",
+  /*  2 */ "TLB Load",
+  /*  3 */ "TLB Store",
+  /*  4 */ "Address Load",
+  /*  5 */ "Address Store",
+  /*  6 */ "Instruction Bus Error",
+  /*  7 */ "Data Bus Error",
+  /*  8 */ "Syscall",
+  /*  9 */ "Breakpoint",
+  /* 10 */ "Reserved Instruction",
+  /* 11 */ "Coprocessor Unuseable",
+  /* 12 */ "Overflow",
+  /* 13 */ "Trap",
+  /* 14 */ "Instruction Virtual Coherency Error",
+  /* 15 */ "FP Exception",
+  /* 16 */ "Reserved 16",
+  /* 17 */ "Reserved 17",
+  /* 18 */ "Reserved 18",
+  /* 19 */ "Reserved 19",
+  /* 20 */ "Reserved 20",
+  /* 21 */ "Reserved 21",
+  /* 22 */ "Reserved 22",
+  /* 23 */ "Watch",
+  /* 24 */ "Reserved 24",
+  /* 25 */ "Reserved 25",
+  /* 26 */ "Reserved 26",
+  /* 27 */ "Reserved 27",
+  /* 28 */ "Reserved 28",
+  /* 29 */ "Reserved 29",
+  /* 30 */ "Reserved 30",
+  /* 31 */ "Data Virtual Coherency Error"
+};
+
+static inline bool bsp_irq_is_valid(rtems_vector_number vector)
+{
+  return vector <= BSP_INTERRUPT_VECTOR_MAX;
+}
+
+rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_facility_initialize(void)
+{
+  mips_install_isr_entries();
+  return RTEMS_SUCCESSFUL;
+}
+
+void bsp_interrupt_handler_default(rtems_vector_number vector)
+{
+  uint32_t sr;
+  uint32_t cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled exception %d\n", vector );
+  printk( "sr: 0x%08x  cause: 0x%08x --> %s\n", sr, cause,
+     cause_strings[(cause >> 2) &0x1f] );
+  #if 0
+    mips_dump_exception_frame( frame );
+  #endif
+  rtems_fatal_error_occurred(1);
+}

c/src/lib/libbsp/mips/shared/irq/maxvectors.c

@@ -1,8 +1,12 @@
-/*
+/**
+ *  @file
+ *  
  *  This file contains the maximum number of vectors.  This can not
  *  be determined without knowing the RTEMS CPU model.
- *
+ */
- *  COPYRIGHT (c) 1989-2000.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -12,8 +16,7 @@
  *  $Id$
  */
 
-/*
+#include <rtems.h>
- *  Reserve first 32 for exceptions.
+#include <bsp/irq.h>
- */
 
-unsigned int mips_interrupt_number_of_vectors = 32 + 8;
+unsigned int mips_interrupt_number_of_vectors = BSP_INTERRUPT_VECTOR_MAX;

c/src/lib/libbsp/mips/shared/irq/vectorexceptions.c

@@ -1,8 +1,19 @@
-/*
+/**
+ *  @file
+ *  
  *  Common Code for Vectoring MIPS Exceptions
  *
  *  The actual decoding of the cause register and vector number assignment
  *  is CPU model specific.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
  * 
  *  $Id$
  */
@@ -13,6 +24,9 @@
 #include <rtems/mips/iregdef.h>
 #include <rtems/mips/idtcpu.h>
 #include <rtems/bspIo.h>
+#include <bsp/irq-generic.h>
+
+void mips_vector_exceptions( CPU_Interrupt_frame *frame );
 
 static const char *cause_strings[32] =
 {
@@ -87,30 +101,6 @@ static void mips_dump_exception_frame( CPU_Interrupt_frame *frame )
   printk( "\n" );
 }
 
-static void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame )
-{
-  uint32_t sr;
-  uint32_t cause;
-
-  mips_get_sr( sr );
-  mips_get_cause( cause );
-
-  printk( "Unhandled exception %d\n", exc );
-  printk( "sr: 0x%08x  cause: 0x%08x --> %s\n", sr, cause,
-     cause_strings[(cause >> 2) &0x1f] );
-  mips_dump_exception_frame( frame );
-
-  rtems_fatal_error_occurred(1);
-}
-
-#define CALL_EXC(_vector,_frame) \
-   do { \
-        if ( _ISR_Vector_table[_vector] ) \
-             (_ISR_Vector_table[_vector])(_vector,_frame); \
-          else \
-             mips_default_exception_code_handler( _vector, _frame ); \
-   } while(0)
-
 /*
  *  There are constants defined for these but they should basically
  *  all be close to the same set.
@@ -124,5 +114,5 @@ void mips_vector_exceptions( CPU_Interrupt_frame *frame )
   mips_get_cause( cause );
   exc = (cause >> 2) & 0x1f;
 
-  CALL_EXC( exc, frame );
+  bsp_interrupt_handler_dispatch( exc );
 }

c/src/lib/libbsp/shared/clockdrv_shell.h

@@ -1,7 +1,11 @@
-/*
+/**
- *  Clock Tick Device Driver Shell
+ *  @file
  *  
- *  COPYRIGHT (c) 1989-2009.
+ *  Clock Tick Device Driver Shell
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -52,10 +56,17 @@ void Clock_exit( void );
  *
  *  Return values:      NONE
  */
+#ifdef BSP_FEATURE_IRQ_EXTENSION
+rtems_isr Clock_isr(void *arg);
+rtems_isr Clock_isr(void *arg)
+{
+#else 
+rtems_isr Clock_isr(rtems_vector_number vector);
 rtems_isr Clock_isr(
   rtems_vector_number vector
 )
 {
+#endif
   /*
    *  Accurate count of ISRs
    */

c/src/lib/libcpu/mips/ChangeLog

@@ -1,3 +1,16 @@
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* Makefile.am, au1x00/include/au1x00.h,
+	mongoosev/duart/mg5uart.c, mongoosev/include/mongoose-v.h,
+	rm52xx/include/rm5231.h, shared/interrupts/isr_entries.h,
+	tx39/include/tx3904.h, tx49/include/tx4925.h,
+	tx49/include/tx4938.h:
+	Mips conversion to PIC IRQ model.
+	* au1x00/vectorisrs/maxvectors.c,mongoosev/vectorisrs/maxvectors.c
+	rm52xx/vectorisrs/maxvectors.c, tx39/vectorisrs/maxvectors.c,
+	tx49/vectorisrs/maxvectors.c: Removed.
+
 2011-12-10	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* shared/interrupts/vectorexceptions.c: Make 

c/src/lib/libcpu/mips/Makefile.am

@@ -41,7 +41,6 @@ endif
 
 noinst_PROGRAMS += shared/interrupts.rel
 shared_interrupts_rel_SOURCES = shared/interrupts/installisrentries.c \
-    shared/interrupts/vectorexceptions.c shared/interrupts/interruptmask.c \
     shared/interrupts/isr_entries.S shared/interrupts/isr_entries.h
 shared_interrupts_rel_CPPFLAGS = $(AM_CPPFLAGS) $(interrupts_CPPFLAGS)
 shared_interrupts_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
@@ -62,32 +61,15 @@ mongoosev_duart_rel_SOURCES = mongoosev/duart/mg5uart.c \
 mongoosev_duart_rel_CPPFLAGS = $(AM_CPPFLAGS)
 mongoosev_duart_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 
-## mongoosev/vectorisrs
-
-noinst_PROGRAMS += mongoosev/vectorisrs.rel
-mongoosev_vectorisrs_rel_SOURCES = mongoosev/vectorisrs/maxvectors.c \
-   mongoosev/vectorisrs/vectorisrs.c
-mongoosev_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
-mongoosev_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
 if tx39
 include_libcpu_HEADERS += tx39/include/tx3904.h
-
-noinst_PROGRAMS += tx39/vectorisrs.rel
-tx39_vectorisrs_rel_SOURCES = tx39/vectorisrs/maxvectors.c tx39/vectorisrs/vectorisrs.c
-tx39_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
-tx39_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
 if tx49
 include_libcpu_HEADERS += tx49/include/tx4925.h tx49/include/tx4938.h
 
-noinst_PROGRAMS += tx49/vectorisrs.rel
-tx49_vectorisrs_rel_SOURCES = tx49/vectorisrs/maxvectors.c tx49/vectorisrs/vectorisrs.c
-tx49_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
-tx49_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-
 noinst_PROGRAMS += tx49/timer.rel
 tx49_timer_rel_SOURCES = timer/timer.c timer/gettime.S
 tx49_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
@@ -97,20 +79,9 @@ endif
 if au1x00
 include_libcpu_HEADERS += au1x00/include/au1x00.h
 
-noinst_PROGRAMS += au1x00/vectorisrs.rel
-au1x00_vectorisrs_rel_SOURCES = au1x00/vectorisrs/maxvectors.c \
-  au1x00/vectorisrs/vectorisrs.c
-au1x00_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
-au1x00_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
 if r46xx
-noinst_PROGRAMS += r46xx/vectorisrs.rel
-r46xx_vectorisrs_rel_SOURCES = r46xx/vectorisrs/maxvectors.c \
-   r46xx/vectorisrs/vectorisrs.c
-r46xx_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
-r46xx_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-
 noinst_PROGRAMS += r46xx/timer.rel
 r46xx_timer_rel_SOURCES = timer/timer.c timer/gettime.S
 r46xx_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
@@ -125,11 +96,6 @@ endif
 if rm52xx
 include_libcpu_HEADERS += rm52xx/include/rm5231.h
 
-noinst_PROGRAMS += rm52xx/vectorisrs.rel
-rm52xx_vectorisrs_rel_SOURCES = rm52xx/vectorisrs/maxvectors.c rm52xx/vectorisrs/vectorisrs.c
-rm52xx_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
-rm52xx_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-
 noinst_PROGRAMS += rm52xx/timer.rel
 rm52xx_timer_rel_SOURCES = timer/timer.c timer/gettime.S
 rm52xx_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)

c/src/lib/libcpu/mips/au1x00/include/au1x00.h

@@ -1,16 +1,18 @@
-/*
+/**
- *  AMD AU1X00 specific information
+ *  @file
  *  
+ *  AMD AU1X00 specific information
+ */
+
+/*
  *  Copyright (c) 2005 by Cogent Computer Systems
  *  Written by Jay Monkman <jtm@lopingdog.com>
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
- *
  *  http://www.rtems.com/license/LICENSE.
  * 
  *  $Id$
- *
  */
 
 #ifndef __AU1X00_H__
@@ -428,90 +430,6 @@ typedef struct {
 extern au1x00_uart_t *uart0;
 extern au1x00_uart_t *uart3;
 
-/*
- *  Interrupt Vector Numbers
- *
- */
-/* MIPS_INTERRUPT_BASE should be 32 (0x20) */
-#define AU1X00_IRQ_SW0                (MIPS_INTERRUPT_BASE + 0)
-#define AU1X00_IRQ_SW1                (MIPS_INTERRUPT_BASE + 1)
-#define AU1X00_IRQ_IC0_REQ0           (MIPS_INTERRUPT_BASE + 2)
-#define AU1X00_IRQ_IC0_REQ1           (MIPS_INTERRUPT_BASE + 3)
-#define AU1X00_IRQ_IC1_REQ0           (MIPS_INTERRUPT_BASE + 4)
-#define AU1X00_IRQ_IC1_REQ1           (MIPS_INTERRUPT_BASE + 5)
-#define AU1X00_IRQ_PERF               (MIPS_INTERRUPT_BASE + 6)
-#define AU1X00_IRQ_CNT                (MIPS_INTERRUPT_BASE + 7)
-
-#define AU1X00_IRQ_IC0_BASE           (MIPS_INTERRUPT_BASE + 8)
-#define AU1X00_IRQ_UART0              (MIPS_INTERRUPT_BASE + 8)
-#define AU1X00_IRQ_INTA               (MIPS_INTERRUPT_BASE + 9)
-#define AU1X00_IRQ_INTB               (MIPS_INTERRUPT_BASE + 10)
-#define AU1X00_IRQ_UART3              (MIPS_INTERRUPT_BASE + 11)
-#define AU1X00_IRQ_INTC               (MIPS_INTERRUPT_BASE + 12)
-#define AU1X00_IRQ_INTD               (MIPS_INTERRUPT_BASE + 13)
-#define AU1X00_IRQ_DMA0               (MIPS_INTERRUPT_BASE + 14)
-#define AU1X00_IRQ_DMA1               (MIPS_INTERRUPT_BASE + 15)
-#define AU1X00_IRQ_DMA2               (MIPS_INTERRUPT_BASE + 16)
-#define AU1X00_IRQ_DMA3               (MIPS_INTERRUPT_BASE + 17)
-#define AU1X00_IRQ_DMA4               (MIPS_INTERRUPT_BASE + 18)
-#define AU1X00_IRQ_DMA5               (MIPS_INTERRUPT_BASE + 19)
-#define AU1X00_IRQ_DMA6               (MIPS_INTERRUPT_BASE + 20)
-#define AU1X00_IRQ_DMA7               (MIPS_INTERRUPT_BASE + 21)
-#define AU1X00_IRQ_TOY_TICK           (MIPS_INTERRUPT_BASE + 22)
-#define AU1X00_IRQ_TOY_MATCH0         (MIPS_INTERRUPT_BASE + 23)
-#define AU1X00_IRQ_TOY_MATCH1         (MIPS_INTERRUPT_BASE + 24)
-#define AU1X00_IRQ_TOY_MATCH2         (MIPS_INTERRUPT_BASE + 25)
-#define AU1X00_IRQ_RTC_TICK           (MIPS_INTERRUPT_BASE + 26)
-#define AU1X00_IRQ_RTC_MATCH0         (MIPS_INTERRUPT_BASE + 27)
-#define AU1X00_IRQ_RTC_MATCH1         (MIPS_INTERRUPT_BASE + 28)
-#define AU1X00_IRQ_RTC_MATCH2         (MIPS_INTERRUPT_BASE + 29)
-#define AU1X00_IRQ_PCI_ERR            (MIPS_INTERRUPT_BASE + 30)
-#define AU1X00_IRQ_RSV0               (MIPS_INTERRUPT_BASE + 31)
-#define AU1X00_IRQ_USB_DEV            (MIPS_INTERRUPT_BASE + 32)
-#define AU1X00_IRQ_USB_SUSPEND        (MIPS_INTERRUPT_BASE + 33)
-#define AU1X00_IRQ_USB_HOST           (MIPS_INTERRUPT_BASE + 34)
-#define AU1X00_IRQ_AC97_ACSYNC        (MIPS_INTERRUPT_BASE + 35)
-#define AU1X00_IRQ_MAC0               (MIPS_INTERRUPT_BASE + 36)
-#define AU1X00_IRQ_MAC1               (MIPS_INTERRUPT_BASE + 37)
-#define AU1X00_IRQ_RSV1               (MIPS_INTERRUPT_BASE + 38)
-#define AU1X00_IRQ_AC97_CMD           (MIPS_INTERRUPT_BASE + 39)
-
-#define AU1X00_IRQ_IC1_BASE           (MIPS_INTERRUPT_BASE + 40)
-#define AU1X00_IRQ_GPIO0              (MIPS_INTERRUPT_BASE + 40)
-#define AU1X00_IRQ_GPIO1              (MIPS_INTERRUPT_BASE + 41)
-#define AU1X00_IRQ_GPIO2              (MIPS_INTERRUPT_BASE + 42)
-#define AU1X00_IRQ_GPIO3              (MIPS_INTERRUPT_BASE + 43)
-#define AU1X00_IRQ_GPIO4              (MIPS_INTERRUPT_BASE + 44)
-#define AU1X00_IRQ_GPIO5              (MIPS_INTERRUPT_BASE + 45)
-#define AU1X00_IRQ_GPIO6              (MIPS_INTERRUPT_BASE + 46)
-#define AU1X00_IRQ_GPIO7              (MIPS_INTERRUPT_BASE + 47)
-#define AU1X00_IRQ_GPIO8              (MIPS_INTERRUPT_BASE + 48)
-#define AU1X00_IRQ_GPIO9              (MIPS_INTERRUPT_BASE + 49)
-#define AU1X00_IRQ_GPIO10             (MIPS_INTERRUPT_BASE + 50)
-#define AU1X00_IRQ_GPIO11             (MIPS_INTERRUPT_BASE + 51)
-#define AU1X00_IRQ_GPIO12             (MIPS_INTERRUPT_BASE + 52)
-#define AU1X00_IRQ_GPIO13             (MIPS_INTERRUPT_BASE + 53)
-#define AU1X00_IRQ_GPIO14             (MIPS_INTERRUPT_BASE + 54)
-#define AU1X00_IRQ_GPIO15             (MIPS_INTERRUPT_BASE + 55)
-#define AU1X00_IRQ_GPIO200            (MIPS_INTERRUPT_BASE + 56)
-#define AU1X00_IRQ_GPIO201            (MIPS_INTERRUPT_BASE + 57)
-#define AU1X00_IRQ_GPIO202            (MIPS_INTERRUPT_BASE + 58)
-#define AU1X00_IRQ_GPIO203            (MIPS_INTERRUPT_BASE + 59)
-#define AU1X00_IRQ_GPIO20             (MIPS_INTERRUPT_BASE + 60)
-#define AU1X00_IRQ_GPIO204            (MIPS_INTERRUPT_BASE + 61)
-#define AU1X00_IRQ_GPIO205            (MIPS_INTERRUPT_BASE + 62)
-#define AU1X00_IRQ_GPIO23             (MIPS_INTERRUPT_BASE + 63)
-#define AU1X00_IRQ_GPIO24             (MIPS_INTERRUPT_BASE + 64)
-#define AU1X00_IRQ_GPIO25             (MIPS_INTERRUPT_BASE + 65)
-#define AU1X00_IRQ_GPIO26             (MIPS_INTERRUPT_BASE + 66)
-#define AU1X00_IRQ_GPIO27             (MIPS_INTERRUPT_BASE + 67)
-#define AU1X00_IRQ_GPIO28             (MIPS_INTERRUPT_BASE + 68)
-#define AU1X00_IRQ_GPIO206            (MIPS_INTERRUPT_BASE + 69)
-#define AU1X00_IRQ_GPIO207            (MIPS_INTERRUPT_BASE + 70)
-#define AU1X00_IRQ_GPIO208_215        (MIPS_INTERRUPT_BASE + 71)
-
-#define AU1X00_MAXIMUM_VECTORS        (MIPS_INTERRUPT_BASE + 72)
-
 void static inline au_sync(void)
 {
 	__asm__ volatile ("sync");

c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c

@@ -1,23 +0,0 @@
-/*
- *  This file contains the maximum number of vectors.  This can not
- *  be determined without knowing the RTEMS CPU model.
- *
- *  COPYRIGHT (c) 1989-2000.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  maxvectors.c,v 1.1 2001/05/24 19:54:22 joel Exp
- */
-
-/*
- *  Reserve first 32 for exceptions.
- */
-
-#include <rtems.h>
-#include <libcpu/au1x00.h>
-
-unsigned int mips_interrupt_number_of_vectors = AU1X00_MAXIMUM_VECTORS;
-

c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c

@@ -1,8 +1,12 @@
-/*
+/**
+ *  @file
+ *  
  *  This file contains the termios TTY driver for the UART found
  *  on the Synova Mongoose-V.
- *
+ */
- *  COPYRIGHT (c) 1989-2001.
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -21,7 +25,8 @@
 #include <libchip/sersupp.h>
 #include <libcpu/mongoose-v.h>
 
-extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
+#include <bsp/irq.h>
+#include <bsp.h>
 
 /*
  *  Indices of registers
@@ -69,6 +74,48 @@ MG5UART_STATIC void mg5uart_enable_interrupts(
   int mask
 );
 
+/*
+ *  mg5uart_isr_XXX
+ *
+ *  This is the single interrupt entry point which parcels interrupts
+ *  out to the handlers for specific sources and makes sure that the
+ *  shared handler gets the right arguments.
+ *
+ *  NOTE: Yes .. this is ugly but it provides 5 interrupt source
+ *  wrappers which are nearly functionally identical.
+ */
+
+
+extern void mips_default_isr(int vector);
+
+#define __ISR(_TYPE, _OFFSET) \
+  MG5UART_STATIC void mg5uart_process_isr_ ## _TYPE ( \
+    int  minor \
+  ); \
+  \
+  MG5UART_STATIC rtems_isr mg5uart_isr_ ## _TYPE ( \
+    void *arg \
+  ) \
+  { \
+    rtems_vector_number vector = (rtems_vector_number) arg; \
+    int   minor; \
+    \
+    for(minor=0 ; minor<Console_Port_Count ; minor++) { \
+      if( Console_Port_Tbl[minor]->deviceType == SERIAL_MG5UART && \
+          vector == Console_Port_Tbl[minor]->ulIntVector + _OFFSET ) { \
+        mg5uart_process_isr_ ## _TYPE (minor); \
+	return; \
+      } \
+    } \
+    mips_default_isr( vector ); \
+  }
+
+__ISR(rx_frame_error, MG5UART_IRQ_RX_FRAME_ERROR)
+__ISR(rx_overrun_error, MG5UART_IRQ_RX_OVERRUN_ERROR)
+__ISR(tx_empty, MG5UART_IRQ_TX_EMPTY)
+__ISR(tx_ready, MG5UART_IRQ_TX_READY)
+__ISR(rx_ready, MG5UART_IRQ_RX_READY)
+
 /*
  *  mg5uart_set_attributes
  *
@@ -425,51 +472,6 @@ MG5UART_STATIC void mg5uart_write_polled(
   MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, c);
 }
 
-
-
-
-/*
- *  mg5uart_isr_XXX
- *
- *  This is the single interrupt entry point which parcels interrupts
- *  out to the handlers for specific sources and makes sure that the
- *  shared handler gets the right arguments.
- *
- *  NOTE: Yes .. this is ugly but it provides 5 interrupt source
- *  wrappers which are nearly functionally identical.
- */
-
-
-extern void mips_default_isr(int vector);
-
-#define __ISR(_TYPE, _OFFSET) \
-  MG5UART_STATIC void mg5uart_process_isr_ ## _TYPE ( \
-    int  minor \
-  ); \
-  \
-  MG5UART_STATIC rtems_isr mg5uart_isr_ ## _TYPE ( \
-    rtems_vector_number vector \
-  ) \
-  { \
-    int   minor; \
-    \
-    for(minor=0 ; minor<Console_Port_Count ; minor++) { \
-      if( Console_Port_Tbl[minor]->deviceType == SERIAL_MG5UART && \
-          vector == Console_Port_Tbl[minor]->ulIntVector + _OFFSET ) { \
-        mg5uart_process_isr_ ## _TYPE (minor); \
-	return; \
-      } \
-    } \
-    mips_default_isr( vector ); \
-  }
-
-__ISR(rx_frame_error, MG5UART_IRQ_RX_FRAME_ERROR)
-__ISR(rx_overrun_error, MG5UART_IRQ_RX_OVERRUN_ERROR)
-__ISR(tx_empty, MG5UART_IRQ_TX_EMPTY)
-__ISR(tx_ready, MG5UART_IRQ_TX_READY)
-__ISR(rx_ready, MG5UART_IRQ_RX_READY)
-
-
 MG5UART_STATIC void mg5uart_process_isr_rx_error(
    int  minor,
    uint32_t   mask
@@ -591,9 +593,50 @@ MG5UART_STATIC void mg5uart_process_isr_rx_ready(
      &c, 1 );
 }
 
+static rtems_irq_connect_data mg5uart_rx_frame_error_cd  = {  \
+  0,                             /* filled in at initialization */
+  mg5uart_isr_rx_frame_error,   /* filled in at initialization */
+  NULL,   /* (void *) minor */
+  NULL,
+  NULL,
+  NULL
+};
 
+static rtems_irq_connect_data mg5uart_rx_overrun_error_cd  = {  \
+  0,                             /* filled in at initialization */
+  mg5uart_isr_rx_overrun_error,   /* filled in at initialization */
+  NULL,   /* (void *) minor */
+  NULL,
+  NULL,
+  NULL
+};
 
+static rtems_irq_connect_data mg5uart_tx_empty_cd  = {  \
+  0,                             /* filled in at initialization */
+  mg5uart_isr_tx_empty,   /* filled in at initialization */
+  NULL,   /* (void *) minor */
+  NULL,
+  NULL,
+  NULL
+};
 
+static rtems_irq_connect_data mg5uart_tx_ready_cd  = {  \
+  0,                             /* filled in at initialization */
+  mg5uart_isr_tx_ready,   /* filled in at initialization */
+  NULL,   /* (void *) minor */
+  NULL,
+  NULL,
+  NULL
+};
+
+static rtems_irq_connect_data mg5uart_rx_ready_cd  = {  \
+  0,                             /* filled in at initialization */
+  mg5uart_isr_rx_ready,   /* filled in at initialization */
+  NULL,   /* (void *) minor */
+  NULL,
+  NULL,
+  NULL
+};
 
 
 /*
@@ -611,19 +654,28 @@ MG5UART_STATIC void mg5uart_initialize_interrupts(int minor)
   Console_Port_Data[minor].bActive = FALSE;
   v = Console_Port_Tbl[minor]->ulIntVector;
 
-  set_vector(mg5uart_isr_rx_frame_error,   v + MG5UART_IRQ_RX_FRAME_ERROR, 1);
+  mg5uart_rx_frame_error_cd.name    =  v + MG5UART_IRQ_RX_FRAME_ERROR;
-  set_vector(mg5uart_isr_rx_overrun_error, v + MG5UART_IRQ_RX_OVERRUN_ERROR, 1);
+  mg5uart_rx_overrun_error_cd.name  =  v + MG5UART_IRQ_RX_OVERRUN_ERROR; 
-  set_vector(mg5uart_isr_tx_empty,         v + MG5UART_IRQ_TX_EMPTY, 1);
+  mg5uart_tx_empty_cd.name          =  v + MG5UART_IRQ_TX_EMPTY;  
-  set_vector(mg5uart_isr_tx_ready,         v + MG5UART_IRQ_TX_READY, 1);
+  mg5uart_tx_ready_cd.name          =  v + MG5UART_IRQ_TX_READY; 
-  set_vector(mg5uart_isr_rx_ready,         v + MG5UART_IRQ_RX_READY, 1);
+  mg5uart_rx_ready_cd.name          =  v + MG5UART_IRQ_RX_READY; 
+
+  mg5uart_rx_frame_error_cd.handle    =  (void *)mg5uart_rx_frame_error_cd.name;
+  mg5uart_rx_overrun_error_cd.handle  =  (void *)mg5uart_rx_overrun_error_cd.name; 
+  mg5uart_tx_empty_cd.handle          =  (void *)mg5uart_tx_empty_cd.name;  
+  mg5uart_tx_ready_cd.handle          =  (void *)mg5uart_tx_ready_cd.name; 
+  mg5uart_rx_ready_cd.handle          =  (void *)mg5uart_rx_ready_cd.name; 
+
+ 
+  BSP_install_rtems_irq_handler( &mg5uart_rx_frame_error_cd );
+  BSP_install_rtems_irq_handler( &mg5uart_rx_overrun_error_cd );
+  BSP_install_rtems_irq_handler( &mg5uart_tx_empty_cd );
+  BSP_install_rtems_irq_handler( &mg5uart_tx_ready_cd );
+  BSP_install_rtems_irq_handler( &mg5uart_rx_ready_cd );
 
   mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
 }
 
-
-
-
-
 /*
  *  mg5uart_write_support_int
  *

c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h

@@ -1,7 +1,11 @@
-/*
+/**
- *  MIPS Mongoose-V specific information
+ *  @file
  *  
- *  COPYRIGHT (c) 1989-2001.
+ *  MIPS Mongoose-V specific information
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -249,62 +253,6 @@
 #define MONGOOSEV_TX_BUFFER    4
 #define MONGOOSEV_BAUD_RATE    8
 
-/*
- *  Interrupt Vector Numbers
- *
- *  NOTE: IRQ INT5 is logical or of peripheral cause register
- *        per p. 5-22 of Mongoose-V manual.
- */
-
-#define MONGOOSEV_IRQ_INT0                    MIPS_INTERRUPT_BASE+0
-#define MONGOOSEV_IRQ_TIMER1                  MONGOOSEV_IRQ_INT0
-#define MONGOOSEV_IRQ_INT1                    MIPS_INTERRUPT_BASE+1
-#define MONGOOSEV_IRQ_TIMER2                  MONGOOSEV_IRQ_INT1
-#define MONGOOSEV_IRQ_INT2                    MIPS_INTERRUPT_BASE+2
-#define MONGOOSEV_IRQ_INT3                    MIPS_INTERRUPT_BASE+3
-#define MONGOOSEV_IRQ_FPU		      MONGOOSEV_IRQ_INT3
-
-#define MONGOOSEV_IRQ_INT4                    MIPS_INTERRUPT_BASE+4
-
-/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
-#define MONGOOSEV_IRQ_PERIPHERAL_BASE         MIPS_INTERRUPT_BASE+5
-#define MONGOOSEV_IRQ_XINT0                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 0
-#define MONGOOSEV_IRQ_XINT1                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 1
-#define MONGOOSEV_IRQ_XINT2                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 2
-#define MONGOOSEV_IRQ_XINT3                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 3
-#define MONGOOSEV_IRQ_XINT4                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 4
-#define MONGOOSEV_IRQ_XINT5                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 5
-#define MONGOOSEV_IRQ_XINT6                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 6
-#define MONGOOSEV_IRQ_XINT7                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 7
-#define MONGOOSEV_IRQ_XINT8                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 8
-#define MONGOOSEV_IRQ_XINT9                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 9
-#define MONGOOSEV_IRQ_RESERVED_BIT_10	     MONGOOSEV_IRQ_PERIPHERAL_BASE + 10
-#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR   MONGOOSEV_IRQ_PERIPHERAL_BASE + 11
-#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12
-#define MONGOOSEV_IRQ_UART0_TX_EMPTY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 13
-#define MONGOOSEV_IRQ_UART0_TX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 14
-#define MONGOOSEV_IRQ_UART0_RX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 15
-#define MONGOOSEV_IRQ_RESERVED_BIT_16        MONGOOSEV_IRQ_PERIPHERAL_BASE + 16
-#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR   MONGOOSEV_IRQ_PERIPHERAL_BASE + 17
-#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18
-#define MONGOOSEV_IRQ_UART1_TX_EMPTY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 19
-#define MONGOOSEV_IRQ_UART1_TX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 20
-#define MONGOOSEV_IRQ_UART1_RX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 21
-#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION  MONGOOSEV_IRQ_PERIPHERAL_BASE + 22
-#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23
-#define MONGOOSEV_IRQ_RESERVED_24            MONGOOSEV_IRQ_PERIPHERAL_BASE + 24
-#define MONGOOSEV_IRQ_RESERVED_25            MONGOOSEV_IRQ_PERIPHERAL_BASE + 25
-#define MONGOOSEV_IRQ_RESERVED_26            MONGOOSEV_IRQ_PERIPHERAL_BASE + 26
-#define MONGOOSEV_IRQ_RESERVED_27            MONGOOSEV_IRQ_PERIPHERAL_BASE + 27
-#define MONGOOSEV_IRQ_RESERVED_28            MONGOOSEV_IRQ_PERIPHERAL_BASE + 28
-#define MONGOOSEV_IRQ_RESERVED_29            MONGOOSEV_IRQ_PERIPHERAL_BASE + 29
-#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR    MONGOOSEV_IRQ_PERIPHERAL_BASE + 30
-#define MONGOOSEV_IRQ_CORRECTABLE_ERROR      MONGOOSEV_IRQ_PERIPHERAL_BASE + 31
-
-#define MONGOOSEV_IRQ_SOFTWARE_1             MIPS_INTERRUPT_BASE+37
-#define MONGOOSEV_IRQ_SOFTWARE_2             MIPS_INTERRUPT_BASE+38
-#define MONGOOSEV_MAXIMUM_VECTORS            MIPS_INTERRUPT_BASE+39
-
 
 /*
  *  Status Register Bits

c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c

@@ -1,31 +0,0 @@
-/*
- *  This file contains the maximum number of vectors.  This can not
- *  be determined without knowing the RTEMS CPU model.
- *
- *  COPYRIGHT (c) 1989-2000.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-/*
- *  Reserve first 32 for exceptions.
- */
-
-/*
- *  The Synova Mongoose-V attached one of the eight interrupt bits
- *  to a Peripheral Function Interrupt Cause Register on-CPU.
- *  This results in: 2 software interrupts, 5 interrupts
- *  through the IP bits, and 32 more from the PFICR.  Some of
- *  these are reserved but for simplicity in processing, we
- *  reserve slots for those bits anyway.
- */
-
-#include <rtems.h>
-#include <libcpu/mongoose-v.h>
-
-unsigned int mips_interrupt_number_of_vectors = MONGOOSEV_MAXIMUM_VECTORS;

c/src/lib/libcpu/mips/rm52xx/include/rm5231.h

@@ -1,12 +1,21 @@
-/*
+/**
- *  MIPS RM5231 specific information
+ *  @file
  *  
- *  rm5231.h,v 1.0 2004/06/23 19:54:22
+ *  MIPS RM5231 specific information
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
  */
 
 #ifndef __RM5231_h
 #define __RM5231_h
 
-#define RM5231_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+8
-
 #endif

c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c

@@ -1,24 +0,0 @@
-/*
- *  This file contains the maximum number of vectors.  This can not
- *  be determined without knowing the RTEMS CPU model.
- *
- *  COPYRIGHT (c) 1989-2000.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  maxvectors.c,v 1.1.6.1 2003/09/04 18:45:49 joel Exp
- */
-
-/*
- *  Reserve first 32 for exceptions.
- */
-
-
-#include <rtems.h>
-#include <libcpu/rm5231.h>
-
-unsigned int mips_interrupt_number_of_vectors = RM5231_MAXIMUM_VECTORS;
-

c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h

@@ -1,4 +1,16 @@
+/**
+ *  @file
+ *  
+ */
+
 /*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
  *  $Id$
  */
 
@@ -6,6 +18,7 @@
 #define _ISR_ENTRIES_H 1
 
 extern void mips_install_isr_entries( void );
+extern void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
 
 #if __mips == 1
 extern void exc_utlb_code(void);

c/src/lib/libcpu/mips/tx39/include/tx3904.h

@@ -1,7 +1,18 @@
-/*
+/**
+ *  @file
+ *  
  *  MIPS Tx3904 specific information
  *
  *  NOTE: This is far from complete.  --joel (13 Dec 2000)
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
  * 
  *  $Id$
  */
@@ -33,32 +44,4 @@
 #define TX3904_TIMER_WRITE( _base, _register, _value ) \
   *((volatile uint32_t*)((_base) + (_register))) = (_value)
 
-/*
- *  Interrupt Vector Numbers
- *
- *  NOTE: Numbers 0-15 directly map to levels on the IRC.
- *        Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
- */
-
-#define TX3904_IRQ_INT1        MIPS_INTERRUPT_BASE+0
-#define TX3904_IRQ_INT2        MIPS_INTERRUPT_BASE+1
-#define TX3904_IRQ_INT3        MIPS_INTERRUPT_BASE+2
-#define TX3904_IRQ_INT4        MIPS_INTERRUPT_BASE+3
-#define TX3904_IRQ_INT5        MIPS_INTERRUPT_BASE+4
-#define TX3904_IRQ_INT6        MIPS_INTERRUPT_BASE+5
-#define TX3904_IRQ_INT7        MIPS_INTERRUPT_BASE+6
-#define TX3904_IRQ_DMAC3       MIPS_INTERRUPT_BASE+7
-#define TX3904_IRQ_DMAC2       MIPS_INTERRUPT_BASE+8
-#define TX3904_IRQ_DMAC1       MIPS_INTERRUPT_BASE+9
-#define TX3904_IRQ_DMAC0       MIPS_INTERRUPT_BASE+10
-#define TX3904_IRQ_SIO0        MIPS_INTERRUPT_BASE+11
-#define TX3904_IRQ_SIO1        MIPS_INTERRUPT_BASE+12
-#define TX3904_IRQ_TMR0        MIPS_INTERRUPT_BASE+13
-#define TX3904_IRQ_TMR1        MIPS_INTERRUPT_BASE+14
-#define TX3904_IRQ_TMR2        MIPS_INTERRUPT_BASE+15
-#define TX3904_IRQ_INT0        MIPS_INTERRUPT_BASE+16
-#define TX3904_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+17
-#define TX3904_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+18
-#define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
-
 #endif

c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c

@@ -1,29 +0,0 @@
-/*
- *  This file contains the maximum number of vectors.  This can not
- *  be determined without knowing the RTEMS CPU model.
- *
- *  COPYRIGHT (c) 1989-2000.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-/*
- *  Reserve first 32 for exceptions.
- */
-
-/*
- *  The Toshiba TX3904 attaches 4 of the eight interrupt bits to an
- *  on-CPU interrupt controller so that these four bits map to 16
- *  unique interrupts.  So you have: 2 software interrupts, an NMI,
- *  and 16 others.
- */
-
-#include <rtems.h>
-#include <libcpu/tx3904.h>
-
-unsigned int mips_interrupt_number_of_vectors = TX3904_MAXIMUM_VECTORS;

c/src/lib/libcpu/mips/tx49/include/tx4925.h

@@ -1,7 +1,18 @@
-/*
+/**
- *  MIPS Tx4925 specific information
+ *  @file
  *  
- *  tx4925.h,v 1.0 2004/06/23 19:54:22
+ *  MIPS Tx4925 specific information
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
  */
 
 #ifndef __TX4925_h
@@ -95,45 +106,4 @@
 #define TX4925_REG_WRITE( _base, _register, _value ) \
   *((volatile uint32_t *)((_base) + (_register))) = (_value)
 
-/*
- *  Interrupt Vector Numbers
- *
- */
-#define TX4925_IRQ_RSV1        MIPS_INTERRUPT_BASE+0
-#define TX4925_IRQ_WTE         MIPS_INTERRUPT_BASE+1
-#define TX4925_IRQ_INT0        MIPS_INTERRUPT_BASE+2
-#define TX4925_IRQ_INT1        MIPS_INTERRUPT_BASE+3
-#define TX4925_IRQ_INT2        MIPS_INTERRUPT_BASE+4
-#define TX4925_IRQ_INT3        MIPS_INTERRUPT_BASE+5
-#define TX4925_IRQ_INT4        MIPS_INTERRUPT_BASE+6
-#define TX4925_IRQ_INT5        MIPS_INTERRUPT_BASE+7
-#define TX4925_IRQ_INT6        MIPS_INTERRUPT_BASE+8
-#define TX4925_IRQ_INT7        MIPS_INTERRUPT_BASE+9
-#define TX4925_IRQ_RSV2        MIPS_INTERRUPT_BASE+10
-#define TX4925_IRQ_NAND        MIPS_INTERRUPT_BASE+11
-#define TX4925_IRQ_SIO0        MIPS_INTERRUPT_BASE+12
-#define TX4925_IRQ_SIO1        MIPS_INTERRUPT_BASE+13
-#define TX4925_IRQ_DMAC0       MIPS_INTERRUPT_BASE+14
-#define TX4925_IRQ_DMAC1       MIPS_INTERRUPT_BASE+15
-#define TX4925_IRQ_DMAC2       MIPS_INTERRUPT_BASE+16
-#define TX4925_IRQ_DMAC3       MIPS_INTERRUPT_BASE+17
-#define TX4925_IRQ_IRC         MIPS_INTERRUPT_BASE+18
-#define TX4925_IRQ_PDMAC       MIPS_INTERRUPT_BASE+19
-#define TX4925_IRQ_PCIC        MIPS_INTERRUPT_BASE+20
-#define TX4925_IRQ_TMR0        MIPS_INTERRUPT_BASE+21
-#define TX4925_IRQ_TMR1        MIPS_INTERRUPT_BASE+22
-#define TX4925_IRQ_TMR2        MIPS_INTERRUPT_BASE+23
-#define TX4925_IRQ_SPI         MIPS_INTERRUPT_BASE+24
-#define TX4925_IRQ_RTC         MIPS_INTERRUPT_BASE+25
-#define TX4925_IRQ_ACLC        MIPS_INTERRUPT_BASE+26
-#define TX4925_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
-#define TX4925_IRQ_CHI         MIPS_INTERRUPT_BASE+28
-#define TX4925_IRQ_PCIERR      MIPS_INTERRUPT_BASE+29
-#define TX4925_IRQ_PCIPME      MIPS_INTERRUPT_BASE+30
-#define TX4925_IRQ_RSV3        MIPS_INTERRUPT_BASE+31
-
-#define TX4925_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
-#define TX4925_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
-#define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
-
 #endif

c/src/lib/libcpu/mips/tx49/include/tx4938.h

@@ -1,7 +1,18 @@
-/*
+/**
- *  MIPS Tx4938 specific information
+ *  @file
  *  
- *  tx4938.h,v 1.0 2004/06/23 19:54:22
+ *  MIPS Tx4938 specific information
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
  */
 
 #ifndef __TX4938_h
@@ -110,47 +121,6 @@
 #define TX4938_REG_WRITE( _base, _register, _value ) \
   *((volatile uint32_t *)((_base) + (_register))) = (_value)
 
-/*
- *  Interrupt Vector Numbers
- *
- */
-#define TX4938_IRQ_ECC         MIPS_INTERRUPT_BASE+0
-#define TX4938_IRQ_WTE         MIPS_INTERRUPT_BASE+1
-#define TX4938_IRQ_INT0        MIPS_INTERRUPT_BASE+2
-#define TX4938_IRQ_INT1        MIPS_INTERRUPT_BASE+3
-#define TX4938_IRQ_INT2        MIPS_INTERRUPT_BASE+4
-#define TX4938_IRQ_INT3        MIPS_INTERRUPT_BASE+5
-#define TX4938_IRQ_INT4        MIPS_INTERRUPT_BASE+6
-#define TX4938_IRQ_INT5        MIPS_INTERRUPT_BASE+7
-#define TX4938_IRQ_SIO0        MIPS_INTERRUPT_BASE+8
-#define TX4938_IRQ_SIO1        MIPS_INTERRUPT_BASE+9
-#define TX4938_IRQ_DMAC00      MIPS_INTERRUPT_BASE+10
-#define TX4938_IRQ_DMAC01      MIPS_INTERRUPT_BASE+11
-#define TX4938_IRQ_DMAC02      MIPS_INTERRUPT_BASE+12
-#define TX4938_IRQ_DMAC03      MIPS_INTERRUPT_BASE+13
-#define TX4938_IRQ_IRC         MIPS_INTERRUPT_BASE+14
-#define TX4938_IRQ_PDMAC       MIPS_INTERRUPT_BASE+15
-#define TX4938_IRQ_PCIC        MIPS_INTERRUPT_BASE+16
-#define TX4938_IRQ_TMR0        MIPS_INTERRUPT_BASE+17
-#define TX4938_IRQ_TMR1        MIPS_INTERRUPT_BASE+18
-#define TX4938_IRQ_TMR2        MIPS_INTERRUPT_BASE+19
-#define TX4938_IRQ_RSV1        MIPS_INTERRUPT_BASE+20
-#define TX4938_IRQ_NDFMC       MIPS_INTERRUPT_BASE+21
-#define TX4938_IRQ_PCIERR      MIPS_INTERRUPT_BASE+22
-#define TX4938_IRQ_PCIPMC      MIPS_INTERRUPT_BASE+23
-#define TX4938_IRQ_ACLC        MIPS_INTERRUPT_BASE+24
-#define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+25
-#define TX4938_IRQ_PCIC1NT     MIPS_INTERRUPT_BASE+26
-#define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
-#define TX4938_IRQ_DMAC10      MIPS_INTERRUPT_BASE+28
-#define TX4938_IRQ_DMAC11      MIPS_INTERRUPT_BASE+29
-#define TX4938_IRQ_DMAC12      MIPS_INTERRUPT_BASE+30
-#define TX4938_IRQ_DMAC13      MIPS_INTERRUPT_BASE+31
-
-#define TX4938_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
-#define TX4938_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
-#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
-
 /************************************************************************
  *      TX49 Register field encodings
 *************************************************************************/

c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c

@@ -1,30 +0,0 @@
-/*
- *  This file contains the maximum number of vectors.  This can not
- *  be determined without knowing the RTEMS CPU model.
- *
- *  COPYRIGHT (c) 1989-2000.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  maxvectors.c,v 1.1.6.1 2003/09/04 18:45:49 joel Exp
- */
-
-/*
- *  Reserve first 32 for exceptions.
- */
-
-/*
- *  The Toshiba TX4925 attaches 5 of the eight interrupt bits to an
- *  on-CPU interrupt controller so that these five bits map to 32
- *  unique interrupts.  So you have: 2 software interrupts, an NMI,
- *  and 32 others.
- */
-
-#include <rtems.h>
-#include <libcpu/tx4925.h>
-
-unsigned int mips_interrupt_number_of_vectors = TX4925_MAXIMUM_VECTORS;
-

cpukit/score/cpu/mips/ChangeLog

@@ -1,3 +1,15 @@
+2012-03-07	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* rtems/score/cpu.h: In order to handle a issue in the 
+	compilation of printk all tasks should be defined as 
+	floating point for the MIPS processor.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* cpu.c, rtems/score/cpu.h:
+	Mips conversion to PIC IRQ model.
+
 2011-12-09	Jennifer Averett
 
 	* cpu.c: Correct typo.

cpukit/score/cpu/mips/cpu.c

@@ -1,4 +1,6 @@
-/*
+/**
+ *  @file
+ *  
  *  Mips CPU Dependent Source
  *
  *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
@@ -17,7 +19,9 @@
  *    wrote the JMR3904 BSP so this could be tested.  Joel also
  *    added the new interrupt vectoring support in libcpu and
  *    tried to better support the various interrupt controllers.
- *
+ */
+
+/*
  *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
  *           COPYRIGHT (c) 1996 by Transition Networks Inc.
  *
@@ -32,7 +36,7 @@
  *             Transition Networks makes no representations about the
  *             suitability of this software for any purpose.
  *
- *  COPYRIGHT (c) 1989-2001.
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -170,74 +174,6 @@ void _CPU_ISR_Set_level( uint32_t   new_level )
   mips_set_sr( sr );
 }
 
-
-
-/*
- *  _CPU_ISR_install_raw_handler
- *
- *  Input parameters:
- *    vector      - interrupt vector number
- *    old_handler - former ISR for this vector number
- *    new_handler - replacement ISR for this vector number
- *
- *  Output parameters:  NONE
- *
- */
-
-void _CPU_ISR_install_raw_handler(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-  /*
-   *  This is where we install the interrupt handler into the "raw" interrupt
-   *  table used by the CPU to dispatch interrupt handlers.
-   *
-   *  Because all interrupts are vectored through the same exception handler
-   *  this is not necessary on this port.
-   */
-}
-
-/*
- *  _CPU_ISR_install_vector
- *
- *  This kernel routine installs the RTEMS handler for the
- *  specified vector.
- *
- *  Input parameters:
- *    vector      - interrupt vector number
- *    old_handler - former ISR for this vector number
- *    new_handler - replacement ISR for this vector number
- *
- *  Output parameters:  NONE
- *
- */
-
-void _CPU_ISR_install_vector(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-   *old_handler = _ISR_Vector_table[ vector ];
-
-   /*
-    *  If the interrupt vector table is a table of pointer to isr entry
-    *  points, then we need to install the appropriate RTEMS interrupt
-    *  handler for this vector number.
-    */
-
-   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
-
-   /*
-    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
-    *  be used by the _ISR_Handler so the user gets control.
-    */
-
-    _ISR_Vector_table[ vector ] = new_handler;
-}
-
 /*
  *  _CPU_Install_interrupt_stack
  */

cpukit/score/cpu/mips/rtems/score/cpu.h

@@ -1,4 +1,6 @@
-/*
+/**
+ *  @file
+ *  
  *  Mips CPU Dependent Header File
  *
  *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
@@ -12,6 +14,9 @@
  *    added the new interrupt vectoring support in libcpu and
  *    tried to better support the various interrupt controllers.
  *
+ */
+
+/*
  *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
  *           COPYRIGHT (c) 1996 by Transition Networks Inc.
  *
@@ -26,7 +31,7 @@
  *      Transition Networks makes no representations about the suitability
  *      of this software for any purpose.
  *
- *  COPYRIGHT (c) 1989-2006.
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -124,7 +129,7 @@ extern "C" {
  *
  *  XXX document implementation including references if appropriate
  */
-#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
 
 /*
  *  Does this CPU have hardware support for a dedicated interrupt stack?
@@ -201,9 +206,13 @@ extern "C" {
  *  In this case, this option should be TRUE.
  *
  *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ *
+ *  Mips Note: It appears the GCC can implicitly generate FPU
+ *  and Altivec instructions when you least expect them.  So make
+ *  all tasks floating point.
  */
 
-#define CPU_ALL_TASKS_ARE_FP    FALSE
+#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP 
 
 /*
  *  Should the IDLE task have a floating point context?