forked from Imagelibrary/rtems
2002-07-30 Joel Sherrill <joel@OARcorp.com>
* intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
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@@ -23,19 +23,19 @@ special control mechanisms to return to the normal processing
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stream. Although RTEMS hides many of the processor dependent
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details of interrupt processing, it is important to understand
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how the RTEMS interrupt manager is mapped onto the processor's
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unique architecture. Discussed in this chapter are the XXX's
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unique architecture. Discussed in this chapter are the SH's
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interrupt response and control mechanisms as they pertain to
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RTEMS.
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@section Vectoring of an Interrupt Handler
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Depending on whether or not the particular CPU
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supports a separate interrupt stack, the XXX family has two
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supports a separate interrupt stack, the SH family has two
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different interrupt handling models.
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@subsection Models Without Separate Interrupt Stacks
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Upon receipt of an interrupt the XXX family
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Upon receipt of an interrupt the SH family
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members without separate interrupt stacks automatically perform
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the following actions:
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@@ -45,7 +45,7 @@ the following actions:
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@subsection Models With Separate Interrupt Stacks
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Upon receipt of an interrupt the XXX family
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Upon receipt of an interrupt the SH family
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members with separate interrupt stacks automatically perform the
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following actions:
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