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2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* shared/include/cache_.h: Moved content of "cache.h" to "cache_.h".
	* shared/include/cache.h: Removed file.
This commit is contained in:
Sebastian Huber
2011-06-07 07:58:16 +00:00
parent 479f876816
commit 07f8af124d
3 changed files with 120 additions and 139 deletions
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5
c/src/lib/libcpu/arm/ChangeLog
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@@ -1,3 +1,8 @@
2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
* shared/include/cache_.h: Moved content of "cache.h" to "cache_.h".
* shared/include/cache.h: Removed file.
2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* pxa255/pmc/pmc.c, shared/include/arm-cp15.h: * pxa255/pmc/pmc.c, shared/include/arm-cp15.h:

131
c/src/lib/libcpu/arm/shared/include/cache.h
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@@ -1,131 +0,0 @@
/**
* @file
*
* @ingroup arm
*
* @brief ARM cache defines and implementation.
*/
/*
* Copyright (c) 2009
* embedded brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBCPU_ARM_CACHE_H
#define LIBCPU_ARM_CACHE_H
#ifdef __ARM_ARCH_5TEJ__
#include <libcpu/arm-cp15.h>
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
{
arm_cp15_data_cache_clean_line(d_addr);
}
static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
arm_cp15_data_cache_invalidate_line(d_addr);
}
static inline void _CPU_cache_freeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
arm_cp15_instruction_cache_invalidate_line(d_addr);
}
static inline void _CPU_cache_freeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_flush_entire_data(void)
{
arm_cp15_data_cache_test_and_clean();
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
arm_cp15_data_cache_invalidate();
}
static inline void _CPU_cache_enable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
arm_cp15_data_cache_test_and_clean_and_invalidate();
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
arm_cp15_instruction_cache_invalidate();
}
static inline void _CPU_cache_enable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
#endif
#endif /* LIBCPU_ARM_CACHE_H */

123
c/src/lib/libcpu/arm/shared/include/cache_.h
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@@ -3,25 +3,132 @@
* *
* @ingroup arm * @ingroup arm
* *
* @brief Empty file. * @brief ARM cache defines and implementation.
*/ */
/* /*
* Copyright (c) 2009 * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
* embedded brains GmbH *
* Obere Lagerstr. 30 * embedded brains GmbH
* D-82178 Puchheim * Obere Lagerstr. 30
* Germany * 82178 Puchheim
* <rtems@embedded-brains.de> * Germany
* <rtems@embedded-brains.de>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
*
* $Id$
*/ */
#ifndef LIBCPU_ARM_CACHE__H #ifndef LIBCPU_ARM_CACHE__H
#define LIBCPU_ARM_CACHE__H #define LIBCPU_ARM_CACHE__H
/* Empty */ #ifdef __ARM_ARCH_5TEJ__
#include <libcpu/arm-cp15.h>
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
{
arm_cp15_data_cache_clean_line(d_addr);
}
static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
arm_cp15_data_cache_invalidate_line(d_addr);
}
static inline void _CPU_cache_freeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
arm_cp15_instruction_cache_invalidate_line(d_addr);
}
static inline void _CPU_cache_freeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_flush_entire_data(void)
{
arm_cp15_data_cache_test_and_clean();
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
arm_cp15_data_cache_invalidate();
}
static inline void _CPU_cache_enable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
arm_cp15_data_cache_test_and_clean_and_invalidate();
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
arm_cp15_instruction_cache_invalidate();
}
static inline void _CPU_cache_enable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
#endif
#endif /* LIBCPU_ARM_CACHE__H */ #endif /* LIBCPU_ARM_CACHE__H */