forked from Imagelibrary/rtems
bsps/arm: basic on core cache support changed to use l1 functions.
The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
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@@ -210,6 +210,18 @@ extern "C" {
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/** @} */
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/**
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* @name CCSIDR, Cache Size ID Register Defines
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*
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* @{
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*/
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#define ARM_CP15_CACHE_CSS_ID_DATA 0
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#define ARM_CP15_CACHE_CSS_ID_INSTRUCTION 1
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#define ARM_CP15_CACHE_CSS_LEVEL(level) ((level) << 1)
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/** @} */
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ARM_CP15_TEXT_SECTION static inline uint32_t
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arm_cp15_get_id_code(void)
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{
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@@ -819,6 +831,21 @@ arm_cp15_set_cache_size_selection(uint32_t val)
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);
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}
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ARM_CP15_TEXT_SECTION static inline uint32_t
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arm_cp15_get_cache_size_id_for_level(uint32_t level_and_inst_dat)
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{
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rtems_interrupt_level irq_level;
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uint32_t ccsidr;
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rtems_interrupt_local_disable(irq_level);
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arm_cp15_set_cache_size_selection(level_and_inst_dat);
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_ARM_Instruction_synchronization_barrier();
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ccsidr = arm_cp15_get_cache_size_id();
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rtems_interrupt_local_enable(irq_level);
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return ccsidr;
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}
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ARM_CP15_TEXT_SECTION static inline void
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arm_cp15_cache_invalidate(void)
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{
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@@ -1036,10 +1063,8 @@ arm_cp15_data_cache_invalidate_all_levels(void)
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uint32_t way;
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uint32_t way_shift;
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arm_cp15_set_cache_size_selection(level << 1);
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_ARM_Instruction_synchronization_barrier();
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ccsidr = arm_cp15_get_cache_size_id_for_level(level << 1);
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ccsidr = arm_cp15_get_cache_size_id();
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line_power = arm_ccsidr_get_line_power(ccsidr);
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associativity = arm_ccsidr_get_associativity(ccsidr);
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way_shift = __builtin_clz(associativity - 1);
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