forked from Imagelibrary/rtems
2003-09-26 Cedric Aubert <cedric_aubert@yahoo.fr>
PR 499/rtems_misc * serial/mc68681.c: Miscellaneous corrections: - Correction of ACR_BIT[7] (Baudrate table) Configuration - Correction of Parity Bit Configuration (Odd was forced) - Correction of Stop Bit configuration (inversed) - Correction of ISR Handler to call rtems_termios_dequeue_character() only if is a Tx Empty IRQ. - Add RTS CTS Hardware flow control Configuration
This commit is contained in:
@@ -1,3 +1,14 @@
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2003-09-26 Cedric Aubert <cedric_aubert@yahoo.fr>
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PR 499/rtems_misc
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* serial/mc68681.c: Miscellaneous corrections:
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- Correction of ACR_BIT[7] (Baudrate table) Configuration
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- Correction of Parity Bit Configuration (Odd was forced)
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- Correction of Stop Bit configuration (inversed)
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- Correction of ISR Handler to call
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rtems_termios_dequeue_character() only if is a Tx Empty IRQ.
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- Add RTS CTS Hardware flow control Configuration
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2003-09-04 Joel Sherrill <joel@OARcorp.com>
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2003-09-04 Joel Sherrill <joel@OARcorp.com>
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* ide/ata.c, ide/ata.h, ide/ata_internal.h, ide/ide_controller.c,
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* ide/ata.c, ide/ata.h, ide/ata_internal.h, ide/ide_controller.c,
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@@ -123,8 +123,8 @@ MC68681_STATIC int mc68681_set_attributes(
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if (t->c_cflag & PARENB) {
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if (t->c_cflag & PARENB) {
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if (t->c_cflag & PARODD)
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if (t->c_cflag & PARODD)
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mode1 |= 0x04;
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mode1 |= 0x04;
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else
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/* else
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mode1 |= 0x04;
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mode1 |= 0x04; */
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} else {
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} else {
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mode1 |= 0x10;
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mode1 |= 0x10;
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}
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}
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@@ -149,13 +149,23 @@ MC68681_STATIC int mc68681_set_attributes(
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*/
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*/
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if (t->c_cflag & CSTOPB) {
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if (t->c_cflag & CSTOPB) {
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mode2 |= 0x07; /* 2 stop bits */
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mode2 |= 0x0F; /* 2 stop bits */
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} else {
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} else {
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if ((t->c_cflag & CSIZE) == CS5) /* CS5 and 2 stop bits not supported */
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if ((t->c_cflag & CSIZE) == CS5) /* CS5 and 1 stop bits not supported */
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return -1;
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return -1;
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mode2 |= 0x0F; /* 1 stop bit */
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mode2 |= 0x07; /* 1 stop bit */
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}
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}
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/*
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* Hardware Flow Control
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*/
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if(t->c_cflag & CRTSCTS) {
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mode1 |= 0x80; /* Enable Rx RTS Control */
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mode2 |= 0x10; /* Enable CTS Enable Tx */
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}
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rtems_interrupt_disable(Irql);
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rtems_interrupt_disable(Irql);
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(*setReg)( pMC68681, MC68681_AUX_CTRL_REG, acr_bit );
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(*setReg)( pMC68681, MC68681_AUX_CTRL_REG, acr_bit );
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(*setReg)( pMC68681_port, MC68681_CLOCK_SELECT, baud_mask );
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(*setReg)( pMC68681_port, MC68681_CLOCK_SELECT, baud_mask );
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@@ -266,27 +276,30 @@ MC68681_STATIC int mc68681_open(
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unsigned32 pMC68681;
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unsigned32 pMC68681;
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unsigned32 pMC68681_port;
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unsigned32 pMC68681_port;
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unsigned int baud;
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unsigned int baud;
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unsigned int acr;
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unsigned int acr_bit;
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unsigned int vector;
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unsigned int vector;
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unsigned int command;
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unsigned int command;
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rtems_interrupt_level Irql;
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rtems_interrupt_level Irql;
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setRegister_f setReg;
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setRegister_f setReg;
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unsigned int status;
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pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
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pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
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pMC68681_port = Console_Port_Tbl[minor].ulCtrlPort2;
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pMC68681_port = Console_Port_Tbl[minor].ulCtrlPort2;
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setReg = Console_Port_Tbl[minor].setRegister;
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setReg = Console_Port_Tbl[minor].setRegister;
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vector = Console_Port_Tbl[minor].ulIntVector;
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vector = Console_Port_Tbl[minor].ulIntVector;
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/* XXX default baud rate should be from configuration table */
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/* XXX default baud rate should be from configuration table */
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(void) mc68681_baud_rate( minor, B9600, &baud, &acr, &command );
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status = mc68681_baud_rate( minor, B9600, &baud, &acr_bit, &command );
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if (status < 0) rtems_fatal_error_occurred (RTEMS_NOT_DEFINED);
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/*
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/*
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* Set the DUART channel to a default useable state
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* Set the DUART channel to a default useable state
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*/
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*/
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rtems_interrupt_disable(Irql);
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rtems_interrupt_disable(Irql);
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(*setReg)( pMC68681, MC68681_AUX_CTRL_REG, acr );
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(*setReg)( pMC68681, MC68681_AUX_CTRL_REG, acr_bit << 7 );
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(*setReg)( pMC68681_port, MC68681_CLOCK_SELECT, baud );
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(*setReg)( pMC68681_port, MC68681_CLOCK_SELECT, baud );
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if ( command ) {
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if ( command ) {
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(*setReg)( pMC68681_port, MC68681_COMMAND, command ); /* RX */
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(*setReg)( pMC68681_port, MC68681_COMMAND, command ); /* RX */
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@@ -553,8 +566,10 @@ MC68681_STATIC int mc68681_baud_rate(
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acr_bit = 0;
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acr_bit = 0;
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status = 0;
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status = 0;
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if ( !(Console_Port_Tbl[minor].ulDataPort & MC68681_DATA_BAUD_RATE_SET_1) )
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if (Console_Port_Tbl[minor].ulDataPort & MC68681_DATA_BAUD_RATE_SET_2)
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{
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acr_bit = 1;
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acr_bit = 1;
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}
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is_extended = 0;
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is_extended = 0;
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@@ -611,6 +626,7 @@ MC68681_STATIC void mc68681_process(
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unsigned32 pMC68681;
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unsigned32 pMC68681;
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unsigned32 pMC68681_port;
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unsigned32 pMC68681_port;
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volatile unsigned8 ucLineStatus;
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volatile unsigned8 ucLineStatus;
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volatile unsigned8 ucISRStatus;
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unsigned char cChar;
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unsigned char cChar;
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getRegister_f getReg;
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getRegister_f getReg;
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setRegister_f setReg;
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setRegister_f setReg;
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@@ -620,6 +636,19 @@ MC68681_STATIC void mc68681_process(
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getReg = Console_Port_Tbl[minor].getRegister;
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getReg = Console_Port_Tbl[minor].getRegister;
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setReg = Console_Port_Tbl[minor].setRegister;
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setReg = Console_Port_Tbl[minor].setRegister;
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/* Get ISR at the beginning of the IT routine */
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ucISRStatus = (*getReg)(pMC68681, MC68681_INTERRUPT_STATUS_REG);
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/* Get good ISR a or b channel */
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if (pMC68681 != pMC68681_port){
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ucISRStatus >>= 4;
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}
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/* See if is usefull to call rtems_termios_dequeue */
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if(Console_Port_Data[minor].bActive == FALSE) {
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ucISRStatus = ucISRStatus & ~MC68681_IR_TX_READY;
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}
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/*
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/*
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* Deal with any received characters
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* Deal with any received characters
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*/
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*/
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@@ -650,18 +679,14 @@ MC68681_STATIC void mc68681_process(
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* Deal with the transmitter
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* Deal with the transmitter
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*/
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*/
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ucLineStatus = (*getReg)(pMC68681, MC68681_INTERRUPT_STATUS_REG);
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if (ucISRStatus & MC68681_IR_TX_READY) {
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if (pMC68681 != pMC68681_port)
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if (!rtems_termios_dequeue_characters(
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ucLineStatus >>= 4;
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Console_Port_Data[minor].termios_data, 1)) {
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/* If no more char to send, disable TX interrupt */
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if(ucLineStatus & MC68681_IR_TX_READY) {
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if (rtems_termios_dequeue_characters(
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Console_Port_Data[minor].termios_data, 1)) {
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Console_Port_Data[minor].bActive = FALSE;
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Console_Port_Data[minor].bActive = FALSE;
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mc68681_enable_interrupts(minor, MC68681_IMR_ENABLE_ALL_EXCEPT_TX);
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mc68681_enable_interrupts(minor, MC68681_IMR_ENABLE_ALL_EXCEPT_TX);
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}
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}
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}
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}
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}
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}
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/*
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/*
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