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Xilinx AXI I2C driver IP race condition causes clock glitch.

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Setting the PIRQ to 0 before reading the data produces a short clock pulse.
Moving the write to after reading the data fixes the issue.

Close #3173
This commit is contained in:
Chris Johns
2018-01-23 13:23:55 +11:00
parent 4cf93658ef
commit 05015dc188
1 changed files with 5 additions and 1 deletions
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6
cpukit/dev/i2c/xilinx-axi-i2c.c
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@@ -512,8 +512,12 @@ xilinx_axi_i2c_read_rx_fifo(xilinx_axi_i2c_bus* bus)
*/ */
xilinx_axi_i2c_disable_clear_irq(bus, INT_TX_ERROR); xilinx_axi_i2c_disable_clear_irq(bus, INT_TX_ERROR);
xilinx_axi_i2c_set_cr(bus, CR_TXAK); xilinx_axi_i2c_set_cr(bus, CR_TXAK);
xilinx_axi_i2c_write_rx_pirq(bus, 0);
xilinx_axi_i2c_read_rx_bytes(bus, level); xilinx_axi_i2c_read_rx_bytes(bus, level);
/*
* Set the RX PIRQ to 0 after the RX data has been read. There is an
* observed timing issue and glitch if written before.
*/
xilinx_axi_i2c_write_rx_pirq(bus, 0);
break; break;
case 0: case 0: