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Update from Erik Ivanenko <erik.ivanenko@utoronto.ca> to bring the

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i386ex bsp up to date.

1) A 'hlt' instruction is coded in case of a return from boot_card in
  start.s.
This commit is contained in:
Joel Sherrill
1998-09-21 00:23:02 +00:00
parent 30ba7529f1
commit 04bc5d97f1
5 changed files with 138 additions and 298 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
c/src/lib/libbsp/i386/i386ex/clock/ckinit.c
View File

@@ -19,6 +19,11 @@
*
* $Id$
*/
#define TMR0 0xF040
#define TMR1 0xF041
#define TMR2 0xF042
#define TMRCON 0xF043
#define TMRCFG 0xF834
#include <bsp.h>
#include <irq.h>
@@ -58,21 +63,12 @@ void Clock_isr()
void ClockOff(const rtems_irq_connect_data* unused)
{
/* should do something here */;
/* should do something here */;
outport_byte ( TMRCFG , 0x80 );
}
void ClockOn(const rtems_irq_connect_data* unused)
{
/* The following is already set up in interns.s ->
( This is test code only... production code will move the
TMRCFG stuff here )
*/
#define TMR0 0xF040
#define TMR1 0xF041
#define TMR2 0xF042
#define TMRCON 0xF043
#define TMRCFG 0xF834
outport_byte ( TMRCFG , 0x80 );
outport_byte ( TMRCON , 0x34 );
@@ -141,6 +137,10 @@ rtems_device_driver Clock_control(
printk("Error installing clock interrupt handler!\n");
rtems_fatal_error_occurred(1);
}
#ifdef DEBUG
else
printk("Clock installed AGAIN\n");
#endif
}
done:
@@ -149,5 +149,6 @@ done:
void Clock_exit()
{
ClockOff(&clockIrqData);
pc386_remove_rtems_irq_handler (&clockIrqData);
}

6
c/src/lib/libbsp/i386/i386ex/include/bsp.h
View File

@@ -45,8 +45,12 @@ extern "C" {
#define MUST_WAIT_FOR_INTERRUTPT 0
#define Install_tm27_vector( handler ) set_vector( (handler), 0x90, 1 )
#define Install_tm27_vector(handler) \
{ \
rtems_isr_entry dummy; \
rtems_interrupt_catch(handler, 0x90, &dummy); \
}
#define Cause_tm27_intr() asm volatile( "int $0x90" : : );
#define Clear_tm27_intr()

271
c/src/lib/libbsp/i386/i386ex/start/start.s
View File

@@ -27,6 +27,12 @@
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
changes:
SetExRegByte(ICW3S , 0x02 ) # MUST be 0x02 according to intel
SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded
*/
#include "asm.h"
@@ -38,75 +44,32 @@
* #define NEXT_GAS
*/
EXTERN (main) /* exits to bspstart */
EXTERN (stack_start) /* defined in startup/linkcmds */
#define NEXT_GAS
.section .idt
EXTERN (boot_card) /* exits to bspstart */
EXTERN (stack_start) /* defined in startup/linkcmds */
EXTERN (Clock_exit)
BEGIN_DATA
PUBLIC (Interrupt_descriptor_table)
PUBLIC(SYM(IDTR) )
SYM(IDTR): DESC3( SYM(IDT), 0x188 );
SYM (Interrupt_descriptor_table):
SYM(IDT):
SYM(GATE_DIVIDE_ERROR): INTERRUPT_GATE( DIVIDE_ERROR );
SYM(GATE_DEBUG_EXCEPTION): INTERRUPT_GATE( DEBUG_EXCEPTION );
SYM(GATE_NMI_INTERRUPT): INTERRUPT_GATE( NMI_INTERRUPT );
SYM(GATE_BREAKPOINT): INTERRUPT_GATE( BREAKPOINT );
SYM(GATE_INTO_OVERFLOW ): INTERRUPT_GATE( INTO_OVERFLOW );
SYM(GATE_BOUND_EXCEEDED ): INTERRUPT_GATE( BOUND_EXCEEDED );
SYM(GATE_INVALID_OPCODE ): INTERRUPT_GATE( INVALID_OPCODE );
SYM(GATE_COPRO_NA ): INTERRUPT_GATE( COPRO_NA );
SYM(GATE_DOUBLE_FAULT ): INTERRUPT_GATE( DOUBLE_FAULT );
SYM(GATE_COPRO_SEG_OVERRUN ): INTERRUPT_GATE( COPRO_SEG_OVERRUN );
SYM(GATE_INVALID_TSS ): INTERRUPT_GATE( INVALID_TSS );
SYM(GATE_SEGMENT_NOT_PRESENT ): INTERRUPT_GATE( SEGMENT_NOT_PRESENT );
SYM(GATE_STACK_FAULT ): INTERRUPT_GATE( STACK_FAULT );
SYM(GATE_GPF ): INTERRUPT_GATE( GPF );
SYM(GATE_PAGE_FAULT ): INTERRUPT_GATE( PAGE_FAULT );
SYM(GATE_RESERVED_1 ): INTERRUPT_GATE( RESERVED );
SYM(GATE_COPRO_ERROR ): INTERRUPT_GATE( COPRO_ERROR );
SYM(GATE_RESERVED_17): INTERRUPT_GATE( RESERVED_17 );
SYM(GATE_RESERVED_18): INTERRUPT_GATE( RESERVED_18 );
SYM(GATE_RESERVED_19): INTERRUPT_GATE( RESERVED_19 );
SYM(GATE_RESERVED_20): INTERRUPT_GATE( RESERVED_20 );
SYM(GATE_RESERVED_21): INTERRUPT_GATE( RESERVED_21 );
SYM(GATE_RESERVED_22): INTERRUPT_GATE( RESERVED_22 );
SYM(GATE_RESERVED_23): INTERRUPT_GATE( RESERVED_23 );
SYM(GATE_RESERVED_24): INTERRUPT_GATE( RESERVED_24 );
SYM(GATE_RESERVED_25): INTERRUPT_GATE( RESERVED_25 );
SYM(GATE_RESERVED_26): INTERRUPT_GATE( RESERVED_26 );
SYM(GATE_RESERVED_27): INTERRUPT_GATE( RESERVED_27 );
SYM(GATE_RESERVED_28): INTERRUPT_GATE( RESERVED_28 );
SYM(GATE_RESERVED_29): INTERRUPT_GATE( RESERVED_29 );
SYM(GATE_RESERVED_30): INTERRUPT_GATE( RESERVED_30 );
SYM(GATE_RESERVED_31): INTERRUPT_GATE( RESERVED_31 );
SYM ( GATE_TIMINT0): INTERRUPT_GATE( TIMINT0 );
SYM ( GATE_MASTER_IR2 ): INTERRUPT_GATE( MASTER_IR2 );
SYM ( GATE_SIOINT1 ): INTERRUPT_GATE( SIOINT1 );
SYM ( GATE_SIOINT2 ): INTERRUPT_GATE( SIOINT2 );
SYM ( GATE_DMAINT ): INTERRUPT_GATE( DMAINT );
SYM ( GATE_UNUSED_IR5 ): INTERRUPT_GATE( UNUSED_IR5);
SYM ( GATE_UNUSED_IR6 ): INTERRUPT_GATE( UNUSED_IR6);
SYM ( GATE_UNUSED_IR7 ): INTERRUPT_GATE( UNUSED_IR7);
SYM ( GATE_SLAVE_IR0 ): INTERRUPT_GATE( SLAVE_IR0 );
SYM ( GATE_SLAVE_IR1 ): INTERRUPT_GATE( SLAVE_IR1 );
SYM ( GATE_SLAVE_IR2 ): INTERRUPT_GATE( SLAVE_IR2 );
SYM ( GATE_SLAVE_IR3 ): INTERRUPT_GATE( SLAVE_IR3 );
SYM ( GATE_SLAVE_IR4 ): INTERRUPT_GATE( SLAVE_IR4 );
SYM ( GATE_SLAVE_IR5 ): INTERRUPT_GATE( SLAVE_IR5 );
SYM ( GATE_SLAVE_IR6 ): INTERRUPT_GATE( SLAVE_IR6 );
SYM ( GATE_SLAVE_IR7 ): INTERRUPT_GATE( SLAVE_IR7 );
PUBLIC ( SYM(IDTR) )
PUBLIC( SYM(_initInternalRegisters) )
BEGIN_DATA
SYM(IDTR): DESC3( SYM(Interrupt_descriptor_table), 0x07ff );
SYM(Interrupt_descriptor_table): /* Now in data section */
.rept 256
.word 0,0,0,0
.endr
END_DATA
.section .gdt
BEGIN_DATA
PUBLIC (_Global_descriptor_table)
/* .section .gdt */
PUBLIC (_Global_descriptor_table)
SYM(GDTR): DESC3( GDT_TABLE, 0x1f ); # one less than the size
SYM (_Global_descriptor_table):
SYM(GDT):
SYM(GDT_TABLE): DESC2(0,0,0,0,0,0);
SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0);
SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00);
@@ -121,71 +84,13 @@ END_DATA
correct vector offsets. It is for symbol definition only.
*/
.section .ints
SYM(INTERRUPT_HANDLERS):
SYM(DIVIDE_ERROR): jmp SYM(DIVIDE_ERROR)
SYM(DEBUG_EXCEPTION): jmp SYM(DEBUG_EXCEPTION)
SYM(NMI_INTERRUPT): jmp SYM(NMI_INTERRUPT)
SYM(BREAKPOINT): jmp SYM(BREAKPOINT)
SYM(INTO_OVERFLOW): jmp SYM(INTO_OVERFLOW)
SYM(BOUND_EXCEEDED): jmp SYM(BOUND_EXCEEDED)
SYM(INVALID_OPCODE): jmp SYM(INVALID_OPCODE)
SYM(COPRO_NA): jmp SYM(COPRO_NA)
SYM(DOUBLE_FAULT): jmp SYM(DOUBLE_FAULT)
SYM(COPRO_SEG_OVERRUN): jmp SYM(COPRO_SEG_OVERRUN)
SYM(INVALID_TSS): jmp SYM(INVALID_TSS)
SYM(RESERVED): JMP SYM(RESERVED)
SYM(COPRO_ERROR): JMP SYM(COPRO_ERROR)
SYM(PAGE_FAULT): JMP SYM(PAGE_FAULT)
SYM(GPF): JMP SYM(GPF)
SYM(STACK_FAULT): JMP SYM(STACK_FAULT)
SYM(SEGMENT_NOT_PRESENT): jmp SYM(SEGMENT_NOT_PRESENT)
SYM(RESERVED_17): jmp SYM(RESERVED_17)
SYM(RESERVED_18): jmp SYM(RESERVED_18)
SYM(RESERVED_19): jmp SYM(RESERVED_19)
SYM(RESERVED_20): jmp SYM(RESERVED_20)
SYM(RESERVED_21): jmp SYM(RESERVED_21)
SYM(RESERVED_22): jmp SYM(RESERVED_22)
SYM(RESERVED_23): jmp SYM(RESERVED_23)
SYM(RESERVED_24): jmp SYM(RESERVED_24)
SYM(RESERVED_25): jmp SYM(RESERVED_25)
SYM(RESERVED_26): jmp SYM(RESERVED_26)
SYM(RESERVED_27): jmp SYM(RESERVED_27)
SYM(RESERVED_28): jmp SYM(RESERVED_28)
SYM(RESERVED_29): jmp SYM(RESERVED_29)
SYM(RESERVED_30): jmp SYM(RESERVED_30)
SYM(RESERVED_31): jmp SYM(RESERVED_31)
SYM(TIMINT0): nop; iret
SYM(MASTER_IR2): jmp SYM(MASTER_IR2)
SYM(SIOINT1): jmp SYM(SIOINT1)
SYM(SIOINT2): jmp SYM(SIOINT2)
SYM(DMAINT): jmp SYM(DMAINT)
SYM(UNUSED_IR5): jmp SYM(UNUSED_IR5)
SYM(UNUSED_IR6): JMP SYM(UNUSED_IR6)
SYM(UNUSED_IR7): JMP SYM(UNUSED_IR7)
SYM(SLAVE_IR0): JMP SYM(SLAVE_IR0)
SYM(SLAVE_IR1): JMP SYM(SLAVE_IR1)
SYM(SLAVE_IR2): nop; iret
SYM(SLAVE_IR3): JMP SYM(SLAVE_IR3)
SYM(SLAVE_IR4): JMP SYM(SLAVE_IR4)
SYM(SLAVE_IR5): JMP SYM(SLAVE_IR5)
SYM(SLAVE_IR6): JMP SYM(SLAVE_IR6)
SYM(SLAVE_IR7): JMP SYM(SLAVE_IR7)
PUBLIC( SYM(_initInternalRegisters) )
.section .reset
PUBLIC ( SYM(reset) )
SYM(reset):
.code16
SYM(reset):
nop
cli
#ifdef NEXT_GAS
addr32
#endif
jmp SYM(_initInternalRegisters) /* different section in this file */
.code32 /* in case this section moves */
nop /* required by CHIP LAB to pad out size */
@@ -193,9 +98,11 @@ SYM(reset):
nop
nop
nop
.section .initial
.section .initial
/*
* Enable access to peripheral register at expanded I/O addresses
*/
@@ -219,8 +126,11 @@ SYM(A20):
orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled.
outb al , dx
SYM(Watchdog):
SetExRegByte( WDTSTATUS, 0x01 ) # disable watchdog timer
SYM(Watchdog):
movw $WDTSTATUS , dx # address the WDT status port
inb dx , al # get the WDT status
orb $0x01 , al # set the CLKDIS bit
outb al , dx # disable the clock to the WDT
/*
* Initialize Refresh Control Unit for:
@@ -408,17 +318,19 @@ SYM(InitInt):
SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED
SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master
SetExRegByte(ICW3S , 0x04 ) # ( was 0x02! )slave cascaded to IR2 on master
SetExRegByte(ICW3S , 0x02 ) # slave cascaded to IR2 on master
SetExRegByte(ICW4S , 0x01 ) # must be 0x01
SetExRegByte(ICW1M , 0x11 ) # edge triggered
SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32
SetExRegByte(ICW3M , 0x02 ) # IR2 is cascaded internally
SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32
SetExRegByte(ICW3M , 0x04) # IR2 is cascaded internally
SetExRegByte(ICW4M , 0x01 ) # idem
SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. for IR5 and IR0 active use 0xde
SetExRegByte(INTCFG , 0x00 )
movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */
SYM(SetCS4):
SetExRegWord(CS4ADL , 0x702) #Configure chip select 4
SetExRegWord(CS4ADH , 0x00)
@@ -430,45 +342,13 @@ SYM(SetUCS1):
SetExRegWord(UCSADH , 0x03F8)
SetExRegWord(UCSMSKH, 0x03F7)
SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select
SYM(xfer_idt):
movw $ _ram_idt_offset , di
movw $ _ram_idt_segment , cx
mov cx, es
/******************************************************
* The GDT must be in RAM since it must be writeable,
* So, move the whole data section down.
********************************************************/
movw $ _rom_idt_offset , si
movw $ _rom_idt_segment , ax
mov ax , ds
movw $ _idt_size , cx
repne
movsb
SYM(xfer_ints):
movw $ _ram_ints_offset , di
movw $ _ram_ints_segment , ax
mov ax , es
movw $ _rom_ints_offset , si
movw $ _rom_ints_segment, ax
mov ax , ds
movw $ _ints_size , cx
repne
movsb
SYM(lidt):
movw $ _ram_idt_offset , di
movw $ 0x0 , si
movw $ _ram_idt_segment , ax
mov ax , ds
lidt _ram_idt_offset
SYM(xfer_gdt):
/* SYM(xfer_gdt):
movw $ _ram_gdt_offset , di
movw $ _ram_gdt_segment , cx
mov cx , es
@@ -478,6 +358,19 @@ SYM(xfer_gdt):
movw $ _rom_gdt_offset , si
mov ax , ds
repne
movsb
*/
movw $ _ram_data_offset , di
movw $ _ram_data_segment, cx
mov cx , es
movw $ _data_size , cx
movw $ _rom_data_segment, ax
movw $ _rom_data_offset , si
mov ax , ds
repne
movsb
@@ -486,17 +379,19 @@ SYM(xfer_gdt):
* Table Register
****************************/
movw $ _ram_gdt_segment, ax
mov ax , ds
/* movw $ _ram_gdt_segment, ax */
#ifdef NEXT_GAS
data32
addr32
#endif
lgdt _ram_gdt_offset # location of GDT
/* lgdt _ram_gdt_offset # location of GDT */
lgdt SYM(GDTR) # location of GDT
SYM(SetUCS):
SetExRegWord(UCSADL, 0x0704) # now 512K starting at 0x3f80000.
SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000.
SetExRegWord(UCSADH, 0x03f8)
SetExRegWord(UCSMSKH, 0x0007)
SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select
@@ -513,11 +408,14 @@ SYM(SetUCS):
* and load CS selector
*********************/
ljmpl $ GDT_CODE_PTR , $ SYM(_copy_data) # sets the code selector
/* ljmpl $ GDT_CODE_PTR , $ SYM(_copy_data) # sets the code selector*/
ljmpl $ GDT_CODE_PTR , $ SYM(_load_segment_registers) # sets the code selector
/*
* Copy the data section down to RAM
*/
SYM(_copy_data):
/*SYM(_copy_data): */
SYM(_load_segment_registers):
.code32
pLOAD_SEGMENT( GDT_DATA_PTR, fs)
pLOAD_SEGMENT( GDT_DATA_PTR, gs)
@@ -525,21 +423,21 @@ SYM(_copy_data):
pLOAD_SEGMENT( GDT_DATA_PTR, ds)
pLOAD_SEGMENT( GDT_DATA_PTR, es)
movl $ SYM(_data_start) , edi # ram destination
/* movl $ SYM(_data_start) , edi # ram destination
movl $ SYM(_rom_data_start) , esi # rom data source
movl $ SYM(_edata) , ecx # end of data section
subl $ SYM(_data_start) , ecx # length of data section
# es, ds preloaded
movl $ SYM(_data_size) , ecx # amount to move
repne # while ecx != 0
movsb # move a byte
*/
/*
* Set up the stack
*/
SYM(lidtr):
lidt SYM(IDTR)
SYM (_establish_stack):
movl $end, eax # stack starts right after bss
/* movl eax, stack_start # save for brk() routine */
movl $stack_origin, esp # this is the high starting address
movl $stack_origin, ebp
/*
@@ -562,21 +460,10 @@ SYM (zero_bss):
pushl $0 # environp
pushl $0 # argv
pushl $0 # argc
call SYM (main) # does not return
call SYM(boot_card)
addl $12,esp
BEGIN_DATA_DCL
/* .align 2
PUBLIC (start_frame)
SYM (start_frame):
.long 0
*/
/* PUBLIC (stack_start)
SYM (stack_start):
.long 0
*/
END_DATA_DCL
hlt
END

19
c/src/lib/libbsp/i386/i386ex/startup/bspstart.c
View File

@@ -21,6 +21,8 @@
* $Id$
*/
void bsp_clean_up(void);
#include <bsp.h>
#include <rtems/libio.h>
@@ -79,6 +81,7 @@ void bsp_pretasking_hook(void)
heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */
bsp_libc_init((void *) heap_start, heap_size, 0);
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
@@ -92,22 +95,27 @@ void bsp_pretasking_hook(void)
void bsp_start( void )
{
/*
* we do not use the pretasking_hook.
/*
* we do not use the pretasking_hook.
*/
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.postdriver_hook = bsp_postdriver_hook;
Cpu_table.interrupt_table_segment = get_ds();
Cpu_table.interrupt_table_offset = (void *)Interrupt_descriptor_table;
Cpu_table.interrupt_stack_size = 4096; /* STACK_MINIMUM_SIZE */
Cpu_table.interrupt_stack_size = 8192; /* changed Sept 14 STACK_MINIMUM_SIZE */
#if defined(RTEMS_POSIX_API)
BSP_Configuration.work_space_size *= 3;
#endif
BSP_Configuration.work_space_start = (void *)
/* BSP_Configuration.work_space_size += 128 * RTEMS_MINIMUM_STACK_SIZE; */
BSP_Configuration.work_space_start = (void *)
RAM_END - BSP_Configuration.work_space_size;
#ifdef DEBUG
printk("workspace size = 0x%x\nstart = 0x%x, RAM_END = 0x%x\n",BSP_Configuration.work_space_size, BSP_Configuration.work_space_start, RAM_END );
#endif
/*
* Account for the console's resources
@@ -119,3 +127,6 @@ void bsp_start( void )
*/
rtems_irq_mngt_init();
}
void bsp_clean_up(void) {
printk("bsp_cleanup called\n");
}

117
c/src/lib/libbsp/i386/i386ex/startup/linkcmds
View File

@@ -11,108 +11,43 @@
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*
* Memory layout:
*
* 0x3f80000 -> 0x3ff0000 : text section
* 0x3ff0000 -> 0x3ff0028 : global descriptor table in ROM
* 0x3ff0028 -> 0x3fff000 : data section ( copied by start.s to RAM )
* 0x3fff000 -> 0x3fffff0 : initial section ( init 386ex, goto protected mode, copy ROM-RAM )
* 0x3fffff0 -> 0x4000000 : reset section ( jmp to initial only )
*/
ENTRY(reset) ;
SECTIONS
{
/*******************************************************************************
* Interrupts section:
*
* This section defines the layout of the interrupts in ROM ( VMA ) as well as their
* location in RAM (LMA). The _rom_ and _ram_ variables are used in start.s
* in order for the code to move the interrupt vector tables from ROM to RAM
* while still running in real-mode. The tables are moved from ROM, as the IDT
* is initialized with only 16-bit offsets for the interrupt handlers.
* This is purely an implementation issue. If you prefer the interrupt handlers
* to be resident in flash, then you must provide the code to create the interrupt
* gates with full 32bit offsets. The code in the current start.s does NOT support
* interrupts in ROM by merely redefining their location.
******************************************************************************/
_rom_ints = 0x3ff0000; /* was 0x3fb0000 */
_rom_ints_segment = 0xF000 ;
_rom_ints_offset = 0x0000 ;
_ram_ints_segment = 0x0000 ;
_ram_ints_offset = 0x0100 ;
.ints _ram_ints_offset :
AT ( _rom_ints )
{
_sints = .;
*(.ints);
_eints = ALIGN (0x010);
}
_ints_size = _eints - _sints ;
/**************************************************************************************
* GDT section:
*
* This section defines the locations of the GDT in ROM as well as in RAM. The _rom_ and
* _ram_ variables are used by start.s to copy the GDT from ROM to RAM when still in
* real-mode. The move from ROM to RAM is made as a writeable GDT is required for the
* jump to protected mode to be successful.
**************************************************************************************/
_rom_gdt = _rom_ints + _ints_size;
_rom_gdt_segment = 0xF000;
_rom_gdt_offset = _rom_ints_offset + _ints_size;
_ram_gdt_segment = 0x0000 ;
_ram_gdt_offset = _ram_ints_offset + _ints_size;
.gdt _ram_gdt_offset :
AT ( _rom_gdt )
{
_sgdt = .;
*(.gdt);
_egdt = ALIGN (0x10);
}
_gdt_size = _egdt - _sgdt;
/*****************************************************************************************
* IDT section:
*
* This section defines the locations of the IDT in ROM as well as in RAM. The _rom_ and
* _ram_ variables are used by start.s to copy the IDT from ROM to RAM when still in real-mode.
* The move from ROM to RAM is required to enable RTEMS to hook the interrupts, however,
* this move could be made when in protected mode.
****************************************************************************************/
_rom_idt = _rom_gdt + _gdt_size ;
_rom_idt_segment = 0xF000 ;
_rom_idt_offset = _rom_gdt_offset + _gdt_size ;
_ram_idt_segment = 0x0000 ;
_ram_idt_offset = _ram_gdt_offset + _gdt_size ;
.idt _ram_idt_offset :
AT ( _rom_idt )
{
_sidt = .;
*(.idt);
_eidt = ALIGN (0x10);
}
_idt_size = _eidt - _sidt;
/****************************************************************************************
* data section:
*
* This section defines the locations of the data section in ROM as well as in RAM.
* start.s copies the data section to RAM when in protected mode.
* start.s copies the data section to RAM in real mode. This is done PRIOR to the lgdt
* instruction since the data section contains the Global_descriptor_table and GDTR.
***********************************************************************************/
_rom_data_start = _rom_idt + _idt_size ;
_rom_data_start = 0x3ff0000;
_rom_data_segment = 0xF000;
_rom_data_offset = 0x0;
_ram_data_segment = 0x0000 ;
_ram_data_offset = 0x0;
_ram_data_location = _ram_data_segment * 16 + _ram_data_offset;
.data :
AT ( _rom_data_start )
AT ( _rom_data_start )
{
_sdata = .;
*(.data);
_edata = ALIGN( 0x10 ) ;
_edata = .;
}
_data_start = ADDR(.data) ;
data_start = _data_start ;
@@ -123,6 +58,7 @@ SECTIONS
*
* The bss section is the last section in RAM.
*************************************************************************************/
_edata = ALIGN( 0x10 );
.bss :
{
_bss_start = .;
@@ -143,7 +79,7 @@ SECTIONS
* the heap used by RTEMS is as large as the RAM remaining after all workspace configurations
* are complete.
*************************************************************************************/
stack_size = 0x1000 ;
stack_size = 0x8000 ;
stack_origin = end + stack_size ;
heap_bottom = stack_origin + 4 ;
@@ -186,7 +122,8 @@ SECTIONS
*
* This section is defined after the data section. It must be in the top 64K of memory
* to enable the initial short jmp from the reset section while still in real-mode. It
* contains ALL initialization and data movement directives.
* initializes the i386ex, moves the gdt from ROM to RAM,loads the gdt,
* jumps to protected mode, copies the data section from ROM to RAM and loads the idt.
******************************************************************************************/
.initial _rom_data_start + _data_size :
@@ -195,14 +132,14 @@ SECTIONS
}
/*******************************************************************************************
* reset section:
* board reset section:
*
* This section contains the short jmp from the reset section to the initial section. It is
* the first code executed on reset/power on.
******************************************************************************************/
.reset 0x3fffff0:
.reset 0x3fffff0:
{
*(.reset);
}
}
}