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All of the Supplemental manuals are now generated as automatically

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as possible.
This commit is contained in:
Joel Sherrill
1998-10-19 21:46:32 +00:00
parent 2df2befc33
commit 03889c1a1e
22 changed files with 146 additions and 498 deletions
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35
doc/supplements/sparc/intr_NOTIMES.t
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@@ -6,25 +6,8 @@
@c $Id$
@c
@ifinfo
@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top
@end ifinfo
@chapter Interrupt Processing
@ifinfo
@menu
* Interrupt Processing Introduction::
* Interrupt Processing Synchronous Versus Asynchronous Traps::
* Interrupt Processing Vectoring of Interrupt Handler::
* Interrupt Processing Traps and Register Windows::
* Interrupt Processing Interrupt Levels::
* Interrupt Processing Disabling of Interrupts by RTEMS::
* Interrupt Processing Interrupt Stack::
@end menu
@end ifinfo
@ifinfo
@node Interrupt Processing Introduction, Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing, Interrupt Processing
@end ifinfo
@section Introduction
Different types of processors respond to the
@@ -47,9 +30,6 @@ interrupt and vector. In the SPARC architecture, these terms
correspond to traps and trap type, respectively. The terms will
be used interchangeably in this manual.
@ifinfo
@node Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Introduction, Interrupt Processing
@end ifinfo
@section Synchronous Versus Asynchronous Traps
The SPARC architecture includes two classes of traps:
@@ -72,9 +52,6 @@ return address reported by the processor for synchronous traps
is the instruction which caused the trap and the following
instruction.
@ifinfo
@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Traps and Register Windows, Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing
@end ifinfo
@section Vectoring of Interrupt Handler
Upon receipt of an interrupt the SPARC automatically
@@ -141,9 +118,6 @@ A nested interrupt is processed similarly with the
exception that the current stack need not be switched to the
interrupt stack.
@ifinfo
@node Interrupt Processing Traps and Register Windows, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
@end ifinfo
@section Traps and Register Windows
One of the register windows must be reserved at all
@@ -161,9 +135,6 @@ RTEMS interrupt handler insures that a register window is
available for subsequent traps before enabling traps and
invoking the user's interrupt handler.
@ifinfo
@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Traps and Register Windows, Interrupt Processing
@end ifinfo
@section Interrupt Levels
Sixteen levels (0-15) of interrupt priorities are
@@ -179,9 +150,6 @@ SPARC only supports sixteen. RTEMS interrupt levels 0 through
other RTEMS interrupt levels are undefined and their behavior is
unpredictable.
@ifinfo
@node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing
@end ifinfo
@section Disabling of Interrupts by RTEMS
During the execution of directive calls, critical
@@ -210,9 +178,6 @@ occur due to the inability of RTEMS to protect its critical
sections. However, ISRs that make no system calls may safely
execute as non-maskable interrupts.
@ifinfo
@node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing
@end ifinfo
@section Interrupt Stack
The SPARC architecture does not provide for a