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Whitespace removal.

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This commit is contained in:
Ralf Corsepius
2009-11-30 05:27:08 +00:00
parent 359e537416
commit 023f1dd927
16 changed files with 75 additions and 75 deletions
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2
c/src/lib/libcpu/m68k/mcf5206/include/mcf5206e.h
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@@ -582,7 +582,7 @@
#define MCF5206E_TMR_CE_NONE (0x0000) /* Disable Interrupt on capture #define MCF5206E_TMR_CE_NONE (0x0000) /* Disable Interrupt on capture
event */ event */
#define MCF5206E_TMR_OM (0x0020) /* Output Mode - Toggle output */ #define MCF5206E_TMR_OM (0x0020) /* Output Mode - Toggle output */
#define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt #define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt
Enable */ Enable */
#define MCF5206E_TMR_FRR (0x0008) /* Free Run/Restart */ #define MCF5206E_TMR_FRR (0x0008) /* Free Run/Restart */
#define MCF5206E_TMR_ICLK (0x0006) /* Input Clock Source */ #define MCF5206E_TMR_ICLK (0x0006) /* Input Clock Source */

6
c/src/lib/libcpu/m68k/mcf5206/include/mcfuart.h
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@@ -27,7 +27,7 @@
#define SYSTEM_CLOCK_FREQUENCY BSP_SYSTEM_FREQUENCY #define SYSTEM_CLOCK_FREQUENCY BSP_SYSTEM_FREQUENCY
#endif #endif
/* /*
* The following structure is a descriptor of single UART channel. * The following structure is a descriptor of single UART channel.
* It contains the initialization information about channel and * It contains the initialization information about channel and
* current operating values * current operating values
@@ -37,12 +37,12 @@ typedef struct mcfuart {
uint8_t intvec; /* UART interrupt vector number, or uint8_t intvec; /* UART interrupt vector number, or
0 if polled I/O */ 0 if polled I/O */
void *tty; /* termios channel descriptor */ void *tty; /* termios channel descriptor */
volatile const uint8_t *tx_buf; /* Transmit buffer from termios */ volatile const uint8_t *tx_buf; /* Transmit buffer from termios */
volatile uint32_t tx_buf_len; /* Transmit buffer length */ volatile uint32_t tx_buf_len; /* Transmit buffer length */
volatile uint32_t tx_ptr; /* Index of next char to transmit*/ volatile uint32_t tx_ptr; /* Index of next char to transmit*/
rtems_isr_entry old_handler; /* Saved interrupt handler */ rtems_isr_entry old_handler; /* Saved interrupt handler */
tcflag_t c_iflag; /* termios input mode flags */ tcflag_t c_iflag; /* termios input mode flags */
bool parerr_mark_flag; /* Parity error processing bool parerr_mark_flag; /* Parity error processing
state */ state */

2
c/src/lib/libcpu/m68k/mcf5206/timer/timerisr.S
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@@ -27,7 +27,7 @@
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
* *
* $Id$ * $Id$
*/ */

2
c/src/lib/libcpu/m68k/mcf5223x/cache/cachepd.c vendored
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@@ -5,7 +5,7 @@
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
* *
* $Id$ * $Id$
*/ */

4
c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c vendored
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@@ -6,13 +6,13 @@
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
* *
* $Id$ * $Id$
*/ */
#include <rtems.h> #include <rtems.h>
#include <mcf5235/mcf5235.h> #include <mcf5235/mcf5235.h>
/* /*
* Default value for the cacr is set by the BSP * Default value for the cacr is set by the BSP
*/ */

24
c/src/lib/libcpu/m68k/mcf5235/include/mcf5235.h
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@@ -158,7 +158,7 @@ typedef volatile uint32 vuint32; /* 32 bits */
/* /*
* Functions provided by mcf5xxx.s * Functions provided by mcf5xxx.s
*/ */
int asm_set_ipl (uint32); int asm_set_ipl (uint32);
void mcf5xxx_wr_cacr (uint32); void mcf5xxx_wr_cacr (uint32);
void mcf5xxx_wr_acr0 (uint32); void mcf5xxx_wr_acr0 (uint32);
@@ -862,16 +862,16 @@ extern uint8 __IPSBAR[];
#define MCF5235_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) #define MCF5235_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
#define MCF5235_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) #define MCF5235_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
#define MCF5235_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) #define MCF5235_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
/* Bit definitions and macros for MCF5235_CAN_CANMCR */ /* Bit definitions and macros for MCF5235_CAN_CANMCR */
#define MCF5235_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) #define MCF5235_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
#define MCF5235_CAN_CANMCR_SUPV (0x00800000) #define MCF5235_CAN_CANMCR_SUPV (0x00800000)
#define MCF5235_CAN_CANMCR_FRZACK (0x01000000) #define MCF5235_CAN_CANMCR_FRZACK (0x01000000)
#define MCF5235_CAN_CANMCR_SOFTRST (0x02000000) #define MCF5235_CAN_CANMCR_SOFTRST (0x02000000)
#define MCF5235_CAN_CANMCR_HALT (0x10000000) #define MCF5235_CAN_CANMCR_HALT (0x10000000)
#define MCF5235_CAN_CANMCR_FRZ (0x40000000) #define MCF5235_CAN_CANMCR_FRZ (0x40000000)
#define MCF5235_CAN_CANMCR_MDIS (0x80000000) #define MCF5235_CAN_CANMCR_MDIS (0x80000000)
#define MCF5235_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) #define MCF5235_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
#define MCF5235_CAN_CANCTRL_LOM (0x00000008) #define MCF5235_CAN_CANCTRL_LOM (0x00000008)
#define MCF5235_CAN_CANCTRL_LBUF (0x00000010) #define MCF5235_CAN_CANCTRL_LBUF (0x00000010)
@@ -1737,7 +1737,7 @@ extern uint8 __IPSBAR[];
/************************************************************ /************************************************************
* *
* Clock * Clock
*************************************************************/ *************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF5235_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000])) #define MCF5235_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000]))

26
c/src/lib/libcpu/m68k/mcf5272/clock/ckinit.c
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@@ -1,8 +1,8 @@
/* /*
* Clock Driver for MCF5272 CPU * Clock Driver for MCF5272 CPU
* *
* This driver initailizes timer1 on the MCF5272 as the * This driver initailizes timer1 on the MCF5272 as the
* main system clock * main system clock
* *
* Copyright 2004 Cogent Computer Systems * Copyright 2004 Cogent Computer Systems
* Author: Jay Monkman <jtm@lopingdog.com> * Author: Jay Monkman <jtm@lopingdog.com>
@@ -40,7 +40,7 @@ volatile uint32_t Clock_driver_ticks;
/* /*
* These are set by clock driver during its init * These are set by clock driver during its init
*/ */
rtems_device_major_number rtems_clock_major = ~0; rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor; rtems_device_minor_number rtems_clock_minor;
@@ -52,7 +52,7 @@ rtems_isr (*rtems_clock_hook)(rtems_vector_number) = NULL;
* *
* PARAMETERS: * PARAMETERS:
* vector - timer interrupt vector number * vector - timer interrupt vector number
* RETURNS: * RETURNS:
* none * none
*/ */
@@ -91,10 +91,10 @@ Clock_exit(void)
icr = icr & ~(MCF5272_ICR1_TMR1_MASK | MCF5272_ICR1_TMR1_PI); icr = icr & ~(MCF5272_ICR1_TMR1_MASK | MCF5272_ICR1_TMR1_PI);
icr |= (MCF5272_ICR1_TMR1_IPL(0) | MCF5272_ICR1_TMR1_PI); icr |= (MCF5272_ICR1_TMR1_IPL(0) | MCF5272_ICR1_TMR1_PI);
g_intctrl_regs->icr1 = icr; g_intctrl_regs->icr1 = icr;
/* reset timer1 */ /* reset timer1 */
g_timer_regs->tmr1 = MCF5272_TMR_CLK_STOP; g_timer_regs->tmr1 = MCF5272_TMR_CLK_STOP;
/* clear pending */ /* clear pending */
g_timer_regs->ter1 = MCF5272_TER_REF | MCF5272_TER_CAP; g_timer_regs->ter1 = MCF5272_TER_REF | MCF5272_TER_CAP;
} }
@@ -117,17 +117,17 @@ Install_clock(rtems_isr_entry clock_isr)
uint32_t icr; uint32_t icr;
Clock_driver_ticks = 0; Clock_driver_ticks = 0;
if (rtems_configuration_get_ticks_per_timeslice()) { if (rtems_configuration_get_ticks_per_timeslice()) {
/* Register the interrupt handler */ /* Register the interrupt handler */
set_vector(clock_isr, BSP_INTVEC_TMR1, 1); set_vector(clock_isr, BSP_INTVEC_TMR1, 1);
/* Reset timer 1 */ /* Reset timer 1 */
g_timer_regs->tmr1 = MCF5272_TMR_RST; g_timer_regs->tmr1 = MCF5272_TMR_RST;
g_timer_regs->tmr1 = MCF5272_TMR_CLK_STOP; g_timer_regs->tmr1 = MCF5272_TMR_CLK_STOP;
g_timer_regs->tmr1 = MCF5272_TMR_RST; g_timer_regs->tmr1 = MCF5272_TMR_RST;
g_timer_regs->tcn1 = 0; /* reset counter */ g_timer_regs->tcn1 = 0; /* reset counter */
g_timer_regs->ter1 = MCF5272_TER_REF | MCF5272_TER_CAP; g_timer_regs->ter1 = MCF5272_TER_REF | MCF5272_TER_CAP;
/* Set Timer 1 prescaler so that it counts in microseconds */ /* Set Timer 1 prescaler so that it counts in microseconds */
g_timer_regs->tmr1 = ( g_timer_regs->tmr1 = (
((((BSP_SYSTEM_FREQUENCY / 1000000) - 1) << MCF5272_TMR_PS_SHIFT) | ((((BSP_SYSTEM_FREQUENCY / 1000000) - 1) << MCF5272_TMR_PS_SHIFT) |
@@ -137,12 +137,12 @@ Install_clock(rtems_isr_entry clock_isr)
MCF5272_TMR_CLK_MSTR | MCF5272_TMR_CLK_MSTR |
MCF5272_TMR_RST)); MCF5272_TMR_RST));
/* Set the timer timeout value from the BSP config */ /* Set the timer timeout value from the BSP config */
g_timer_regs->trr1 = rtems_configuration_get_microseconds_per_tick() - 1; g_timer_regs->trr1 = rtems_configuration_get_microseconds_per_tick() - 1;
/* Feed system frequency to the timer */ /* Feed system frequency to the timer */
g_timer_regs->tmr1 |= MCF5272_TMR_CLK_MSTR; g_timer_regs->tmr1 |= MCF5272_TMR_CLK_MSTR;
/* Configure timer1 interrupts */ /* Configure timer1 interrupts */
icr = g_intctrl_regs->icr1; icr = g_intctrl_regs->icr1;
icr = icr & ~(MCF5272_ICR1_TMR1_MASK | MCF5272_ICR1_TMR1_PI); icr = icr & ~(MCF5272_ICR1_TMR1_MASK | MCF5272_ICR1_TMR1_PI);
@@ -174,10 +174,10 @@ Clock_initialize(rtems_device_major_number major,
void *pargp) void *pargp)
{ {
Install_clock (Clock_isr); Install_clock (Clock_isr);
/* Make major/minor avail to others such as shared memory driver */ /* Make major/minor avail to others such as shared memory driver */
rtems_clock_major = major; rtems_clock_major = major;
rtems_clock_minor = minor; rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL; return RTEMS_SUCCESSFUL;
} }

8
c/src/lib/libcpu/m68k/mcf5272/include/mcf5272.h
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@@ -281,7 +281,7 @@ typedef struct {
volatile uint16_t _res3; volatile uint16_t _res3;
volatile uint16_t pbdat; volatile uint16_t pbdat;
volatile uint16_t pcddr; volatile uint16_t pcddr;
volatile uint16_t _res4; volatile uint16_t _res4;
volatile uint16_t _res5; volatile uint16_t _res5;
@@ -321,7 +321,7 @@ typedef struct {
typedef struct { typedef struct {
volatile uint32_t dcmr; volatile uint32_t dcmr;
volatile uint16_t _res0; volatile uint16_t _res0;
volatile uint16_t dcir; volatile uint16_t dcir;
@@ -586,12 +586,12 @@ typedef struct {
volatile uint16_t rfmr; volatile uint16_t rfmr;
volatile uint16_t _res3; volatile uint16_t _res3;
volatile uint16_t rfmmr; volatile uint16_t rfmmr;
volatile uint8_t _res4[3]; volatile uint8_t _res4[3];
volatile uint8_t far; volatile uint8_t far;
volatile uint32_t asr; volatile uint32_t asr;
volatile uint32_t drr1; volatile uint32_t drr1;
volatile uint32_t drr2; volatile uint32_t drr2;
volatile uint16_t _res5; volatile uint16_t _res5;
volatile uint16_t specr; volatile uint16_t specr;
volatile uint16_t _res6; volatile uint16_t _res6;
volatile uint16_t ep0sr; volatile uint16_t ep0sr;

10
c/src/lib/libcpu/m68k/mcf5272/timer/timer.c
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@@ -18,7 +18,7 @@
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
* *
* timer.c,v 1.1 2001/10/26 19:32:40 joel Exp * timer.c,v 1.1 2001/10/26 19:32:40 joel Exp
*/ */
@@ -26,7 +26,7 @@
#include <bsp.h> #include <bsp.h>
#include <mcf5272/mcf5272.h> #include <mcf5272/mcf5272.h>
#define TRR2_VAL 65530 #define TRR2_VAL 65530
uint32_t Timer_interrupts; uint32_t Timer_interrupts;
@@ -51,7 +51,7 @@ benchmark_timer_initialize(void)
uint32_t icr; uint32_t icr;
/* Catch timer2 interrupts */ /* Catch timer2 interrupts */
set_vector(timerisr, BSP_INTVEC_TMR2, 0); set_vector(timerisr, BSP_INTVEC_TMR2, 0);
/* Reset Timer */ /* Reset Timer */
g_timer_regs->tmr2 = MCF5272_TMR_RST; g_timer_regs->tmr2 = MCF5272_TMR_RST;
g_timer_regs->tmr2 = MCF5272_TMR_CLK_STOP; g_timer_regs->tmr2 = MCF5272_TMR_CLK_STOP;
@@ -116,12 +116,12 @@ benchmark_timer_read( void )
* rolled over. * rolled over.
*/ */
clicks = g_timer_regs->tcn2; clicks = g_timer_regs->tcn2;
/* Stop Timer... */ /* Stop Timer... */
g_timer_regs->tmr2 = MCF5272_TMR_CLK_STOP | MCF5272_TMR_RST; g_timer_regs->tmr2 = MCF5272_TMR_CLK_STOP | MCF5272_TMR_RST;
/* /*
* Total is calculated by taking into account the number of timer * Total is calculated by taking into account the number of timer
* overflow interrupts since the timer was initialized and clicks * overflow interrupts since the timer was initialized and clicks
* since the last interrupts. * since the last interrupts.
*/ */

2
c/src/lib/libcpu/m68k/mcf5272/timer/timerisr.S
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@@ -27,7 +27,7 @@
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
* *
* timerisr.S,v 1.1 2001/10/26 19:32:40 joel Exp * timerisr.S,v 1.1 2001/10/26 19:32:40 joel Exp
*/ */

8
c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c vendored
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@@ -47,13 +47,13 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
adr += 1; adr += 1;
asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1; adr += 1;
asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
} }
void _CPU_cache_flush_entire_data(void) void _CPU_cache_flush_entire_data(void)
{ {
register unsigned long set, adr; register unsigned long set, adr;
for(set = 0; set < 256; ++set) { for(set = 0; set < 256; ++set) {
adr = (set << 4); adr = (set << 4);
asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
@@ -62,7 +62,7 @@ void _CPU_cache_flush_entire_data(void)
adr += 1; adr += 1;
asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1; adr += 1;
asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
} }
} }
@@ -136,4 +136,4 @@ void _CPU_cache_invalidate_entire_data(void)
void _CPU_cache_invalidate_1_data_line(const void *addr) void _CPU_cache_invalidate_1_data_line(const void *addr)
{ {
_CPU_cache_invalidate_1_instruction_line(addr); _CPU_cache_invalidate_1_instruction_line(addr);
} }

24
c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dma.h
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@@ -294,53 +294,53 @@ int MCD_startDma (
u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
); );
/* /*
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task structures, and * registers, relocating and creating the appropriate task structures, and
* setting up some global settings * setting up some global settings
*/ */
int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
/* /*
* MCD_dmaStatus() returns the status of the DMA on the requested channel. * MCD_dmaStatus() returns the status of the DMA on the requested channel.
*/ */
int MCD_dmaStatus (int channel); int MCD_dmaStatus (int channel);
/* /*
* MCD_XferProgrQuery() returns progress of DMA on requested channel * MCD_XferProgrQuery() returns progress of DMA on requested channel
*/ */
int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep); int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
/* /*
* MCD_killDma() halts the DMA on the requested channel, without any * MCD_killDma() halts the DMA on the requested channel, without any
* intention of resuming the DMA. * intention of resuming the DMA.
*/ */
int MCD_killDma (int channel); int MCD_killDma (int channel);
/* /*
* MCD_continDma() continues a DMA which as stopped due to encountering an * MCD_continDma() continues a DMA which as stopped due to encountering an
* unready buffer descriptor. * unready buffer descriptor.
*/ */
int MCD_continDma (int channel); int MCD_continDma (int channel);
/* /*
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
* running on that channel). * running on that channel).
*/ */
int MCD_pauseDma (int channel); int MCD_pauseDma (int channel);
/* /*
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
* running on that channel). * running on that channel).
*/ */
int MCD_resumeDma (int channel); int MCD_resumeDma (int channel);
/* /*
* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
*/ */
int MCD_csumQuery (int channel, u32 *csum); int MCD_csumQuery (int channel, u32 *csum);
/* /*
* MCD_getCodeSize provides the packed size required by the microcoded task * MCD_getCodeSize provides the packed size required by the microcoded task
* and structures. * and structures.
*/ */

14
c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dmaApi.c
View File

@@ -246,9 +246,9 @@ int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4; entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4;
} }
#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls #ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
where they are since DMA might write to them */ where they are since DMA might write to them */
MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4); MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
#else /* DMA does not touch them so they can be wherever and we don't need to #else /* DMA does not touch them so they can be wherever and we don't need to
waste SRAM on them */ waste SRAM on them */
MCD_relocBuffDesc = MCD_singleBufDescs; MCD_relocBuffDesc = MCD_singleBufDescs;
#endif #endif
@@ -379,14 +379,14 @@ int MCD_startDma (
if((channel < 0) || (channel >= NCHANNELS)) if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID); return(MCD_CHANNEL_INVALID);
/* tbd - need to determine the proper response to a bad funcDesc when not /* tbd - need to determine the proper response to a bad funcDesc when not
including EU functions, for now, assign a benign funcDesc, but maybe including EU functions, for now, assign a benign funcDesc, but maybe
should return an error */ should return an error */
#ifndef MCD_INCLUDE_EU #ifndef MCD_INCLUDE_EU
funcDesc = MCD_FUNC_NOEU1; funcDesc = MCD_FUNC_NOEU1;
#endif #endif
#ifdef MCD_DEBUG #ifdef MCD_DEBUG
printf("startDma:Setting up params\n"); printf("startDma:Setting up params\n");
#endif #endif
@@ -562,7 +562,7 @@ printf("startDma:Setting up params\n");
* Notes: * Notes:
* MCD_XferProgrQuery() upon completing or after aborting a DMA, or * MCD_XferProgrQuery() upon completing or after aborting a DMA, or
* while the DMA is in progress, this function returns the first * while the DMA is in progress, this function returns the first
* DMA-destination address not (or not yet) used in the DMA. When * DMA-destination address not (or not yet) used in the DMA. When
* encountering a non-ready buffer descriptor, the information for * encountering a non-ready buffer descriptor, the information for
* the last completed descriptor is returned. * the last completed descriptor is returned.
* *
@@ -808,7 +808,7 @@ int MCD_continDma (int channel)
* this means that bits 14 and 0 must enable debug functions before * this means that bits 14 and 0 must enable debug functions before
* bits 1 and 2, respectively, have any effect. * bits 1 and 2, respectively, have any effect.
* *
* NOTE: It's extremely important to not pause more than one DMA channel * NOTE: It's extremely important to not pause more than one DMA channel
* at a time. * at a time.
********************************************************************/ ********************************************************************/

2
c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasks.c
View File

@@ -1982,7 +1982,7 @@ u32 MCD_modelTaskTableSrc[]=
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
#endif #endif
(u32)MCD_ENetRcv_TDT, (u32)MCD_ENetRcv_TDT,
(u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c], (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c],
0x00000000, 0x00000000,

12
c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasksInit.c
View File

@@ -18,7 +18,7 @@ extern dmaRegs *MCD_dmaBar;
/* /*
* Task 0 * Task 0
*/ */
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{ {
@@ -55,7 +55,7 @@ void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer
/* /*
* Task 1 * Task 1
*/ */
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{ {
@@ -85,7 +85,7 @@ void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short
/* /*
* Task 2 * Task 2
*/ */
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{ {
@@ -125,7 +125,7 @@ void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi
/* /*
* Task 3 * Task 3
*/ */
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{ {
@@ -159,7 +159,7 @@ void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short d
/* /*
* Task 4 * Task 4
*/ */
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel) void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
{ {
@@ -189,7 +189,7 @@ void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile
/* /*
* Task 5 * Task 5
*/ */
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel) void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
{ {

4
c/src/lib/libcpu/m68k/mcf548x/mcdma/mcdma_glue.c
View File

@@ -216,10 +216,10 @@ void mcdma_glue_init
&old_handler)) { &old_handler)) {
rtems_panic ("Can't attach MFC548x MCDma interrupt handler\n"); rtems_panic ("Can't attach MFC548x MCDma interrupt handler\n");
} }
MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) = MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) =
MCF548X_INTC_ICRn_IL(MCDMA_IRQ_LEVEL) | MCF548X_INTC_ICRn_IL(MCDMA_IRQ_LEVEL) |
MCF548X_INTC_ICRn_IP(MCDMA_IRQ_PRIORITY); MCF548X_INTC_ICRn_IP(MCDMA_IRQ_PRIORITY);
MCF548X_INTC_IMRH &= ~(1 << (MCDMA_IRQ_VECTOR % 32)); MCF548X_INTC_IMRH &= ~(1 << (MCDMA_IRQ_VECTOR % 32));
} }
} }