Add thread-local storage (TLS) support

Tested and implemented on ARM, m68k, PowerPC and SPARC.  Other
architectures need more work.

doc/cpu_supplement/Makefile.am

@@ -10,8 +10,25 @@ include $(top_srcdir)/main.am
 
 REPLACE2 = $(PERL) $(top_srcdir)/tools/word-replace2
 
-GENERATED_FILES = general.texi arm.texi avr.texi bfin.texi i386.texi lm32.texi \
-    m68k.texi mips.texi powerpc.texi sh.texi sparc.texi sparc64.texi v850.texi
+GENERATED_FILES =
+GENERATED_FILES += general.texi
+GENERATED_FILES += arm.texi
+GENERATED_FILES += avr.texi
+GENERATED_FILES += bfin.texi
+GENERATED_FILES += h8300.texi
+GENERATED_FILES += i386.texi
+GENERATED_FILES += lm32.texi
+GENERATED_FILES += m32c.texi
+GENERATED_FILES += m32r.texi
+GENERATED_FILES += m68k.texi
+GENERATED_FILES += microblaze.texi
+GENERATED_FILES += mips.texi
+GENERATED_FILES += powerpc.texi
+GENERATED_FILES += nios2.texi
+GENERATED_FILES += sh.texi
+GENERATED_FILES += sparc.texi
+GENERATED_FILES += sparc64.texi
+GENERATED_FILES += v850.texi
 
 COMMON_FILES += $(top_srcdir)/common/cpright.texi
 
@@ -44,11 +61,26 @@ bfin.texi: bfin.t
 	    -u "Top" \
 	    -n "" < $< > $@
 
+h8300.texi: h8300.t
+	$(BMENU2) -p "" \
+	    -u "Top" \
+	    -n "" < $< > $@
+
 i386.texi: i386.t
 	$(BMENU2) -p "" \
 	    -u "Top" \
 	    -n "" < $< > $@
 
+m32c.texi: m32c.t
+	$(BMENU2) -p "" \
+	    -u "Top" \
+	    -n "" < $< > $@
+
+m32r.texi: m32r.t
+	$(BMENU2) -p "" \
+	    -u "Top" \
+	    -n "" < $< > $@
+
 lm32.texi: lm32.t
 	$(BMENU2) -p "" \
 	    -u "Top" \
@@ -59,6 +91,11 @@ m68k.texi: m68k.t
 	    -u "Top" \
 	    -n "" < $< > $@
 
+microblaze.texi: microblaze.t
+	$(BMENU2) -p "" \
+	    -u "Top" \
+	    -n "" < $< > $@
+
 mips.texi: mips.t
 	$(BMENU2) -p "" \
 	    -u "Top" \
@@ -69,6 +106,11 @@ powerpc.texi: powerpc.t
 	    -u "Top" \
 	    -n "" < $< > $@
 
+nios2.texi: nios2.t
+	$(BMENU2) -p "" \
+	    -u "Top" \
+	    -n "" < $< > $@
+
 sh.texi: sh.t
 	$(BMENU2) -p "" \
 	    -u "Top" \

doc/cpu_supplement/arm.t

@@ -97,3 +97,7 @@ following actions:
 @item places the error code in @code{r0}, and
 @item executes an infinite loop to simulate a halt processor instruction.
 @end itemize
+
+@section Thread-Local Storage
+
+Thread-local storage is supported.

doc/cpu_supplement/avr.t

@@ -117,6 +117,10 @@ actions:
 simulate a halt processor instruction.
 @end itemize
 
+@section Thread-Local Storage
+
+Thread-local storage is not supported due to a broken tool chain.
+
 @section Board Support Packages
 
 

doc/cpu_supplement/bfin.t

@@ -130,6 +130,10 @@ actions:
 simulate a halt processor instruction.
 @end itemize
 
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.
+
 @section Board Support Packages
 
 

doc/cpu_supplement/cpu_supplement.texi

@@ -65,10 +65,15 @@
 * ARM Specific Information::
 * Atmel AVR Specific Information::
 * Blackfin Specific Information::
+* Renesas H8/300 Specific Information::
 * Intel/AMD x86 Specific Information::
 * Lattice Mico32 Specific Information::
+* Renesas M32C Specific Information::
+* Renesas M32R Specific Information::
 * M68xxx and Coldfire Specific Information::
+* Xilinx MicroBlaze Specific Information::
 * MIPS Specific Information::
+* Altera Nios II Specific Information::
 * PowerPC Specific Information::
 * SuperH Specific Information::
 * SPARC Specific Information::
@@ -83,10 +88,15 @@
 @include arm.texi
 @include avr.texi
 @include bfin.texi
+@include h8300.texi
 @include i386.texi
 @include lm32.texi
+@include m32c.texi
+@include m32r.texi
 @include m68k.texi
+@include microblaze.texi
 @include mips.texi
+@include nios2.texi
 @include powerpc.texi
 @include sh.texi
 @include sparc.texi

doc/cpu_supplement/general.t

@@ -314,6 +314,33 @@ interrupts and halts the processor.
 In each of the architecture specific chapters, this describes the precise
 operations of the default CPU specific fatal error handler.
 
+@section Thread-Local Storage
+
+In order to support thread-local storage (TLS) the CPU port must implement the
+facilities mandated by the application binary interface (ABI) of the CPU
+architecture.  The CPU port must initialize the TLS area in the
+@code{_CPU_Context_Initialize} function.
+
+The board support package (BSP) must provide the following sections and symbols
+in its linker command file:
+
+@example
+.tdata : @{
+  _TLS_Data_begin = .;
+  *(.tdata .tdata.* .gnu.linkonce.td.*)
+  _TLS_Data_end = .;
+@}
+.tbss : @{
+  _TLS_BSS_begin = .;
+  *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+  _TLS_BSS_end = .;
+@}
+_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
+_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
+_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
+_TLS_Alignment = ALIGNOF (.tdata);
+@end example
+
 @c
 @c
 @c

doc/cpu_supplement/h8300.t

@@ -0,0 +1,7 @@
+@c Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+
+@chapter Renesas H8/300 Specific Information
+
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.

doc/cpu_supplement/i386.t

@@ -266,6 +266,10 @@ The default fatal error handler for this architecture disables processor
 interrupts, places the error code in EAX, and executes a HLT instruction
 to halt the processor.
 
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.
+
 @c
 @c
 @c

doc/cpu_supplement/lm32.t

@@ -163,6 +163,10 @@ interrupts and halts the processor.
 In each of the architecture specific chapters, this describes the precise
 operations of the default CPU specific fatal error handler.
 
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.
+
 @c
 @c
 @c

doc/cpu_supplement/m32c.t

@@ -0,0 +1,7 @@
+@c Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+
+@chapter Renesas M32C Specific Information
+
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.

doc/cpu_supplement/m32r.t

@@ -0,0 +1,7 @@
+@c Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+
+@chapter Renesas M32R Specific Information
+
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.

doc/cpu_supplement/m68k.t

@@ -357,6 +357,10 @@ The default fatal error handler for this architecture disables processor
 interrupts to level 7, places the error code in D0, and executes a
 @code{stop} instruction to simulate a halt processor instruction.
 
+@section Thread-Local Storage
+
+Thread-local storage is supported.
+
 @c
 @c
 @c

doc/cpu_supplement/microblaze.t

@@ -0,0 +1,7 @@
+@c Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+
+@chapter Xilinx MicroBlaze Specific Information
+
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.

doc/cpu_supplement/mips.t

@@ -122,6 +122,10 @@ The default fatal error handler for this target architecture disables
 processor interrupts, places the error code in @b{XXX}, and executes a
 @code{XXX} instruction to simulate a halt processor instruction.
 
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.
+
 @c
 @c
 @c

doc/cpu_supplement/nios2.t

@@ -0,0 +1,7 @@
+@c Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+
+@chapter Altera Nios II Specific Information
+
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.

doc/cpu_supplement/powerpc.t

@@ -623,6 +623,10 @@ If the Program Exception returns, then the following actions are performed:
 
 @end itemize
 
+@section Thread-Local Storage
+
+Thread-local storage is supported.
+
 @c
 @c
 @c

doc/cpu_supplement/sh.t

@@ -139,6 +139,10 @@ The default fatal error handler for this architecture disables processor
 interrupts, places the error code in @b{XXX}, and executes a @code{XXX}
 instruction to simulate a halt processor instruction.
 
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.
+
 @c
 @c
 @c

doc/cpu_supplement/sparc.t

@@ -917,6 +917,9 @@ default fatal error handler disables processor interrupts to
 level 15, places the error code in g1, and goes into an infinite
 loop to simulate a halt processor instruction.
 
+@section Thread-Local Storage
+
+Thread-local storage is supported.
 
 @c
 @c  COPYRIGHT (c) 1988-2002.

doc/cpu_supplement/sparc64.t

@@ -773,6 +773,9 @@ default fatal error handler disables processor interrupts to
 level 15, places the error code in g1, and goes into an infinite
 loop to simulate a halt processor instruction.
 
+@section Thread-Local Storage
+
+Thread-local storage is supported.
 
 @c
 @c  COPYRIGHT (c) 1988-2002.

doc/cpu_supplement/v850.t

@@ -102,3 +102,7 @@ following actions:
 @item places the error code in @code{r10}, and
 @item executes a halt processor instruction.
 @end itemize
+
+@section Thread-Local Storage
+
+Thread-local storage is not implemented.