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riscv64-tok.h: update with more instructions from the spec

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defined tokens for C, M, Ziscr extensions.

separate the base RV32 instructions from the RV64, for potential future
re-use in a RV32-only assembler, from which the RV64-tok can #include

scall, sbreak have been renamed (page 7 of spec),
necessitating some renaming in riscv64-asm.c

riscv-spec-20191213.pdf was used,
in which the "V" extension is not yet ratified.
available under https://riscv.org/technical/specifications/

Tables 16.5–16.7 do not list any "scall"
neither does the privileged spec

3 additional tokens not present in the tables were removed

note that this riscv64-asm.c still contains defects, which will
be addressed in another commit
This commit is contained in:
noneofyourbusiness
2023-08-10 13:27:11 +02:00
parent c29420ab0d
commit e70fec871b
2 changed files with 121 additions and 33 deletions
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18
riscv64-asm.c
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@@ -75,22 +75,13 @@ static void asm_nullary_opcode(TCCState *s1, int token)
// System calls
case TOK_ASM_scall: // I (pseudo)
case TOK_ASM_ecall: // I (pseudo)
asm_emit_opcode((0x1C << 2) | 3 | (0 << 12));
return;
case TOK_ASM_sbreak: // I (pseudo)
case TOK_ASM_ebreak: // I (pseudo)
asm_emit_opcode((0x1C << 2) | 3 | (0 << 12) | (1 << 20));
return;
// Privileged Instructions
case TOK_ASM_ecall:
asm_emit_opcode((0x1C << 2) | 3 | (0 << 20));
return;
case TOK_ASM_ebreak:
asm_emit_opcode((0x1C << 2) | 3 | (1 << 20));
return;
// Other
case TOK_ASM_wfi:
@@ -577,8 +568,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
switch (token) {
case TOK_ASM_fence:
case TOK_ASM_fence_i:
case TOK_ASM_scall:
case TOK_ASM_sbreak:
case TOK_ASM_ecall:
case TOK_ASM_ebreak:
case TOK_ASM_mrts:
@@ -627,11 +616,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
case TOK_ASM_addi:
case TOK_ASM_sub:
case TOK_ASM_addw:
case TOK_ASM_addd:
case TOK_ASM_addiw:
case TOK_ASM_addid:
case TOK_ASM_subw:
case TOK_ASM_subd:
case TOK_ASM_xor:
case TOK_ASM_xori:
case TOK_ASM_or: