mirror of
https://github.com/eclipse-threadx/threadx.git
synced 2025-11-16 04:24:48 +00:00
Release 6.1.7
This commit is contained in:
Bo Chen
@@ -1,24 +0,0 @@
|
||||
# Parameters:
|
||||
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
|
||||
#----------------------------------------------------------------------------------------------
|
||||
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
|
||||
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
|
||||
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
|
||||
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
|
||||
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
|
||||
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
|
||||
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
|
||||
cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
|
||||
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
|
||||
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
|
||||
cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
|
||||
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
|
||||
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
|
||||
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
|
||||
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
|
||||
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
|
||||
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
|
||||
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
|
||||
cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
|
||||
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
|
||||
#----------------------------------------------------------------------------------------------
|
||||
@@ -1,23 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<WorkspaceName>WorkSpace</WorkspaceName>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\demo_secure_zone\demo_secure_zone.uvprojx</PathAndName>
|
||||
<NodeIsActive>1</NodeIsActive>
|
||||
</project>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx</PathAndName>
|
||||
</project>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\ThreadX_Library.uvprojx</PathAndName>
|
||||
</project>
|
||||
|
||||
</ProjectWorkspace>
|
||||
@@ -1,4 +0,0 @@
|
||||
LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental
|
||||
LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental
|
||||
RESET
|
||||
g, \\demo_secure_zone\main_s\main
|
||||
@@ -1,21 +0,0 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'ThreadX_Library'
|
||||
* Target: 'ThreadX_Library_Project'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
|
||||
This ARM Cortex-M33 secure/non-secure example project that
|
||||
shows the setup of the CMSIS-RTOS2 RTX for TrustZone for
|
||||
ARMv8-M applications.
|
||||
|
||||
The application uses CMSIS and can be executed on a Fixed
|
||||
Virtual Platform (FVP) simulation model. The application
|
||||
demonstrates three RTOS threads.
|
||||
|
||||
|
||||
Secure application:
|
||||
- Setup code and start non-secure application.
|
||||
|
||||
Non-secure application:
|
||||
- Calls a secure function from non-secure state.
|
||||
- Calls a secure function that call back to a non-secure function.
|
||||
|
||||
Output:
|
||||
Variables used in this application can be viewed in the Debugger
|
||||
Watch window.
|
||||
@@ -1,78 +0,0 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
|
||||
; command above MUST be in first line (no comment above!)
|
||||
|
||||
/*
|
||||
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Flash Configuration ----------------------------------
|
||||
; <h> Flash Configuration
|
||||
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __ROM_BASE 0x00000000
|
||||
#define __ROM_SIZE 0x00200000
|
||||
|
||||
/*--------------------- Embedded RAM Configuration ---------------------------
|
||||
; <h> RAM Configuration
|
||||
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_BASE 0x20000000
|
||||
#define __RAM_SIZE 0x00020000
|
||||
|
||||
/*--------------------- Stack / Heap Configuration ---------------------------
|
||||
; <h> Stack / Heap Configuration
|
||||
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_SIZE 0x00000400
|
||||
#define __HEAP_SIZE 0x00000C00
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
User Stack & Heap boundery definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
|
||||
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Scatter File Definitions definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RO_BASE __ROM_BASE
|
||||
#define __RO_SIZE __ROM_SIZE
|
||||
|
||||
#define __RW_BASE (__RAM_BASE )
|
||||
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
|
||||
|
||||
|
||||
|
||||
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
|
||||
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
; *(Veneer$$CMSE) ; uncomment for secure applications
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
RW_RAM __RW_BASE __RW_SIZE { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
#if __HEAP_SIZE > 0
|
||||
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
|
||||
}
|
||||
#endif
|
||||
|
||||
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
|
||||
}
|
||||
SEAL +0
|
||||
{
|
||||
*.o(.seal+FIRST)
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,139 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCM33.c
|
||||
* @brief CMSIS Core Device Startup File for Cortex-M33 Device
|
||||
* @version V2.0.0
|
||||
* @date 20. May 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM33)
|
||||
#include "ARMCM33.h"
|
||||
#elif defined (ARMCM33_TZ)
|
||||
#include "ARMCM33_TZ.h"
|
||||
#elif defined (ARMCM33_DSP_FP)
|
||||
#include "ARMCM33_DSP_FP.h"
|
||||
#elif defined (ARMCM33_DSP_FP_TZ)
|
||||
#include "ARMCM33_DSP_FP_TZ.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler Function Prototype
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef void( *pFunc )( void );
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __INITIAL_SP;
|
||||
extern uint32_t __STACK_LIMIT;
|
||||
|
||||
extern void __PROGRAM_START(void) __NO_RETURN;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void) __NO_RETURN;
|
||||
void Reset_Handler (void) __NO_RETURN;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const pFunc __VECTOR_TABLE[496];
|
||||
const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
Reset_Handler, /* Reset Handler */
|
||||
NMI_Handler, /* -14 NMI Handler */
|
||||
HardFault_Handler, /* -13 Hard Fault Handler */
|
||||
MemManage_Handler, /* -12 MPU Fault Handler */
|
||||
BusFault_Handler, /* -11 Bus Fault Handler */
|
||||
UsageFault_Handler, /* -10 Usage Fault Handler */
|
||||
SecureFault_Handler, /* -9 Secure Fault Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
SVC_Handler, /* -5 SVCall Handler */
|
||||
DebugMon_Handler, /* -4 Debug Monitor Handler */
|
||||
0, /* Reserved */
|
||||
PendSV_Handler, /* -2 PendSV Handler */
|
||||
SysTick_Handler, /* -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
Interrupt0_Handler, /* 0 Interrupt 0 */
|
||||
Interrupt1_Handler, /* 1 Interrupt 1 */
|
||||
Interrupt2_Handler, /* 2 Interrupt 2 */
|
||||
Interrupt3_Handler, /* 3 Interrupt 3 */
|
||||
Interrupt4_Handler, /* 4 Interrupt 4 */
|
||||
Interrupt5_Handler, /* 5 Interrupt 5 */
|
||||
Interrupt6_Handler, /* 6 Interrupt 6 */
|
||||
Interrupt7_Handler, /* 7 Interrupt 7 */
|
||||
Interrupt8_Handler, /* 8 Interrupt 8 */
|
||||
Interrupt9_Handler /* 9 Interrupt 9 */
|
||||
/* Interrupts 10 .. 480 are left out */
|
||||
};
|
||||
|
||||
/* The linker will place this value at the bottom of the stack to seal the secure main stack. */
|
||||
const int stack_seal __attribute__((section (".seal"))) = 0xFEF5EDA5;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
|
||||
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
@@ -1,115 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM33.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM33 Device
|
||||
* @version V5.3.1
|
||||
* @date 09. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM33)
|
||||
#include "ARMCM33.h"
|
||||
#elif defined (ARMCM33_TZ)
|
||||
#include "ARMCM33_TZ.h"
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#include "partition_ARMCM33.h"
|
||||
#endif
|
||||
#elif defined (ARMCM33_DSP_FP)
|
||||
#include "ARMCM33_DSP_FP.h"
|
||||
#elif defined (ARMCM33_DSP_FP_TZ)
|
||||
#include "ARMCM33_DSP_FP_TZ.h"
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#include "partition_ARMCM33.h"
|
||||
#endif
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (50000000UL) /* Oscillator frequency */
|
||||
|
||||
#define SYSTEM_CLOCK (XTAL / 2U)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Externals
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
extern uint32_t __Vectors;
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System initialization function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
SCB->VTOR = (uint32_t) &__Vectors;
|
||||
#endif
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
|
||||
(3U << 11U*2U) ); /* enable CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
TZ_SAU_Setup();
|
||||
#endif
|
||||
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
|
||||
*(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */
|
||||
*(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */
|
||||
}
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
|
||||
}
|
||||
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
#endif
|
||||
@@ -1,21 +0,0 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'demo_secure_zone'
|
||||
* Target: 'FVP Simulation Model'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -1,318 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>0</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>15</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>..\Debug.ini</tIfile>
|
||||
<pMon>BIN\DbgFMv8M.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(6010=245,200,722,796,0)(6018=306,263,495,612,0)(6019=488,279,677,615,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=724,129,982,860,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DbgFMv8M</Key>
|
||||
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -PF -MA</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2V8M</Key>
|
||||
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<WatchWindow1>
|
||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_0_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>1</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_1_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>2</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_2_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>3</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_3_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>4</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_4_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>5</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_5_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>6</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_6_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>7</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_7_counter</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<MemoryWindow1>
|
||||
<Mm>
|
||||
<WinNumber>1</WinNumber>
|
||||
<SubType>2</SubType>
|
||||
<ItemText>0x2001ffd8</ItemText>
|
||||
<AccSizeX>0</AccSizeX>
|
||||
</Mm>
|
||||
</MemoryWindow1>
|
||||
<MemoryWindow2>
|
||||
<Mm>
|
||||
<WinNumber>2</WinNumber>
|
||||
<SubType>2</SubType>
|
||||
<ItemText>0xE000ED28</ItemText>
|
||||
<AccSizeX>0</AccSizeX>
|
||||
</Mm>
|
||||
</MemoryWindow2>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Secure Code</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\main_s.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main_s.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\src\tx_thread_secure_stack.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tx_thread_secure_stack.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Interface</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\interface.c</PathWithFileName>
|
||||
<FilenameWithoutPath>interface.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -1,497 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>ARMCM33_DSP_FP_TZ</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<PackID>ARM.CMSIS.5.7.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>demo_secure_zone</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>1</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName></SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll></SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMV8M.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>0</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>0</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M33"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>1</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x200000</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>7</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>3</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>3</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\..\..\..\common\inc, ..\..\inc</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_AC6.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Secure Code</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main_s.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main_s.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tx_thread_secure_stack.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\src\tx_thread_secure_stack.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Interface</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>interface.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\interface.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.0" condition="ARMCM33 CMSIS">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.0.0">
|
||||
<instance index="0" removed="1">RTE\CMSIS\RTX_Config.c</instance>
|
||||
<component Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.0.0" condition="RTOS2 RTX5 NS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" condition="TZ Secure" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.1">
|
||||
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayDesc></LayDesc>
|
||||
<LayUrl></LayUrl>
|
||||
<LayKeys></LayKeys>
|
||||
<LayCat></LayCat>
|
||||
<LayLic></LayLic>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
@@ -1,49 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* interface.c Secure/non-secure callable application code
|
||||
*
|
||||
* Version 1.0
|
||||
* Initial Release
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include <arm_cmse.h> // CMSE definitions
|
||||
#include "interface.h" // Header file with secure interface API
|
||||
|
||||
/* typedef for non-secure callback functions */
|
||||
typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));
|
||||
|
||||
/* Non-secure callable (entry) function */
|
||||
int func1(int x) __attribute__((cmse_nonsecure_entry)) {
|
||||
return x+3;
|
||||
}
|
||||
|
||||
/* Non-secure callable (entry) function, calling a non-secure callback function */
|
||||
int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) {
|
||||
funcptr_NS callback_NS; // non-secure callback function pointer
|
||||
int y;
|
||||
|
||||
/* return function pointer with cleared LSB */
|
||||
callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);
|
||||
|
||||
y = callback_NS (x+1);
|
||||
|
||||
return (y+2);
|
||||
}
|
||||
@@ -1,31 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* interface.h API definition for the non-secure state
|
||||
*
|
||||
* Version 1.0
|
||||
* Initial Release
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/* Function pointer declaration */
|
||||
typedef int (*funcptr)(int);
|
||||
|
||||
/* Non-secure callable functions */
|
||||
extern int func1(int x);
|
||||
extern int func2(funcptr callback, int x);
|
||||
@@ -1,108 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* main_ns.c Non-secure main function - RTOS demo
|
||||
*
|
||||
* Version 1.0
|
||||
* Initial Release
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "interface.h" // Interface API
|
||||
//#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
|
||||
|
||||
//static osStatus_t Status;
|
||||
|
||||
//static osThreadId_t ThreadA_Id;
|
||||
//static osThreadId_t ThreadB_Id;
|
||||
//static osThreadId_t ThreadC_Id;
|
||||
|
||||
void ThreadA (void *argument);
|
||||
void ThreadB (void *argument);
|
||||
void ThreadC (void *argument);
|
||||
|
||||
|
||||
extern volatile int counterA;
|
||||
extern volatile int counterB;
|
||||
extern volatile int counterC;
|
||||
|
||||
volatile int counterA;
|
||||
volatile int counterB;
|
||||
volatile int counterC;
|
||||
|
||||
/*
|
||||
static int callbackA (int val) {
|
||||
return (val);
|
||||
}
|
||||
|
||||
__attribute__((noreturn))
|
||||
void ThreadA (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {
|
||||
counterA = func1 (counterA);
|
||||
counterA = func2 (callbackA, counterA);
|
||||
osDelay(2U);
|
||||
}
|
||||
}
|
||||
|
||||
static int callbackB (int val) {
|
||||
uint32_t flags;
|
||||
|
||||
flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever);
|
||||
if (flags == 1U) {
|
||||
return (val+1);
|
||||
} else {
|
||||
return (0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
__attribute__((noreturn))
|
||||
void ThreadB (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {
|
||||
counterB = func1 (counterB);
|
||||
counterB = func2 (callbackB, counterB);
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((noreturn))
|
||||
void ThreadC (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {
|
||||
counterC = counterC + 1;
|
||||
if ((counterC % 0x10) == 0) {
|
||||
osThreadFlagsSet (ThreadB_Id, 1);
|
||||
}
|
||||
osDelay(1U);
|
||||
}
|
||||
}
|
||||
|
||||
static const osThreadAttr_t ThreadAttr = {
|
||||
.tz_module = 1U, // indicate calls to secure mode
|
||||
};
|
||||
*/
|
||||
#if 1
|
||||
int main (void) {
|
||||
|
||||
for (;;);
|
||||
}
|
||||
#endif
|
||||
@@ -1,61 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 15. October 2016
|
||||
* $Revision: 1.1.0
|
||||
*
|
||||
* Project: TrustZone for ARMv8-M
|
||||
* Title: Code template for secure main function
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/* Use CMSE intrinsics */
|
||||
#include <arm_cmse.h>
|
||||
#include <stdlib.h>
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* TZ_START_NS: Start address of non-secure application */
|
||||
#ifndef TZ_START_NS
|
||||
#define TZ_START_NS (0x200000U)
|
||||
#endif
|
||||
|
||||
/* typedef for non-secure callback functions */
|
||||
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
|
||||
|
||||
/* Secure main() */
|
||||
int main(void) {
|
||||
funcptr_void NonSecure_ResetHandler;
|
||||
|
||||
/* Add user setup code for secure part here*/
|
||||
|
||||
/* Set non-secure main stack (MSP_NS) */
|
||||
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
|
||||
|
||||
/* Get non-secure reset handler */
|
||||
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
|
||||
|
||||
/* Start non-secure state software application */
|
||||
NonSecure_ResetHandler();
|
||||
|
||||
/* Non-secure software does not return, this code is not executed */
|
||||
while (1) {
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
@@ -1,203 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 15. October 2016
|
||||
* $Revision: 1.1.0
|
||||
*
|
||||
* Project: TrustZone for ARMv8-M
|
||||
* Title: Context Management for ARMv8-M TrustZone - Sample implementation
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "tz_context.h"
|
||||
|
||||
/// Number of process slots (threads may call secure library code)
|
||||
#ifndef TZ_PROCESS_STACK_SLOTS
|
||||
#define TZ_PROCESS_STACK_SLOTS 8U
|
||||
#endif
|
||||
|
||||
/// Stack size of the secure library code
|
||||
#ifndef TZ_PROCESS_STACK_SIZE
|
||||
#define TZ_PROCESS_STACK_SIZE 256U
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint32_t sp_top; // stack space top
|
||||
uint32_t sp_limit; // stack space limit
|
||||
uint32_t sp; // current stack pointer
|
||||
} stack_info_t;
|
||||
|
||||
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
|
||||
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
|
||||
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
|
||||
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_InitContextSystem_S (void) {
|
||||
uint32_t n;
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
|
||||
ProcessStackInfo[n].sp = 0U;
|
||||
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
|
||||
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
|
||||
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
|
||||
}
|
||||
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
|
||||
|
||||
ProcessStackFreeSlot = 0U;
|
||||
|
||||
// Default process stack pointer and stack limit
|
||||
__set_PSPLIM((uint32_t)ProcessStackMemory);
|
||||
__set_PSP ((uint32_t)ProcessStackMemory);
|
||||
|
||||
// Privileged Thread Mode using PSP
|
||||
__set_CONTROL(0x02U);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
|
||||
uint32_t slot;
|
||||
|
||||
(void)module; // Ignore (fixed Stack size)
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
|
||||
return 0U; // No slot available
|
||||
}
|
||||
|
||||
slot = ProcessStackFreeSlot;
|
||||
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
|
||||
|
||||
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
|
||||
|
||||
return (slot + 1U);
|
||||
}
|
||||
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
ProcessStackInfo[slot].sp = 0U;
|
||||
|
||||
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
|
||||
ProcessStackFreeSlot = slot;
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
|
||||
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
|
||||
return 0U; // Thread Mode or using Main Stack for threads
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
|
||||
// Setup process stack pointer and stack limit
|
||||
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
|
||||
__set_PSP (ProcessStackInfo[slot].sp);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
uint32_t sp;
|
||||
|
||||
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
|
||||
return 0U; // Thread Mode or using Main Stack for threads
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
|
||||
sp = __get_PSP();
|
||||
if ((sp < ProcessStackInfo[slot].sp_limit) ||
|
||||
(sp > ProcessStackInfo[slot].sp_top)) {
|
||||
return 0U; // SP out of range
|
||||
}
|
||||
ProcessStackInfo[slot].sp = sp;
|
||||
|
||||
// Default process stack pointer and stack limit
|
||||
__set_PSPLIM((uint32_t)ProcessStackMemory);
|
||||
__set_PSP ((uint32_t)ProcessStackMemory);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
@@ -1,64 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*
|
||||
* $Revision: V5.1.0
|
||||
*
|
||||
* Project: CMSIS-RTOS RTX
|
||||
* Title: RTX Configuration
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "cmsis_compiler.h"
|
||||
#include "rtx_os.h"
|
||||
|
||||
// OS Idle Thread
|
||||
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {}
|
||||
}
|
||||
|
||||
// OS Error Callback function
|
||||
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
|
||||
(void)object_id;
|
||||
|
||||
switch (code) {
|
||||
case osRtxErrorStackUnderflow:
|
||||
// Stack overflow detected for thread (thread_id=object_id)
|
||||
break;
|
||||
case osRtxErrorISRQueueOverflow:
|
||||
// ISR Queue overflow detected when inserting object (object_id)
|
||||
break;
|
||||
case osRtxErrorTimerQueueOverflow:
|
||||
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
|
||||
break;
|
||||
case osRtxErrorClibSpace:
|
||||
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
|
||||
break;
|
||||
case osRtxErrorClibMutex:
|
||||
// Standard C/C++ library mutex initialization failed
|
||||
break;
|
||||
default:
|
||||
// Reserved
|
||||
break;
|
||||
}
|
||||
for (;;) {}
|
||||
//return 0U;
|
||||
}
|
||||
@@ -1,578 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*
|
||||
* $Revision: V5.5.0
|
||||
*
|
||||
* Project: CMSIS-RTOS RTX
|
||||
* Title: RTX Configuration definitions
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef RTX_CONFIG_H_
|
||||
#define RTX_CONFIG_H_
|
||||
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
|
||||
#ifdef RTE_RTX_CONFIG_H
|
||||
#include RTE_RTX_CONFIG_H
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>System Configuration
|
||||
// =======================
|
||||
|
||||
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined global dynamic memory size.
|
||||
// <i> Default: 4096
|
||||
#ifndef OS_DYNAMIC_MEM_SIZE
|
||||
#define OS_DYNAMIC_MEM_SIZE 4096
|
||||
#endif
|
||||
|
||||
// <o>Kernel Tick Frequency [Hz] <1-1000000>
|
||||
// <i> Defines base time unit for delays and timeouts.
|
||||
// <i> Default: 1000 (1ms tick)
|
||||
#ifndef OS_TICK_FREQ
|
||||
#define OS_TICK_FREQ 1000
|
||||
#endif
|
||||
|
||||
// <e>Round-Robin Thread switching
|
||||
// <i> Enables Round-Robin Thread switching.
|
||||
#ifndef OS_ROBIN_ENABLE
|
||||
#define OS_ROBIN_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o>Round-Robin Timeout <1-1000>
|
||||
// <i> Defines how many ticks a thread will execute before a thread switch.
|
||||
// <i> Default: 5
|
||||
#ifndef OS_ROBIN_TIMEOUT
|
||||
#define OS_ROBIN_TIMEOUT 5
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>ISR FIFO Queue
|
||||
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
|
||||
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
|
||||
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
|
||||
// <i> RTOS Functions called from ISR store requests to this buffer.
|
||||
// <i> Default: 16 entries
|
||||
#ifndef OS_ISR_FIFO_QUEUE
|
||||
#define OS_ISR_FIFO_QUEUE 16
|
||||
#endif
|
||||
|
||||
// <q>Object Memory usage counters
|
||||
// <i> Enables object memory usage counters (requires RTX source variant).
|
||||
#ifndef OS_OBJ_MEM_USAGE
|
||||
#define OS_OBJ_MEM_USAGE 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Thread Configuration
|
||||
// =======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_THREAD_OBJ_MEM
|
||||
#define OS_THREAD_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of user Threads <1-1000>
|
||||
// <i> Defines maximum number of user threads that can be active at the same time.
|
||||
// <i> Applies to user threads with system provided memory for control blocks.
|
||||
#ifndef OS_THREAD_NUM
|
||||
#define OS_THREAD_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Number of user Threads with default Stack size <0-1000>
|
||||
// <i> Defines maximum number of user threads with default stack size.
|
||||
// <i> Applies to user threads with zero stack size specified.
|
||||
#ifndef OS_THREAD_DEF_STACK_NUM
|
||||
#define OS_THREAD_DEF_STACK_NUM 0
|
||||
#endif
|
||||
|
||||
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
|
||||
// <i> Defines the combined stack size for user threads with user-provided stack size.
|
||||
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_THREAD_USER_STACK_SIZE
|
||||
#define OS_THREAD_USER_STACK_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
|
||||
// <i> Defines stack size for threads with zero stack size specified.
|
||||
// <i> Default: 256
|
||||
#ifndef OS_STACK_SIZE
|
||||
#define OS_STACK_SIZE 256
|
||||
#endif
|
||||
|
||||
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
|
||||
// <i> Defines stack size for Idle thread.
|
||||
// <i> Default: 256
|
||||
#ifndef OS_IDLE_THREAD_STACK_SIZE
|
||||
#define OS_IDLE_THREAD_STACK_SIZE 256
|
||||
#endif
|
||||
|
||||
// <o>Idle Thread TrustZone Module Identifier
|
||||
// <i> Defines TrustZone Thread Context Management Identifier.
|
||||
// <i> Applies only to cores with TrustZone technology.
|
||||
// <i> Default: 0 (not used)
|
||||
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
|
||||
#define OS_IDLE_THREAD_TZ_MOD_ID 0
|
||||
#endif
|
||||
|
||||
// <q>Stack overrun checking
|
||||
// <i> Enables stack overrun check at thread switch.
|
||||
// <i> Enabling this option increases slightly the execution time of a thread switch.
|
||||
#ifndef OS_STACK_CHECK
|
||||
#define OS_STACK_CHECK 1
|
||||
#endif
|
||||
|
||||
// <q>Stack usage watermark
|
||||
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
|
||||
// <i> Enabling this option increases significantly the execution time of thread creation.
|
||||
#ifndef OS_STACK_WATERMARK
|
||||
#define OS_STACK_WATERMARK 0
|
||||
#endif
|
||||
|
||||
// <o>Processor mode for Thread execution
|
||||
// <0=> Unprivileged mode
|
||||
// <1=> Privileged mode
|
||||
// <i> Default: Privileged mode
|
||||
#ifndef OS_PRIVILEGE_MODE
|
||||
#define OS_PRIVILEGE_MODE 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Timer Configuration
|
||||
// ======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_TIMER_OBJ_MEM
|
||||
#define OS_TIMER_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Timer objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_TIMER_NUM
|
||||
#define OS_TIMER_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>Timer Thread Priority
|
||||
// <8=> Low
|
||||
// <16=> Below Normal <24=> Normal <32=> Above Normal
|
||||
// <40=> High
|
||||
// <48=> Realtime
|
||||
// <i> Defines priority for timer thread
|
||||
// <i> Default: High
|
||||
#ifndef OS_TIMER_THREAD_PRIO
|
||||
#define OS_TIMER_THREAD_PRIO 40
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
|
||||
// <i> Defines stack size for Timer thread.
|
||||
// <i> May be set to 0 when timers are not used.
|
||||
// <i> Default: 256
|
||||
#ifndef OS_TIMER_THREAD_STACK_SIZE
|
||||
#define OS_TIMER_THREAD_STACK_SIZE 256
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread TrustZone Module Identifier
|
||||
// <i> Defines TrustZone Thread Context Management Identifier.
|
||||
// <i> Applies only to cores with TrustZone technology.
|
||||
// <i> Default: 0 (not used)
|
||||
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
|
||||
#define OS_TIMER_THREAD_TZ_MOD_ID 0
|
||||
#endif
|
||||
|
||||
// <o>Timer Callback Queue entries <0-256>
|
||||
// <i> Number of concurrent active timer callback functions.
|
||||
// <i> May be set to 0 when timers are not used.
|
||||
// <i> Default: 4
|
||||
#ifndef OS_TIMER_CB_QUEUE
|
||||
#define OS_TIMER_CB_QUEUE 4
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Event Flags Configuration
|
||||
// ============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_EVFLAGS_OBJ_MEM
|
||||
#define OS_EVFLAGS_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Event Flags objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_EVFLAGS_NUM
|
||||
#define OS_EVFLAGS_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Mutex Configuration
|
||||
// ======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MUTEX_OBJ_MEM
|
||||
#define OS_MUTEX_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Mutex objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MUTEX_NUM
|
||||
#define OS_MUTEX_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Semaphore Configuration
|
||||
// ==========================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_SEMAPHORE_OBJ_MEM
|
||||
#define OS_SEMAPHORE_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Semaphore objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_SEMAPHORE_NUM
|
||||
#define OS_SEMAPHORE_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Memory Pool Configuration
|
||||
// ============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MEMPOOL_OBJ_MEM
|
||||
#define OS_MEMPOOL_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Memory Pool objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MEMPOOL_NUM
|
||||
#define OS_MEMPOOL_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined data storage memory size.
|
||||
// <i> Applies to objects with system provided memory for data storage.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_MEMPOOL_DATA_SIZE
|
||||
#define OS_MEMPOOL_DATA_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Message Queue Configuration
|
||||
// ==============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MSGQUEUE_OBJ_MEM
|
||||
#define OS_MSGQUEUE_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Message Queue objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MSGQUEUE_NUM
|
||||
#define OS_MSGQUEUE_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined data storage memory size.
|
||||
// <i> Applies to objects with system provided memory for data storage.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_MSGQUEUE_DATA_SIZE
|
||||
#define OS_MSGQUEUE_DATA_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Event Recorder Configuration
|
||||
// ===============================
|
||||
|
||||
// <e>Global Initialization
|
||||
// <i> Initialize Event Recorder during 'osKernelInitialize'.
|
||||
#ifndef OS_EVR_INIT
|
||||
#define OS_EVR_INIT 0
|
||||
#endif
|
||||
|
||||
// <q>Start recording
|
||||
// <i> Start event recording after initialization.
|
||||
#ifndef OS_EVR_START
|
||||
#define OS_EVR_START 1
|
||||
#endif
|
||||
|
||||
// <h>Global Event Filter Setup
|
||||
// <i> Initial recording level applied to all components.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_LEVEL
|
||||
#define OS_EVR_LEVEL 0x00U
|
||||
#endif
|
||||
|
||||
// <h>RTOS Event Filter Setup
|
||||
// <i> Recording levels for RTX components.
|
||||
// <i> Only applicable if events for the respective component are generated.
|
||||
|
||||
// <h>Memory Management
|
||||
// <i> Recording level for Memory Management events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_MEMORY_LEVEL
|
||||
#define OS_EVR_MEMORY_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Kernel
|
||||
// <i> Recording level for Kernel events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_KERNEL_LEVEL
|
||||
#define OS_EVR_KERNEL_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Thread
|
||||
// <i> Recording level for Thread events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_THREAD_LEVEL
|
||||
#define OS_EVR_THREAD_LEVEL 0x05U
|
||||
#endif
|
||||
|
||||
// <h>Generic Wait
|
||||
// <i> Recording level for Generic Wait events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_WAIT_LEVEL
|
||||
#define OS_EVR_WAIT_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Thread Flags
|
||||
// <i> Recording level for Thread Flags events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_THFLAGS_LEVEL
|
||||
#define OS_EVR_THFLAGS_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Event Flags
|
||||
// <i> Recording level for Event Flags events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_EVFLAGS_LEVEL
|
||||
#define OS_EVR_EVFLAGS_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Timer
|
||||
// <i> Recording level for Timer events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_TIMER_LEVEL
|
||||
#define OS_EVR_TIMER_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Mutex
|
||||
// <i> Recording level for Mutex events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_MUTEX_LEVEL
|
||||
#define OS_EVR_MUTEX_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Semaphore
|
||||
// <i> Recording level for Semaphore events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_SEMAPHORE_LEVEL
|
||||
#define OS_EVR_SEMAPHORE_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Memory Pool
|
||||
// <i> Recording level for Memory Pool events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_MEMPOOL_LEVEL
|
||||
#define OS_EVR_MEMPOOL_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Message Queue
|
||||
// <i> Recording level for Message Queue events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_MSGQUEUE_LEVEL
|
||||
#define OS_EVR_MSGQUEUE_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <h>RTOS Event Generation
|
||||
// <i> Enables event generation for RTX components (requires RTX source variant).
|
||||
|
||||
// <q>Memory Management
|
||||
// <i> Enables Memory Management event generation.
|
||||
#ifndef OS_EVR_MEMORY
|
||||
#define OS_EVR_MEMORY 1
|
||||
#endif
|
||||
|
||||
// <q>Kernel
|
||||
// <i> Enables Kernel event generation.
|
||||
#ifndef OS_EVR_KERNEL
|
||||
#define OS_EVR_KERNEL 1
|
||||
#endif
|
||||
|
||||
// <q>Thread
|
||||
// <i> Enables Thread event generation.
|
||||
#ifndef OS_EVR_THREAD
|
||||
#define OS_EVR_THREAD 1
|
||||
#endif
|
||||
|
||||
// <q>Generic Wait
|
||||
// <i> Enables Generic Wait event generation.
|
||||
#ifndef OS_EVR_WAIT
|
||||
#define OS_EVR_WAIT 1
|
||||
#endif
|
||||
|
||||
// <q>Thread Flags
|
||||
// <i> Enables Thread Flags event generation.
|
||||
#ifndef OS_EVR_THFLAGS
|
||||
#define OS_EVR_THFLAGS 1
|
||||
#endif
|
||||
|
||||
// <q>Event Flags
|
||||
// <i> Enables Event Flags event generation.
|
||||
#ifndef OS_EVR_EVFLAGS
|
||||
#define OS_EVR_EVFLAGS 1
|
||||
#endif
|
||||
|
||||
// <q>Timer
|
||||
// <i> Enables Timer event generation.
|
||||
#ifndef OS_EVR_TIMER
|
||||
#define OS_EVR_TIMER 1
|
||||
#endif
|
||||
|
||||
// <q>Mutex
|
||||
// <i> Enables Mutex event generation.
|
||||
#ifndef OS_EVR_MUTEX
|
||||
#define OS_EVR_MUTEX 1
|
||||
#endif
|
||||
|
||||
// <q>Semaphore
|
||||
// <i> Enables Semaphore event generation.
|
||||
#ifndef OS_EVR_SEMAPHORE
|
||||
#define OS_EVR_SEMAPHORE 1
|
||||
#endif
|
||||
|
||||
// <q>Memory Pool
|
||||
// <i> Enables Memory Pool event generation.
|
||||
#ifndef OS_EVR_MEMPOOL
|
||||
#define OS_EVR_MEMPOOL 1
|
||||
#endif
|
||||
|
||||
// <q>Message Queue
|
||||
// <i> Enables Message Queue event generation.
|
||||
#ifndef OS_EVR_MSGQUEUE
|
||||
#define OS_EVR_MSGQUEUE 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </h>
|
||||
|
||||
// Number of Threads which use standard C/C++ library libspace
|
||||
// (when thread specific memory allocation is not used).
|
||||
#if (OS_THREAD_OBJ_MEM == 0)
|
||||
#define OS_THREAD_LIBSPACE_NUM 4
|
||||
#else
|
||||
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
|
||||
#endif
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
|
||||
#endif // RTX_CONFIG_H_
|
||||
@@ -1,74 +0,0 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
|
||||
; command above MUST be in first line (no comment above!)
|
||||
|
||||
/*
|
||||
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Flash Configuration ----------------------------------
|
||||
; <h> Flash Configuration
|
||||
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __ROM_BASE 0x00200000
|
||||
#define __ROM_SIZE 0x00200000
|
||||
|
||||
/*--------------------- Embedded RAM Configuration ---------------------------
|
||||
; <h> RAM Configuration
|
||||
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_BASE 0x20200000
|
||||
#define __RAM_SIZE 0x00020000
|
||||
|
||||
/*--------------------- Stack / Heap Configuration ---------------------------
|
||||
; <h> Stack / Heap Configuration
|
||||
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_SIZE 0x00000400
|
||||
#define __HEAP_SIZE 0x00000C00
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
User Stack & Heap boundery definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
|
||||
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Scatter File Definitions definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RO_BASE __ROM_BASE
|
||||
#define __RO_SIZE __ROM_SIZE
|
||||
|
||||
#define __RW_BASE (__RAM_BASE )
|
||||
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
|
||||
|
||||
|
||||
|
||||
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
|
||||
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
; *(Veneer$$CMSE) ; uncomment for secure applications
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
RW_RAM __RW_BASE __RW_SIZE { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
#if __HEAP_SIZE > 0
|
||||
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
|
||||
}
|
||||
#endif
|
||||
|
||||
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,138 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCM33.c
|
||||
* @brief CMSIS Core Device Startup File for Cortex-M33 Device
|
||||
* @version V2.0.0
|
||||
* @date 20. May 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM33)
|
||||
#include "ARMCM33.h"
|
||||
#elif defined (ARMCM33_TZ)
|
||||
#include "ARMCM33_TZ.h"
|
||||
#elif defined (ARMCM33_DSP_FP)
|
||||
#include "ARMCM33_DSP_FP.h"
|
||||
#elif defined (ARMCM33_DSP_FP_TZ)
|
||||
#include "ARMCM33_DSP_FP_TZ.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler Function Prototype
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef void( *pFunc )( void );
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __INITIAL_SP;
|
||||
extern uint32_t __STACK_LIMIT;
|
||||
|
||||
extern void __PROGRAM_START(void) __NO_RETURN;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void) __NO_RETURN;
|
||||
void Reset_Handler (void) __NO_RETURN;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const pFunc __VECTOR_TABLE[496];
|
||||
const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
Reset_Handler, /* Reset Handler */
|
||||
NMI_Handler, /* -14 NMI Handler */
|
||||
HardFault_Handler, /* -13 Hard Fault Handler */
|
||||
MemManage_Handler, /* -12 MPU Fault Handler */
|
||||
BusFault_Handler, /* -11 Bus Fault Handler */
|
||||
UsageFault_Handler, /* -10 Usage Fault Handler */
|
||||
SecureFault_Handler, /* -9 Secure Fault Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
SVC_Handler, /* -5 SVCall Handler */
|
||||
DebugMon_Handler, /* -4 Debug Monitor Handler */
|
||||
0, /* Reserved */
|
||||
PendSV_Handler, /* -2 PendSV Handler */
|
||||
SysTick_Handler, /* -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
Interrupt0_Handler, /* 0 Interrupt 0 */
|
||||
Interrupt1_Handler, /* 1 Interrupt 1 */
|
||||
Interrupt2_Handler, /* 2 Interrupt 2 */
|
||||
Interrupt3_Handler, /* 3 Interrupt 3 */
|
||||
Interrupt4_Handler, /* 4 Interrupt 4 */
|
||||
Interrupt5_Handler, /* 5 Interrupt 5 */
|
||||
Interrupt6_Handler, /* 6 Interrupt 6 */
|
||||
Interrupt7_Handler, /* 7 Interrupt 7 */
|
||||
Interrupt8_Handler, /* 8 Interrupt 8 */
|
||||
Interrupt9_Handler /* 9 Interrupt 9 */
|
||||
/* Interrupts 10 .. 480 are left out */
|
||||
};
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
|
||||
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
@@ -1,99 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM33.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM33 Device
|
||||
* @version V5.3.1
|
||||
* @date 09. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM33)
|
||||
#include "ARMCM33.h"
|
||||
#elif defined (ARMCM33_TZ)
|
||||
#include "ARMCM33_TZ.h"
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#include "partition_ARMCM33.h"
|
||||
#endif
|
||||
#elif defined (ARMCM33_DSP_FP)
|
||||
#include "ARMCM33_DSP_FP.h"
|
||||
#elif defined (ARMCM33_DSP_FP_TZ)
|
||||
#include "ARMCM33_DSP_FP_TZ.h"
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#include "partition_ARMCM33.h"
|
||||
#endif
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (50000000UL) /* Oscillator frequency */
|
||||
|
||||
#define SYSTEM_CLOCK (XTAL / 2U)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Externals
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
extern uint32_t __Vectors;
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System initialization function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
SCB->VTOR = (uint32_t) &__Vectors;
|
||||
#endif
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
|
||||
(3U << 11U*2U) ); /* enable CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
TZ_SAU_Setup();
|
||||
#endif
|
||||
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
@@ -1,21 +0,0 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'demo_threadx_non-secure_zone'
|
||||
* Target: 'FVP Simulation Model'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -1,21 +0,0 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'ThreadX_Library'
|
||||
* Target: 'ThreadX_Library_Project'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -1,305 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>ThreadX_Demo</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>1</RunSim>
|
||||
<RunTarget>0</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
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<LComments>1</LComments>
|
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<LGenerateSymbols>1</LGenerateSymbols>
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|
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|
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<LLocSym>1</LLocSym>
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<LPubSym>1</LPubSym>
|
||||
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|
||||
<LExpSel>0</LExpSel>
|
||||
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|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>1</uSim>
|
||||
<uTrg>0</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>0</sGomain>
|
||||
<sRbreak>1</sRbreak>
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||||
<sRwatch>1</sRwatch>
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||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
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||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>0</tGomain>
|
||||
<tRbreak>1</tRbreak>
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||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>0</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>-1</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon></pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGDARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name>-T5F</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>-UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
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||||
<Breakpoint/>
|
||||
<WatchWindow1>
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||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_0_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>1</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_1_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>2</count>
|
||||
<WinNumber>1</WinNumber>
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||||
<ItemText>thread_2_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>3</count>
|
||||
<WinNumber>1</WinNumber>
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||||
<ItemText>thread_3_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>4</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_4_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>5</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_5_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>6</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>_tx_thread_current_ptr</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
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||||
<trace>0</trace>
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||||
<periodic>0</periodic>
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||||
<aLwin>1</aLwin>
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||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
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||||
<AscS2>0</AscS2>
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||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
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||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source Group</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\tx_initialize_low_level.s</PathWithFileName>
|
||||
<FilenameWithoutPath>tx_initialize_low_level.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
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<GroupNumber>1</GroupNumber>
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<FileNumber>2</FileNumber>
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<FileType>1</FileType>
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||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\demo_threadx.c</PathWithFileName>
|
||||
<FilenameWithoutPath>demo_threadx.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
<WindowPosition>
|
||||
<length>44</length>
|
||||
<flags>0</flags>
|
||||
<showCmd>1</showCmd>
|
||||
<MinPosition>
|
||||
<xPos>-1</xPos>
|
||||
<yPos>-1</yPos>
|
||||
</MinPosition>
|
||||
<MaxPosition>
|
||||
<xPos>-1</xPos>
|
||||
<yPos>-1</yPos>
|
||||
</MaxPosition>
|
||||
<NormalPosition>
|
||||
<Top>56</Top>
|
||||
<Left>12</Left>
|
||||
<Right>1633</Right>
|
||||
<Bottom>671</Bottom>
|
||||
</NormalPosition>
|
||||
</WindowPosition>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Library_Group</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
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<RteFlg>0</RteFlg>
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<File>
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<GroupNumber>2</GroupNumber>
|
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<FileNumber>3</FileNumber>
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<FileType>4</FileType>
|
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<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\ThreadX_Library.lib</PathWithFileName>
|
||||
<FilenameWithoutPath>ThreadX_Library.lib</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -1,556 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||
|
||||
<SchemaVersion>1.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>ThreadX_Demo</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>Cortex-M4 FPU</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll></FlashDriverDll>
|
||||
<DeviceId>5237</DeviceId>
|
||||
<RegisterFile></RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile></SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath>Luminary\</RegisterFilePath>
|
||||
<DBRegisterFilePath>Luminary\</DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\</OutputDirectory>
|
||||
<OutputName>threadx_demo</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
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<UserProg1Name></UserProg1Name>
|
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<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4F</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4F</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>1</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>0</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>0</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>0</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>0</RestoreTracepoints>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>-1</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver></Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>0</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>0</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>0</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>0</RoSelD>
|
||||
<RwSelD>0</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>0</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--first __tx_vectors --entry=__main</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source Group</GroupName>
|
||||
<GroupOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>1</RVCTCodeConst>
|
||||
<RVCTZI>1</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>2</IncludeInBuild>
|
||||
<AlwaysBuild>2</AlwaysBuild>
|
||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>0</ComprImg>
|
||||
</CommonProperty>
|
||||
<GroupArmAds>
|
||||
<Cads>
|
||||
<interw>0</interw>
|
||||
<Optim>0</Optim>
|
||||
<oTime>2</oTime>
|
||||
<SplitLS>2</SplitLS>
|
||||
<OneElfS>2</OneElfS>
|
||||
<Strict>2</Strict>
|
||||
<EnumInt>2</EnumInt>
|
||||
<PlainCh>2</PlainCh>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>2</uThumb>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<uC99>2</uC99>
|
||||
<uGnu>2</uGnu>
|
||||
<useXO>2</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>2</vShortEn>
|
||||
<vShortWch>2</vShortWch>
|
||||
<v6Lto>2</v6Lto>
|
||||
<v6WtE>2</v6WtE>
|
||||
<v6Rtti>2</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>2</interw>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<thumb>2</thumb>
|
||||
<SplitLS>2</SplitLS>
|
||||
<SwStkChk>2</SwStkChk>
|
||||
<NoWarn>2</NoWarn>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<useXO>2</useXO>
|
||||
<uClangAs>2</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
</GroupArmAds>
|
||||
</GroupOption>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tx_initialize_low_level.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\tx_initialize_low_level.s</FilePath>
|
||||
<FileOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>2</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>2</IncludeInBuild>
|
||||
<AlwaysBuild>2</AlwaysBuild>
|
||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<FileArmAds>
|
||||
<Aads>
|
||||
<interw>2</interw>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<thumb>1</thumb>
|
||||
<SplitLS>2</SplitLS>
|
||||
<SwStkChk>2</SwStkChk>
|
||||
<NoWarn>2</NoWarn>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<useXO>2</useXO>
|
||||
<uClangAs>2</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>demo_threadx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\demo_threadx.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Library_Group</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>ThreadX_Library.lib</FileName>
|
||||
<FileType>4</FileType>
|
||||
<FilePath>.\ThreadX_Library.lib</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
@@ -1,400 +0,0 @@
|
||||
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
|
||||
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
|
||||
byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete
|
||||
description of this demonstration. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "..\demo_secure_zone\interface.h" /* Interface to sample secure functions. */
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
#define DEMO_BYTE_POOL_SIZE 9120
|
||||
#define DEMO_BLOCK_POOL_SIZE 100
|
||||
#define DEMO_QUEUE_SIZE 100
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
static TX_THREAD thread_0;
|
||||
static TX_THREAD thread_1;
|
||||
static TX_THREAD thread_2;
|
||||
static TX_THREAD thread_3;
|
||||
static TX_THREAD thread_4;
|
||||
static TX_THREAD thread_5;
|
||||
static TX_THREAD thread_6;
|
||||
static TX_THREAD thread_7;
|
||||
static TX_QUEUE queue_0;
|
||||
static TX_SEMAPHORE semaphore_0;
|
||||
static TX_MUTEX mutex_0;
|
||||
static TX_EVENT_FLAGS_GROUP event_flags_0;
|
||||
static TX_BYTE_POOL byte_pool_0;
|
||||
static TX_BLOCK_POOL block_pool_0;
|
||||
|
||||
/* Define byte pool memory. */
|
||||
|
||||
static UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE];
|
||||
|
||||
|
||||
/* Define event buffer. */
|
||||
|
||||
#ifdef TX_ENABLE_EVENT_TRACE
|
||||
UCHAR trace_buffer[0x10000];
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the counters used in the demo application... */
|
||||
|
||||
static ULONG thread_0_counter;
|
||||
static ULONG thread_1_counter;
|
||||
static ULONG thread_1_messages_sent;
|
||||
static ULONG thread_2_counter;
|
||||
static ULONG thread_2_messages_received;
|
||||
static ULONG thread_3_counter;
|
||||
static ULONG thread_4_counter;
|
||||
static ULONG thread_5_counter;
|
||||
static ULONG thread_6_counter;
|
||||
static ULONG thread_7_counter;
|
||||
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input);
|
||||
void thread_1_entry(ULONG thread_input);
|
||||
void thread_2_entry(ULONG thread_input);
|
||||
void thread_3_and_4_entry(ULONG thread_input);
|
||||
void thread_5_entry(ULONG thread_input);
|
||||
void thread_6_and_7_entry(ULONG thread_input);
|
||||
|
||||
/* Define main entry point. */
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
/* Please refer to Chapter 6 of the ThreadX User Guide for a complete
|
||||
description of this demonstration. */
|
||||
|
||||
|
||||
/* Enter the ThreadX kernel. */
|
||||
tx_kernel_enter();
|
||||
}
|
||||
|
||||
|
||||
/* Define what the initial system looks like. */
|
||||
|
||||
void tx_application_define(void *first_unused_memory)
|
||||
{
|
||||
|
||||
CHAR *pointer;
|
||||
|
||||
(VOID)first_unused_memory; /* unused parameter. */
|
||||
|
||||
#ifdef TX_ENABLE_EVENT_TRACE
|
||||
tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32);
|
||||
#endif
|
||||
|
||||
/* Create a byte memory pool from which to allocate the thread stacks. */
|
||||
tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE);
|
||||
|
||||
/* Put system definition stuff in here, e.g. thread creates and other assorted
|
||||
create information. */
|
||||
|
||||
/* Allocate the stack for thread 0. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create the main thread. */
|
||||
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 1. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 1 and 2. These threads pass information through a ThreadX
|
||||
message queue. It is also interesting to note that these threads have a time
|
||||
slice. */
|
||||
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 2. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 3. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
|
||||
An interesting thing here is that both threads share the same instruction area. */
|
||||
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 4. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 5. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create thread 5. This thread simply pends on an event flag which will be set
|
||||
by thread_0. */
|
||||
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 6. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
|
||||
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 7. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the message queue. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
|
||||
|
||||
/* Create the message queue shared by threads 1 and 2. */
|
||||
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
|
||||
|
||||
/* Create the semaphore used by threads 3 and 4. */
|
||||
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
|
||||
|
||||
/* Create the event flags group used by threads 1 and 5. */
|
||||
tx_event_flags_create(&event_flags_0, "event flags 0");
|
||||
|
||||
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
|
||||
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
|
||||
|
||||
/* Allocate the memory for a small block pool. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create a block memory pool to allocate a message buffer from. */
|
||||
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
|
||||
|
||||
/* Allocate a block and release the block memory. */
|
||||
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
|
||||
|
||||
/* Release the block back to the pool. */
|
||||
tx_block_release(pointer);
|
||||
|
||||
tx_thread_secure_stack_allocate(&thread_0,256);
|
||||
tx_thread_secure_stack_allocate(&thread_1,256);
|
||||
tx_thread_secure_stack_allocate(&thread_2,256);
|
||||
tx_thread_secure_stack_allocate(&thread_3,256);
|
||||
tx_thread_secure_stack_allocate(&thread_4,256);
|
||||
tx_thread_secure_stack_allocate(&thread_5,256);
|
||||
tx_thread_secure_stack_allocate(&thread_6,256);
|
||||
tx_thread_secure_stack_allocate(&thread_7,256);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input)
|
||||
{
|
||||
UINT status;
|
||||
|
||||
(VOID)thread_input; /* unused parameter. */
|
||||
|
||||
/* This thread simply sits in while-forever-sleep loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_0_counter++;
|
||||
|
||||
/* Sleep for 10 ticks. */
|
||||
tx_thread_sleep(10);
|
||||
|
||||
/* Set event flag 0 to wakeup thread 5. */
|
||||
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_1_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
(VOID)thread_input; /* unused parameter. */
|
||||
|
||||
/* This thread simply sends messages to a queue shared by thread 2. */
|
||||
while(1)
|
||||
{
|
||||
/* Increment the thread counter. */
|
||||
thread_1_counter++;
|
||||
|
||||
/* Send message to queue 0. */
|
||||
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Increment the message sent. */
|
||||
thread_1_messages_sent++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_2_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
ULONG received_message;
|
||||
UINT status;
|
||||
|
||||
(VOID)thread_input; /* unused parameter. */
|
||||
|
||||
/* This thread retrieves messages placed on the queue by thread 1. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_2_counter++;
|
||||
|
||||
/* Retrieve a message from the queue. */
|
||||
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status and make sure the message is what we
|
||||
expected. */
|
||||
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
|
||||
break;
|
||||
|
||||
/* Otherwise, all is okay. Increment the received message count. */
|
||||
thread_2_messages_received++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_3_and_4_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
/* This function is executed from thread 3 and thread 4. As the loop
|
||||
below shows, these function compete for ownership of semaphore_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 3)
|
||||
thread_3_counter++;
|
||||
else
|
||||
thread_4_counter++;
|
||||
|
||||
/* Get the semaphore with suspension. */
|
||||
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the semaphore. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the semaphore. */
|
||||
status = tx_semaphore_put(&semaphore_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_5_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
ULONG actual_flags;
|
||||
|
||||
(VOID)thread_input; /* unused parameter. */
|
||||
|
||||
/* This thread simply waits for an event in a forever loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_5_counter++;
|
||||
|
||||
/* Wait for event flag 0. */
|
||||
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
|
||||
&actual_flags, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_6_and_7_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 6 and thread 7. As the loop
|
||||
below shows, these function compete for ownership of mutex_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 6)
|
||||
thread_6_counter++;
|
||||
else
|
||||
thread_7_counter++;
|
||||
|
||||
/* Get the mutex with suspension. */
|
||||
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Get the mutex again with suspension. This shows
|
||||
that an owning thread may retrieve the mutex it
|
||||
owns multiple times. */
|
||||
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the mutex. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the mutex. */
|
||||
status = tx_mutex_put(&mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Release the mutex again. This will actually
|
||||
release ownership since it was obtained twice. */
|
||||
status = tx_mutex_put(&mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -1,359 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>0</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>15</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>..\Debug.ini</tIfile>
|
||||
<pMon>BIN\DbgFMv8M.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>PWSTATINFO</Key>
|
||||
<Name>200,50,700</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(6010=636,564,1113,1160,0)(6018=1284,352,1473,701,0)(6019=1328,34,1517,370,0)(6008=-1,-1,-1,-1,0)(6009=1290,960,1584,1146,0)(6014=1111,129,1369,860,0)(6015=872,146,1130,768,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=150,186,829,544,0)(106=511,345,1277,659,0)(107=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DbgFMv8M</Key>
|
||||
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -MA</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2V8M</Key>
|
||||
<Name>UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>251</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>2111470</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename><3>.\tx_initialize_low_level.S</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\demo_threadx_non_secure_zone\tx_initialize_low_level.S\251</Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<WatchWindow1>
|
||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_0_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>1</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_1_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>2</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_2_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>3</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_3_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>4</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_4_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>5</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_5_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>6</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_6_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>7</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_7_counter</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<MemoryWindow1>
|
||||
<Mm>
|
||||
<WinNumber>1</WinNumber>
|
||||
<SubType>2</SubType>
|
||||
<ItemText>0x2001ffd8</ItemText>
|
||||
<AccSizeX>0</AccSizeX>
|
||||
</Mm>
|
||||
</MemoryWindow1>
|
||||
<MemoryWindow2>
|
||||
<Mm>
|
||||
<WinNumber>2</WinNumber>
|
||||
<SubType>2</SubType>
|
||||
<ItemText>0xE000ED28</ItemText>
|
||||
<AccSizeX>0</AccSizeX>
|
||||
</Mm>
|
||||
</MemoryWindow2>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>1</Protocol>
|
||||
<DbgClock>10000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Non-secure Code</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\demo_threadx.c</PathWithFileName>
|
||||
<FilenameWithoutPath>demo_threadx.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>4</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\ThreadX_Library.lib</PathWithFileName>
|
||||
<FilenameWithoutPath>ThreadX_Library.lib</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>CMSE Library</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\demo_secure_zone\interface.h</PathWithFileName>
|
||||
<FilenameWithoutPath>interface.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>3</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</PathWithFileName>
|
||||
<FilenameWithoutPath>demo_secure_zone_CMSE_Lib.o</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -1,585 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>ARMCM33_DSP_FP_TZ</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<PackID>ARM.CMSIS.5.7.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>demo_threadx_non-secure_zone</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>1</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName></SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll></SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMV8M.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>0</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M33"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>16</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>4</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>1</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>1</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x200000</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>2</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls>-Wno-unused-function -Wno-visibility</MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\..\..\..\common\inc, ..\..\inc</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>13</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_AC6.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Non-secure Code</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>demo_threadx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\demo_threadx.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ThreadX_Library.lib</FileName>
|
||||
<FileType>4</FileType>
|
||||
<FilePath>..\ThreadX_Library.lib</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSE Library</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>interface.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\demo_secure_zone\interface.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>demo_secure_zone_CMSE_Lib.o</FileName>
|
||||
<FileType>3</FileType>
|
||||
<FilePath>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis>
|
||||
<api Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
</apis>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.0" condition="ARMCM33 CMSIS">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
|
||||
<instance index="0" removed="1">RTE\CMSIS\RTX_Config.c</instance>
|
||||
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 NS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
|
||||
<instance index="0" removed="1">RTE\CMSIS\RTX_Config.h</instance>
|
||||
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 NS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.1">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_TZ\partition_ARMCM33.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_TZ\startup_ARMCM33.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_TZ\system_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="Device\ARM\ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMv8MBL\partition_ARMv8MBL.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMv8MBL\Source\ARM\startup_ARMv8MBL.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMv8MBL\startup_ARMv8MBL.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMv8MBL\Source\system_ARMv8MBL.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMv8MBL\system_ARMv8MBL.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="CMSIS\Config\RTE_Device.h" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
|
||||
<package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="Device\CMSDK_ARMv8MBL\Include\Template\partition_CMSDK_ARMv8MBL.h" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
|
||||
<package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" condition="ARMCC" name="Device\CMSDK_ARMv8MBL\Source\ARM\startup_CMSDK_ARMv8MBL.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
|
||||
<package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Device\CMSDK_ARMv8MBL\Source\system_CMSDK_ARMv8MBL.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
|
||||
<package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayDesc></LayDesc>
|
||||
<LayUrl></LayUrl>
|
||||
<LayKeys></LayKeys>
|
||||
<LayCat></LayCat>
|
||||
<LayLic></LayLic>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
@@ -1,284 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Initialize */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_system_stack_ptr
|
||||
IMPORT _tx_initialize_unused_memory
|
||||
IMPORT _tx_thread_context_save
|
||||
IMPORT _tx_thread_context_restore
|
||||
IMPORT _tx_timer_interrupt
|
||||
IMPORT __main
|
||||
IMPORT |Image$$RW_RAM$$ZI$$Limit|
|
||||
IMPORT __Vectors
|
||||
IMPORT SystemInit
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_stack_error_handler
|
||||
;
|
||||
;
|
||||
SYSTEM_CLOCK EQU 6000000
|
||||
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
|
||||
;
|
||||
;
|
||||
;/* Setup the stack and heap areas. */
|
||||
;
|
||||
STACK_SIZE EQU 0x00000400
|
||||
HEAP_SIZE EQU 0x00000000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
StackMem
|
||||
SPACE STACK_SIZE
|
||||
__initial_sp
|
||||
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
HeapMem
|
||||
SPACE HEAP_SIZE
|
||||
__heap_limit
|
||||
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_initialize_low_level Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for any low-level processor */
|
||||
;/* initialization, including setting up interrupt vectors, setting */
|
||||
;/* up a periodic timer interrupt source, saving the system stack */
|
||||
;/* pointer for use in ISR processing later, and finding the first */
|
||||
;/* available RAM memory address for tx_application_define. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_initialize_low_level(VOID)
|
||||
;{
|
||||
EXPORT _tx_initialize_low_level
|
||||
_tx_initialize_low_level FUNCTION
|
||||
;
|
||||
; /* Disable interrupts during ThreadX initialization. */
|
||||
;
|
||||
CPSID i
|
||||
;
|
||||
; /* Set base of available memory to end of non-initialised RAM area. */
|
||||
;
|
||||
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
|
||||
LDR r1, =|Image$$RW_RAM$$ZI$$Limit| ; Build first free address
|
||||
ADD r1, r1, #4 ;
|
||||
STR r1, [r0] ; Setup first unused memory pointer
|
||||
;
|
||||
; /* Setup Vector Table Offset Register. */
|
||||
;
|
||||
MOV r0, #0xE000E000 ; Build address of NVIC registers
|
||||
LDR r1, =__Vectors ; Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] ; Set vector table address
|
||||
;
|
||||
; /* Enable the cycle count register. */
|
||||
;
|
||||
; LDR r0, =0xE0001000 ; Build address of DWT register
|
||||
; LDR r1, [r0] ; Pickup the current value
|
||||
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
|
||||
; STR r1, [r0] ; Enable the cycle count register
|
||||
;
|
||||
; /* Set system stack pointer from vector value. */
|
||||
;
|
||||
LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
|
||||
LDR r1, =__Vectors ; Pickup address of vector table
|
||||
LDR r1, [r1] ; Pickup reset stack pointer
|
||||
STR r1, [r0] ; Save system stack pointer
|
||||
;
|
||||
; /* Configure SysTick. */
|
||||
;
|
||||
MOV r0, #0xE000E000 ; Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] ; Setup SysTick Reload Value
|
||||
MOV r1, #0x7 ; Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] ; Setup SysTick Control
|
||||
;
|
||||
; /* Configure handler priorities. */
|
||||
;
|
||||
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers
|
||||
; Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers
|
||||
; Note: PnSV must be lowest priority, which is 0xFF
|
||||
;
|
||||
; /* Return to caller. */
|
||||
;
|
||||
BX lr
|
||||
ENDFUNC
|
||||
;}
|
||||
;
|
||||
;
|
||||
;/* Define initial heap/stack routine for the ARM startup code.
|
||||
; This routine will set the initial stack and heap locations. */
|
||||
;
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap FUNCTION
|
||||
LDR r0, =HeapMem
|
||||
LDR r1, =(StackMem + STACK_SIZE)
|
||||
LDR r2, =(HeapMem + HEAP_SIZE)
|
||||
LDR r3, =StackMem
|
||||
BX lr
|
||||
ENDFUNC
|
||||
;
|
||||
;
|
||||
;/* Define shells for each of the unused vectors. */
|
||||
;
|
||||
EXPORT __tx_BadHandler
|
||||
__tx_BadHandler FUNCTION
|
||||
B __tx_BadHandler
|
||||
ENDFUNC
|
||||
|
||||
EXPORT __tx_IntHandler
|
||||
__tx_IntHandler FUNCTION
|
||||
; VOID InterruptHandler (VOID)
|
||||
; {
|
||||
PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment)
|
||||
|
||||
; /* Do interrupt handler work here */
|
||||
; /* .... */
|
||||
|
||||
POP {r0, lr}
|
||||
BX lr
|
||||
; }
|
||||
ENDFUNC
|
||||
|
||||
|
||||
EXPORT __tx_SysTickHandler
|
||||
EXPORT SysTick_Handler
|
||||
SysTick_Handler FUNCTION
|
||||
__tx_SysTickHandler
|
||||
; VOID TimerInterruptHandler (VOID)
|
||||
; {
|
||||
;
|
||||
PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment)
|
||||
BL _tx_timer_interrupt
|
||||
POP {r0, lr}
|
||||
BX lr
|
||||
; }
|
||||
ENDFUNC
|
||||
|
||||
|
||||
EXPORT HardFault_Handler
|
||||
HardFault_Handler FUNCTION
|
||||
B HardFault_Handler
|
||||
ENDFUNC
|
||||
|
||||
|
||||
EXPORT UsageFault_Handler
|
||||
UsageFault_Handler FUNCTION
|
||||
CPSID i ; Disable interrupts
|
||||
; Check for stack limit fault
|
||||
LDR r0, =0xE000ED28 ; CFSR address
|
||||
LDR r1,[r0] ; Pick up CFSR
|
||||
TST r1, #0x00100000 ; Check for Stack Overflow
|
||||
_unhandled_usage_loop
|
||||
BEQ _unhandled_usage_loop ; If not stack overflow then loop
|
||||
|
||||
; Handle stack overflow
|
||||
STR r1, [r0] ; Clear CFSR flag(s)
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address
|
||||
LDR r1, [r0] ; Load FPCCR
|
||||
BIC r1, r1, #1 ; Clear the lazy preservation active bit
|
||||
STR r1, [r0] ; Store the value
|
||||
ENDIF
|
||||
|
||||
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r0,[r0] ; Pick up current thread pointer
|
||||
PUSH {r0,lr} ; Save LR (and r0 to maintain stack alignment)
|
||||
BL _tx_thread_stack_error_handler ; Call ThreadX/user handler
|
||||
POP {r0,lr} ; Restore LR and dummy reg
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
; Call the thread exit function to indicate the thread is no longer executing.
|
||||
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
POP {r0, lr} ; Recover LR
|
||||
ENDIF
|
||||
|
||||
MOV r1, #0 ; Build NULL value
|
||||
LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer
|
||||
STR r1, [r0] ; Clear current thread pointer
|
||||
|
||||
; Return from UsageFault_Handler exception
|
||||
LDR r0, =0xE000ED04 ; Load ICSR
|
||||
LDR r1, =0x10000000 ; Set PENDSVSET bit
|
||||
STR r1, [r0] ; Store ICSR
|
||||
DSB ; Wait for memory access to complete
|
||||
CPSIE i ; Enable interrupts
|
||||
BX lr ; Return from exception
|
||||
ENDFUNC
|
||||
|
||||
|
||||
|
||||
EXPORT __tx_NMIHandler
|
||||
__tx_NMIHandler FUNCTION
|
||||
B __tx_NMIHandler
|
||||
ENDFUNC
|
||||
|
||||
|
||||
EXPORT __tx_DBGHandler
|
||||
__tx_DBGHandler FUNCTION
|
||||
B __tx_DBGHandler
|
||||
ENDFUNC
|
||||
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
@@ -1,550 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Port Specific */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* PORT SPECIFIC C INFORMATION RELEASE */
|
||||
/* */
|
||||
/* tx_port.h Cortex-M33/AC5 */
|
||||
/* 6.1.6 */
|
||||
/* */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file contains data type definitions that make the ThreadX */
|
||||
/* real-time kernel function identically on a variety of different */
|
||||
/* processor architectures. For example, the size or number of bits */
|
||||
/* in an "int" data type vary between microprocessor architectures and */
|
||||
/* even C compilers for the same microprocessor. ThreadX does not */
|
||||
/* directly use native C data types. Instead, ThreadX creates its */
|
||||
/* own special types that can be mapped to actual data types by this */
|
||||
/* file to guarantee consistency in the interface and functionality. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
|
||||
/* macro definition, */
|
||||
/* resulting in version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TX_PORT_H
|
||||
#define TX_PORT_H
|
||||
|
||||
/* Determine if the optional ThreadX user define file should be used. */
|
||||
#ifdef TX_INCLUDE_USER_DEFINE_FILE
|
||||
|
||||
/* Yes, include the user defines in tx_user.h. The defines in this file may
|
||||
alternately be defined on the command line. */
|
||||
|
||||
#include "tx_user.h"
|
||||
#endif
|
||||
|
||||
/* Define compiler library include files. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <arm_compat.h>
|
||||
#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */
|
||||
|
||||
/* Define ThreadX basic types for this port. */
|
||||
|
||||
#define VOID void
|
||||
typedef char CHAR;
|
||||
typedef unsigned char UCHAR;
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
typedef unsigned long long ULONG64;
|
||||
typedef short SHORT;
|
||||
typedef unsigned short USHORT;
|
||||
|
||||
/* Function prototypes for this port. */
|
||||
struct TX_THREAD_STRUCT;
|
||||
UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size);
|
||||
UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
|
||||
UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
|
||||
UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
|
||||
|
||||
/* This hardware has stack checking that we take advantage of - do NOT define. */
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#error "Do not define TX_ENABLE_STACK_CHECKING"
|
||||
#endif
|
||||
|
||||
/* If user does not want to terminate thread on stack overflow,
|
||||
#define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol.
|
||||
The thread will be rescheduled and continue to cause the exception.
|
||||
It is suggested user code handle this by registering a notification with the
|
||||
tx_thread_stack_error_notify function. */
|
||||
/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */
|
||||
|
||||
/* Define the system API mappings based on the error checking
|
||||
selected by the user. Note: this section is only applicable to
|
||||
application source code, hence the conditional that turns off this
|
||||
stuff when the include file is processed by the ThreadX source. */
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Determine if error checking is desired. If so, map API functions
|
||||
to the appropriate error checking front-ends. Otherwise, map API
|
||||
functions to the core functions that actually perform the work.
|
||||
Note: error checking is enabled by default. */
|
||||
|
||||
#ifdef TX_DISABLE_ERROR_CHECKING
|
||||
|
||||
/* Services without error checking. */
|
||||
|
||||
#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate
|
||||
#define tx_thread_secure_stack_free _tx_thread_secure_stack_free
|
||||
|
||||
#else
|
||||
|
||||
/* Services with error checking. */
|
||||
|
||||
#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate
|
||||
#define tx_thread_secure_stack_free _txe_thread_secure_stack_free
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Define the priority levels for ThreadX. Legal values range
|
||||
from 32 to 1024 and MUST be evenly divisible by 32. */
|
||||
|
||||
#ifndef TX_MAX_PRIORITIES
|
||||
#define TX_MAX_PRIORITIES 32
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
|
||||
thread creation is less than this value, the thread create call will return an error. */
|
||||
|
||||
#ifndef TX_MINIMUM_STACK
|
||||
#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the system timer thread's default stack size and priority. These are only applicable
|
||||
if TX_TIMER_PROCESS_IN_ISR is not defined. */
|
||||
|
||||
#ifndef TX_TIMER_THREAD_STACK_SIZE
|
||||
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
|
||||
#endif
|
||||
|
||||
#ifndef TX_TIMER_THREAD_PRIORITY
|
||||
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define various constants for the ThreadX Cortex-M33 port. */
|
||||
|
||||
#define TX_INT_DISABLE 1 /* Disable interrupts */
|
||||
#define TX_INT_ENABLE 0 /* Enable interrupts */
|
||||
|
||||
|
||||
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
|
||||
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
|
||||
source constants would be:
|
||||
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
|
||||
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
|
||||
|
||||
*/
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#ifndef TX_TRACE_TIME_SOURCE
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
|
||||
#endif
|
||||
#else
|
||||
ULONG _tx_misra_time_stamp_get(VOID);
|
||||
#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get()
|
||||
#endif
|
||||
|
||||
#ifndef TX_TRACE_TIME_MASK
|
||||
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the port specific options for the _tx_build_options variable. This variable indicates
|
||||
how the ThreadX library was built. */
|
||||
|
||||
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
|
||||
|
||||
|
||||
/* Define the in-line initialization constant so that modules with in-line
|
||||
initialization capabilities can prevent their initialization from being
|
||||
a function call. */
|
||||
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
#define TX_DISABLE_INLINE
|
||||
#else
|
||||
#define TX_INLINE_INITIALIZATION
|
||||
#endif
|
||||
|
||||
|
||||
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
|
||||
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
|
||||
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
|
||||
define is negated, thereby forcing the stack fill which is necessary for the stack checking
|
||||
logic. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#undef TX_DISABLE_STACK_FILLING
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the TX_THREAD control block extensions for this port. The main reason
|
||||
for the multiple macros is so that backward compatibility can be maintained with
|
||||
existing ThreadX kernel awareness modules. */
|
||||
|
||||
#define TX_THREAD_EXTENSION_0
|
||||
#define TX_THREAD_EXTENSION_1
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context;
|
||||
#else
|
||||
#define TX_THREAD_EXTENSION_2
|
||||
#endif
|
||||
#define TX_THREAD_EXTENSION_3
|
||||
|
||||
|
||||
/* Define the port extensions of the remaining ThreadX objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_EXTENSION
|
||||
#define TX_BYTE_POOL_EXTENSION
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION
|
||||
#define TX_MUTEX_EXTENSION
|
||||
#define TX_QUEUE_EXTENSION
|
||||
#define TX_SEMAPHORE_EXTENSION
|
||||
#define TX_TIMER_EXTENSION
|
||||
|
||||
|
||||
/* Define the user extension field of the thread control block. Nothing
|
||||
additional is needed for this port so it is defined as white space. */
|
||||
|
||||
#ifndef TX_THREAD_USER_EXTENSION
|
||||
#define TX_THREAD_USER_EXTENSION
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
|
||||
tx_thread_shell_entry, and tx_thread_terminate. */
|
||||
|
||||
|
||||
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);}
|
||||
#else
|
||||
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
|
||||
#endif
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */
|
||||
#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256
|
||||
#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE);
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
|
||||
inline static unsigned int _get_ipsr(void);
|
||||
inline static unsigned int _get_ipsr(void)
|
||||
{
|
||||
unsigned int _ipsr;
|
||||
__asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
|
||||
return _ipsr;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __ARM_PCS_VFP
|
||||
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
|
||||
ULONG _tx_misra_control_get(void);
|
||||
void _tx_misra_control_set(ULONG value);
|
||||
ULONG _tx_misra_fpccr_get(void);
|
||||
void _tx_misra_vfp_touch(void);
|
||||
|
||||
#else
|
||||
|
||||
#ifdef TX_SOURCE_CODE
|
||||
|
||||
static unsigned int _get_control(void);
|
||||
static unsigned int _get_control(void)
|
||||
{
|
||||
unsigned int _control;
|
||||
__asm("MRS %[result], control" : [result] "=r" (_control) : );
|
||||
return _control;
|
||||
}
|
||||
|
||||
static void _set_control(unsigned int _control);
|
||||
static void _set_control(unsigned int _control)
|
||||
{
|
||||
__asm("MSR control, %[input]" : : [input] "r" (_control));
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
|
||||
in order to ensure no lazy stacking will occur. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _get_control(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_set_control(_tx_vfp_state);; \
|
||||
}
|
||||
#else
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
|
||||
If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
|
||||
this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush
|
||||
the lazy FPU save, then restore the CONTROL.FPCA state. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
void _tx_vfp_access(void);
|
||||
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_system_state; \
|
||||
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
|
||||
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _get_control(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_set_control(_tx_vfp_state); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
ULONG _tx_fpccr; \
|
||||
_tx_fpccr = *((ULONG *) 0xE000EF34); \
|
||||
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
|
||||
if (_tx_fpccr == ((ULONG) 0x01)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _get_control(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
|
||||
_tx_vfp_access(); \
|
||||
if (_tx_vfp_state == ((ULONG) 0)) \
|
||||
{ \
|
||||
_tx_vfp_state = _get_control(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_set_control(_tx_vfp_state); \
|
||||
} \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_system_state; \
|
||||
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
|
||||
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
ULONG _tx_fpccr; \
|
||||
_tx_fpccr = _tx_misra_fpccr_get(); \
|
||||
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
|
||||
if (_tx_fpccr == ((ULONG) 0x01)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
|
||||
_tx_misra_vfp_touch(); \
|
||||
if (_tx_vfp_state == ((ULONG) 0)) \
|
||||
{ \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
} \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the ThreadX object creation extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the ThreadX object deletion extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the get system state macro. */
|
||||
|
||||
#ifndef TX_THREAD_GET_SYSTEM_STATE
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr())
|
||||
#else
|
||||
ULONG _tx_misra_ipsr_get(VOID);
|
||||
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get())
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value
|
||||
indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
|
||||
for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
|
||||
zero after initialization for Cortex-M ports. */
|
||||
|
||||
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
|
||||
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
|
||||
#endif
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
/* Initialize secure stacks for threads calling secure functions. */
|
||||
extern void _tx_thread_secure_stack_initialize(void);
|
||||
#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize();
|
||||
#endif
|
||||
|
||||
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
|
||||
prevent early scheduling on Cortex-M parts. */
|
||||
|
||||
#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++;
|
||||
|
||||
|
||||
/* Determine if the ARM architecture has the CLZ instruction. This is available on
|
||||
architectures v5 and above. If available, redefine the macro for calculating the
|
||||
lowest bit set. */
|
||||
|
||||
#ifndef TX_DISABLE_INLINE
|
||||
|
||||
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m)));
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Define ThreadX interrupt lockout and restore macros for protection on
|
||||
access of critical kernel information. The restore interrupt macro must
|
||||
restore the interrupt posture of the running thread prior to the value
|
||||
present prior to the disable macro. In most cases, the save area macro
|
||||
is used to define a local function save area for the disable and restore
|
||||
macros. */
|
||||
|
||||
#ifdef TX_DISABLE_INLINE
|
||||
|
||||
UINT _tx_thread_interrupt_disable(VOID);
|
||||
VOID _tx_thread_interrupt_restore(UINT previous_posture);
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
|
||||
|
||||
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
|
||||
|
||||
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
|
||||
|
||||
#else
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA UINT was_masked;
|
||||
#define TX_DISABLE was_masked = __disable_irq();
|
||||
#define TX_RESTORE if (was_masked == 0) __enable_irq();
|
||||
|
||||
#define _tx_thread_system_return _tx_thread_system_return_inline
|
||||
|
||||
|
||||
static void _tx_thread_system_return_inline(void)
|
||||
{
|
||||
unsigned int was_masked;
|
||||
|
||||
|
||||
/* Set PendSV to invoke ThreadX scheduler. */
|
||||
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
|
||||
if (_get_ipsr() == 0)
|
||||
{
|
||||
was_masked = __disable_irq();
|
||||
__enable_irq();
|
||||
if (was_masked != 0)
|
||||
__disable_irq();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the version ID of ThreadX. This may be utilized by the application. */
|
||||
|
||||
#ifdef TX_THREAD_INIT
|
||||
CHAR _tx_version_id[] =
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC5 Version 6.1.6 *";
|
||||
#else
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
extern CHAR _tx_version_id[100];
|
||||
#else
|
||||
extern CHAR _tx_version_id[];
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,60 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* COMPONENT DEFINITION RELEASE */
|
||||
/* */
|
||||
/* tx_secure_interface.h Cortex-M33 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file defines the ThreadX secure thread stack components, */
|
||||
/* including data types and external references. */
|
||||
/* It is assumed that tx_api.h and tx_port.h have already been */
|
||||
/* included. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TX_SECURE_INTERFACE_H
|
||||
#define TX_SECURE_INTERFACE_H
|
||||
|
||||
/* Define internal secure thread stack function prototypes. */
|
||||
|
||||
extern void _tx_thread_secure_stack_initialize(void);
|
||||
extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size);
|
||||
extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr);
|
||||
extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr);
|
||||
extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr);
|
||||
|
||||
#endif
|
||||
@@ -1,217 +0,0 @@
|
||||
Microsoft's Azure RTOS ThreadX for Cortex-M33
|
||||
|
||||
Using the AC5 Tools in Keil uVision
|
||||
|
||||
1. Import the ThreadX Projects
|
||||
|
||||
In order to build the ThreadX library and the ThreadX demonstration, first open
|
||||
the AzureRTOS.uvmpw workspace (located in the "example_build" directory)
|
||||
into Keil.
|
||||
|
||||
|
||||
2. Building the ThreadX run-time Library
|
||||
|
||||
Building the ThreadX library is easy; simply set the ThreadX_Library project
|
||||
as active, then then build the library. You should now observe the compilation
|
||||
and assembly of the ThreadX library. This project build produces the ThreadX
|
||||
library file ThreadX_Library.lib.
|
||||
|
||||
|
||||
3. Demonstration System
|
||||
|
||||
The ThreadX demonstration is designed to execute under the Keil debugger on the
|
||||
FVP_MPS2_Cortex-M33_MDK simulator.
|
||||
|
||||
Building the demonstration is easy; simply select the "Batch Build" button.
|
||||
You should now observe the compilation and assembly of the ThreadX demonstration of
|
||||
both the demo_secure_zone and demo_threadx_non-secure_zone projects.
|
||||
Then click the Start/Stop Debug Session button to start the simulator and begin debugging.
|
||||
You are now ready to execute the ThreadX demonstration.
|
||||
|
||||
|
||||
4. System Initialization
|
||||
|
||||
The entry point in ThreadX for the Cortex-M33 using AC5 tools uses the standard AC5
|
||||
Cortex-M33 reset sequence. From the reset vector the C runtime will be initialized.
|
||||
|
||||
The ThreadX tx_initialize_low_level.S file is responsible for setting up
|
||||
various system data structures, the vector area, and a periodic timer interrupt
|
||||
source.
|
||||
|
||||
In addition, _tx_initialize_low_level determines the first available
|
||||
address for use by the application, which is supplied as the sole input
|
||||
parameter to your application definition function, tx_application_define.
|
||||
|
||||
|
||||
5. Register Usage and Stack Frames
|
||||
|
||||
The following defines the saved context stack frames for context switches
|
||||
that occur as a result of interrupt handling or from thread-level API calls.
|
||||
All suspended threads have the same stack frame in the Cortex-M33 version of
|
||||
ThreadX. The top of the suspended thread's stack is pointed to by
|
||||
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
|
||||
|
||||
Non-FPU Stack Frame:
|
||||
|
||||
Stack Offset Stack Contents
|
||||
|
||||
0x00 LR Interrupted LR (LR at time of PENDSV)
|
||||
0x04 r4 Software stacked GP registers
|
||||
0x08 r5
|
||||
0x0C r6
|
||||
0x10 r7
|
||||
0x14 r8
|
||||
0x18 r9
|
||||
0x1C r10
|
||||
0x20 r11
|
||||
0x24 r0 Hardware stacked registers
|
||||
0x28 r1
|
||||
0x2C r2
|
||||
0x30 r3
|
||||
0x34 r12
|
||||
0x38 lr
|
||||
0x3C pc
|
||||
0x40 xPSR
|
||||
|
||||
FPU Stack Frame (only interrupted thread with FPU enabled):
|
||||
|
||||
Stack Offset Stack Contents
|
||||
|
||||
0x00 LR Interrupted LR (LR at time of PENDSV)
|
||||
0x04 s16 Software stacked FPU registers
|
||||
0x08 s17
|
||||
0x0C s18
|
||||
0x10 s19
|
||||
0x14 s20
|
||||
0x18 s21
|
||||
0x1C s22
|
||||
0x20 s23
|
||||
0x24 s24
|
||||
0x28 s25
|
||||
0x2C s26
|
||||
0x30 s27
|
||||
0x34 s28
|
||||
0x38 s29
|
||||
0x3C s30
|
||||
0x40 s31
|
||||
0x44 r4 Software stacked registers
|
||||
0x48 r5
|
||||
0x4C r6
|
||||
0x50 r7
|
||||
0x54 r8
|
||||
0x58 r9
|
||||
0x5C r10
|
||||
0x60 r11
|
||||
0x64 r0 Hardware stacked registers
|
||||
0x68 r1
|
||||
0x6C r2
|
||||
0x70 r3
|
||||
0x74 r12
|
||||
0x78 lr
|
||||
0x7C pc
|
||||
0x80 xPSR
|
||||
0x84 s0 Hardware stacked FPU registers
|
||||
0x88 s1
|
||||
0x8C s2
|
||||
0x90 s3
|
||||
0x94 s4
|
||||
0x98 s5
|
||||
0x9C s6
|
||||
0xA0 s7
|
||||
0xA4 s8
|
||||
0xA8 s9
|
||||
0xAC s10
|
||||
0xB0 s11
|
||||
0xB4 s12
|
||||
0xB8 s13
|
||||
0xBC s14
|
||||
0xC0 s15
|
||||
0xC4 fpscr
|
||||
|
||||
|
||||
6. Improving Performance
|
||||
|
||||
To make ThreadX and the application(s) run faster, you can enable
|
||||
all compiler optimizations.
|
||||
|
||||
In addition, you can eliminate the ThreadX basic API error checking by
|
||||
compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
|
||||
defined.
|
||||
|
||||
|
||||
7. Interrupt Handling
|
||||
|
||||
ThreadX provides complete and high-performance interrupt handling for Cortex-M33
|
||||
targets. There are a certain set of requirements that are defined in the
|
||||
following sub-sections:
|
||||
|
||||
|
||||
7.1 Vector Area
|
||||
|
||||
The Cortex-M33 vectors start at the label __Vectors or similar. The application may modify
|
||||
the vector area according to its needs. There is code in tx_initialize_low_level() that will
|
||||
configure the vector base register.
|
||||
|
||||
|
||||
7.2 Managed Interrupts
|
||||
|
||||
ISRs can be written completely in C (or assembly language) without any calls to
|
||||
_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the
|
||||
ThreadX API that is available to ISRs.
|
||||
|
||||
ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
|
||||
|
||||
void your_C_isr(void)
|
||||
{
|
||||
|
||||
/* ISR processing goes here, including any needed function calls. */
|
||||
}
|
||||
|
||||
ISRs written in assembly language will take the form:
|
||||
|
||||
|
||||
.global your_assembly_isr
|
||||
.thumb_func
|
||||
your_assembly_isr:
|
||||
; VOID your_assembly_isr(VOID)
|
||||
; {
|
||||
PUSH {r0, lr}
|
||||
;
|
||||
; /* Do interrupt handler work here */
|
||||
; /* BL <your interrupt routine in C> */
|
||||
|
||||
POP {r0, lr}
|
||||
BX lr
|
||||
; }
|
||||
|
||||
Note: the Cortex-M33 requires exception handlers to be thumb labels, this implies bit 0 set.
|
||||
To accomplish this, the declaration of the label has to be preceded by the assembler directive
|
||||
.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to
|
||||
be inserted in the correct location in the interrupt vector table. This table is typically
|
||||
located in either your runtime startup file or in the tx_initialize_low_level.S file.
|
||||
|
||||
|
||||
8. FPU Support
|
||||
|
||||
ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads
|
||||
can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread
|
||||
context.
|
||||
|
||||
|
||||
9. Revision History
|
||||
|
||||
For generic code revision information, please refer to the readme_threadx_generic.txt
|
||||
file, which is included in your distribution. The following details the revision
|
||||
information associated with this specific port of ThreadX:
|
||||
|
||||
04-02-2021 Release 6.1.6 changes:
|
||||
tx_port.h Updated macro definition
|
||||
|
||||
09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using AC5 tools.
|
||||
|
||||
|
||||
Copyright(c) 1996-2020 Microsoft Corporation
|
||||
|
||||
|
||||
https://azure.com/rtos
|
||||
|
||||
@@ -1,92 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_exit
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_restore Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function restores the interrupt context if it is processing a */
|
||||
;/* nested interrupt. If not, it returns to the interrupt thread if no */
|
||||
;/* preemption is necessary. Otherwise, if preemption is necessary or */
|
||||
;/* if no thread was running, the function returns to the scheduler. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling routine */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs Interrupt Service Routines */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_restore(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_context_restore
|
||||
_tx_thread_context_restore FUNCTION
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR exit function to indicate an ISR is complete. */
|
||||
;
|
||||
PUSH {r0, lr} ; Save return address
|
||||
BL _tx_execution_isr_exit ; Call the ISR exit function
|
||||
POP {r0, lr} ; Recover Save return address
|
||||
ENDIF
|
||||
;
|
||||
; /* Return to interrupt processing. */
|
||||
;
|
||||
BX lr
|
||||
;}
|
||||
ENDFUNC
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
|
||||
@@ -1,91 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_enter
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_save Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function saves the context of an executing thread in the */
|
||||
;/* beginning of interrupt processing. The function also ensures that */
|
||||
;/* the system stack is used upon return to the calling ISR. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_save(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_context_save
|
||||
_tx_thread_context_save FUNCTION
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {r0, lr} ; Save return address
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {r0, lr} ; Recover return address
|
||||
ENDIF
|
||||
;
|
||||
; /* Return to interrupt processing. */
|
||||
;
|
||||
BX lr
|
||||
;}
|
||||
ENDFUNC
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
|
||||
@@ -1,78 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_control Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for changing the interrupt lockout */
|
||||
;/* posture of the system. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* new_posture New interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_control
|
||||
_tx_thread_interrupt_control FUNCTION
|
||||
;
|
||||
; /* Pickup current interrupt lockout posture. */
|
||||
;
|
||||
MRS r1, PRIMASK
|
||||
MSR PRIMASK, r0
|
||||
MOV r0, r1
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
ENDFUNC
|
||||
END
|
||||
@@ -1,77 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_disable Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for disabling interrupts and returning */
|
||||
;/* the previous interrupt lockout posture. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_disable(UINT new_posture)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_disable
|
||||
_tx_thread_interrupt_disable FUNCTION
|
||||
;
|
||||
; /* Return current interrupt lockout posture. */
|
||||
;
|
||||
MRS r0, PRIMASK
|
||||
CPSID i
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
ENDFUNC
|
||||
END
|
||||
@@ -1,76 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_restore Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for restoring the previous */
|
||||
;/* interrupt lockout posture. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* previous_posture Previous interrupt posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_interrupt_restore(UINT new_posture)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_restore
|
||||
_tx_thread_interrupt_restore FUNCTION
|
||||
;
|
||||
; /* Restore previous interrupt lockout posture. */
|
||||
;
|
||||
MSR PRIMASK, r0
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
ENDFUNC
|
||||
END
|
||||
@@ -1,341 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_thread_system_stack_ptr
|
||||
IMPORT _tx_thread_preempt_disable
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_thread_enter
|
||||
IMPORT _tx_execution_thread_exit
|
||||
ENDIF
|
||||
|
||||
IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE
|
||||
IMPORT _tx_thread_secure_stack_context_restore
|
||||
IMPORT _tx_thread_secure_stack_context_save
|
||||
IMPORT _tx_thread_secure_mode_stack_allocate
|
||||
IMPORT _tx_thread_secure_mode_stack_free
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function waits for a thread control block pointer to appear in */
|
||||
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
;/* in the variable, the corresponding thread is resumed. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* _tx_thread_system_return Return to system from thread */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_schedule(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_schedule
|
||||
_tx_thread_schedule FUNCTION
|
||||
;
|
||||
; /* This function should only ever be called on Cortex-M
|
||||
; from the first schedule request. Subsequent scheduling occurs
|
||||
; from the PendSV handling routines below. */
|
||||
;
|
||||
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
;
|
||||
MOV r0, #0 ; Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
|
||||
STR r0, [r2, #0] ; Clear preempt disable flag
|
||||
;
|
||||
; /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
|
||||
;
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
BIC r0, r0, #4 ; Clear the FPCA bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
ENDIF
|
||||
;
|
||||
; /* Enable the interrupts */
|
||||
;
|
||||
CPSIE i
|
||||
;
|
||||
; /* Enter the scheduler for the first time. */
|
||||
;
|
||||
MOV r0, #0x10000000 ; Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 ; Load NVIC base
|
||||
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
|
||||
DSB ; Complete all memory accesses
|
||||
ISB ; Flush pipeline
|
||||
;
|
||||
; /* Wait here for the PendSV to take place. */
|
||||
;
|
||||
__tx_wait_here
|
||||
B __tx_wait_here ; Wait for the PendSV to happen
|
||||
ENDFUNC
|
||||
;}
|
||||
;
|
||||
; /* Generic context switching PendSV handler. */
|
||||
;
|
||||
EXPORT PendSV_Handler
|
||||
PendSV_Handler FUNCTION
|
||||
;
|
||||
; /* Get current thread value and new thread pointer. */
|
||||
;
|
||||
__tx_ts_handler
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
POP {r0, lr} ; Recover LR
|
||||
CPSIE i ; Enable interrupts
|
||||
ENDIF
|
||||
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
|
||||
MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address
|
||||
MOV r3, #0 ; Build NULL value
|
||||
LDR r1, [r0] ; Pickup current thread pointer
|
||||
;
|
||||
; /* Determine if there is a current thread to finish preserving. */
|
||||
;
|
||||
CBZ r1, __tx_ts_new ; If NULL, skip preservation
|
||||
;
|
||||
; /* Recover PSP and preserve current thread context. */
|
||||
;
|
||||
STR r3, [r0] ; Set _tx_thread_current_ptr to NULL
|
||||
MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer)
|
||||
STMDB r12!, {r4-r11} ; Save its remaining registers
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
TST LR, #0x10 ; Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_save
|
||||
VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers
|
||||
_skip_vfp_save
|
||||
ENDIF
|
||||
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
|
||||
STMDB r12!, {LR} ; Save LR on the stack
|
||||
STR r12, [r1, #8] ; Save the thread stack pointer
|
||||
|
||||
IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE
|
||||
; Save secure context
|
||||
LDR r5, [r1,#0x90] ; Load secure stack index
|
||||
CBZ r5, _skip_secure_save ; Skip save if there is no secure context
|
||||
PUSH {r0,r1,r2,r3} ; Save scratch registers
|
||||
MOV r0, r1 ; Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_save ; Save secure stack
|
||||
POP {r0,r1,r2,r3} ; Restore secure registers
|
||||
_skip_secure_save
|
||||
ENDIF
|
||||
;
|
||||
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
;
|
||||
LDR r5, [r4] ; Pickup current time-slice
|
||||
CBZ r5, __tx_ts_new ; If not active, skip processing
|
||||
;
|
||||
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
;
|
||||
STR r5, [r1, #24] ; Save current time-slice
|
||||
;
|
||||
; /* Clear the global time-slice. */
|
||||
;
|
||||
STR r3, [r4] ; Clear time-slice
|
||||
;
|
||||
; /* Executing thread is now completely preserved!!! */
|
||||
;
|
||||
__tx_ts_new
|
||||
;
|
||||
; /* Now we are looking for a new thread to execute! */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
LDR r1, [r2] ; Is there another thread ready to execute?
|
||||
CBZ r1, __tx_ts_wait ; No, skip to the wait processing
|
||||
;
|
||||
; /* Yes, another thread is ready for else, make the current thread the new thread. */
|
||||
;
|
||||
STR r1, [r0] ; Setup the current thread pointer to the new thread
|
||||
CPSIE i ; Enable interrupts
|
||||
;
|
||||
; /* Increment the thread run count. */
|
||||
;
|
||||
__tx_ts_restore
|
||||
LDR r7, [r1, #4] ; Pickup the current thread run count
|
||||
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
|
||||
LDR r5, [r1, #24] ; Pickup thread's current time-slice
|
||||
ADD r7, r7, #1 ; Increment the thread run count
|
||||
STR r7, [r1, #4] ; Store the new run count
|
||||
;
|
||||
; /* Setup global time-slice with thread's current time-slice. */
|
||||
;
|
||||
STR r5, [r4] ; Setup global time-slice
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread entry function to indicate the thread is executing. */
|
||||
;
|
||||
PUSH {r0, r1} ; Save r0/r1
|
||||
BL _tx_execution_thread_enter ; Call the thread execution enter function
|
||||
POP {r0, r1} ; Recover r0/r1
|
||||
ENDIF
|
||||
|
||||
IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE
|
||||
; Restore secure context
|
||||
LDR r0, [r1,#0x90] ; Load secure stack index
|
||||
CBZ r0, _skip_secure_restore ; Skip restore if there is no secure context
|
||||
PUSH {r0,r1} ; Save r1 (and dummy r0)
|
||||
MOV r0, r1 ; Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_restore ; Restore secure stack
|
||||
POP {r0,r1} ; Restore r1 (and dummy r0)
|
||||
_skip_secure_restore
|
||||
ENDIF
|
||||
|
||||
;
|
||||
; /* Restore the thread context and PSP. */
|
||||
;
|
||||
LDR r12, [r1, #12] ; Get stack start
|
||||
MSR PSPLIM, r12 ; Set stack limit
|
||||
LDR r12, [r1, #8] ; Pickup thread's stack pointer
|
||||
LDMIA r12!, {LR} ; Pickup LR
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
TST LR, #0x10 ; Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_restore ; If not, skip VFP restore
|
||||
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
|
||||
_skip_vfp_restore
|
||||
ENDIF
|
||||
LDMIA r12!, {r4-r11} ; Recover thread's registers
|
||||
MSR PSP, r12 ; Setup the thread's stack pointer
|
||||
;
|
||||
; /* Return to thread. */
|
||||
;
|
||||
BX lr ; Return to thread!
|
||||
;
|
||||
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
; are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
;
|
||||
__tx_ts_wait
|
||||
CPSID i ; Disable interrupts
|
||||
LDR r1, [r2] ; Pickup the next thread to execute pointer
|
||||
STR r1, [r0] ; Store it in the current pointer
|
||||
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
|
||||
IF :DEF:TX_ENABLE_WFI
|
||||
DSB ; Ensure no outstanding memory transactions
|
||||
WFI ; Wait for interrupt
|
||||
ISB ; Ensure pipeline is flushed
|
||||
ENDIF
|
||||
CPSIE i ; Enable interrupts
|
||||
B __tx_ts_wait ; Loop to continue waiting
|
||||
;
|
||||
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
; already in the handler! */
|
||||
;
|
||||
__tx_ts_ready
|
||||
MOV r7, #0x08000000 ; Build clear PendSV value
|
||||
MOV r8, #0xE000E000 ; Build base NVIC address
|
||||
STR r7, [r8, #0xD04] ; Clear any PendSV
|
||||
;
|
||||
; /* Re-enable interrupts and restore new thread. */
|
||||
;
|
||||
CPSIE i ; Enable interrupts
|
||||
B __tx_ts_restore ; Restore the thread
|
||||
ENDFUNC
|
||||
|
||||
|
||||
|
||||
IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE
|
||||
; SVC_Handler is not needed when ThreadX is running in single mode.
|
||||
EXPORT SVC_Handler
|
||||
SVC_Handler FUNCTION
|
||||
TST lr, #0x04 ; Determine return stack from EXC_RETURN bit 2
|
||||
ITE EQ
|
||||
MRSEQ r0, MSP ; Get MSP if return stack is MSP
|
||||
MRSNE r0, PSP ; Get PSP if return stack is PSP
|
||||
|
||||
LDR r1, [r0,#24] ; Load saved PC from stack
|
||||
LDRB r1, [r1,#-2] ; Load SVC number
|
||||
|
||||
CMP r1, #1 ; Is it a secure stack allocate request?
|
||||
BEQ _tx_svc_secure_alloc ; Yes, go there
|
||||
|
||||
CMP r1, #2 ; Is it a secure stack free request?
|
||||
BEQ _tx_svc_secure_free ; Yes, go there
|
||||
|
||||
; Unknown SVC argument - just return
|
||||
BX lr
|
||||
|
||||
_tx_svc_secure_alloc
|
||||
PUSH {r0,lr} ; Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} ; Load function parameters from stack
|
||||
BL _tx_thread_secure_mode_stack_allocate
|
||||
POP {r12,lr} ; Restore SP and EXC_RETURN
|
||||
STR r0,[r12] ; Store function return value
|
||||
BX lr
|
||||
_tx_svc_secure_free
|
||||
PUSH {r0,lr} ; Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} ; Load function parameters from stack
|
||||
BL _tx_thread_secure_mode_stack_free
|
||||
POP {r12,lr} ; Restore SP and EXC_RETURN
|
||||
STR r0,[r12] ; Store function return value
|
||||
BX lr
|
||||
ENDFUNC
|
||||
ENDIF ; End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
|
||||
|
||||
EXPORT _tx_vfp_access
|
||||
_tx_vfp_access FUNCTION
|
||||
VMOV.F32 s0, s0 ; Simply access the VFP
|
||||
BX lr ; Return to caller
|
||||
ENDFUNC
|
||||
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
@@ -1,482 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
#include "tx_api.h"
|
||||
|
||||
/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined,
|
||||
no secure stack functionality is needed. */
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */
|
||||
#include "tx_secure_interface.h" /* Interface for NS code. */
|
||||
|
||||
/* Minimum size of secure stack. */
|
||||
#ifndef TX_THREAD_SECURE_STACK_MINIMUM
|
||||
#define TX_THREAD_SECURE_STACK_MINIMUM 256
|
||||
#endif
|
||||
/* Maximum size of secure stack. */
|
||||
#ifndef TX_THREAD_SECURE_STACK_MAXIMUM
|
||||
#define TX_THREAD_SECURE_STACK_MAXIMUM 1024
|
||||
#endif
|
||||
|
||||
/* 8 bytes added to stack size to "seal" stack. */
|
||||
#define TX_THREAD_STACK_SEAL_SIZE 8
|
||||
#define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5
|
||||
|
||||
/* Secure stack info struct to hold stack start, stack limit,
|
||||
current stack pointer, and pointer to owning thread.
|
||||
This will be allocated for each thread with a secure stack. */
|
||||
typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
{
|
||||
VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */
|
||||
VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */
|
||||
VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */
|
||||
TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */
|
||||
} TX_THREAD_SECURE_STACK_INFO;
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M33/AC5 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function initializes secure mode to use PSP stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_CONTROL Intrinsic to get CONTROL */
|
||||
/* __set_CONTROL Intrinsic to set CONTROL */
|
||||
/* __set_PSPLIM Intrinsic to set PSP limit */
|
||||
/* __set_PSP Intrinsic to set PSP */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_initialize(void)
|
||||
{
|
||||
|
||||
/* Set secure mode to use PSP. */
|
||||
__set_CONTROL(__get_CONTROL() | 2);
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
__set_PSPLIM(0);
|
||||
__set_PSP(0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_mode_stack_allocate Cortex-M33/AC5 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function allocates a thread's secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of stack to allocates */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_SIZE_ERROR Invalid stack size */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_IPSR Intrinsic to get IPSR */
|
||||
/* calloc Compiler's calloc function */
|
||||
/* malloc Compiler's malloc function */
|
||||
/* free Compiler's free() function */
|
||||
/* __set_PSPLIM Intrinsic to set PSP limit */
|
||||
/* __set_PSP Intrinsic to set PSP */
|
||||
/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* SVC Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* added stack sealing, */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
{
|
||||
UINT status;
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
UCHAR *stack_mem;
|
||||
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM)
|
||||
{
|
||||
status = TX_SIZE_ERROR;
|
||||
}
|
||||
|
||||
/* Check if thread already has secure stack allocated. */
|
||||
else if (thread_ptr -> tx_thread_secure_stack_context != 0)
|
||||
{
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Allocate space for secure stack info. */
|
||||
info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO));
|
||||
|
||||
if(info_ptr != TX_NULL)
|
||||
{
|
||||
/* If stack info allocated, allocate a stack & seal. */
|
||||
stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE);
|
||||
|
||||
if(stack_mem != TX_NULL)
|
||||
{
|
||||
/* Secure stack has been allocated, save in the stack info struct. */
|
||||
info_ptr -> tx_thread_secure_stack_limit = stack_mem;
|
||||
info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size;
|
||||
info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start;
|
||||
info_ptr -> tx_thread_ptr = thread_ptr;
|
||||
|
||||
/* Seal bottom of stack. */
|
||||
*(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE;
|
||||
|
||||
/* Save info pointer in thread. */
|
||||
thread_ptr -> tx_thread_secure_stack_context = info_ptr;
|
||||
|
||||
/* Check if this thread is running by looking at its stack start and PSPLIM_NS */
|
||||
if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS())
|
||||
{
|
||||
/* If this thread is running, set Secure PSP and PSPLIM. */
|
||||
__set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit));
|
||||
__set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr));
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Stack not allocated, free the info struct. */
|
||||
free(info_ptr);
|
||||
status = TX_NO_MEMORY;
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
status = TX_NO_MEMORY;
|
||||
}
|
||||
}
|
||||
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_mode_stack_free Cortex-M33/AC5 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function frees a thread's secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_IPSR Intrinsic to get IPSR */
|
||||
/* free Compiler's free() function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* SVC Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
|
||||
{
|
||||
UINT status;
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Pickup stack info from thread. */
|
||||
info_ptr = thread_ptr -> tx_thread_secure_stack_context;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
else if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
|
||||
/* Free secure stack. */
|
||||
free(info_ptr -> tx_thread_secure_stack_limit);
|
||||
|
||||
/* Free info struct. */
|
||||
free(info_ptr);
|
||||
|
||||
/* Clear secure context from thread. */
|
||||
thread_ptr -> tx_thread_secure_stack_context = 0;
|
||||
}
|
||||
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_save Cortex-M33/AC5 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function saves context of the secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_IPSR Intrinsic to get IPSR */
|
||||
/* __get_PSP Intrinsic to get PSP */
|
||||
/* __set_PSPLIM Intrinsic to set PSP limit */
|
||||
/* __set_PSP Intrinsic to set PSP */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* PendSV Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr)
|
||||
{
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
ULONG sp;
|
||||
|
||||
/* This function should be called from scheduler only. */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Pickup the secure context pointer. */
|
||||
info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context);
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Check that stack pointer is in range */
|
||||
sp = __get_PSP();
|
||||
if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) ||
|
||||
(sp > (ULONG)info_ptr -> tx_thread_secure_stack_start))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Save stack pointer. */
|
||||
*(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp;
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
__set_PSPLIM(0);
|
||||
__set_PSP(0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_restore Cortex-M33/AC5 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function restores context of the secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_IPSR Intrinsic to get IPSR */
|
||||
/* __set_PSPLIM Intrinsic to set PSP limit */
|
||||
/* __set_PSP Intrinsic to set PSP */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* PendSV Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr)
|
||||
{
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
|
||||
/* This function should be called from scheduler only. */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Pickup the secure context pointer. */
|
||||
info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context);
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set stack pointer and limit. */
|
||||
__set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit);
|
||||
__set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,83 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_secure_stack_allocate Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function enters the SVC handler to allocate a secure stack. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Thread control block pointer */
|
||||
;/* stack_size Size of secure stack to */
|
||||
;/* allocate */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* status Actual completion status */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* SVC 1 */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
;{
|
||||
EXPORT _tx_thread_secure_stack_allocate
|
||||
_tx_thread_secure_stack_allocate FUNCTION
|
||||
IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE
|
||||
MRS r3, PRIMASK ; Save interrupt mask
|
||||
CPSIE i ; Enable interrupts for SVC call
|
||||
SVC 1
|
||||
CMP r3, #0 ; If interrupts enabled, just return
|
||||
BEQ _alloc_return_interrupt_enabled
|
||||
CPSID i ; Otherwise, disable interrupts
|
||||
ELSE
|
||||
MOV32 r0, #0xFF ; Feature not enabled
|
||||
ENDIF
|
||||
_alloc_return_interrupt_enabled
|
||||
BX lr
|
||||
ENDFUNC
|
||||
|
||||
END
|
||||
@@ -1,81 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_secure_stack_free Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function enters the SVC handler to free a secure stack. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Thread control block pointer */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* status Actual completion status */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* SVC 2 */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)
|
||||
;{
|
||||
EXPORT _tx_thread_secure_stack_free
|
||||
_tx_thread_secure_stack_free FUNCTION
|
||||
IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE
|
||||
MRS r3, PRIMASK ; Save interrupt mask
|
||||
CPSIE i ; Enable interrupts for SVC call
|
||||
SVC 2
|
||||
CMP r3, #0 ; If interrupts enabled, just return
|
||||
BEQ _free_return_interrupt_enabled
|
||||
CPSID i ; Otherwise, disable interrupts
|
||||
ELSE
|
||||
MOV32 r0, #0xFF ; Feature not enabled
|
||||
ENDIF
|
||||
_free_return_interrupt_enabled
|
||||
BX lr
|
||||
ENDFUNC
|
||||
END
|
||||
|
||||
@@ -1,139 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_stack_build Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread control blk */
|
||||
;/* function_ptr Pointer to return function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
;{
|
||||
EXPORT _tx_thread_stack_build
|
||||
_tx_thread_stack_build FUNCTION
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the Cortex-M33 should look like the following after it is built:
|
||||
;
|
||||
; Stack Top:
|
||||
; LR Interrupted LR (LR at time of PENDSV)
|
||||
; r4 Initial value for r4
|
||||
; r5 Initial value for r5
|
||||
; r6 Initial value for r6
|
||||
; r7 Initial value for r7
|
||||
; r8 Initial value for r8
|
||||
; r9 Initial value for r9
|
||||
; r10 Initial value for r10
|
||||
; r11 Initial value for r11
|
||||
; r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
; r1 Initial value for r1
|
||||
; r2 Initial value for r2
|
||||
; r3 Initial value for r3
|
||||
; r12 Initial value for r12
|
||||
; lr Initial value for lr
|
||||
; pc Initial value for pc
|
||||
; xPSR Initial value for xPSR
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
LDR r2, [r0, #16] ; Pickup end of stack area
|
||||
BIC r2, r2, #0x7 ; Align frame for 8-byte alignment
|
||||
SUB r2, r2, #68 ; Subtract frame size
|
||||
IF :DEF: TX_SINGLE_MODE_SECURE
|
||||
LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode
|
||||
ELSE
|
||||
LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP
|
||||
ENDIF
|
||||
STR r3, [r2, #0] ; Save on the stack
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #4] ; Store initial r4
|
||||
STR r3, [r2, #8] ; Store initial r5
|
||||
STR r3, [r2, #12] ; Store initial r6
|
||||
STR r3, [r2, #16] ; Store initial r7
|
||||
STR r3, [r2, #20] ; Store initial r8
|
||||
STR r3, [r2, #24] ; Store initial r9
|
||||
STR r3, [r2, #28] ; Store initial r10
|
||||
STR r3, [r2, #32] ; Store initial r11
|
||||
;
|
||||
; /* Hardware stack follows. */
|
||||
;
|
||||
STR r3, [r2, #36] ; Store initial r0
|
||||
STR r3, [r2, #40] ; Store initial r1
|
||||
STR r3, [r2, #44] ; Store initial r2
|
||||
STR r3, [r2, #48] ; Store initial r3
|
||||
STR r3, [r2, #52] ; Store initial r12
|
||||
MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] ; Store initial lr
|
||||
STR r1, [r2, #60] ; Store initial pc
|
||||
MOV r3, #0x01000000 ; Only T-bit need be set
|
||||
STR r3, [r2, #64] ; Store initial xPSR
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
;
|
||||
STR r2, [r0, #8] ; Save stack pointer in thread's
|
||||
; control block
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
ENDFUNC
|
||||
END
|
||||
|
||||
@@ -1,87 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_system_return Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is target processor specific. It is used to transfer */
|
||||
;/* control from a thread back to the ThreadX system. Only a */
|
||||
;/* minimal context is saved since the compiler assumes temp registers */
|
||||
;/* are going to get slicked by a function call anyway. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling loop */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ThreadX components */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_system_return(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_system_return
|
||||
_tx_thread_system_return FUNCTION
|
||||
;
|
||||
; /* Return to real scheduler via PendSV. Note that this routine is often
|
||||
; replaced with in-line assembly in tx_port.h to improved performance. */
|
||||
;
|
||||
MOV r0, #0x10000000 ; Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 ; Load NVIC base
|
||||
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
|
||||
MRS r0, IPSR ; Pickup IPSR
|
||||
CMP r0, #0 ; Is it a thread returning?
|
||||
BNE _isr_context ; If ISR, skip interrupt enable
|
||||
MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK
|
||||
CPSIE i ; Enable interrupts
|
||||
MSR PRIMASK, r1 ; Restore original interrupt posture
|
||||
_isr_context
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
ENDFUNC
|
||||
END
|
||||
@@ -1,260 +0,0 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Timer */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_timer_system_clock
|
||||
IMPORT _tx_timer_current_ptr
|
||||
IMPORT _tx_timer_list_start
|
||||
IMPORT _tx_timer_list_end
|
||||
IMPORT _tx_timer_expired_time_slice
|
||||
IMPORT _tx_timer_expired
|
||||
IMPORT _tx_thread_time_slice
|
||||
IMPORT _tx_timer_expiration_process
|
||||
IMPORT _tx_thread_preempt_disable
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_timer_interrupt Cortex-M33/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function processes the hardware timer interrupt. This */
|
||||
;/* processing includes incrementing the system clock and checking for */
|
||||
;/* time slice and/or timer expiration. If either is found, the */
|
||||
;/* the expiration functions are called. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_timer_expiration_process Timer expiration processing */
|
||||
;/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* interrupt vector */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_timer_interrupt(VOID)
|
||||
;{
|
||||
EXPORT _tx_timer_interrupt
|
||||
_tx_timer_interrupt FUNCTION
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available
|
||||
; for use. */
|
||||
;
|
||||
; /* Increment the system clock. */
|
||||
; _tx_timer_system_clock++;
|
||||
;
|
||||
MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock
|
||||
LDR r0, [r1, #0] ; Pickup system clock
|
||||
ADD r0, r0, #1 ; Increment system clock
|
||||
STR r0, [r1, #0] ; Store new system clock
|
||||
;
|
||||
; /* Test for time-slice expiration. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
|
||||
LDR r2, [r3, #0] ; Pickup time-slice
|
||||
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
|
||||
; Yes, skip time-slice processing
|
||||
;
|
||||
; /* Decrement the time_slice. */
|
||||
; _tx_timer_time_slice--;
|
||||
;
|
||||
SUB r2, r2, #1 ; Decrement the time-slice
|
||||
STR r2, [r3, #0] ; Store new time-slice value
|
||||
;
|
||||
; /* Check for expiration. */
|
||||
; if (__tx_timer_time_slice == 0)
|
||||
;
|
||||
CBNZ r2, __tx_timer_no_time_slice ; Has it expired?
|
||||
;
|
||||
; /* Set the time-slice expired flag. */
|
||||
; _tx_timer_expired_time_slice = TX_TRUE;
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag
|
||||
MOV r0, #1 ; Build expired value
|
||||
STR r0, [r3, #0] ; Set time-slice expiration flag
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_no_time_slice
|
||||
;
|
||||
; /* Test for timer expiration. */
|
||||
; if (*_tx_timer_current_ptr)
|
||||
; {
|
||||
;
|
||||
MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address
|
||||
LDR r0, [r1, #0] ; Pickup current timer
|
||||
LDR r2, [r0, #0] ; Pickup timer list entry
|
||||
CBZ r2, __tx_timer_no_timer ; Is there anything in the list?
|
||||
; No, just increment the timer
|
||||
;
|
||||
; /* Set expiration flag. */
|
||||
; _tx_timer_expired = TX_TRUE;
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired ; Pickup expiration flag address
|
||||
MOV r2, #1 ; Build expired value
|
||||
STR r2, [r3, #0] ; Set expired flag
|
||||
B __tx_timer_done ; Finished timer processing
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
__tx_timer_no_timer
|
||||
;
|
||||
; /* No timer expired, increment the timer pointer. */
|
||||
; _tx_timer_current_ptr++;
|
||||
;
|
||||
ADD r0, r0, #4 ; Move to next timer
|
||||
;
|
||||
; /* Check for wrap-around. */
|
||||
; if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
;
|
||||
MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end
|
||||
LDR r2, [r3, #0] ; Pickup list end
|
||||
CMP r0, r2 ; Are we at list end?
|
||||
BNE __tx_timer_skip_wrap ; No, skip wrap-around logic
|
||||
;
|
||||
; /* Wrap to beginning of list. */
|
||||
; _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
;
|
||||
MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start
|
||||
LDR r0, [r3, #0] ; Set current pointer to list start
|
||||
;
|
||||
__tx_timer_skip_wrap
|
||||
;
|
||||
STR r0, [r1, #0] ; Store new current timer pointer
|
||||
; }
|
||||
;
|
||||
__tx_timer_done
|
||||
;
|
||||
;
|
||||
; /* See if anything has expired. */
|
||||
; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag
|
||||
LDR r2, [r3, #0] ; Pickup time-slice expired flag
|
||||
CBNZ r2, __tx_something_expired ; Did a time-slice expire?
|
||||
; If non-zero, time-slice expired
|
||||
MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag
|
||||
LDR r0, [r1, #0] ; Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_nothing_expired ; Did a timer expire?
|
||||
; No, nothing expired
|
||||
;
|
||||
__tx_something_expired
|
||||
;
|
||||
;
|
||||
STMDB sp!, {r0, lr} ; Save the lr register on the stack
|
||||
; and save r0 just to keep 8-byte alignment
|
||||
;
|
||||
; /* Did a timer expire? */
|
||||
; if (_tx_timer_expired)
|
||||
; {
|
||||
;
|
||||
MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag
|
||||
LDR r0, [r1, #0] ; Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_dont_activate ; Check for timer expiration
|
||||
; If not set, skip timer activation
|
||||
;
|
||||
; /* Process timer expiration. */
|
||||
; _tx_timer_expiration_process();
|
||||
;
|
||||
BL _tx_timer_expiration_process ; Call the timer expiration handling routine
|
||||
;
|
||||
; }
|
||||
__tx_timer_dont_activate
|
||||
;
|
||||
; /* Did time slice expire? */
|
||||
; if (_tx_timer_expired_time_slice)
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
|
||||
LDR r2, [r3, #0] ; Pickup the actual flag
|
||||
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
|
||||
; No, skip time-slice processing
|
||||
;
|
||||
; /* Time slice interrupted thread. */
|
||||
; _tx_thread_time_slice();
|
||||
|
||||
BL _tx_thread_time_slice ; Call time-slice processing
|
||||
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
|
||||
LDR r1, [r0] ; Is the preempt disable flag set?
|
||||
CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
|
||||
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r1, [r0] ; Pickup the current thread pointer
|
||||
MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address
|
||||
LDR r3, [r2] ; Pickup the execute thread pointer
|
||||
MOV32 r0, 0xE000ED04 ; Build address of control register
|
||||
MOV32 r2, 0x10000000 ; Build value for PendSV bit
|
||||
CMP r1, r3 ; Are they the same?
|
||||
BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed
|
||||
STR r2, [r0] ; Not the same, issue the PendSV for preemption
|
||||
__tx_timer_skip_time_slice
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_not_ts_expiration
|
||||
;
|
||||
LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for
|
||||
; the 8-byte stack alignment
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_nothing_expired
|
||||
|
||||
DSB ; Complete all memory access
|
||||
BX lr ; Return to caller
|
||||
;
|
||||
;}
|
||||
ENDFUNC
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
|
||||
@@ -1,119 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_initialize.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_allocate Cortex-M33 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function checks for errors in the secure stack allocate */
|
||||
/* function call. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of secure stack to */
|
||||
/* allocate */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_allocate Actual stack alloc function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
{
|
||||
#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
return(TX_FEATURE_NOT_ENABLED);
|
||||
#else
|
||||
UINT status;
|
||||
|
||||
/* Default status to success. */
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Check for an invalid thread pointer. */
|
||||
if (thread_ptr == TX_NULL)
|
||||
{
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Now check for invalid thread ID. */
|
||||
else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
|
||||
{
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Check for interrupt call. */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0))
|
||||
{
|
||||
/* Is call from an interrupt and not initialization? */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
|
||||
{
|
||||
/* Invalid caller of this function, return appropriate error code. */
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine if everything is okay. */
|
||||
if (status == TX_SUCCESS)
|
||||
{
|
||||
/* Call actual secure stack allocate function. */
|
||||
status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size);
|
||||
}
|
||||
|
||||
/* Return completion status. */
|
||||
return(status);
|
||||
#endif
|
||||
}
|
||||
@@ -2551,6 +2551,18 @@
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>199</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\src\tx_thread_secure_stack_initialize.S</PathWithFileName>
|
||||
<FilenameWithoutPath>tx_thread_secure_stack_initialize.S</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
|
||||
@@ -1373,6 +1373,11 @@
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\tx_initialize_low_level.S</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tx_thread_secure_stack_initialize.S</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\src\tx_thread_secure_stack_initialize.S</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
|
||||
@@ -11,8 +11,8 @@
|
||||
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __ROM_BASE 0x00000000
|
||||
#define __ROM_SIZE 0x00200000
|
||||
#define __ROM_BASE 0x00000000
|
||||
#define __ROM_SIZE 0x00080000
|
||||
|
||||
/*--------------------- Embedded RAM Configuration ---------------------------
|
||||
; <h> RAM Configuration
|
||||
@@ -20,8 +20,8 @@
|
||||
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_BASE 0x20000000
|
||||
#define __RAM_SIZE 0x00020000
|
||||
#define __RAM_BASE 0x20000000
|
||||
#define __RAM_SIZE 0x00040000
|
||||
|
||||
/*--------------------- Stack / Heap Configuration ---------------------------
|
||||
; <h> Stack / Heap Configuration
|
||||
@@ -29,26 +29,29 @@
|
||||
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_SIZE 0x00000400
|
||||
#define __HEAP_SIZE 0x00000C00
|
||||
#define __STACK_SIZE 0x00000200
|
||||
#define __HEAP_SIZE 0x00000C00
|
||||
|
||||
/*
|
||||
;------------- <<< end of configuration section >>> ---------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
User Stack & Heap boundery definition
|
||||
User Stack & Heap boundary definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
|
||||
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
|
||||
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
|
||||
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Scatter File Definitions definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RO_BASE __ROM_BASE
|
||||
#define __RO_SIZE __ROM_SIZE
|
||||
|
||||
#define __RW_BASE (__RAM_BASE )
|
||||
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
|
||||
#define __RO_BASE __ROM_BASE
|
||||
#define __RO_SIZE __ROM_SIZE
|
||||
|
||||
#define __RW_BASE __RAM_BASE
|
||||
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
|
||||
|
||||
|
||||
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
|
||||
|
||||
@@ -1,11 +1,11 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCM33.c
|
||||
* @brief CMSIS Core Device Startup File for Cortex-M33 Device
|
||||
* @version V2.0.0
|
||||
* @date 20. May 2019
|
||||
* @version V2.0.3
|
||||
* @date 31. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -34,31 +34,26 @@
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler Function Prototype
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef void( *pFunc )( void );
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __INITIAL_SP;
|
||||
extern uint32_t __STACK_LIMIT;
|
||||
|
||||
extern void __PROGRAM_START(void) __NO_RETURN;
|
||||
extern __NO_RETURN void __PROGRAM_START(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void) __NO_RETURN;
|
||||
void Reset_Handler (void) __NO_RETURN;
|
||||
__NO_RETURN void Reset_Handler (void);
|
||||
void Default_Handler(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak));
|
||||
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
@@ -83,9 +78,15 @@ void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const pFunc __VECTOR_TABLE[496];
|
||||
const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpedantic"
|
||||
#endif
|
||||
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
|
||||
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
Reset_Handler, /* Reset Handler */
|
||||
NMI_Handler, /* -14 NMI Handler */
|
||||
HardFault_Handler, /* -13 Hard Fault Handler */
|
||||
@@ -116,13 +117,17 @@ extern const pFunc __VECTOR_TABLE[496];
|
||||
/* Interrupts 10 .. 480 are left out */
|
||||
};
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
/* The linker will place this value at the bottom of the stack to seal the secure main stack. */
|
||||
const int stack_seal __attribute__((section (".seal"))) = 0xFEF5EDA5;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void)
|
||||
__NO_RETURN void Reset_Handler(void)
|
||||
{
|
||||
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
|
||||
|
||||
@@ -130,6 +135,20 @@ void Reset_Handler(void)
|
||||
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wmissing-noreturn"
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Hard Fault Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
@@ -137,3 +156,8 @@ void Default_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic pop
|
||||
#endif
|
||||
|
||||
|
||||
@@ -2,11 +2,11 @@
|
||||
* @file system_ARMCM33.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM33 Device
|
||||
* @version V5.3.1
|
||||
* @date 09. July 2018
|
||||
* @version V1.0.1
|
||||
* @date 15. November 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -50,13 +50,11 @@
|
||||
|
||||
#define SYSTEM_CLOCK (XTAL / 2U)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Externals
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
extern uint32_t __Vectors;
|
||||
#endif
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
@@ -79,7 +77,7 @@ void SystemInit (void)
|
||||
{
|
||||
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
SCB->VTOR = (uint32_t) &__Vectors;
|
||||
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
|
||||
#endif
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
/* PORT SPECIFIC C INFORMATION RELEASE */
|
||||
/* */
|
||||
/* tx_port.h Cortex-M33/AC6 */
|
||||
/* 6.1.5 */
|
||||
/* 6.1.7 */
|
||||
/* */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
@@ -51,6 +51,11 @@
|
||||
/* 03-02-2021 Scott Larson Modified comment(s), added */
|
||||
/* ULONG64_DEFINED, */
|
||||
/* resulting in version 6.1.5 */
|
||||
/* 06-02-2021 Yuxin Zhou Modified comment(s), removed */
|
||||
/* unneeded header file, */
|
||||
/* added symbol to enable */
|
||||
/* stack error handler, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
@@ -71,7 +76,6 @@
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <arm_compat.h>
|
||||
#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */
|
||||
|
||||
/* Define ThreadX basic types for this port. */
|
||||
|
||||
@@ -94,6 +98,12 @@ UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
|
||||
UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
|
||||
UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
|
||||
|
||||
/* This port overrides tx_thread_stack_error_notify with an architecture specific version */
|
||||
#define TX_PORT_THREAD_STACK_ERROR_NOTIFY
|
||||
|
||||
/* This port overrides tx_thread_stack_error_handler with an architecture specific version */
|
||||
#define TX_PORT_THREAD_STACK_ERROR_HANDLER
|
||||
|
||||
/* This hardware has stack checking that we take advantage of - do NOT define. */
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#error "Do not define TX_ENABLE_STACK_CHECKING"
|
||||
@@ -229,14 +239,14 @@ ULONG _tx_misra_time_stamp_get(VOID);
|
||||
for the multiple macros is so that backward compatibility can be maintained with
|
||||
existing ThreadX kernel awareness modules. */
|
||||
|
||||
#define TX_THREAD_EXTENSION_0
|
||||
#define TX_THREAD_EXTENSION_1
|
||||
#define TX_THREAD_EXTENSION_0
|
||||
#define TX_THREAD_EXTENSION_1
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context;
|
||||
#else
|
||||
#define TX_THREAD_EXTENSION_2
|
||||
#define TX_THREAD_EXTENSION_2
|
||||
#endif
|
||||
#define TX_THREAD_EXTENSION_3
|
||||
#define TX_THREAD_EXTENSION_3
|
||||
|
||||
|
||||
/* Define the port extensions of the remaining ThreadX objects. */
|
||||
@@ -485,7 +495,7 @@ extern void _tx_thread_secure_stack_initialize(void);
|
||||
|
||||
#ifndef TX_DISABLE_INLINE
|
||||
|
||||
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__clz(__rbit((m)));
|
||||
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m)));
|
||||
|
||||
#endif
|
||||
|
||||
@@ -539,7 +549,7 @@ unsigned int was_masked;
|
||||
|
||||
#ifdef TX_THREAD_INIT
|
||||
CHAR _tx_version_id[] =
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1 *";
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1.7 *";
|
||||
#else
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
extern CHAR _tx_version_id[100];
|
||||
@@ -548,8 +558,4 @@ extern CHAR _tx_version_id[];
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -205,6 +205,12 @@ For generic code revision information, please refer to the readme_threadx_generi
|
||||
file, which is included in your distribution. The following details the revision
|
||||
information associated with this specific port of ThreadX:
|
||||
|
||||
06-02-2021 Release 6.1.7 changes:
|
||||
tx_port.h Remove unneeded include file
|
||||
tx_thread_secure_stack_initialize.S New file
|
||||
tx_thread_schedule.S Added secure stack initialize to SVC hander
|
||||
tx_thread_secure_stack.c Fixed stack pointer save, initialize in handler mode
|
||||
|
||||
04-02-2021 Release 6.1.6 changes:
|
||||
tx_port.h Updated macro definition
|
||||
tx_thread_schedule.s Added low power support
|
||||
|
||||
@@ -19,6 +19,9 @@
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
.global _tx_execution_isr_exit
|
||||
#endif
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
@@ -68,7 +71,14 @@
|
||||
.thumb_func
|
||||
.type _tx_thread_context_restore, function
|
||||
_tx_thread_context_restore:
|
||||
/* Just return! */
|
||||
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
/* Call the ISR exit function to indicate an ISR is complete. */
|
||||
PUSH {r0, lr} // Save return address
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
POP {r0, lr} // Recover return address
|
||||
#endif
|
||||
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
|
||||
@@ -21,6 +21,9 @@
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
.global _tx_execution_isr_enter
|
||||
#endif
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
@@ -68,7 +71,16 @@
|
||||
.thumb_func
|
||||
.type _tx_thread_context_save, function
|
||||
_tx_thread_context_save:
|
||||
/* Return to interrupt processing. */
|
||||
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
/* Call the ISR enter function to indicate an ISR is starting. */
|
||||
PUSH {r0, lr} // Save return address
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
POP {r0, lr} // Recover return address
|
||||
#endif
|
||||
|
||||
/* Context is already saved - just return. */
|
||||
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
|
||||
@@ -21,6 +21,10 @@
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
.global _tx_execution_thread_enter
|
||||
.global _tx_execution_thread_exit
|
||||
#endif
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
@@ -62,6 +66,9 @@
|
||||
/* 04-02-2021 Scott Larson Modified comment(s), added */
|
||||
/* low power code, */
|
||||
/* resulting in version 6.1.6 */
|
||||
/* 06-02-2021 Scott Larson Added secure stack initialize */
|
||||
/* in SVC handler, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_schedule(VOID)
|
||||
@@ -83,9 +90,8 @@ _tx_thread_schedule:
|
||||
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
STR r0, [r2, #0] // Clear preempt disable flag
|
||||
|
||||
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
|
||||
|
||||
#ifdef __ARM_PCS_VFP
|
||||
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
BIC r0, r0, #4 // Clear the FPCA bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
@@ -121,10 +127,8 @@ __tx_wait_here:
|
||||
PendSV_Handler:
|
||||
__tx_ts_handler:
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
|
||||
CPSID i // Disable interrupts
|
||||
PUSH {r0, lr} // Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
@@ -207,11 +211,11 @@ __tx_ts_restore:
|
||||
|
||||
STR r5, [r4] // Setup global time-slice
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
/* Call the thread entry function to indicate the thread is executing. */
|
||||
PUSH {r0, r1} // Save r0/r1
|
||||
PUSH {r0, r1} // Save r0 and r1
|
||||
BL _tx_execution_thread_enter // Call the thread execution enter function
|
||||
POP {r0, r1} // Recover r0/r1
|
||||
POP {r0, r1} // Recover r0 and r1
|
||||
#endif
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
@@ -308,6 +312,9 @@ SVC_Handler:
|
||||
|
||||
CMP r1, #2 // Is it a secure stack free request?
|
||||
BEQ _tx_svc_secure_free // Yes, go there
|
||||
|
||||
CMP r1, #3 // Is it a secure stack init request?
|
||||
BEQ _tx_svc_secure_init // Yes, go there
|
||||
|
||||
// Unknown SVC argument - just return
|
||||
BX lr
|
||||
@@ -326,7 +333,12 @@ _tx_svc_secure_free:
|
||||
POP {r12,lr} // Restore SP and EXC_RETURN
|
||||
STR r0,[r12] // Store function return value
|
||||
BX lr
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
_tx_svc_secure_init:
|
||||
PUSH {r0,lr} // Save SP and EXC_RETURN
|
||||
BL _tx_thread_secure_mode_stack_initialize
|
||||
POP {r12,lr} // Restore SP and EXC_RETURN
|
||||
BX lr
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
|
||||
|
||||
.section .text
|
||||
|
||||
@@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */
|
||||
/* 6.1.1 */
|
||||
/* _tx_thread_secure_mode_stack_initialize Cortex-M33/AC6 */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
@@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
@@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 06-02-2021 Scott Larson Modified comment(s), and */
|
||||
/* changed name, execute in */
|
||||
/* handler mode, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_initialize(void)
|
||||
UINT _tx_thread_secure_mode_stack_initialize(void)
|
||||
{
|
||||
|
||||
/* Set secure mode to use PSP. */
|
||||
__set_CONTROL(__get_CONTROL() | 2);
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
__set_PSPLIM(0);
|
||||
__set_PSP(0);
|
||||
|
||||
return;
|
||||
UINT status;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set secure mode to use PSP. */
|
||||
__set_CONTROL(__get_CONTROL() | 2);
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
__set_PSPLIM(0);
|
||||
__set_PSP(0);
|
||||
|
||||
status = TX_SUCCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
@@ -332,7 +346,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_save Cortex-M33/AC6 */
|
||||
/* 6.1.1 */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
@@ -367,6 +381,8 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 06-02-2021 Scott Larson Fix stack pointer save, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
@@ -399,7 +415,7 @@ ULONG sp;
|
||||
}
|
||||
|
||||
/* Save stack pointer. */
|
||||
*(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp;
|
||||
info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp;
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
|
||||
@@ -20,77 +20,60 @@
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "tx_trace.h"
|
||||
|
||||
extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_error_notify Cortex-M33 */
|
||||
/* 6.1 */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function registers an application stack error handler. If */
|
||||
/* ThreadX detects a stack error, this application handler is called. */
|
||||
/* */
|
||||
/* This function enters the SVC handler to initialize a secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* stack_error_handler Pointer to stack error */
|
||||
/* handler, TX_NULL to disable */
|
||||
/* none */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Service return status */
|
||||
/* none */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* SVC 3 */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr))
|
||||
{
|
||||
|
||||
TX_INTERRUPT_SAVE_AREA
|
||||
|
||||
/* Disable interrupts. */
|
||||
TX_DISABLE
|
||||
|
||||
/* Make entry in event log. */
|
||||
TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS)
|
||||
|
||||
/* Make entry in event log. */
|
||||
TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT
|
||||
|
||||
/* Setup global thread stack error handler. */
|
||||
_tx_thread_application_stack_error_handler = stack_error_handler;
|
||||
|
||||
/* Restore interrupts. */
|
||||
TX_RESTORE
|
||||
|
||||
/* Return success to caller. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
// VOID _tx_thread_secure_stack_initialize(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_secure_stack_initialize
|
||||
.thumb_func
|
||||
.type _tx_thread_secure_stack_initialize, function
|
||||
_tx_thread_secure_stack_initialize:
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
CPSIE i // Enable interrupts for SVC call
|
||||
SVC 3
|
||||
CPSID i // Disable interrupts
|
||||
#else
|
||||
MOV r0, #0xFF // Feature not enabled
|
||||
#endif
|
||||
BX lr
|
||||
.end
|
||||
@@ -26,7 +26,7 @@
|
||||
/* PORT SPECIFIC C INFORMATION RELEASE */
|
||||
/* */
|
||||
/* tx_port.h Cortex-M33/GNU */
|
||||
/* 6.1.5 */
|
||||
/* 6.1.7 */
|
||||
/* */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
@@ -51,6 +51,12 @@
|
||||
/* 03-02-2021 Scott Larson Modified comment(s), added */
|
||||
/* ULONG64_DEFINED, */
|
||||
/* resulting in version 6.1.5 */
|
||||
/* 06-02-2021 Scott Larson Modified comment(s), changed */
|
||||
/* set_control and get_control */
|
||||
/* to be inline functions, */
|
||||
/* added symbol to enable */
|
||||
/* stack error handler, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
@@ -92,6 +98,12 @@ UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
|
||||
UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
|
||||
UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
|
||||
|
||||
/* This port overrides tx_thread_stack_error_notify with an architecture specific version */
|
||||
#define TX_PORT_THREAD_STACK_ERROR_NOTIFY
|
||||
|
||||
/* This port overrides tx_thread_stack_error_handler with an architecture specific version */
|
||||
#define TX_PORT_THREAD_STACK_ERROR_HANDLER
|
||||
|
||||
/* This hardware has stack checking that we take advantage of - do NOT define. */
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#error "Do not define TX_ENABLE_STACK_CHECKING"
|
||||
@@ -302,16 +314,16 @@ void _tx_misra_vfp_touch(void);
|
||||
|
||||
#ifdef TX_SOURCE_CODE
|
||||
|
||||
static unsigned int _get_control(void);
|
||||
static unsigned int _get_control(void)
|
||||
static inline unsigned int _get_control(void);
|
||||
static inline unsigned int _get_control(void)
|
||||
{
|
||||
unsigned int _control;
|
||||
__asm("MRS %[result], control" : [result] "=r" (_control) : );
|
||||
return _control;
|
||||
}
|
||||
|
||||
static void _set_control(unsigned int _control);
|
||||
static void _set_control(unsigned int _control)
|
||||
static inline void _set_control(unsigned int _control);
|
||||
static inline void _set_control(unsigned int _control)
|
||||
{
|
||||
__asm("MSR control, %[input]" : : [input] "r" (_control));
|
||||
}
|
||||
@@ -570,7 +582,7 @@ unsigned int interrupt_save;
|
||||
|
||||
#ifdef TX_THREAD_INIT
|
||||
CHAR _tx_version_id[] =
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/GNU Version 6.1 *";
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/GNU Version 6.1.7 *";
|
||||
#else
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
extern CHAR _tx_version_id[100];
|
||||
|
||||
@@ -188,6 +188,11 @@ For generic code revision information, please refer to the readme_threadx_generi
|
||||
file, which is included in your distribution. The following details the revision
|
||||
information associated with this specific port of ThreadX:
|
||||
|
||||
06-02-2021 Release 6.1.7 changes:
|
||||
tx_thread_secure_stack_initialize.S New file
|
||||
tx_thread_schedule.S Added secure stack initialize to SVC hander
|
||||
tx_thread_secure_stack.c Fixed stack pointer save, initialize in handler mode
|
||||
|
||||
04-02-2021 Release 6.1.6 changes:
|
||||
tx_port.h Updated macro definition
|
||||
tx_thread_schedule.s Added low power support
|
||||
|
||||
@@ -19,6 +19,9 @@
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
.global _tx_execution_isr_exit
|
||||
#endif
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
@@ -68,7 +71,14 @@
|
||||
.thumb_func
|
||||
.type _tx_thread_context_restore, function
|
||||
_tx_thread_context_restore:
|
||||
/* Just return! */
|
||||
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
/* Call the ISR exit function to indicate an ISR is complete. */
|
||||
PUSH {r0, lr} // Save return address
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
POP {r0, lr} // Recover return address
|
||||
#endif
|
||||
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
|
||||
@@ -68,7 +68,16 @@
|
||||
.thumb_func
|
||||
.type _tx_thread_context_save, function
|
||||
_tx_thread_context_save:
|
||||
/* Return to interrupt processing. */
|
||||
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
/* Call the ISR enter function to indicate an ISR is starting. */
|
||||
PUSH {r0, lr} // Save return address
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
POP {r0, lr} // Recover return address
|
||||
#endif
|
||||
|
||||
/* Context is already saved - just return. */
|
||||
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
|
||||
@@ -62,6 +62,9 @@
|
||||
/* 04-02-2021 Scott Larson Modified comment(s), added */
|
||||
/* low power code, */
|
||||
/* resulting in version 6.1.6 */
|
||||
/* 06-02-2021 Scott Larson Added secure stack initialize */
|
||||
/* in SVC handler, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_schedule(VOID)
|
||||
@@ -83,9 +86,8 @@ _tx_thread_schedule:
|
||||
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
STR r0, [r2, #0] // Clear preempt disable flag
|
||||
|
||||
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
|
||||
|
||||
#ifdef __ARM_PCS_VFP
|
||||
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
BIC r0, r0, #4 // Clear the FPCA bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
@@ -121,10 +123,8 @@ __tx_wait_here:
|
||||
PendSV_Handler:
|
||||
__tx_ts_handler:
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
|
||||
CPSID i // Disable interrupts
|
||||
PUSH {r0, lr} // Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
@@ -207,11 +207,11 @@ __tx_ts_restore:
|
||||
|
||||
STR r5, [r4] // Setup global time-slice
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
/* Call the thread entry function to indicate the thread is executing. */
|
||||
PUSH {r0, r1} // Save r0/r1
|
||||
PUSH {r0, r1} // Save r0 and r1
|
||||
BL _tx_execution_thread_enter // Call the thread execution enter function
|
||||
POP {r0, r1} // Recover r0/r1
|
||||
POP {r0, r1} // Recover r0 and r1
|
||||
#endif
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
@@ -308,6 +308,9 @@ SVC_Handler:
|
||||
|
||||
CMP r1, #2 // Is it a secure stack free request?
|
||||
BEQ _tx_svc_secure_free // Yes, go there
|
||||
|
||||
CMP r1, #3 // Is it a secure stack init request?
|
||||
BEQ _tx_svc_secure_init // Yes, go there
|
||||
|
||||
// Unknown SVC argument - just return
|
||||
BX lr
|
||||
@@ -326,7 +329,12 @@ _tx_svc_secure_free:
|
||||
POP {r12,lr} // Restore SP and EXC_RETURN
|
||||
STR r0,[r12] // Store function return value
|
||||
BX lr
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
_tx_svc_secure_init:
|
||||
PUSH {r0,lr} // Save SP and EXC_RETURN
|
||||
BL _tx_thread_secure_mode_stack_initialize
|
||||
POP {r12,lr} // Restore SP and EXC_RETURN
|
||||
BX lr
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
|
||||
|
||||
.section .text
|
||||
|
||||
@@ -61,8 +61,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M33/GNU */
|
||||
/* 6.1.1 */
|
||||
/* _tx_thread_secure_mode_stack_initialize Cortex-M33/GNU */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
@@ -77,7 +77,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
@@ -97,24 +97,40 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 06-02-2021 Scott Larson Change name, execute in */
|
||||
/* handler mode, */
|
||||
/* disable optimizations, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_initialize(void)
|
||||
__attribute__((cmse_nonsecure_entry, optimize(0)))
|
||||
UINT _tx_thread_secure_mode_stack_initialize(void)
|
||||
{
|
||||
ULONG control;
|
||||
|
||||
/* Set secure mode to use PSP. */
|
||||
asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */
|
||||
control |= 2; /* Use PSP. */
|
||||
asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
asm volatile("MSR PSPLIM, %0" :: "r" (0));
|
||||
asm volatile("MSR PSP, %0" :: "r" (0));
|
||||
|
||||
return;
|
||||
UINT status;
|
||||
ULONG control;
|
||||
ULONG ipsr;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
|
||||
if (ipsr == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set secure mode to use PSP. */
|
||||
asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */
|
||||
control |= 2; /* Use PSP. */
|
||||
asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
asm volatile("MSR PSPLIM, %0" :: "r" (0));
|
||||
asm volatile("MSR PSP, %0" :: "r" (0));
|
||||
|
||||
status = TX_SUCCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
@@ -339,7 +355,7 @@ ULONG ipsr;
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_save Cortex-M33/GNU */
|
||||
/* 6.1.1 */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
@@ -374,6 +390,8 @@ ULONG ipsr;
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 06-02-2021 Scott Larson Fix stack pointer save, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
@@ -408,7 +426,7 @@ ULONG ipsr;
|
||||
}
|
||||
|
||||
/* Save stack pointer. */
|
||||
*(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp;
|
||||
info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp;
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
|
||||
@@ -20,74 +20,60 @@
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/* Define the global function pointer for stack error handling. If a stack error is
|
||||
detected and the application has registered a stack error handler, it will be
|
||||
called via this function pointer. */
|
||||
|
||||
VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_error_handler Cortex-M33 */
|
||||
/* 6.1 */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M33/GNU */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function processes stack errors detected during run-time. */
|
||||
/* */
|
||||
/* This function enters the SVC handler to initialize a secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* none */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* none */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_terminate */
|
||||
/* _tx_thread_application_stack_error_handler */
|
||||
/* SVC 3 */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* ThreadX internal code */
|
||||
/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr)
|
||||
{
|
||||
#ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR
|
||||
/* Is there a thread? */
|
||||
if (thread_ptr)
|
||||
{
|
||||
/* Terminate the current thread. */
|
||||
_tx_thread_terminate(_tx_thread_current_ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Determine if the application has registered an error handler. */
|
||||
if (_tx_thread_application_stack_error_handler != TX_NULL)
|
||||
{
|
||||
/* Yes, an error handler is present, simply call the application error handler. */
|
||||
(_tx_thread_application_stack_error_handler)(thread_ptr);
|
||||
}
|
||||
}
|
||||
// VOID _tx_thread_secure_stack_initialize(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_secure_stack_initialize
|
||||
.thumb_func
|
||||
.type _tx_thread_secure_stack_initialize, function
|
||||
_tx_thread_secure_stack_initialize:
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
CPSIE i // Enable interrupts for SVC call
|
||||
SVC 3
|
||||
CPSID i // Disable interrupts
|
||||
#else
|
||||
MOV r0, #0xFF // Feature not enabled
|
||||
#endif
|
||||
BX lr
|
||||
.end
|
||||
@@ -26,7 +26,7 @@
|
||||
/* PORT SPECIFIC C INFORMATION RELEASE */
|
||||
/* */
|
||||
/* tx_port.h Cortex-M33/IAR */
|
||||
/* 6.1.5 */
|
||||
/* 6.1.7 */
|
||||
/* */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
@@ -51,6 +51,10 @@
|
||||
/* 03-02-2021 Scott Larson Modified comment(s), added */
|
||||
/* ULONG64_DEFINED, */
|
||||
/* resulting in version 6.1.5 */
|
||||
/* 06-02-2021 Yuxin Zhou Modified comment(s), and */
|
||||
/* added symbol to enable */
|
||||
/* stack error handler, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
@@ -97,6 +101,12 @@ UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
|
||||
UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
|
||||
UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
|
||||
|
||||
/* This port overrides tx_thread_stack_error_notify with an architecture specific version */
|
||||
#define TX_PORT_THREAD_STACK_ERROR_NOTIFY
|
||||
|
||||
/* This port overrides tx_thread_stack_error_handler with an architecture specific version */
|
||||
#define TX_PORT_THREAD_STACK_ERROR_HANDLER
|
||||
|
||||
/* This hardware has stack checking that we take advantage of - do NOT define. */
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#error "Do not define TX_ENABLE_STACK_CHECKING"
|
||||
@@ -258,14 +268,7 @@ ULONG _tx_misra_time_stamp_get(VOID);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
#define TX_THREAD_EXTENSION_3
|
||||
#else
|
||||
#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \
|
||||
unsigned long long tx_thread_execution_time_last_start;
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the port extensions of the remaining ThreadX objects. */
|
||||
|
||||
@@ -504,12 +507,6 @@ extern void _tx_thread_secure_stack_initialize(void);
|
||||
is used to define a local function save area for the disable and restore
|
||||
macros. */
|
||||
|
||||
/* The embedded assembler blocks are design so as to be inlinable by the
|
||||
armlink linker inlining. This requires them to consist of either a
|
||||
single 32-bit instruction, or either one or two 16-bit instructions
|
||||
followed by a "BX lr". Note that to reduce the critical region size, the
|
||||
16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */
|
||||
|
||||
#ifdef TX_DISABLE_INLINE
|
||||
|
||||
UINT _tx_thread_interrupt_disable(VOID);
|
||||
@@ -560,7 +557,7 @@ __istate_t interrupt_save;
|
||||
|
||||
#ifdef TX_THREAD_INIT
|
||||
CHAR _tx_version_id[] =
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.1 *";
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.1.7 *";
|
||||
#else
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
extern CHAR _tx_version_id[100];
|
||||
@@ -569,8 +566,4 @@ extern CHAR _tx_version_id[];
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -199,6 +199,11 @@ For generic code revision information, please refer to the readme_threadx_generi
|
||||
file, which is included in your distribution. The following details the revision
|
||||
information associated with this specific port of ThreadX:
|
||||
|
||||
06-02-2021 Release 6.1.7 changes:
|
||||
tx_thread_secure_stack_initialize.s New file
|
||||
tx_thread_schedule.s Added secure stack initialize to SVC hander
|
||||
tx_thread_secure_stack.c Fixed stack pointer save, initialize in handler mode
|
||||
|
||||
04-02-2021 Release 6.1.6 changes:
|
||||
tx_port.h Updated macro definition
|
||||
tx_thread_schedule.s Added low power support
|
||||
|
||||
@@ -1,26 +1,25 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
EXTERN _tx_thread_current_ptr
|
||||
EXTERN _tx_thread_execute_ptr
|
||||
EXTERN _tx_timer_time_slice
|
||||
@@ -32,320 +31,313 @@
|
||||
EXTERN _tx_thread_secure_stack_context_save
|
||||
EXTERN _tx_thread_secure_mode_stack_allocate
|
||||
EXTERN _tx_thread_secure_mode_stack_free
|
||||
EXTERN _tx_thread_secure_mode_stack_initialize
|
||||
#ifdef TX_LOW_POWER
|
||||
EXTERN tx_low_power_enter
|
||||
EXTERN tx_low_power_exit
|
||||
#endif
|
||||
;
|
||||
;
|
||||
SECTION `.text`:CODE:NOROOT(2)
|
||||
THUMB
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Cortex-M33/IAR */
|
||||
;/* 6.1.6 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function waits for a thread control block pointer to appear in */
|
||||
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
;/* in the variable, the corresponding thread is resumed. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* _tx_thread_system_return Return to system from thread */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* 04-02-2021 Scott Larson Modified comment(s), added */
|
||||
;/* low power code, */
|
||||
;/* resulting in version 6.1.6 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_schedule(VOID)
|
||||
;{
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_schedule Cortex-M33/IAR */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function waits for a thread control block pointer to appear in */
|
||||
/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
/* in the variable, the corresponding thread is resumed. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* _tx_thread_system_return Return to system from thread */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 04-02-2021 Scott Larson Modified comment(s), added */
|
||||
/* low power code, */
|
||||
/* resulting in version 6.1.6 */
|
||||
/* 06-02-2021 Scott Larson Added secure stack initialize */
|
||||
/* in SVC handler, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_schedule(VOID)
|
||||
// {
|
||||
PUBLIC _tx_thread_schedule
|
||||
_tx_thread_schedule:
|
||||
;
|
||||
; /* This function should only ever be called on Cortex-M
|
||||
; from the first schedule request. Subsequent scheduling occurs
|
||||
; from the PendSV handling routines below. */
|
||||
;
|
||||
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
;
|
||||
MOV r0, #0 ; Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
|
||||
STR r0, [r2, #0] ; Clear preempt disable flag
|
||||
;
|
||||
; /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
|
||||
;
|
||||
/* This function should only ever be called on Cortex-M
|
||||
from the first schedule request. Subsequent scheduling occurs
|
||||
from the PendSV handling routine below. */
|
||||
|
||||
/* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
MOV r0, #0 // Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
STR r0, [r2, #0] // Clear preempt disable flag
|
||||
|
||||
#ifdef __ARMVFP__
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
BIC r0, r0, #4 ; Clear the FPCA bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
/* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
BIC r0, r0, #4 // Clear the FPCA bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
#endif
|
||||
;
|
||||
; /* Enable interrupts */
|
||||
;
|
||||
|
||||
/* Enable interrupts */
|
||||
CPSIE i
|
||||
;
|
||||
; /* Enter the scheduler for the first time. */
|
||||
;
|
||||
MOV r0, #0x10000000 ; Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 ; Load NVIC base
|
||||
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
|
||||
DSB ; Complete all memory accesses
|
||||
ISB ; Flush pipeline
|
||||
;
|
||||
; /* Wait here for the PendSV to take place. */
|
||||
;
|
||||
|
||||
/* Enter the scheduler for the first time. */
|
||||
|
||||
MOV r0, #0x10000000 // Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 // Load NVIC base
|
||||
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
|
||||
DSB // Complete all memory accesses
|
||||
ISB // Flush pipeline
|
||||
|
||||
/* Wait here for the PendSV to take place. */
|
||||
|
||||
__tx_wait_here:
|
||||
B __tx_wait_here ; Wait for the PendSV to happen
|
||||
;}
|
||||
;
|
||||
; /* Generic context switching PendSV handler. */
|
||||
;
|
||||
B __tx_wait_here // Wait for the PendSV to happen
|
||||
// }
|
||||
|
||||
/* Generic context switching PendSV handler. */
|
||||
|
||||
PUBLIC PendSV_Handler
|
||||
PendSV_Handler:
|
||||
;
|
||||
; /* Get current thread value and new thread pointer. */
|
||||
;
|
||||
__tx_ts_handler:
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
POP {r0, lr} ; Recover LR
|
||||
CPSIE i ; Enable interrupts
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
CPSID i // Disable interrupts
|
||||
PUSH {r0, lr} // Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
POP {r0, lr} // Recover LR
|
||||
CPSIE i // Enable interrupts
|
||||
#endif
|
||||
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
|
||||
MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address
|
||||
MOV r3, #0 ; Build NULL value
|
||||
LDR r1, [r0] ; Pickup current thread pointer
|
||||
;
|
||||
; /* Determine if there is a current thread to finish preserving. */
|
||||
;
|
||||
CBZ r1, __tx_ts_new ; If NULL, skip preservation
|
||||
;
|
||||
; /* Recover PSP and preserve current thread context. */
|
||||
;
|
||||
STR r3, [r0] ; Set _tx_thread_current_ptr to NULL
|
||||
MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer)
|
||||
STMDB r12!, {r4-r11} ; Save its remaining registers
|
||||
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
|
||||
MOV r3, #0 // Build NULL value
|
||||
LDR r1, [r0] // Pickup current thread pointer
|
||||
|
||||
/* Determine if there is a current thread to finish preserving. */
|
||||
|
||||
CBZ r1, __tx_ts_new // If NULL, skip preservation
|
||||
|
||||
/* Recover PSP and preserve current thread context. */
|
||||
|
||||
STR r3, [r0] // Set _tx_thread_current_ptr to NULL
|
||||
MRS r12, PSP // Pickup PSP pointer (thread's stack pointer)
|
||||
STMDB r12!, {r4-r11} // Save its remaining registers
|
||||
#ifdef __ARMVFP__
|
||||
TST LR, #0x10 ; Determine if the VFP extended frame is present
|
||||
TST LR, #0x10 // Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_save
|
||||
VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers
|
||||
VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers
|
||||
_skip_vfp_save:
|
||||
#endif
|
||||
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
|
||||
STMDB r12!, {LR} ; Save LR on the stack
|
||||
STR r12, [r1, #8] ; Save the thread stack pointer
|
||||
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
|
||||
STMDB r12!, {LR} // Save LR on the stack
|
||||
STR r12, [r1, #8] // Save the thread stack pointer
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
; Save secure context
|
||||
LDR r5, [r1,#0x90] ; Load secure stack index
|
||||
CBZ r5, _skip_secure_save ; Skip save if there is no secure context
|
||||
PUSH {r0,r1,r2,r3} ; Save scratch registers
|
||||
MOV r0, r1 ; Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_save ; Save secure stack
|
||||
POP {r0,r1,r2,r3} ; Restore secure registers
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
// Save secure context
|
||||
LDR r5, [r1,#0x90] // Load secure stack index
|
||||
CBZ r5, _skip_secure_save // Skip save if there is no secure context
|
||||
PUSH {r0,r1,r2,r3} // Save scratch registers
|
||||
MOV r0, r1 // Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_save // Save secure stack
|
||||
POP {r0,r1,r2,r3} // Restore secure registers
|
||||
_skip_secure_save:
|
||||
#endif
|
||||
;
|
||||
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
;
|
||||
LDR r5, [r4] ; Pickup current time-slice
|
||||
CBZ r5, __tx_ts_new ; If not active, skip processing
|
||||
;
|
||||
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
;
|
||||
STR r5, [r1, #24] ; Save current time-slice
|
||||
;
|
||||
; /* Clear the global time-slice. */
|
||||
;
|
||||
STR r3, [r4] ; Clear time-slice
|
||||
;
|
||||
; /* Executing thread is now completely preserved!!! */
|
||||
;
|
||||
|
||||
/* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
|
||||
LDR r5, [r4] // Pickup current time-slice
|
||||
CBZ r5, __tx_ts_new // If not active, skip processing
|
||||
|
||||
/* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
|
||||
STR r5, [r1, #24] // Save current time-slice
|
||||
|
||||
/* Clear the global time-slice. */
|
||||
|
||||
STR r3, [r4] // Clear time-slice
|
||||
|
||||
/* Executing thread is now completely preserved!!! */
|
||||
|
||||
__tx_ts_new:
|
||||
;
|
||||
; /* Now we are looking for a new thread to execute! */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
LDR r1, [r2] ; Is there another thread ready to execute?
|
||||
CBZ r1, __tx_ts_wait ; No, skip to the wait processing
|
||||
;
|
||||
; /* Yes, another thread is ready for else, make the current thread the new thread. */
|
||||
;
|
||||
STR r1, [r0] ; Setup the current thread pointer to the new thread
|
||||
CPSIE i ; Enable interrupts
|
||||
;
|
||||
; /* Increment the thread run count. */
|
||||
;
|
||||
|
||||
/* Now we are looking for a new thread to execute! */
|
||||
|
||||
CPSID i // Disable interrupts
|
||||
LDR r1, [r2] // Is there another thread ready to execute?
|
||||
CBZ r1, __tx_ts_wait // No, skip to the wait processing
|
||||
|
||||
/* Yes, another thread is ready for else, make the current thread the new thread. */
|
||||
|
||||
STR r1, [r0] // Setup the current thread pointer to the new thread
|
||||
CPSIE i // Enable interrupts
|
||||
|
||||
/* Increment the thread run count. */
|
||||
|
||||
__tx_ts_restore:
|
||||
LDR r7, [r1, #4] ; Pickup the current thread run count
|
||||
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
|
||||
LDR r5, [r1, #24] ; Pickup thread's current time-slice
|
||||
ADD r7, r7, #1 ; Increment the thread run count
|
||||
STR r7, [r1, #4] ; Store the new run count
|
||||
;
|
||||
; /* Setup global time-slice with thread's current time-slice. */
|
||||
;
|
||||
STR r5, [r4] ; Setup global time-slice
|
||||
LDR r7, [r1, #4] // Pickup the current thread run count
|
||||
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
|
||||
LDR r5, [r1, #24] // Pickup thread's current time-slice
|
||||
ADD r7, r7, #1 // Increment the thread run count
|
||||
STR r7, [r1, #4] // Store the new run count
|
||||
|
||||
/* Setup global time-slice with thread's current time-slice. */
|
||||
|
||||
STR r5, [r4] // Setup global time-slice
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread entry function to indicate the thread is executing. */
|
||||
;
|
||||
PUSH {r0, r1} ; Save r0/r1
|
||||
BL _tx_execution_thread_enter ; Call the thread execution enter function
|
||||
POP {r0, r1} ; Recover r0/r1
|
||||
/* Call the thread entry function to indicate the thread is executing. */
|
||||
PUSH {r0, r1} // Save r0 and r1
|
||||
BL _tx_execution_thread_enter // Call the thread execution enter function
|
||||
POP {r0, r1} // Recover r0 and r1
|
||||
#endif
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
; Restore secure context
|
||||
LDR r0, [r1,#0x90] ; Load secure stack index
|
||||
CBZ r0, _skip_secure_restore ; Skip restore if there is no secure context
|
||||
PUSH {r0,r1} ; Save r1 (and dummy r0)
|
||||
MOV r0, r1 ; Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_restore ; Restore secure stack
|
||||
POP {r0,r1} ; Restore r1 (and dummy r0)
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
// Restore secure context
|
||||
LDR r0, [r1,#0x90] // Load secure stack index
|
||||
CBZ r0, _skip_secure_restore // Skip restore if there is no secure context
|
||||
PUSH {r0,r1} // Save r1 (and dummy r0)
|
||||
MOV r0, r1 // Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_restore // Restore secure stack
|
||||
POP {r0,r1} // Restore r1 (and dummy r0)
|
||||
_skip_secure_restore:
|
||||
#endif
|
||||
|
||||
;
|
||||
; /* Restore the thread context and PSP. */
|
||||
;
|
||||
LDR r12, [r1, #12] ; Get stack start
|
||||
MSR PSPLIM, r12 ; Set stack limit
|
||||
LDR r12, [r1, #8] ; Pickup thread's stack pointer
|
||||
LDMIA r12!, {LR} ; Pickup LR
|
||||
/* Restore the thread context and PSP. */
|
||||
LDR r12, [r1, #12] // Get stack start
|
||||
MSR PSPLIM, r12 // Set stack limit
|
||||
LDR r12, [r1, #8] // Pickup thread's stack pointer
|
||||
LDMIA r12!, {LR} // Pickup LR
|
||||
#ifdef __ARMVFP__
|
||||
TST LR, #0x10 ; Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_restore ; If not, skip VFP restore
|
||||
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
|
||||
TST LR, #0x10 // Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_restore // If not, skip VFP restore
|
||||
VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers
|
||||
_skip_vfp_restore:
|
||||
#endif
|
||||
LDMIA r12!, {r4-r11} ; Recover thread's registers
|
||||
MSR PSP, r12 ; Setup the thread's stack pointer
|
||||
;
|
||||
; /* Return to thread. */
|
||||
;
|
||||
BX lr ; Return to thread!
|
||||
;
|
||||
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
; are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
;
|
||||
LDMIA r12!, {r4-r11} // Recover thread's registers
|
||||
MSR PSP, r12 // Setup the thread's stack pointer
|
||||
|
||||
/* Return to thread. */
|
||||
BX lr // Return to thread!
|
||||
|
||||
/* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
|
||||
__tx_ts_wait:
|
||||
CPSID i ; Disable interrupts
|
||||
LDR r1, [r2] ; Pickup the next thread to execute pointer
|
||||
STR r1, [r0] ; Store it in the current pointer
|
||||
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
|
||||
CPSID i // Disable interrupts
|
||||
LDR r1, [r2] // Pickup the next thread to execute pointer
|
||||
STR r1, [r0] // Store it in the current pointer
|
||||
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
|
||||
|
||||
#ifdef TX_LOW_POWER
|
||||
PUSH {r0-r3}
|
||||
BL tx_low_power_enter ; Possibly enter low power mode
|
||||
BL tx_low_power_enter // Possibly enter low power mode
|
||||
POP {r0-r3}
|
||||
#endif
|
||||
|
||||
#ifdef TX_ENABLE_WFI
|
||||
DSB ; Ensure no outstanding memory transactions
|
||||
WFI ; Wait for interrupt
|
||||
ISB ; Ensure pipeline is flushed
|
||||
DSB // Ensure no outstanding memory transactions
|
||||
WFI // Wait for interrupt
|
||||
ISB // Ensure pipeline is flushed
|
||||
#endif
|
||||
|
||||
#ifdef TX_LOW_POWER
|
||||
PUSH {r0-r3}
|
||||
BL tx_low_power_exit ; Exit low power mode
|
||||
BL tx_low_power_exit // Exit low power mode
|
||||
POP {r0-r3}
|
||||
#endif
|
||||
|
||||
CPSIE i ; Enable interrupts
|
||||
B __tx_ts_wait ; Loop to continue waiting
|
||||
;
|
||||
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
; already in the handler! */
|
||||
;
|
||||
CPSIE i // Enable interrupts
|
||||
B __tx_ts_wait // Loop to continue waiting
|
||||
|
||||
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
already in the handler! */
|
||||
__tx_ts_ready:
|
||||
MOV r7, #0x08000000 ; Build clear PendSV value
|
||||
MOV r8, #0xE000E000 ; Build base NVIC address
|
||||
STR r7, [r8, #0xD04] ; Clear any PendSV
|
||||
;
|
||||
; /* Re-enable interrupts and restore new thread. */
|
||||
;
|
||||
CPSIE i ; Enable interrupts
|
||||
B __tx_ts_restore ; Restore the thread
|
||||
MOV r7, #0x08000000 // Build clear PendSV value
|
||||
MOV r8, #0xE000E000 // Build base NVIC address
|
||||
STR r7, [r8, #0xD04] // Clear any PendSV
|
||||
|
||||
/* Re-enable interrupts and restore new thread. */
|
||||
CPSIE i // Enable interrupts
|
||||
B __tx_ts_restore // Restore the thread
|
||||
|
||||
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
; SVC_Handler is not needed when ThreadX is running in single mode.
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
// SVC_Handler is not needed when ThreadX is running in single mode.
|
||||
PUBLIC SVC_Handler
|
||||
SVC_Handler:
|
||||
TST lr, #0x04 ; Determine return stack from EXC_RETURN bit 2
|
||||
TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2
|
||||
ITE EQ
|
||||
MRSEQ r0, MSP ; Get MSP if return stack is MSP
|
||||
MRSNE r0, PSP ; Get PSP if return stack is PSP
|
||||
MRSEQ r0, MSP // Get MSP if return stack is MSP
|
||||
MRSNE r0, PSP // Get PSP if return stack is PSP
|
||||
|
||||
LDR r1, [r0,#24] ; Load saved PC from stack
|
||||
LDRB r1, [r1,#-2] ; Load SVC number
|
||||
LDR r1, [r0,#24] // Load saved PC from stack
|
||||
LDRB r1, [r1,#-2] // Load SVC number
|
||||
|
||||
CMP r1, #1 ; Is it a secure stack allocate request?
|
||||
BEQ _tx_svc_secure_alloc ; Yes, go there
|
||||
CMP r1, #1 // Is it a secure stack allocate request?
|
||||
BEQ _tx_svc_secure_alloc // Yes, go there
|
||||
|
||||
CMP r1, #2 ; Is it a secure stack free request?
|
||||
BEQ _tx_svc_secure_free ; Yes, go there
|
||||
CMP r1, #2 // Is it a secure stack free request?
|
||||
BEQ _tx_svc_secure_free // Yes, go there
|
||||
|
||||
CMP r1, #3 // Is it a secure stack init request?
|
||||
BEQ _tx_svc_secure_init // Yes, go there
|
||||
|
||||
; Unknown SVC argument - just return
|
||||
// Unknown SVC argument - just return
|
||||
BX lr
|
||||
|
||||
_tx_svc_secure_alloc:
|
||||
PUSH {r0,lr} ; Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} ; Load function parameters from stack
|
||||
PUSH {r0,lr} // Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} // Load function parameters from stack
|
||||
BL _tx_thread_secure_mode_stack_allocate
|
||||
POP {r12,lr} ; Restore SP and EXC_RETURN
|
||||
STR r0,[r12] ; Store function return value
|
||||
POP {r12,lr} // Restore SP and EXC_RETURN
|
||||
STR r0,[r12] // Store function return value
|
||||
BX lr
|
||||
_tx_svc_secure_free:
|
||||
PUSH {r0,lr} ; Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} ; Load function parameters from stack
|
||||
PUSH {r0,lr} // Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} // Load function parameters from stack
|
||||
BL _tx_thread_secure_mode_stack_free
|
||||
POP {r12,lr} ; Restore SP and EXC_RETURN
|
||||
STR r0,[r12] ; Store function return value
|
||||
POP {r12,lr} // Restore SP and EXC_RETURN
|
||||
STR r0,[r12] // Store function return value
|
||||
BX lr
|
||||
#endif ; End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
_tx_svc_secure_init:
|
||||
PUSH {r0,lr} // Save SP and EXC_RETURN
|
||||
BL _tx_thread_secure_mode_stack_initialize
|
||||
POP {r12,lr} // Restore SP and EXC_RETURN
|
||||
BX lr
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
|
||||
|
||||
PUBLIC _tx_vfp_access
|
||||
_tx_vfp_access:
|
||||
VMOV.F32 s0, s0 ; Simply access the VFP
|
||||
BX lr ; Return to caller
|
||||
VMOV.F32 s0, s0 // Simply access the VFP
|
||||
BX lr // Return to caller
|
||||
|
||||
END
|
||||
|
||||
@@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M33/IAR */
|
||||
/* 6.1.1 */
|
||||
/* _tx_thread_secure_mode_stack_initialize Cortex-M33/IAR */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
@@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
@@ -98,21 +98,34 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 06-02-2021 Scott Larson Change name, execute in */
|
||||
/* handler mode, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_initialize(void)
|
||||
UINT _tx_thread_secure_mode_stack_initialize(void)
|
||||
{
|
||||
|
||||
/* Set secure mode to use PSP. */
|
||||
__set_CONTROL(__get_CONTROL() | 2);
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
__set_PSPLIM(0);
|
||||
__set_PSP(0);
|
||||
|
||||
return;
|
||||
UINT status;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set secure mode to use PSP. */
|
||||
__set_CONTROL(__get_CONTROL() | 2);
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
__set_PSPLIM(0);
|
||||
__set_PSP(0);
|
||||
|
||||
status = TX_SUCCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
@@ -332,7 +345,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_save Cortex-M33/IAR */
|
||||
/* 6.1.1 */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
@@ -367,6 +380,8 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 06-02-2021 Scott Larson Fix stack pointer save, */
|
||||
/* resulting in version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
@@ -399,7 +414,7 @@ ULONG sp;
|
||||
}
|
||||
|
||||
/* Save stack pointer. */
|
||||
*(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp;
|
||||
info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp;
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
|
||||
@@ -20,101 +20,55 @@
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_initialize.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
SECTION `.text`:CODE:NOROOT(2)
|
||||
THUMB
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_free Cortex-M33 */
|
||||
/* 6.1 */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M33/IAR */
|
||||
/* 6.1.7 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function checks for errors in the secure stack free */
|
||||
/* function call. */
|
||||
/* This function enters the SVC handler to initialize a secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* none */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* none */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_free Actual stack free function */
|
||||
/* SVC 3 */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)
|
||||
{
|
||||
#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
return(TX_FEATURE_NOT_ENABLED);
|
||||
// VOID _tx_thread_secure_stack_initialize(VOID)
|
||||
// {
|
||||
EXPORT _tx_thread_secure_stack_initialize
|
||||
_tx_thread_secure_stack_initialize:
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
CPSIE i // Enable interrupts for SVC call
|
||||
SVC 3
|
||||
CPSID i // Disable interrupts
|
||||
#else
|
||||
UINT status;
|
||||
|
||||
/* Default status to success. */
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Check for an invalid thread pointer. */
|
||||
if (thread_ptr == TX_NULL)
|
||||
{
|
||||
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Now check for invalid thread ID. */
|
||||
else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
|
||||
{
|
||||
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Check for interrupt call. */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0))
|
||||
{
|
||||
/* Is call from an interrupt and not initialization? */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
|
||||
{
|
||||
/* Invalid caller of this function, return appropriate error code. */
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine if everything is okay. */
|
||||
if (status == TX_SUCCESS)
|
||||
{
|
||||
|
||||
/* Call actual secure stack allocate function. */
|
||||
status = _tx_thread_secure_stack_free(thread_ptr);
|
||||
}
|
||||
|
||||
/* Return completion status. */
|
||||
return(status);
|
||||
MOV r0, #0xFF // Feature not enabled
|
||||
#endif
|
||||
}
|
||||
BX lr
|
||||
END
|
||||
Reference in New Issue
Block a user