diff --git a/README.md b/README.md
index 083368bb..92f79ff9 100644
--- a/README.md
+++ b/README.md
@@ -36,7 +36,7 @@ $ git clone https://github.com/azure-rtos/threadx.git
 
 ## Building as a static library
 
-Each component of Azure RTOS comes with a composible CMake-based build system that supports many different MCUs and host systems. Integrating any of these components into your device app code is as simple as adding a git submodule and then including it in your build using the CMake command `add_subdirectory()`.
+Each component of Azure RTOS comes with a composable CMake-based build system that supports many different MCUs and host systems. Integrating any of these components into your device app code is as simple as adding a git submodule and then including it in your build using the CMake command `add_subdirectory()`.
 
 While the typical usage pattern is to include threadx into your device code source tree to be built & linked with your code, you can compile this project as a standalone static library to confirm your build is set up correctly.
 
@@ -103,7 +103,7 @@ The following are references to additional Azure RTOS and Azure IoT in general:
 |   |   |
 |---|---|
 | TraceX Installer | https://aka.ms/azrtos-tracex-installer |
-| Azure RTOS Documenation and Guides: | https://docs.microsoft.com/azure/rtos |
+| Azure RTOS Documentation and Guides: | https://docs.microsoft.com/azure/rtos |
 | Azure RTOS Website: | https://azure.microsoft.com/services/rtos/ |
 | Azure RTOS Sales Questions: | https://azure-rtos.ms-iot-contact.com/ |
 | For technical questions check out Microsoft Q/A for Azure IoT: | https://aka.ms/QnA/azure-rtos |
diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h
index 4b7dbc51..140e4cc2 100644
--- a/common/inc/tx_api.h
+++ b/common/inc/tx_api.h
@@ -26,7 +26,7 @@
 /*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
 /*                                                                        */
 /*    tx_api.h                                            PORTABLE C      */
-/*                                                           6.1.2        */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    William E. Lamie, Microsoft Corporation                             */
@@ -58,6 +58,9 @@
 /*                                            moved TX_THREAD_GET_SYSTEM_ */
 /*                                            STATE to tx_api.h,          */
 /*                                            resulting in version 6.1.2  */
+/*  12-31-2020     William E. Lamie         Modified comment(s), and      */
+/*                                            increased patch version,    */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -90,7 +93,7 @@ extern   "C" {
 #define AZURE_RTOS_THREADX
 #define THREADX_MAJOR_VERSION           6
 #define THREADX_MINOR_VERSION           1
-#define THREADX_PATCH_VERSION           2
+#define THREADX_PATCH_VERSION           3
 
 /* Define the following symbol for backward compatibility */
 #define EL_PRODUCT_THREADX
diff --git a/common_modules/inc/txm_module.h b/common_modules/inc/txm_module.h
index bac2c581..aa9d2f92 100644
--- a/common_modules/inc/txm_module.h
+++ b/common_modules/inc/txm_module.h
@@ -10,37 +10,40 @@
 /**************************************************************************/
 
 
-/**************************************************************************/ 
-/**************************************************************************/ 
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
-/**                                                                       */ 
-/**   Module Interface (API)                                              */ 
-/**                                                                       */ 
-/**************************************************************************/ 
-/**************************************************************************/ 
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Interface (API)                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
 
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  APPLICATION INTERFACE DEFINITION                       RELEASE        */ 
-/*                                                                        */ 
-/*    txm_module.h                                        PORTABLE C      */ 
-/*                                                           6.1          */
+/**************************************************************************/
+/*                                                                        */
+/*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
+/*                                                                        */
+/*    txm_module.h                                        PORTABLE C      */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
 /*                                                                        */
-/*  DESCRIPTION                                                           */ 
-/*                                                                        */ 
-/*    This file defines the basic module constants, interface structures, */ 
-/*    and function prototypes.                                            */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file defines the basic module constants, interface structures, */
+/*    and function prototypes.                                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
-/*  09-30-2020     Scott Larson             Initial Version 6.1           */
+/*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  12-31-2020      Scott Larson            Modified comment(s), added    */
+/*                                            port-specific extension,    */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -329,6 +332,8 @@ extern   "C" {
 #define TXM_MODULE_OBJECT_ALLOCATE_CALL                     95
 #define TXM_MODULE_OBJECT_DEALLOCATE_CALL                   96
 
+#define TXM_MODULE_PORT_EXTENSION_API_ID_START              500
+#define TXM_MODULE_PORT_EXTENSION_API_ID_END                999
 
 /* Determine the API call IDs for other components.  */
 
@@ -508,7 +513,7 @@ typedef struct TXM_MODULE_ALLOCATED_OBJECT_STRUCT
                         *txm_module_allocated_object_next,
                         *txm_module_allocated_object_previous;
     ULONG               txm_module_object_size;
-} TXM_MODULE_ALLOCATED_OBJECT;                  
+} TXM_MODULE_ALLOCATED_OBJECT;
 
 
 /*  Determine if module code is being compiled. If so, remap the ThreadX API to 
@@ -571,6 +576,7 @@ VOID  _txm_module_usbx_duo_callback_request(TXM_MODULE_CALLBACK_MESSAGE *callbac
    resident portion of the application.  */
    
 #define txm_module_manager_initialize                   _txm_module_manager_initialize
+#define txm_module_manager_absolute_load                _txm_module_manager_absolute_load
 #define txm_module_manager_in_place_load                _txm_module_manager_in_place_load
 #define txm_module_manager_file_load                    _txm_module_manager_file_load
 #define txm_module_manager_memory_load                  _txm_module_manager_memory_load
@@ -607,6 +613,7 @@ UINT  _txm_module_manager_application_request(ULONG request, ALIGN_TYPE param_1,
 UINT  _txm_module_manager_file_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, FX_MEDIA *media_ptr, CHAR *file_name);
 #endif
 UINT  _txm_module_manager_initialize(VOID *module_memory_start, ULONG module_memory_size);
+UINT  _txm_module_manager_absolute_load(TXM_MODULE_INSTANCE *module_instance, CHAR *name, VOID *module_location);
 UINT  _txm_module_manager_in_place_load(TXM_MODULE_INSTANCE *module_instance, CHAR *name, VOID *module_location);
 UINT  _txm_module_manager_internal_load(TXM_MODULE_INSTANCE *module_instance, CHAR *name, VOID *module_location, 
                                         ULONG code_size, VOID *code_allocation_ptr, ULONG code_allocation_size);
diff --git a/common_modules/module_manager/src/txm_module_manager_absolute_load.c b/common_modules/module_manager/src/txm_module_manager_absolute_load.c
new file mode 100644
index 00000000..f0868234
--- /dev/null
+++ b/common_modules/module_manager/src/txm_module_manager_absolute_load.c
@@ -0,0 +1,439 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_mutex.h"
+#include "tx_thread.h"
+#include "tx_byte_pool.h"
+#include "txm_module.h"
+#include "txm_module_manager_util.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_absolute_load                   PORTABLE C      */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function ensures the code-related and data-related parts of    */
+/*    the module preamble are valid and prepares the module for           */
+/*    execution.                                                          */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Module instance pointer           */
+/*    module_name                       Module name pointer               */
+/*    module_location                   Module code location              */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_byte_allocate                 Allocate data area                */
+/*    _tx_mutex_get                     Get protection mutex              */
+/*    _tx_mutex_put                     Release protection mutex          */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT  _txm_module_manager_absolute_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location)
+{
+
+TX_INTERRUPT_SAVE_AREA
+
+TXM_MODULE_PREAMBLE     *module_preamble;
+ULONG                   code_size;
+ULONG                   code_alignment;
+ULONG                   code_allocation_size_ignored;
+UINT                    status;
+
+TXM_MODULE_INSTANCE     *next_module, *previous_module;
+ULONG                   start_stop_stack_size;
+ULONG                   callback_stack_size;
+ULONG                   code_size_ignored;
+ULONG                   code_alignment_ignored;
+ALIGN_TYPE              data_start;
+ULONG                   data_size;
+ULONG                   data_alignment;
+ULONG                   data_allocation_size;
+ULONG                   module_properties;
+CHAR                    *memory_ptr;
+
+
+    /* Check for interrupt call.  */
+    if (TX_THREAD_GET_SYSTEM_STATE() != 0)
+    {
+
+        /* Now, make sure the call is from an interrupt and not initialization.  */
+        if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
+        {
+
+            /* Invalid caller of this function, return appropriate error code.  */
+            return(TX_CALLER_ERROR);
+        }
+    }
+
+    /* Determine if the module manager has not been initialized yet.  */
+    if (_txm_module_manager_ready != TX_TRUE)
+    {
+
+        /* Module manager has not been initialized.  */
+        return(TX_NOT_AVAILABLE);
+    }
+
+    /* Determine if the module is valid.  */
+    if (module_instance == TX_NULL)
+    {
+
+        /* Invalid module pointer.  */
+        return(TX_PTR_ERROR);
+    }
+
+    /* Get module manager protection mutex.  */
+    _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
+
+    /* Determine if the module is already valid.  */
+    if (module_instance -> txm_module_instance_id == TXM_MODULE_ID)
+    {
+
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+
+        /* Module already loaded.  */
+        return(TXM_MODULE_ALREADY_LOADED);
+    }
+
+    /* Pickup the module's information.  */
+    module_preamble = (TXM_MODULE_PREAMBLE *) module_location;
+
+    /* Check to make sure there is a valid module to load.  */
+    if (module_preamble -> txm_module_preamble_id != TXM_MODULE_ID)
+    {
+
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+
+        /* Invalid module preamble.  */
+        return(TXM_MODULE_INVALID);
+    }
+
+    /* Check the properties of this module.  */
+    module_properties =  module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_OPTIONS_MASK;
+    if (/* Ensure the requested properties are supported.  */
+        ((module_properties & _txm_module_manager_properties_supported) != module_properties) ||
+        /* Ensure the required properties are there.  */
+        ((_txm_module_manager_properties_required & module_properties) != _txm_module_manager_properties_required) ||
+        /* If memory protection is enabled, then so must user mode.  */
+        ((module_properties & TXM_MODULE_MEMORY_PROTECTION) && !(module_properties & TXM_MODULE_USER_MODE))
+        )
+    {
+
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+
+        /* Invalid properties. Return error.  */
+        return(TXM_MODULE_INVALID_PROPERTIES);
+    }
+
+    /* Check for valid module entry offsets.  */
+    if ((module_preamble -> txm_module_preamble_shell_entry_function == 0) ||
+        (module_preamble -> txm_module_preamble_start_function == 0))
+    {
+
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+
+        /* Invalid module preamble.  */
+        return(TXM_MODULE_INVALID);
+    }
+
+    /* Check for valid sizes.  */
+    if ((module_preamble -> txm_module_preamble_code_size == 0) ||
+     /* (module_preamble -> txm_module_preamble_data_size == 0) || *** a zero data size is valid */
+        (module_preamble -> txm_module_preamble_start_stop_stack_size == 0) ||
+        (module_preamble -> txm_module_preamble_callback_stack_size == 0))
+    {
+
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+
+        /* Invalid module preamble.  */
+        return(TXM_MODULE_INVALID);
+    }
+
+    /* Get the amount of the bytes we need to allocate for the module's code
+       as well as the required alignment. Note that because this is an absolute
+       load, we only want the code alignment so we can check it.  */
+    status =  _txm_module_manager_util_code_allocation_size_and_alignment_get(module_preamble, &code_alignment, &code_allocation_size_ignored);
+    if (status != TX_SUCCESS)
+    {
+
+        /* Math overflow error occurred.  */
+        return(status);
+    }
+
+    /* Since this is an absolute load, check the alignment of the module's instruction area (code).  */
+    TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment)
+
+    /* Initialize module control block to all zeros.  */
+    TX_MEMSET(module_instance, 0, sizeof(TXM_MODULE_INSTANCE));
+
+    /* Pickup the basic module sizes.  */
+    code_size =              module_preamble -> txm_module_preamble_code_size;
+    data_size =              module_preamble -> txm_module_preamble_data_size;
+    start_stop_stack_size =  module_preamble -> txm_module_preamble_start_stop_stack_size;
+    callback_stack_size =    module_preamble -> txm_module_preamble_callback_stack_size;
+
+    TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_size, TXM_MODULE_DATA_ALIGNMENT, data_size);
+    data_size =              ((data_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
+
+    /* Adjust the size of the module elements to be aligned to the default alignment. We do this
+       so that when we partition the allocated memory, we can simply place these regions right beside
+       each other without having to align their pointers. Note this only works when they all have
+       the same alignment.  */
+
+    TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(start_stop_stack_size, TXM_MODULE_DATA_ALIGNMENT, start_stop_stack_size);
+    start_stop_stack_size =  ((start_stop_stack_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
+
+    TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(callback_stack_size, TXM_MODULE_DATA_ALIGNMENT, callback_stack_size);
+    callback_stack_size =    ((callback_stack_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
+
+    /* Update the data size to account for the default thread stacks.  */
+    data_allocation_size = 0;
+    TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_allocation_size, start_stop_stack_size, data_allocation_size);
+    TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_allocation_size, callback_stack_size, data_allocation_size);
+
+    /* Setup the default code and data alignments.  */
+    data_alignment =  (ULONG) TXM_MODULE_DATA_ALIGNMENT;
+
+    /* Get the port-specific alignment for the data size. Note we only want data
+       so we pass values of 1 for code (to avoid any possible div by 0 errors).  */
+    code_size_ignored = 1;
+    code_alignment_ignored = 1;
+    TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size_ignored, code_alignment_ignored, data_allocation_size, data_alignment)
+
+    /* Calculate the module's total RAM memory requirement. This entire area is allocated from the module
+       manager's byte pool. The general layout is defined as follows:
+
+    Lowest Address:         Start of start/stop thread stack
+                            ... [note: thread entry info is embedded near end of stack areas]
+                            End of start/stop thread stack
+
+                            Start of callback thread stack
+                            ... [note: thread entry info is embedded near end of stack areas]
+                            End of callback thread stack
+
+    Highest Address:    */
+
+    /* Add an extra alignment increment so we can align the pointer after allocation.  */
+    TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_allocation_size, data_alignment, data_allocation_size);
+
+    /* Allocate memory for the module.  */
+    status =  _tx_byte_allocate(&_txm_module_manager_byte_pool, (VOID **) &memory_ptr, data_allocation_size, TX_NO_WAIT);
+
+    /* Determine if the module memory allocation was successful.  */
+    if (status)
+    {
+
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+
+        /* No memory, return an error.  */
+        return(TX_NO_MEMORY);
+    }
+
+    /* Clear the allocated memory.  */
+    TX_MEMSET(memory_ptr, ((UCHAR) 0), data_allocation_size);
+
+    /* Disable interrupts.  */
+    TX_DISABLE
+
+    /* Setup the module instance structure.  */
+    module_instance -> txm_module_instance_id = TXM_MODULE_ID;
+
+    /* Save the module name.  */
+    module_instance -> txm_module_instance_name =  module_name;
+
+    /* Save the module properties.  */
+    module_instance -> txm_module_instance_property_flags =  module_preamble -> txm_module_preamble_property_flags;
+
+    /* Set the module data memory allocation. This is the address released
+       when the module is unloaded.  */
+    module_instance -> txm_module_instance_data_allocation_ptr =  (VOID *) memory_ptr;
+
+    /* Save the data allocation size.  */
+    module_instance -> txm_module_instance_data_allocation_size =   data_allocation_size;
+
+    /* Calculate the actual start of the data area. This needs to be adjusted based on the alignment.  */
+    data_start =  (ALIGN_TYPE) memory_ptr;
+    data_start =  (data_start + (((ALIGN_TYPE)data_alignment) - 1)) & ~(((ALIGN_TYPE)data_alignment) - 1);
+    memory_ptr =  (CHAR *) data_start;
+
+    /* Compute the beginning and end of the data area. */
+#ifdef ALIGN_TYPE_DEFINED
+    module_instance -> txm_module_instance_data_start =  (VOID *) (((CHAR *) (ALIGN_TYPE) module_preamble->txm_module_preamble_code_size) + sizeof(TXM_MODULE_PREAMBLE));
+    module_instance -> txm_module_instance_data_end =  (VOID *) (((CHAR *) (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) + module_preamble->txm_module_preamble_data_size);
+#else
+    module_instance -> txm_module_instance_data_start =  (VOID *) (((CHAR *) module_preamble->txm_module_preamble_code_size) + sizeof(TXM_MODULE_PREAMBLE));
+    module_instance -> txm_module_instance_data_end =  (VOID *) (((CHAR *) module_instance -> txm_module_instance_data_start) + module_preamble->txm_module_preamble_data_size);
+#endif
+
+    /* Save the size of the data area.  */
+    module_instance -> txm_module_instance_data_size =  data_size;
+
+    /* Set the module code memory allocation. This is the address released
+       when the module is unloaded.  */
+    module_instance -> txm_module_instance_code_allocation_ptr =  (VOID *) NULL;
+
+    /* Save the code allocation size.  */
+    module_instance -> txm_module_instance_code_allocation_size =   0;
+
+    /* Setup the code pointers.  Since the code was loaded in-place, this is effectively just the values supplied in the API call.  */
+    module_instance -> txm_module_instance_code_start =     (VOID *) module_location;
+    module_instance -> txm_module_instance_code_end =       (VOID *) (((CHAR *) module_location) + (code_size - 1));
+
+    /* Setup the code size.  */
+    module_instance -> txm_module_instance_code_size =      code_size;
+
+    /* Save the module's total memory usage.  */
+    module_instance -> txm_module_instance_total_ram_usage =  0 /* Code is executed in place */ + data_allocation_size /* just the size of stacks */;
+
+    /* Set the module state to started.  */
+    module_instance -> txm_module_instance_state =  TXM_MODULE_LOADED;
+
+    /* Save the preamble pointer.  */
+    module_instance -> txm_module_instance_preamble_ptr =  module_preamble;
+
+    /* Save the module application ID in the module instance.  */
+    module_instance -> txm_module_instance_application_module_id =  module_preamble -> txm_module_preamble_application_module_id;
+
+    /* Setup the module's start/stop thread stack area.  */
+    module_instance -> txm_module_instance_start_stop_stack_start_address =  (VOID *) (memory_ptr);
+    module_instance -> txm_module_instance_start_stop_stack_size =           start_stop_stack_size;
+    module_instance -> txm_module_instance_start_stop_stack_end_address =    (VOID *) (memory_ptr + (start_stop_stack_size - 1));
+
+    /* Move the memory pointer forward.  */
+    memory_ptr =  memory_ptr + start_stop_stack_size;
+
+    /* Save the start/stop thread priority.  */
+    module_instance -> txm_module_instance_start_stop_priority =     module_preamble -> txm_module_preamble_start_stop_priority;
+
+    /* Setup the module's callback thread stack area.  */
+    module_instance -> txm_module_instance_callback_stack_start_address =  (VOID *) (memory_ptr);
+    module_instance -> txm_module_instance_callback_stack_size =           callback_stack_size;
+    module_instance -> txm_module_instance_callback_stack_end_address =    (VOID *) (memory_ptr + (callback_stack_size - 1));
+
+    /* Move the memory pointer forward.  */
+    memory_ptr =  memory_ptr + callback_stack_size;
+
+    /* Save the callback thread priority.  */
+    module_instance -> txm_module_instance_callback_priority =  module_preamble -> txm_module_preamble_callback_priority;
+
+    /* Setup the start of the module data section.  */
+    module_instance -> txm_module_instance_module_data_base_address =  (VOID *) (memory_ptr);
+
+    /* Build actual addresses based on load...  Setup all the function pointers. Any adjustments needed to shell entry, start function, and callback function are defined in the
+       module preamble. */
+#ifdef ALIGN_TYPE_DEFINED
+    module_instance -> txm_module_instance_shell_entry_function  =          (VOID (*)(TX_THREAD *, TXM_MODULE_INSTANCE *)) ((VOID *) (ALIGN_TYPE) module_preamble -> txm_module_preamble_shell_entry_function);
+    module_instance -> txm_module_instance_start_thread_entry =             (VOID (*)(ULONG)) ((VOID *) (ALIGN_TYPE) module_preamble -> txm_module_preamble_start_function);
+    module_instance -> txm_module_instance_callback_request_thread_entry =  (VOID (*)(ULONG)) ((VOID *) (ALIGN_TYPE) module_preamble -> txm_module_preamble_callback_function);
+#else
+    module_instance -> txm_module_instance_shell_entry_function  =          (VOID (*)(TX_THREAD *, TXM_MODULE_INSTANCE *)) ((VOID *) module_preamble -> txm_module_preamble_shell_entry_function);
+    module_instance -> txm_module_instance_start_thread_entry =             (VOID (*)(ULONG)) ((VOID *) module_preamble -> txm_module_preamble_start_function);
+    module_instance -> txm_module_instance_callback_request_thread_entry =  (VOID (*)(ULONG)) ((VOID *) module_preamble -> txm_module_preamble_callback_function);
+#endif
+
+    /* Determine if there is a stop function for this module.  */
+    if (module_preamble -> txm_module_preamble_stop_function)
+    {
+
+        /* Yes, there is a stop function, build the address.  */
+#ifdef ALIGN_TYPE_DEFINED
+    	module_instance -> txm_module_instance_stop_thread_entry =  (VOID (*)(ULONG)) ((VOID *) (ALIGN_TYPE) module_preamble -> txm_module_preamble_stop_function);
+#else
+    	module_instance -> txm_module_instance_stop_thread_entry =  (VOID (*)(ULONG)) ((VOID *) module_preamble -> txm_module_preamble_stop_function);
+#endif
+    }
+    else
+    {
+
+        /* No, there is no stop function. Just set the pointer to NULL.  */
+        module_instance -> txm_module_instance_stop_thread_entry =  TX_NULL;
+    }
+
+    /* Load the module control block with port-specific information. */
+    TXM_MODULE_MANAGER_MODULE_SETUP(module_instance);
+
+    /* Now add the module to the linked list of created modules.  */
+    if (_txm_module_manger_loaded_count++ == 0)
+    {
+
+        /* The loaded module list is empty.  Add module to empty list.  */
+        _txm_module_manager_loaded_list_ptr =                     module_instance;
+        module_instance -> txm_module_instance_loaded_next =      module_instance;
+        module_instance -> txm_module_instance_loaded_previous =  module_instance;
+    }
+    else
+    {
+
+        /* This list is not NULL, add to the end of the list.  */
+        next_module =      _txm_module_manager_loaded_list_ptr;
+        previous_module =  next_module -> txm_module_instance_loaded_previous;
+
+        /* Place the new module in the list.  */
+        next_module -> txm_module_instance_loaded_previous =  module_instance;
+        previous_module -> txm_module_instance_loaded_next =  module_instance;
+
+        /* Setup this module's created links.  */
+        module_instance -> txm_module_instance_loaded_previous =  previous_module;
+        module_instance -> txm_module_instance_loaded_next =      next_module;
+    }
+
+    /* Restore interrupts.  */
+    TX_RESTORE
+
+    /* Release the protection mutex.  */
+    _tx_mutex_put(&_txm_module_manager_mutex);
+
+    /* Return success.  */
+    return(TX_SUCCESS);
+}
diff --git a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c
index 63c1acc5..355de996 100644
--- a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c
+++ b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c
@@ -12,8 +12,8 @@
 
 /**************************************************************************/
 /**************************************************************************/
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
+/**                                                                       */
+/** ThreadX Component                                                     */
 /**                                                                       */
 /**   Module Manager                                                      */
 /**                                                                       */
@@ -36,50 +36,53 @@
 #include "txm_module_manager_util.h"
 #include "txm_module_manager_dispatch.h"
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  FUNCTION                                               RELEASE        */ 
-/*                                                                        */ 
-/*    _txm_module_kernel_dispatch                         PORTABLE C      */ 
-/*                                                           6.1          */
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_kernel_dispatch                 PORTABLE C      */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
 /*                                                                        */
-/*  DESCRIPTION                                                           */ 
-/*                                                                        */ 
-/*    This function dispatches the module's kernel request based upon the */ 
-/*    ID and parameters specified in the request.                         */ 
-/*                                                                        */ 
-/*  INPUT                                                                 */ 
-/*                                                                        */ 
-/*    kernel_request                    Module's kernel request           */ 
-/*    param_1                           First parameter                   */ 
-/*    param_2                           Second parameter                  */ 
-/*    param_3                           Third parameter                   */ 
-/*                                                                        */ 
-/*  OUTPUT                                                                */ 
-/*                                                                        */ 
-/*    status                            Completion status                 */ 
-/*                                                                        */ 
-/*  CALLS                                                                 */ 
-/*                                                                        */ 
-/*    _txm_module_manager_application_request   Application-specific req  */ 
-/*    _txm_module_manager_object_pointer_get    Find object pointer       */ 
-/*    _txm_module_manager_thread_create         Module thread create      */ 
-/*    [_txm_module_manager_*_dispatch]          Optional external         */ 
-/*                                                component dispatch      */ 
-/*    ThreadX API Calls                                                   */ 
-/*                                                                        */ 
-/*  CALLED BY                                                             */ 
-/*                                                                        */ 
-/*    Application code                                                    */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function dispatches the module's kernel request based upon the */
+/*    ID and parameters specified in the request.                         */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    kernel_request                    Module's kernel request           */
+/*    param_1                           First parameter                   */
+/*    param_2                           Second parameter                  */
+/*    param_3                           Third parameter                   */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_manager_application_request   Application-specific req  */
+/*    _txm_module_manager_object_pointer_get    Find object pointer       */
+/*    _txm_module_manager_thread_create         Module thread create      */
+/*    [_txm_module_manager_*_dispatch]          Optional external         */
+/*                                                component dispatch      */
+/*    ThreadX API Calls                                                   */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
-/*  09-30-2020     Scott Larson             Initial Version 6.1           */
+/*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  12-31-2020      Scott Larson            Modified comment(s), added    */
+/*                                            port-specific dispatch,     */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 ALIGN_TYPE _txm_module_manager_kernel_dispatch(ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)
@@ -679,6 +682,15 @@ TXM_MODULE_INSTANCE *module_instance;
 
     default:
     {
+#ifdef TXM_MODULE_PORT_DISPATCH
+        /* Is this a port-specific request? */
+        if ((kernel_request >= TXM_MODULE_PORT_EXTENSION_API_ID_START) && (kernel_request <= TXM_MODULE_PORT_EXTENSION_API_ID_END))
+        {
+            /* Yes, call the port-specific dispatcher. */
+            return_value = (ALIGN_TYPE) _txm_module_manager_port_dispatch(module_instance, kernel_request, param_0, param_1, param_2);
+        }
+#endif
+        
         /* Determine if an application request is present.   */
         if (kernel_request >= TXM_APPLICATION_REQUEST_ID_BASE)
         {
diff --git a/common_modules/module_manager/src/txm_module_manager_start.c b/common_modules/module_manager/src/txm_module_manager_start.c
index e793e8ef..365803b5 100644
--- a/common_modules/module_manager/src/txm_module_manager_start.c
+++ b/common_modules/module_manager/src/txm_module_manager_start.c
@@ -10,15 +10,15 @@
 /**************************************************************************/
 
 
-/**************************************************************************/ 
-/**************************************************************************/ 
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
-/**                                                                       */ 
-/**   Module Manager                                                      */ 
-/**                                                                       */ 
-/**************************************************************************/ 
-/**************************************************************************/ 
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
 
 #define TX_SOURCE_CODE
 
@@ -29,47 +29,48 @@
 #include "txm_module.h"
 
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  FUNCTION                                               RELEASE        */ 
-/*                                                                        */ 
-/*    _txm_module_manager_start                           PORTABLE C      */ 
-/*                                                           6.1          */
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_start                           PORTABLE C      */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
 /*                                                                        */
-/*  DESCRIPTION                                                           */ 
-/*                                                                        */ 
-/*    This function starts execution of the specified module.             */ 
-/*                                                                        */ 
-/*  INPUT                                                                 */ 
-/*                                                                        */ 
-/*    module_instance                   Module instance pointer           */ 
-/*                                                                        */ 
-/*  OUTPUT                                                                */ 
-/*                                                                        */ 
-/*    status                            Completion status                 */ 
-/*                                                                        */ 
-/*  CALLS                                                                 */ 
-/*                                                                        */ 
-/*    _txm_module_manager_name_build        Build module:thread name      */ 
-/*    _txm_module_manager_thread_create     Module thread create          */ 
-/*    _tx_mutex_get                         Get protection mutex          */ 
-/*    _tx_mutex_put                         Release protection mutex      */ 
-/*    _tx_queue_create                      Create module callback queue  */ 
-/*    _tx_queue_delete                      Delete module callback queue  */ 
-/*    _tx_thread_resume                     Resume start thread           */ 
-/*                                                                        */ 
-/*  CALLED BY                                                             */ 
-/*                                                                        */ 
-/*    Application code                                                    */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function starts execution of the specified module.             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Module instance pointer           */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_manager_thread_create     Module thread create          */
+/*    _tx_mutex_get                         Get protection mutex          */
+/*    _tx_mutex_put                         Release protection mutex      */
+/*    _tx_queue_create                      Create module callback queue  */
+/*    _tx_queue_delete                      Delete module callback queue  */
+/*    _tx_thread_resume                     Resume start thread           */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
-/*  09-30-2020     Scott Larson             Initial Version 6.1           */
+/*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  12-31-2020      Scott Larson            Modified comment(s),          */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 UINT  _txm_module_manager_start(TXM_MODULE_INSTANCE *module_instance)
diff --git a/common_modules/module_manager/src/txm_module_manager_thread_create.c b/common_modules/module_manager/src/txm_module_manager_thread_create.c
index 9a36d25d..58c8211e 100644
--- a/common_modules/module_manager/src/txm_module_manager_thread_create.c
+++ b/common_modules/module_manager/src/txm_module_manager_thread_create.c
@@ -21,11 +21,15 @@
 /**************************************************************************/
 
 #define TX_SOURCE_CODE
+#define TX_THREAD_SMP_SOURCE_CODE
+
+
+/* Include necessary system files.  */
 
 #include "tx_api.h"
 #include "tx_trace.h"
-#include "tx_initialize.h"
 #include "tx_thread.h"
+#include "tx_initialize.h"
 #include "tx_timer.h"
 #include "txm_module.h"
 
@@ -35,7 +39,7 @@
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _txm_module_manager_thread_create                   PORTABLE C      */
-/*                                                           6.1          */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -47,22 +51,22 @@
 /*                                                                        */
 /*  INPUT                                                                 */
 /*                                                                        */
-/*    thread_ptr                        Thread control block pointer      */
-/*    name                              Pointer to thread name string     */
-/*    shell_function                    Shell function of the thread      */
-/*    entry_function                    Entry function of the thread      */
-/*    entry_input                       32-bit input value to thread      */
-/*    stack_start                       Pointer to start of stack         */
-/*    stack_size                        Stack size in bytes               */
-/*    priority                          Priority of thread                */
-/*                                        (default 0-31)                  */
-/*    preempt_threshold                 Preemption threshold              */
-/*    time_slice                        Thread time-slice value           */
-/*    auto_start                        Automatic start selection         */
+/*    thread_ptr                            Thread control block pointer  */
+/*    name                                  Pointer to thread name string */
+/*    shell_function                        Shell function of the thread  */
+/*    entry_function                        Entry function of the thread  */
+/*    entry_input                           32-bit input value to thread  */
+/*    stack_start                           Pointer to start of stack     */
+/*    stack_size                            Stack size in bytes           */
+/*    priority                              Priority of thread            */
+/*                                            (default 0-31)              */
+/*    preempt_threshold                     Preemption threshold          */
+/*    time_slice                            Thread time-slice value       */
+/*    auto_start                            Automatic start selection     */
 /*                                                                        */
 /*  OUTPUT                                                                */
 /*                                                                        */
-/*    status                            Completion status                 */
+/*    return status                         Thread create return status   */
 /*                                                                        */
 /*  CALLS                                                                 */
 /*                                                                        */
@@ -81,35 +85,41 @@
 /*                                                                        */
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
-/*  09-30-2020     Scott Larson             Initial Version 6.1           */
+/*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  12-31-2020      Scott Larson            Modified comment(s),          */
+/*                                            fix stack overlap checking, */
+/*                                            added 64-bit support,       */
+/*                                            added SMP support,          */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
-UINT  _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name, VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *), 
-                               VOID (*entry_function)(ULONG), ULONG entry_input,
-                               VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold,
-                               ULONG time_slice, UINT auto_start, UINT thread_control_block_size, TXM_MODULE_INSTANCE *module_instance)
+UINT  _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr,
+                            VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *),
+                            VOID (*entry_function)(ULONG id), ULONG entry_input,
+                            VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold,
+                            ULONG time_slice, UINT auto_start,
+                            UINT thread_control_block_size, TXM_MODULE_INSTANCE *module_instance)
 {
 
 TX_INTERRUPT_SAVE_AREA
 
-TX_THREAD                       *next_thread;
-TX_THREAD                       *previous_thread;
+#ifdef TX_THREAD_SMP
+UINT                    core_index;
+#endif
+TX_THREAD               *next_thread;
+TX_THREAD               *previous_thread;
 #ifndef TX_DISABLE_PREEMPTION_THRESHOLD
-TX_THREAD                       *saved_thread_ptr;
-UINT                            saved_threshold =  0;
+TX_THREAD               *saved_thread_ptr;
+UINT                    saved_threshold =  ((UINT) 0);
 #endif
+UCHAR                   *temp_ptr;
 #ifdef TX_ENABLE_STACK_CHECKING
-ULONG                           new_stack_start;
-#endif
-TXM_MODULE_THREAD_ENTRY_INFO    *thread_entry_info;
-VOID                            *stack_end;
-ULONG                           i;
-#ifndef TX_TIMER_PROCESS_IN_ISR
-TX_THREAD                       *current_thread;
-#endif
-#if TXM_MODULE_MEMORY_PROTECTION
-ULONG                           status;
+ALIGN_TYPE              new_stack_start;
+ALIGN_TYPE              updated_stack_start;
 #endif
+TXM_MODULE_THREAD_ENTRY_INFO *thread_entry_info;
+VOID                    *stack_end;
+ULONG                   i;
 
     /* First, check for an invalid thread pointer.  */
     if (thread_ptr == TX_NULL)
@@ -150,37 +160,12 @@ ULONG                           status;
         }
 
         /* Check the stack pointer to see if it overlaps with this thread's stack.  */
- 
-        /*lint -e{946} suppress pointer comparison, since this is necessary. */
-        if (((UCHAR *) ((VOID *) stack_start)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start)))
+        if ((((UCHAR *) ((VOID *) stack_start)) <= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end))) &&
+            (((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start))))
         {
-
-            /*lint -e{946} suppress pointer comparison, since this is necessary. */
-            if (((UCHAR *) ((VOID *) stack_start)) < ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end)))
-            {
-        
-                /* This stack overlaps with an existing thread, clear the stack pointer to 
-                   force a stack error below.  */
-                stack_start =  TX_NULL;
-                break;
-            }
-        }
-
-        /* Check the end of the stack to see if it is inside this thread's stack area as well.  */
-
-        /*lint -e{946} suppress pointer comparison, since this is necessary. */
-        if (((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start)))
-        {
-
-            /*lint -e{946} suppress pointer comparison, since this is necessary. */
-            if (((UCHAR *) ((VOID *) stack_end)) < ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end)))
-            {
-        
-                /* This stack overlaps with an existing thread, clear the stack pointer to 
-                   force a stack error below.  */
-                stack_start =  TX_NULL;
-                break;
-            }
+            /* Stacks overlap, clear the stack pointer to force a stack error below.  */
+            stack_start =  TX_NULL;
+            break;
         }
 
         /* Move to the next thread.  */
@@ -256,16 +241,19 @@ ULONG                           status;
     }
 
 #ifndef TX_TIMER_PROCESS_IN_ISR
-
-    /* Pickup thread pointer.  */
-    TX_THREAD_GET_CURRENT(current_thread)
-
-    /* Check for invalid caller of this function.  First check for a calling thread.  */
-    if (current_thread == &_tx_timer_thread)
     {
+        TX_THREAD *current_thread;
 
-        /* Invalid caller of this function, return appropriate error code.  */
-        return(TX_CALLER_ERROR);
+        /* Pickup thread pointer.  */
+        TX_THREAD_GET_CURRENT(current_thread)
+
+        /* Check for invalid caller of this function.  First check for a calling thread.  */
+        if (current_thread == &_tx_timer_thread)
+        {
+
+            /* Invalid caller of this function, return appropriate error code.  */
+            return(TX_CALLER_ERROR);
+        }
     }
 #endif
 
@@ -295,21 +283,22 @@ ULONG                           status;
     /* Ensure that there are two ULONG of 0xEF patterns at the top and 
        bottom of the thread's stack. This will be used to check for stack
        overflow conditions during run-time.  */
-    stack_size =  ((stack_size/sizeof(ULONG)) * sizeof(ULONG)) - sizeof(ULONG);
+    stack_size =  ((stack_size/(sizeof(ULONG))) * (sizeof(ULONG))) - (sizeof(ULONG));
 
     /* Ensure the starting stack address is evenly aligned.  */
-    new_stack_start =  ((((ULONG) stack_start) + (sizeof(ULONG) - 1) ) & (~(sizeof(ULONG) - 1)));
+    new_stack_start =  TX_POINTER_TO_ALIGN_TYPE_CONVERT(stack_start);
+    updated_stack_start =  ((((ULONG) new_stack_start) + ((sizeof(ULONG)) - ((ULONG) 1)) ) & (~((sizeof(ULONG)) - ((ULONG) 1))));
 
     /* Determine if the starting stack address is different.  */
-    if (new_stack_start != ((ULONG) stack_start))
+    if (new_stack_start != updated_stack_start)
     {
     
         /* Yes, subtract another ULONG from the size to avoid going past the stack area.  */
-        stack_size =  stack_size - sizeof(ULONG);
+        stack_size =  stack_size - (sizeof(ULONG));
     }
 
     /* Update the starting stack pointer.  */
-    stack_start =  (VOID *) new_stack_start;
+    stack_start =  TX_ALIGN_TYPE_TO_POINTER_CONVERT(updated_stack_start);
 #endif
 
     /* Allocate the thread entry information at the top of thread's stack - Leaving one 
@@ -321,53 +310,81 @@ ULONG                           status;
 
     /* Initialize thread control block to all zeros.  */
     TX_MEMSET(thread_ptr, 0, sizeof(TX_THREAD));
-    
+
 #if TXM_MODULE_MEMORY_PROTECTION
     /* If this is a memory protected module, allocate a kernel stack.  */
     if((module_instance -> txm_module_instance_property_flags) & TXM_MODULE_MEMORY_PROTECTION)
     {
+        ULONG status;
+
         /* Allocate kernel stack space. */
         status = _txm_module_manager_object_allocate((VOID **) &(thread_ptr -> tx_thread_module_kernel_stack_start), TXM_MODULE_KERNEL_STACK_SIZE, module_instance);
         if(status)
         {
             return(status);
         }
-        
+
 #ifndef TX_DISABLE_STACK_FILLING
         /* Set the thread stack to a pattern prior to creating the initial
            stack frame.  This pattern is used by the stack checking routines
            to see how much has been used.  */
         TX_MEMSET(thread_ptr -> tx_thread_module_kernel_stack_start, ((UCHAR) TX_STACK_FILL), TXM_MODULE_KERNEL_STACK_SIZE);
 #endif
-        
+
         /* Align kernel stack pointer.  */
         thread_ptr -> tx_thread_module_kernel_stack_end = (VOID *) (((ALIGN_TYPE)(thread_ptr -> tx_thread_module_kernel_stack_start) + TXM_MODULE_KERNEL_STACK_SIZE) & ~0x07);
 
         /* Set kernel stack size.  */
         thread_ptr -> tx_thread_module_kernel_stack_size = TXM_MODULE_KERNEL_STACK_SIZE;
     }
-    
+
     /* Place the stack parameters into the thread's control block.  */
-    thread_ptr -> tx_thread_module_stack_start =    stack_start;
-    thread_ptr -> tx_thread_module_stack_size =     stack_size;
+    thread_ptr -> tx_thread_module_stack_start =  stack_start;
+    thread_ptr -> tx_thread_module_stack_size =   stack_size;
 #endif
 
     /* Place the supplied parameters into the thread's control block.  */
-    thread_ptr -> tx_thread_name =              name;
-    thread_ptr -> tx_thread_entry =             entry_function;
-    thread_ptr -> tx_thread_entry_parameter =   entry_input;
-    thread_ptr -> tx_thread_stack_start =       stack_start;
-    thread_ptr -> tx_thread_stack_size =        stack_size;
-    thread_ptr -> tx_thread_stack_end =         (VOID *) (((UCHAR *) stack_start) + (stack_size-1));
+    thread_ptr -> tx_thread_name =                name_ptr;
+    thread_ptr -> tx_thread_entry =               entry_function;
+    thread_ptr -> tx_thread_entry_parameter =     entry_input;
+    thread_ptr -> tx_thread_stack_start =         stack_start;
+    thread_ptr -> tx_thread_stack_size =          stack_size;
+    thread_ptr -> tx_thread_priority =            priority;
+    thread_ptr -> tx_thread_user_priority =       priority;
+    thread_ptr -> tx_thread_time_slice =          time_slice;
+    thread_ptr -> tx_thread_new_time_slice =      time_slice;
+    thread_ptr -> tx_thread_inherit_priority =    ((UINT) TX_MAX_PRIORITIES);
+#ifdef TX_THREAD_SMP
+    thread_ptr -> tx_thread_smp_core_executing =  ((UINT) TX_THREAD_SMP_MAX_CORES);
+    thread_ptr -> tx_thread_smp_cores_excluded =  ((ULONG) 0);
+#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX
+    thread_ptr -> tx_thread_smp_cores_allowed =   ((ULONG) TX_THREAD_SMP_CORE_MASK);
+#else
+    thread_ptr -> tx_thread_smp_cores_allowed =   (((ULONG) 1) << _tx_thread_smp_max_cores) - 1;
+#endif
+
+#ifdef TX_THREAD_SMP_ONLY_CORE_0_DEFAULT
+
+    /* Default thread creation such that core0 is the only allowed core for execution, i.e., bit 1 is set to exclude core1.  */
+    thread_ptr -> tx_thread_smp_cores_excluded =  (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE);
+    thread_ptr -> tx_thread_smp_cores_allowed  =  1;
+    
+    /* Default the timers to run on core 0 as well.  */
+    thread_ptr -> tx_thread_timer.tx_timer_internal_smp_cores_excluded =  (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE);
+
+    /* Default the mapped to 0 too.  */
+    thread_ptr -> tx_thread_smp_core_mapped =  0;
+#endif
+#endif
+
+    /* Calculate the end of the thread's stack area.  */
+    temp_ptr =  TX_VOID_TO_UCHAR_POINTER_CONVERT(stack_start);
+    temp_ptr =  (TX_UCHAR_POINTER_ADD(temp_ptr, (stack_size - ((ULONG) 1))));
+    thread_ptr -> tx_thread_stack_end =         TX_UCHAR_TO_VOID_POINTER_CONVERT(temp_ptr);
 #if TXM_MODULE_MEMORY_PROTECTION
     thread_ptr -> tx_thread_module_stack_end =  thread_ptr -> tx_thread_stack_end;
-#endif
-    thread_ptr -> tx_thread_priority =          priority;
-    thread_ptr -> tx_thread_user_priority =     priority;
-    thread_ptr -> tx_thread_time_slice =        time_slice;
-    thread_ptr -> tx_thread_new_time_slice =    time_slice;
-    thread_ptr -> tx_thread_inherit_priority =  TX_MAX_PRIORITIES;
-    
+#endif /* TXM_MODULE_MEMORY_PROTECTION */
+
 #ifndef TX_DISABLE_PREEMPTION_THRESHOLD
 
     /* Preemption-threshold is enabled, setup accordingly.  */
@@ -381,9 +398,9 @@ ULONG                           status;
 
         /* Preemption-threshold specified. Since specific preemption-threshold is not supported,
            disable all preemption.  */
-        thread_ptr -> tx_thread_preempt_threshold =       0;
-        thread_ptr -> tx_thread_user_preempt_threshold =  0;
-    } 
+        thread_ptr -> tx_thread_preempt_threshold =       ((UINT) 0);
+        thread_ptr -> tx_thread_user_preempt_threshold =  ((UINT) 0);
+    }
     else
     {
 
@@ -399,6 +416,9 @@ ULONG                           status;
     /* Setup the necessary fields in the thread timer block.  */
     TX_THREAD_CREATE_TIMEOUT_SETUP(thread_ptr)
 
+    /* Perform any additional thread setup activities for tool or user purpose.  */
+    TX_THREAD_CREATE_INTERNAL_EXTENSION(thread_ptr)
+
     /* Setup pointer to the thread entry information structure, which will live at the top of each
        module thread's stack. This will allow the module thread entry function to avoid direct 
        access to the actual thread control block.  */
@@ -420,9 +440,9 @@ ULONG                           status;
 
 #ifndef TX_DISABLE_NOTIFY_CALLBACKS
     thread_entry_info ->  txm_module_thread_entry_info_exit_notify =        thread_ptr -> tx_thread_entry_exit_notify;
-#else
+#else /* TX_DISABLE_NOTIFY_CALLBACKS */
     thread_entry_info ->  txm_module_thread_entry_info_exit_notify =        TX_NULL;
-#endif
+#endif /* TX_DISABLE_NOTIFY_CALLBACKS */
     if (thread_ptr -> tx_thread_entry == module_instance -> txm_module_instance_start_thread_entry)
         thread_entry_info ->  txm_module_thread_entry_info_start_thread =   TX_TRUE;
     else
@@ -457,7 +477,7 @@ ULONG                           status;
 
     /* Place the thread on the list of created threads.  First,
        check for an empty list.  */
-    if (_tx_thread_created_count++ == 0)
+    if (_tx_thread_created_count == TX_EMPTY)
     {
 
         /* The created thread list is empty.  Add thread to empty list.  */
@@ -478,14 +498,17 @@ ULONG                           status;
 
         /* Setup this thread's created links.  */
         thread_ptr -> tx_thread_created_previous =  previous_thread;
-        thread_ptr -> tx_thread_created_next =      next_thread;    
+        thread_ptr -> tx_thread_created_next =      next_thread;
     }
 
+    /* Increment the thread created count.  */
+    _tx_thread_created_count++;
+
     /* If trace is enabled, register this object.  */
-    TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_THREAD, thread_ptr, name, stack_start, stack_size)
+    TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_THREAD, thread_ptr, name_ptr, TX_POINTER_TO_ULONG_CONVERT(stack_start), stack_size)
 
     /* If trace is enabled, insert this event into the trace buffer.  */
-    TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_CREATE, thread_ptr, priority, stack_start, stack_size, TX_TRACE_THREAD_EVENTS)
+    TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_CREATE, thread_ptr, priority, TX_POINTER_TO_ULONG_CONVERT(stack_start), stack_size, TX_TRACE_THREAD_EVENTS)
 
     /* Register thread in the thread array structure.  */
     TX_EL_THREAD_REGISTER(thread_ptr)
@@ -493,13 +516,131 @@ ULONG                           status;
     /* Log this kernel call.  */
     TX_EL_THREAD_CREATE_INSERT
 
+#ifdef TX_THREAD_SMP
+
+#ifndef TX_NOT_INTERRUPTABLE
+
+    /* Temporarily disable preemption.  */
+    _tx_thread_preempt_disable++;
+#endif
+
     /* Determine if an automatic start was requested.  If so, call the resume
        thread function and then check for a preemption condition.  */
     if (auto_start == TX_AUTO_START)
     {
 
+#ifdef TX_NOT_INTERRUPTABLE
+
+        /* Perform any additional activities for tool or user purpose.  */
+        TX_THREAD_CREATE_EXTENSION(thread_ptr)
+
+        /* Resume the thread!  */
+        _tx_thread_system_ni_resume(thread_ptr);
+
+#else
+
+        /* Restore previous interrupt posture.  */
+        TX_RESTORE
+
+        /* Perform any additional activities for tool or user purpose.  */
+        TX_THREAD_CREATE_EXTENSION(thread_ptr)
+
+        /* Call the resume thread function to make this thread ready.  */
+        _tx_thread_system_resume(thread_ptr);
+
+        /* Disable interrupts again.  */
+        TX_DISABLE
+#endif
+
+        /* Determine if the execution list needs to be re-evaluated.  */
+        if (_tx_thread_smp_current_state_get() >= TX_INITIALIZE_IN_PROGRESS)
+        {
+
 #ifndef TX_DISABLE_PREEMPTION_THRESHOLD
 
+            /* Clear the preemption bit maps, since nothing has yet run during initialization.  */
+            TX_MEMSET(_tx_thread_preempted_maps, 0, sizeof(_tx_thread_preempted_maps));
+#if TX_MAX_PRIORITIES > 32
+            _tx_thread_preempted_map_active =  ((ULONG) 0);
+#endif
+
+            /* Clear the entry in the preempted thread list.  */
+            _tx_thread_preemption_threshold_list[priority] =  TX_NULL;
+#endif
+
+            /* Set the pointer to the thread currently with preemption-threshold set to NULL.  */
+            _tx_thread_preemption__threshold_scheduled =  TX_NULL;
+
+#ifdef TX_THREAD_SMP_DEBUG_ENABLE
+
+            /* Debug entry.  */
+            _tx_thread_smp_debug_entry_insert(12, 0, thread_ptr);
+#endif
+
+            /* Get the core index.  */
+            core_index =  TX_SMP_CORE_ID;
+
+            /* Call the rebalance routine. This routine maps cores and ready threads.  */
+            _tx_thread_smp_rebalance_execute_list(core_index);
+
+#ifdef TX_THREAD_SMP_DEBUG_ENABLE
+
+            /* Debug entry.  */
+            _tx_thread_smp_debug_entry_insert(13, 0, thread_ptr);
+#endif
+        }
+
+#ifndef TX_NOT_INTERRUPTABLE
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#endif
+    }
+    else
+    {
+
+#ifdef TX_NOT_INTERRUPTABLE
+
+        /* Perform any additional activities for tool or user purpose.  */
+        TX_THREAD_CREATE_EXTENSION(thread_ptr)
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#else
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+
+        /* Perform any additional activities for tool or user purpose.  */
+        TX_THREAD_CREATE_EXTENSION(thread_ptr)
+
+        /* Disable interrupts.  */
+        TX_DISABLE
+
+        /* Re-enable preemption.  */
+        _tx_thread_preempt_disable--;
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+
+        /* Check for preemption.  */
+        _tx_thread_system_preempt_check();
+#endif
+    }
+
+#else /* TX_THREAD_SMP */
+
+#ifndef TX_NOT_INTERRUPTABLE
+
+    /* Temporarily disable preemption.  */
+    _tx_thread_preempt_disable++;
+#endif
+
+    /* Determine if an automatic start was requested.  If so, call the resume
+       thread function and then check for a preemption condition.  */
+    if (auto_start == TX_AUTO_START)
+    {
+
         /* Determine if the create call is being called from initialization.  */
         if (TX_THREAD_GET_SYSTEM_STATE() >= TX_INITIALIZE_IN_PROGRESS)
         {
@@ -526,14 +667,13 @@ ULONG                           status;
                    initialization is complete.  */
                 saved_thread_ptr -> tx_thread_preempt_threshold =  saved_thread_ptr -> tx_thread_priority;
             }
-        } 
+        }
         else
         {
 
             /* Simply set the saved thread pointer to NULL.  */
             saved_thread_ptr =  TX_NULL;
         }
-#endif
 
 #ifdef TX_NOT_INTERRUPTABLE
 
@@ -547,20 +687,15 @@ ULONG                           status;
         TX_RESTORE
 #else
 
-        /* Temporarily disable preemption.  */
-        _tx_thread_preempt_disable++;
-
         /* Restore previous interrupt posture.  */
         TX_RESTORE
 
         /* Perform any additional activities for tool or user purpose.  */
         TX_THREAD_CREATE_EXTENSION(thread_ptr)
 
-        /* Call the resume thread function to make this thread ready.  */ 
+        /* Call the resume thread function to make this thread ready.  */
         _tx_thread_system_resume(thread_ptr);
 #endif
- 
-#ifndef TX_DISABLE_PREEMPTION_THRESHOLD
 
         /* Determine if the thread's preemption-threshold needs to be restored.  */
         if (saved_thread_ptr != TX_NULL)
@@ -569,15 +704,41 @@ ULONG                           status;
             /* Yes, restore the previous highest-priority thread's preemption-threshold. This
                can only happen if this routine is called from initialization.  */
             saved_thread_ptr -> tx_thread_preempt_threshold =  saved_threshold;
-        } 
-#endif
+        }
+    }
+    else
+    {
 
-        /* Interrupts are already restored, simply return success.  */
-        return(TX_SUCCESS);
+#ifdef TX_NOT_INTERRUPTABLE
+
+        /* Perform any additional activities for tool or user purpose.  */
+        TX_THREAD_CREATE_EXTENSION(thread_ptr)
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#else
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+
+        /* Perform any additional activities for tool or user purpose.  */
+        TX_THREAD_CREATE_EXTENSION(thread_ptr)
+
+        /* Disable interrupts.  */
+        TX_DISABLE
+
+        /* Re-enable preemption.  */
+        _tx_thread_preempt_disable--;
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+
+        /* Check for preemption.  */
+        _tx_thread_system_preempt_check();
+#endif
     }
 
-    /* Restore interrupts.  */
-    TX_RESTORE
+#endif /* TX_THREAD_SMP */
 
     /* Return success.  */
     return(TX_SUCCESS);
diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h
index f67d8fdc..36e9067e 100644
--- a/common_smp/inc/tx_api.h
+++ b/common_smp/inc/tx_api.h
@@ -26,7 +26,7 @@
 /*  APPLICATION INTERFACE DEFINITION                       RELEASE        */ 
 /*                                                                        */ 
 /*    tx_api.h                                            PORTABLE SMP    */ 
-/*                                                           6.1.1        */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    William E. Lamie, Microsoft Corporation                             */
@@ -47,6 +47,9 @@
 /*  10-16-2020     William E. Lamie         Modified comment(s), and      */
 /*                                            increased patch version,    */
 /*                                            resulting in version 6.1.1  */
+/*  12-31-2020     William E. Lamie         Modified comment(s), and      */
+/*                                            increased patch version,    */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -86,7 +89,7 @@ extern   "C" {
 #define AZURE_RTOS_THREADX
 #define THREADX_MAJOR_VERSION           6
 #define THREADX_MINOR_VERSION           1
-#define THREADX_PATCH_VERSION           1
+#define THREADX_PATCH_VERSION           3
 
 /* Define the following symbol for backward compatibility */
 #define EL_PRODUCT_THREADX
diff --git a/common_smp/src/tx_thread_create.c b/common_smp/src/tx_thread_create.c
index 63440bcc..70557627 100644
--- a/common_smp/src/tx_thread_create.c
+++ b/common_smp/src/tx_thread_create.c
@@ -12,8 +12,8 @@
 
 /**************************************************************************/
 /**************************************************************************/
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
+/**                                                                       */
+/** ThreadX Component                                                     */
 /**                                                                       */
 /**   Thread                                                              */
 /**                                                                       */
@@ -32,58 +32,61 @@
 #include "tx_initialize.h"
 
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  FUNCTION                                               RELEASE        */ 
-/*                                                                        */ 
-/*    _tx_thread_create                                  PORTABLE SMP     */ 
-/*                                                           6.1          */
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_create                                  PORTABLE SMP     */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    William E. Lamie, Microsoft Corporation                             */
 /*                                                                        */
 /*  DESCRIPTION                                                           */
-/*                                                                        */ 
-/*    This function creates a thread and places it on the list of created */ 
-/*    threads.                                                            */ 
-/*                                                                        */ 
-/*  INPUT                                                                 */ 
-/*                                                                        */ 
-/*    thread_ptr                            Thread control block pointer  */ 
-/*    name_ptr                              Pointer to thread name string */ 
-/*    entry_function                        Entry function of the thread  */ 
-/*    entry_input                           32-bit input value to thread  */ 
-/*    stack_start                           Pointer to start of stack     */ 
-/*    stack_size                            Stack size in bytes           */ 
-/*    priority                              Priority of thread (0-31)     */ 
+/*                                                                        */
+/*    This function creates a thread and places it on the list of created */
+/*    threads.                                                            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*    name_ptr                              Pointer to thread name string */
+/*    entry_function                        Entry function of the thread  */
+/*    entry_input                           32-bit input value to thread  */
+/*    stack_start                           Pointer to start of stack     */
+/*    stack_size                            Stack size in bytes           */
+/*    priority                              Priority of thread (0-31)     */
 /*    preempt_threshold                     Preemption threshold          */
-/*    time_slice                            Thread time-slice value       */ 
-/*    auto_start                            Automatic start selection     */ 
-/*                                                                        */ 
-/*  OUTPUT                                                                */ 
-/*                                                                        */ 
-/*    return status                         Thread create return status   */ 
-/*                                                                        */ 
-/*  CALLS                                                                 */ 
-/*                                                                        */ 
-/*    _tx_thread_smp_rebalance_execute_list Rebalance execution list      */ 
-/*    _tx_thread_stack_build                Build initial thread stack    */ 
-/*    _tx_thread_system_resume              Resume automatic start thread */ 
-/*    _tx_thread_system_ni_resume           Noninterruptable resume thread*/ 
-/*                                                                        */ 
-/*  CALLED BY                                                             */ 
-/*                                                                        */ 
-/*    Application Code                                                    */ 
-/*    _tx_timer_initialize                  Create system timer thread    */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
+/*    time_slice                            Thread time-slice value       */
+/*    auto_start                            Automatic start selection     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    return status                         Thread create return status   */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_smp_rebalance_execute_list Rebalance execution list      */
+/*    _tx_thread_stack_build                Build initial thread stack    */
+/*    _tx_thread_system_resume              Resume automatic start thread */
+/*    _tx_thread_system_ni_resume           Noninterruptable resume thread*/
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*    _tx_timer_initialize                  Create system timer thread    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*  12-31-2020     Andres Mlinar            Modified comment(s),          */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
-UINT  _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input,
+UINT  _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr,
+                            VOID (*entry_function)(ULONG id), ULONG entry_input,
                             VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold,
                             ULONG time_slice, UINT auto_start)
 {
@@ -135,7 +138,7 @@ ALIGN_TYPE              updated_stack_start;
        list.  */
 
     /* Initialize thread control block to all zeros.  */
-    TX_MEMSET(thread_ptr, 0, (sizeof(TX_THREAD)));
+    TX_MEMSET(thread_ptr, 0, sizeof(TX_THREAD));
 
     /* Place the supplied parameters into the thread's control block.  */
     thread_ptr -> tx_thread_name =                name_ptr;
@@ -190,7 +193,7 @@ ALIGN_TYPE              updated_stack_start;
            disable all preemption.  */
         thread_ptr -> tx_thread_preempt_threshold =       ((UINT) 0);
         thread_ptr -> tx_thread_user_preempt_threshold =  ((UINT) 0);
-    } 
+    }
     else
     {
 
@@ -207,7 +210,7 @@ ALIGN_TYPE              updated_stack_start;
     TX_THREAD_CREATE_TIMEOUT_SETUP(thread_ptr)
 
     /* Perform any additional thread setup activities for tool or user purpose.  */
-    TX_THREAD_CREATE_INTERNAL_EXTENSION(thread_ptr) 
+    TX_THREAD_CREATE_INTERNAL_EXTENSION(thread_ptr)
 
     /* Call the target specific stack frame building routine to build the 
        thread's initial stack and to setup the actual stack pointer in the
@@ -249,7 +252,7 @@ ALIGN_TYPE              updated_stack_start;
 
         /* Setup this thread's created links.  */
         thread_ptr -> tx_thread_created_previous =  previous_thread;
-        thread_ptr -> tx_thread_created_next =      next_thread;    
+        thread_ptr -> tx_thread_created_next =      next_thread;
     }
 
     /* Increment the thread created count.  */
@@ -272,7 +275,7 @@ ALIGN_TYPE              updated_stack_start;
     /* Temporarily disable preemption.  */
     _tx_thread_preempt_disable++;
 #endif
-     
+
     /* Determine if an automatic start was requested.  If so, call the resume
        thread function and then check for a preemption condition.  */
     if (auto_start == TX_AUTO_START)
@@ -294,13 +297,13 @@ ALIGN_TYPE              updated_stack_start;
         /* Perform any additional activities for tool or user purpose.  */
         TX_THREAD_CREATE_EXTENSION(thread_ptr)
 
-        /* Call the resume thread function to make this thread ready.  */ 
+        /* Call the resume thread function to make this thread ready.  */
         _tx_thread_system_resume(thread_ptr);
-        
+
         /* Disable interrupts again.  */
         TX_DISABLE
 #endif
- 
+
         /* Determine if the execution list needs to be re-evaluated.  */
         if (_tx_thread_smp_current_state_get() >= TX_INITIALIZE_IN_PROGRESS)
         {
@@ -325,7 +328,7 @@ ALIGN_TYPE              updated_stack_start;
             /* Debug entry.  */
             _tx_thread_smp_debug_entry_insert(12, 0, thread_ptr);
 #endif
-            
+
             /* Get the core index.  */
             core_index =  TX_SMP_CORE_ID;
 
@@ -337,7 +340,7 @@ ALIGN_TYPE              updated_stack_start;
             /* Debug entry.  */
             _tx_thread_smp_debug_entry_insert(13, 0, thread_ptr);
 #endif
-        } 
+        }
 
 #ifndef TX_NOT_INTERRUPTABLE
 
@@ -377,7 +380,7 @@ ALIGN_TYPE              updated_stack_start;
 #endif
     }
 
-    /* Always return a success.  */
+    /* Return success.  */
     return(TX_SUCCESS);
 }
 
diff --git a/common_smp/src/tx_thread_smp_high_level_initialize.c b/common_smp/src/tx_thread_smp_high_level_initialize.c
index 4dd63dce..b0082967 100644
--- a/common_smp/src/tx_thread_smp_high_level_initialize.c
+++ b/common_smp/src/tx_thread_smp_high_level_initialize.c
@@ -38,7 +38,7 @@
 /*  FUNCTION                                               RELEASE        */ 
 /*                                                                        */ 
 /*    _tx_thread_smp_high_level_initialize               PORTABLE SMP     */ 
-/*                                                           6.1          */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    William E. Lamie, Microsoft Corporation                             */
@@ -69,6 +69,10 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*  12-31-2020     William E. Lamie         Modified comments, added      */
+/*                                            cast to address a MISRA     */
+/*                                            compliant issue,            */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 void  _tx_thread_smp_high_level_initialize(void)
@@ -95,7 +99,7 @@ void  _tx_thread_smp_high_level_initialize(void)
     TX_MEMSET(&_tx_thread_smp_protect_wait_list[0], 0xff, sizeof(_tx_thread_smp_protect_wait_list));
 
     /* Set the wait list size so we can access it from assembly functions.  */
-    _tx_thread_smp_protect_wait_list_size =  TX_THREAD_SMP_PROTECT_WAIT_LIST_SIZE;
+    _tx_thread_smp_protect_wait_list_size =  ((ULONG) TX_THREAD_SMP_PROTECT_WAIT_LIST_SIZE);
 
 #ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX
 
diff --git a/common_smp/src/tx_time_get.c b/common_smp/src/tx_time_get.c
index 695b502b..80cde187 100644
--- a/common_smp/src/tx_time_get.c
+++ b/common_smp/src/tx_time_get.c
@@ -12,8 +12,8 @@
 
 /**************************************************************************/
 /**************************************************************************/
-/**                                                                       */ 
-/** ThreadX Component                                                     */ 
+/**                                                                       */
+/** ThreadX Component                                                     */
 /**                                                                       */
 /**   Timer                                                               */
 /**                                                                       */
@@ -26,47 +26,48 @@
 /* Include necessary system files.  */
 
 #include "tx_api.h"
-#ifdef TX_MISRA_ENABLE
 #include "tx_trace.h"
 #include "tx_timer.h"
 
 
-/**************************************************************************/ 
-/*                                                                        */ 
-/*  FUNCTION                                               RELEASE        */ 
-/*                                                                        */ 
-/*    _tx_time_get                                        PORTABLE C      */ 
-/*                                                           6.1          */
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_time_get                                        PORTABLE C      */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    William E. Lamie, Microsoft Corporation                             */
 /*                                                                        */
 /*  DESCRIPTION                                                           */
-/*                                                                        */ 
-/*    This function retrieves the internal, free-running, system clock    */ 
-/*    and returns it to the caller.                                       */ 
-/*                                                                        */ 
-/*  INPUT                                                                 */ 
-/*                                                                        */ 
-/*    None                                                                */ 
-/*                                                                        */ 
-/*  OUTPUT                                                                */ 
-/*                                                                        */ 
-/*    _tx_timer_system_clock            Returns the system clock value    */ 
-/*                                                                        */ 
-/*  CALLS                                                                 */ 
-/*                                                                        */ 
-/*    None                                                                */ 
-/*                                                                        */ 
-/*  CALLED BY                                                             */ 
-/*                                                                        */ 
-/*    Application Code                                                    */ 
-/*                                                                        */ 
-/*  RELEASE HISTORY                                                       */ 
-/*                                                                        */ 
+/*                                                                        */
+/*    This function retrieves the internal, free-running, system clock    */
+/*    and returns it to the caller.                                       */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    _tx_timer_system_clock            Returns the system clock value    */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*  12-31-2020     Andres Mlinar            Modified comment(s),          */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 ULONG  _tx_time_get(VOID)
@@ -98,5 +99,4 @@ ULONG   temp_time;
     /* Return the time.  */
     return(temp_time);
 }
-#endif /* TX_MISRA_ENABLE */
 
diff --git a/ports/arc_em/metaware/src/tx_timer_interrupt.s b/ports/arc_em/metaware/src/tx_timer_interrupt.s
index 67b06941..27141e01 100644
--- a/ports/arc_em/metaware/src/tx_timer_interrupt.s
+++ b/ports/arc_em/metaware/src/tx_timer_interrupt.s
@@ -35,7 +35,7 @@
 ;/*  FUNCTION                                               RELEASE        */ 
 ;/*                                                                        */ 
 ;/*    _tx_timer_interrupt                             ARCv2_EM/MetaWare   */
-;/*                                                           6.1          */
+;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -72,6 +72,10 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+;/*  12-31-2020     Scott Larson             Modified comment(s), remove   */
+;/*                                            unneeded load of            */
+;/*                                            _tx_thread_preempt_disable, */
+;/*                                            resulting in version 6.1.3  */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_timer_interrupt(VOID)
@@ -187,7 +191,6 @@ __tx_something_expired:
 ;    {
 ;
     ld      r2, [gp, _tx_timer_expired@sda]             ; Pickup timer expired flag
-    ld      r4, [gp, _tx_thread_preempt_disable@sda]    ; Pickup preempt disable
     breq    r2, 0, __tx_timer_dont_activate             ; If not set, skip expiration processing
 ;
 ;        /* Process the timer expiration.  */
diff --git a/ports/arc_hs/metaware/src/tx_timer_interrupt.s b/ports/arc_hs/metaware/src/tx_timer_interrupt.s
index 663e9060..fdb70898 100644
--- a/ports/arc_hs/metaware/src/tx_timer_interrupt.s
+++ b/ports/arc_hs/metaware/src/tx_timer_interrupt.s
@@ -35,7 +35,7 @@
 ;/*  FUNCTION                                               RELEASE        */ 
 ;/*                                                                        */ 
 ;/*    _tx_timer_interrupt                               ARC_HS/MetaWare   */
-;/*                                                           6.1          */
+;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -72,6 +72,10 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+;/*  12-31-2020     Scott Larson             Modified comment(s), remove   */
+;/*                                            unneeded load of            */
+;/*                                            _tx_thread_preempt_disable, */
+;/*                                            resulting in version 6.1.3  */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_timer_interrupt(VOID)
@@ -187,7 +191,6 @@ __tx_something_expired:
 ;    {
 ;
     ld      r2, [gp, _tx_timer_expired@sda]             ; Pickup timer expired flag
-    ld      r4, [gp, _tx_thread_preempt_disable@sda]    ; Pickup preempt disable
     breq    r2, 0, __tx_timer_dont_activate             ; If not set, skip expiration processing
 ;
 ;        /* Process the timer expiration.  */
diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a35/ac6/example_build/sample_threadx/.settings/language.settings.xml
deleted file mode 100644
index 16ac1af8..00000000
--- a/ports/cortex_a35/ac6/example_build/sample_threadx/.settings/language.settings.xml
+++ /dev/null
@@ -1,48 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-    	
-    <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" name="Debug">
-        		
-        <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-            			
-            <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-890320463837788586" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
-                			
-            </provider>
-            		
-        </extension>
-        	
-    </configuration>
-    	
-    <configuration id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" name="Release">
-        		
-        <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-            			
-            <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-936373864897685072" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
-                			
-            </provider>
-            		
-        </extension>
-        	
-    </configuration>
-    
-</project>
diff --git a/ports/cortex_a35/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_a35/ac6/example_build/tx/.settings/language.settings.xml
deleted file mode 100644
index 830dd5dd..00000000
--- a/ports/cortex_a35/ac6/example_build/tx/.settings/language.settings.xml
+++ /dev/null
@@ -1,48 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-    	
-    <configuration id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915" name="Debug">
-        		
-        <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-            			
-            <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-890320463837788586" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
-                			
-            </provider>
-            		
-        </extension>
-        	
-    </configuration>
-    	
-    <configuration id="com.arm.eclipse.build.config.v6.lib.release.base.979090268" name="Release">
-        		
-        <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-            			
-            <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-936373864897685072" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
-                			
-            </provider>
-            		
-        </extension>
-        	
-    </configuration>
-    
-</project>
diff --git a/ports/cortex_m23/gnu/example_build/build_threadx.bat b/ports/cortex_m23/gnu/example_build/build_threadx.bat
new file mode 100644
index 00000000..822d45f2
--- /dev/null
+++ b/ports/cortex_m23/gnu/example_build/build_threadx.bat
@@ -0,0 +1,235 @@
+del tx.a
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_context_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_context_save.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_interrupt_control.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_interrupt_disable.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_interrupt_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_schedule.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_secure_stack_allocate.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_secure_stack_free.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_stack_build.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_system_return.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_timer_interrupt.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../src/txe_thread_secure_stack_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../src/txe_thread_secure_stack_free.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../src/tx_thread_stack_error_handler.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../src/tx_thread_stack_error_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+arm-none-eabi-ar -r tx.a tx_thread_secure_stack_allocate.o txe_thread_secure_stack_allocate.o tx_thread_secure_stack_free.o txe_thread_secure_stack_free.o
+arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_initialize_low_level.o
+arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h
index 69acde04..bb9c05a9 100644
--- a/ports/cortex_m23/gnu/inc/tx_port.h
+++ b/ports/cortex_m23/gnu/inc/tx_port.h
@@ -26,7 +26,7 @@
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
 /*    tx_port.h                                         Cortex-M23/GNU    */
-/*                                                           6.1          */
+/*                                                           6.1.3        */
 /*                                                                        */
 /*  AUTHOR                                                                */
 /*                                                                        */
@@ -48,6 +48,10 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020     Scott Larson             Initial Version 6.1           */
+/*  12-31-2020     Scott Larson             Modified comment(s),          */
+/*                                            remove unneeded headers,    */
+/*                                            use builtins,               */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -67,8 +71,6 @@
 
 #include <stdlib.h>
 #include <string.h>
-#include <arm_compat.h>
-#include "ARMCM23_TZ.h"          /* For intrinsic functions. */
 
 /* Define ThreadX basic types for this port.  */
 
@@ -275,8 +277,6 @@ ULONG   _tx_misra_time_stamp_get(VOID);
 
 #ifndef TX_MISRA_ENABLE
 
-//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
-inline static unsigned int _get_ipsr(void);
 inline static unsigned int _get_ipsr(void)
 {
     unsigned int _ipsr;
@@ -352,7 +352,7 @@ extern void    _tx_thread_secure_stack_initialize(void);
 
 #ifndef TX_DISABLE_INLINE
 
-#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) = (UINT) __clz(__rbit((m)));
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) = (UINT) __builtin_ctz(m);
 
 #endif
 
@@ -364,41 +364,73 @@ extern void    _tx_thread_secure_stack_initialize(void);
    is used to define a local function save area for the disable and restore
    macros.  */
 
-#ifdef TX_DISABLE_INLINE
+#ifndef TX_DISABLE_INLINE
 
-UINT                                            _tx_thread_interrupt_disable(VOID);
-VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+/* Define GNU specific macros, with in-line assembly for performance.  */
 
-#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void)
+{
 
-#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+unsigned int  primask_value;
 
-#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+    __asm__ volatile (" MRS  %0,PRIMASK ": "=r" (primask_value) );
+    __asm__ volatile (" CPSID i" : : : "memory" );
+    return(primask_value);
+}
 
-#else
+__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value)
+{
 
-#define TX_INTERRUPT_SAVE_AREA                  unsigned int  was_masked;
-#define TX_DISABLE                              was_masked = __disable_irq();
-#define TX_RESTORE                              if (was_masked == 0) __enable_irq();
+    __asm__ volatile (" MSR  PRIMASK,%0": : "r" (primask_value): "memory" );
+}
+
+__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void)
+{
+
+unsigned int  primask_value;
+
+    __asm__ volatile (" MRS  %0,PRIMASK ": "=r" (primask_value) );
+    return(primask_value);
+}
+
+__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
+{
+
+    __asm__ volatile (" CPSIE  i": : : "memory" );
+}
+
+
+__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void)
+{
+unsigned int interrupt_save;
+
+    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    if (_get_ipsr() == 0)
+    {
+        interrupt_save = __get_primask_value();
+        __enable_interrupts();
+        __restore_interrupts(interrupt_save);
+    }
+}
+
+
+#define TX_INTERRUPT_SAVE_AREA  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  __disable_interrupts();
+#define TX_RESTORE                              __restore_interrupts(interrupt_save);
+
+
+/* Redefine _tx_thread_system_return for improved performance.  */
 
 #define _tx_thread_system_return                _tx_thread_system_return_inline
 
 
-static void _tx_thread_system_return_inline(void)
-{
-unsigned int          was_masked;
+#else
 
+#define TX_INTERRUPT_SAVE_AREA  unsigned int interrupt_save;
 
-    /* Set PendSV to invoke ThreadX scheduler.  */
-    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
-    if (_get_ipsr() == 0)
-    {
-        was_masked = __disable_irq();
-        __enable_irq();
-        if (was_masked != 0)
-            __disable_irq();
-    }
-}
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
+#define TX_RESTORE                              _tx_thread_interrupt_control(interrupt_save);
 #endif
 
 
@@ -406,7 +438,7 @@ unsigned int          was_masked;
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] = 
-                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-M23/GNU Version 6.1 *";
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-M23/GNU Version 6.1.3 *";
 #else
 #ifdef TX_MISRA_ENABLE
 extern  CHAR                    _tx_version_id[100];
diff --git a/ports/cortex_m23/gnu/readme_threadx.txt b/ports/cortex_m23/gnu/readme_threadx.txt
index fa581684..e5dacfec 100644
--- a/ports/cortex_m23/gnu/readme_threadx.txt
+++ b/ports/cortex_m23/gnu/readme_threadx.txt
@@ -5,12 +5,12 @@
 
 1.  Building the ThreadX run-time Library
 
-
+An example .bat file is in the example_build directory.
 
 
 2.  Demonstration System
 
-
+No demonstration example is provided.
 
 
 3.  System Initialization
@@ -127,6 +127,18 @@ For generic code revision information, please refer to the readme_threadx_generi
 file, which is included in your distribution. The following details the revision
 information associated with this specific port of ThreadX:
 
+12-31-2020  The following files were 
+            changed/added for port specific version 6.1.3:
+            
+            
+            tx_port.h                       Remove unneeded include files, 
+                                            use builtin functions,
+                                            modified comments.
+                                            
+            tx_thread_secure_stack.c        Remove unneeded include file, 
+                                            use inline get/set functions,
+                                            modified comments.
+
 09-30-2020  Initial ThreadX 6.1 version for Cortex-M23 using GNU tools.
 
 
diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c
index 9ca7ccff..0e8cbde0 100644
--- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c
+++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c
@@ -29,7 +29,6 @@
 
 #define TX_SOURCE_CODE
 
-#include "ARMCM23_TZ.h"                 /* For intrinsic functions. */
 #include "tx_secure_interface.h"        /* Interface for NS code. */
 
 /* Minimum size of secure stack. */
@@ -63,7 +62,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _tx_thread_secure_stack_initialize                Cortex-M23/GNU    */
-/*                                                           6.1.1        */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -82,10 +81,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
 /*                                                                        */
 /*  CALLS                                                                 */
 /*                                                                        */
-/*    __get_CONTROL                         Intrinsic to get CONTROL      */
-/*    __set_CONTROL                         Intrinsic to set CONTROL      */
-/*    __set_PSPLIM                          Intrinsic to set PSP limit    */
-/*    __set_PSP                             Intrinsic to set PSP          */
+/*    None                                                                */
 /*                                                                        */
 /*  CALLED BY                                                             */
 /*                                                                        */
@@ -98,19 +94,25 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
 /*  10-16-2020      Scott Larson            Modified comment(s),          */
 /*                                            resulting in version 6.1.1  */
+/*  12-31-2020      Scott Larson            Modified comment(s), and      */
+/*                                            fixed M23 GCC build,        */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 __attribute__((cmse_nonsecure_entry))
 void    _tx_thread_secure_stack_initialize(void)
 {
+    ULONG control;
     
     /* Set secure mode to use PSP. */
-    __set_CONTROL(__get_CONTROL() | 2);
+    asm volatile("MRS     %0, CONTROL" : "=r" (control));   /* Get CONTROL register. */
+    control |= 2;                                           /* Use PSP. */
+    asm volatile("MSR     CONTROL, %0" :: "r" (control));   /* Set CONTROL register. */
     
     /* Set process stack pointer and stack limit to 0 to throw exception when a thread
        without a secure stack calls a secure function that tries to use secure stack. */
-    __set_PSPLIM(0);
-    __set_PSP(0);
+    asm volatile("MSR     PSPLIM, %0" :: "r" (0));
+    asm volatile("MSR     PSP, %0" :: "r" (0));
     
     return;
 }
@@ -122,7 +124,7 @@ void    _tx_thread_secure_stack_initialize(void)
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _tx_thread_secure_mode_stack_allocate             Cortex-M23/GNU    */
-/*                                                           6.1.1        */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -145,13 +147,9 @@ void    _tx_thread_secure_stack_initialize(void)
 /*                                                                        */
 /*  CALLS                                                                 */
 /*                                                                        */
-/*    __get_IPSR                            Intrinsic to get IPSR         */
 /*    calloc                                Compiler's calloc function    */
 /*    malloc                                Compiler's malloc function    */
 /*    free                                  Compiler's free() function    */
-/*    __set_PSPLIM                          Intrinsic to set PSP limit    */
-/*    __set_PSP                             Intrinsic to set PSP          */
-/*    __TZ_get_PSPLIM_NS                    Intrinsic to get NS PSP       */
 /*                                                                        */
 /*  CALLED BY                                                             */
 /*                                                                        */
@@ -165,6 +163,10 @@ void    _tx_thread_secure_stack_initialize(void)
 /*  10-16-2020      Scott Larson            Modified comment(s),          */
 /*                                            added stack sealing,        */
 /*                                            resulting in version 6.1.1  */
+/*  12-31-2020      Scott Larson            Modified comment(s), and      */
+/*                                            fixed M23 GCC build,        */
+/*                                            resulting in version 6.1.3  */
+
 /*                                                                        */
 /**************************************************************************/
 __attribute__((cmse_nonsecure_entry))
@@ -173,12 +175,14 @@ UINT    _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack
 UINT    status;
 TX_THREAD_SECURE_STACK_INFO *info_ptr;
 UCHAR   *stack_mem;
-ULONG   sp;
+ULONG   ipsr;
+ULONG   psplim_ns;
 
     status = TX_SUCCESS;
     
     /* Make sure function is called from interrupt (threads should not call). */
-    if (__get_IPSR() == 0)
+    asm volatile("MRS     %0, IPSR" : "=r" (ipsr));   /* Get IPSR register. */
+    if (ipsr == 0)
     {
         status = TX_CALLER_ERROR;
     }
@@ -217,14 +221,13 @@ ULONG   sp;
                 /* Save info pointer in thread. */
                 thread_ptr -> tx_thread_secure_stack_context = info_ptr;
                 
-                /* Check if this thread is running by looking at PSP_NS and seeing if it is within
-                   the stack_start and stack_end range. */
-                sp = __TZ_get_PSP_NS();
-                if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end))
+                /* Check if this thread is running by looking at its stack start and PSPLIM_NS */
+                asm volatile("MRS     %0, PSPLIM_NS" : "=r" (psplim_ns));   /* Get PSPLIM_NS register. */
+                if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == psplim_ns)
                 {
                     /* If this thread is running, set Secure PSP and PSPLIM. */
-                    __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit));
-                    __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr));
+                    asm volatile("MSR     PSPLIM, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_limit)));
+                    asm volatile("MSR     PSP, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)));
                 }
             }
             
@@ -252,7 +255,7 @@ ULONG   sp;
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _tx_thread_secure_mode_stack_free                 Cortex-M23/GNU    */
-/*                                                           6.1.1        */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -273,7 +276,6 @@ ULONG   sp;
 /*                                                                        */
 /*  CALLS                                                                 */
 /*                                                                        */
-/*    __get_IPSR                            Intrinsic to get IPSR         */
 /*    free                                  Compiler's free() function    */
 /*                                                                        */
 /*  CALLED BY                                                             */
@@ -287,6 +289,9 @@ ULONG   sp;
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
 /*  10-16-2020      Scott Larson            Modified comment(s),          */
 /*                                            resulting in version 6.1.1  */
+/*  12-31-2020      Scott Larson            Modified comment(s), and      */
+/*                                            fixed M23 GCC build,        */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 __attribute__((cmse_nonsecure_entry))
@@ -294,14 +299,16 @@ UINT    _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
 {
 UINT    status;
 TX_THREAD_SECURE_STACK_INFO *info_ptr;
-    
+ULONG   ipsr;
+
     status = TX_SUCCESS;
     
     /* Pickup stack info from thread. */
     info_ptr = thread_ptr -> tx_thread_secure_stack_context;
     
     /* Make sure function is called from interrupt (threads should not call). */
-    if (__get_IPSR() == 0)
+    asm volatile("MRS     %0, IPSR" : "=r" (ipsr));   /* Get IPSR register. */
+    if (ipsr == 0)
     {
         status = TX_CALLER_ERROR;
     }
@@ -335,7 +342,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _tx_thread_secure_stack_context_save              Cortex-M23/GNU    */
-/*                                                           6.1.1        */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -354,10 +361,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
 /*                                                                        */
 /*  CALLS                                                                 */
 /*                                                                        */
-/*    __get_IPSR                            Intrinsic to get IPSR         */
-/*    __get_PSP                             Intrinsic to get PSP          */
-/*    __set_PSPLIM                          Intrinsic to set PSP limit    */
-/*    __set_PSP                             Intrinsic to set PSP          */
+/*    None                                                                */
 /*                                                                        */
 /*  CALLED BY                                                             */
 /*                                                                        */
@@ -370,6 +374,9 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
 /*  10-16-2020      Scott Larson            Modified comment(s),          */
 /*                                            resulting in version 6.1.1  */
+/*  12-31-2020      Scott Larson            Modified comment(s), and      */
+/*                                            fixed M23 GCC build,        */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 __attribute__((cmse_nonsecure_entry))
@@ -377,9 +384,11 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr)
 {
 TX_THREAD_SECURE_STACK_INFO *info_ptr;
 ULONG   sp;
-    
+ULONG   ipsr;
+
     /* This function should be called from scheduler only. */
-    if (__get_IPSR() == 0)
+    asm volatile("MRS     %0, IPSR" : "=r" (ipsr));   /* Get IPSR register. */
+    if (ipsr == 0)
     {
         return;
     }
@@ -394,7 +403,7 @@ ULONG   sp;
     }
     
     /* Check that stack pointer is in range */
-    sp = __get_PSP();
+    asm volatile("MRS     %0, PSP" : "=r" (sp));   /* Get PSP register. */
     if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || 
         (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start))
     {
@@ -406,8 +415,8 @@ ULONG   sp;
     
     /* Set process stack pointer and stack limit to 0 to throw exception when a thread
        without a secure stack calls a secure function that tries to use secure stack. */
-    __set_PSPLIM(0);
-    __set_PSP(0);
+    asm volatile("MSR     PSPLIM, %0" :: "r" (0));
+    asm volatile("MSR     PSP, %0" :: "r" (0));
     
     return;
 }
@@ -419,7 +428,7 @@ ULONG   sp;
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _tx_thread_secure_stack_context_restore           Cortex-M23/GNU    */
-/*                                                           6.1.1        */
+/*                                                           6.1.3        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -438,9 +447,7 @@ ULONG   sp;
 /*                                                                        */
 /*  CALLS                                                                 */
 /*                                                                        */
-/*    __get_IPSR                            Intrinsic to get IPSR         */
-/*    __set_PSPLIM                          Intrinsic to set PSP limit    */
-/*    __set_PSP                             Intrinsic to set PSP          */
+/*    None                                                                */
 /*                                                                        */
 /*  CALLED BY                                                             */
 /*                                                                        */
@@ -453,15 +460,20 @@ ULONG   sp;
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
 /*  10-16-2020      Scott Larson            Modified comment(s),          */
 /*                                            resulting in version 6.1.1  */
+/*  12-31-2020      Scott Larson            Modified comment(s), and      */
+/*                                            fixed M23 GCC build,        */
+/*                                            resulting in version 6.1.3  */
 /*                                                                        */
 /**************************************************************************/
 __attribute__((cmse_nonsecure_entry))
 void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr)
 {
 TX_THREAD_SECURE_STACK_INFO *info_ptr;
+ULONG   ipsr;
 
     /* This function should be called from scheduler only. */
-    if (__get_IPSR() == 0)
+    asm volatile("MRS     %0, IPSR" : "=r" (ipsr));   /* Get IPSR register. */
+    if (ipsr == 0)
     {
         return;
     }
@@ -476,8 +488,8 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
     }
     
     /* Set stack pointer and limit. */
-    __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit);
-    __set_PSP   ((ULONG)info_ptr -> tx_thread_secure_stack_ptr);
+    asm volatile("MSR     PSPLIM, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_limit));
+    asm volatile("MSR     PSP, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_ptr));
     
     return;
 }
diff --git a/ports/rxv2/ccrx/inc/tx_port.h b/ports/rxv2/ccrx/inc/tx_port.h
new file mode 100644
index 00000000..21931297
--- /dev/null
+++ b/ports/rxv2/ccrx/inc/tx_port.h
@@ -0,0 +1,281 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                            RX/CCRX        */
+/*                                                           6.1.3        */
+/*                                                                        */
+/*  AUTHOR                                                                */ 
+/*                                                                        */ 
+/*    William E. Lamie, Express Logic, Inc.                               */ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        256         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          0
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2          
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+/* UINT   _tx_thread_interrupt_control(UINT new_posture); */
+
+#pragma inline_asm _tx_thread_interrupt_disable 
+static UINT _tx_thread_interrupt_disable(void){
+    MVFC PSW,R1  ;
+    CLRPSW I     ;
+}
+
+
+#pragma inline_asm _tx_thread_interrupt_restore
+static void _tx_thread_interrupt_restore(UINT old_posture){
+    MVFC PSW, R2  ;
+    BTST #16,r1   ;
+    BMC  #16,r2   ;
+    MVTC r2,PSW   ;
+}
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_disable();
+
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+static void _tx_thread_system_return_inline(void)
+{
+    UINT interrupt_save;
+
+    interrupt_save = _tx_thread_interrupt_disable();
+
+    *((volatile UCHAR *)(0x872E0u)) = 1u;
+
+    _tx_thread_interrupt_restore(interrupt_save);
+}
+
+
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+
+#pragma inline_asm _get_psw
+static UINT _get_psw(void){
+    MVFC PSW,R1  ;
+}
+
+extern volatile ULONG  _tx_thread_system_state;
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | ((~_get_psw()) & (1u << 17u)))
+#endif
+
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RX/CCRX Version 6.1.3 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
+
diff --git a/ports/rxv2/ccrx/readme_threadx.txt b/ports/rxv2/ccrx/readme_threadx.txt
new file mode 100644
index 00000000..c496fbb3
--- /dev/null
+++ b/ports/rxv2/ccrx/readme_threadx.txt
@@ -0,0 +1,175 @@
+                  Microsoft's Azure RTOS ThreadX for Renesas RXv2
+
+                              Using the CC-RX Tools
+
+1.  Building the ThreadX run-time Library
+
+Please see the Samples repository on GitHub for the Azure RTOS demonstrations
+for the RXv2.
+
+
+2.  Demonstration System
+
+Please see the Samples repository on GitHub for the Azure RTOS demonstrations
+for the RXv2
+
+
+3.  System Initialization
+
+The system entry point using Renesas tools is at the label _PowerON_Reset_PC. 
+Use the resetprg.c file that comes with your release. Most notable is that Threadx 
+applications run in supervisor mode and do not use user mode. Hence switching to 
+user mode has been commented out.
+
+The vector area is set up using either intprg.c or in the file tx_initialize_low_level.src.
+The file tx_initialize_low_level.src is responsible for setting up various system data 
+structures, interrupt vectors, and a periodic timer. This is the ideal place add 
+application specific hardware initialization code.
+
+ThreadX utilizes CMT0 as a periodic timer interrupt source. The CMT0 interrupt is 
+typically setup for 10ms periodic interrupts and the interrupt priority level is set to 
+level 7. You may change any of the timer parameters to suit your needs.
+
+In addition, _tx_initialize_low_level determines the first available address for use by 
+the application, which is supplied as the sole input parameter to your application 
+definition function, tx_application_define(). The mechanism is implemented by creating the 
+FREEMEM section, this section should be linked last in the RAM area. tx_initialize_low_level 
+will pick up the starting label of this section and put it in the global variable:
+_tx_initialize_unused_memory
+
+
+4.  Context Switch, Register Usage and Stack Frames
+
+The RXv2 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #17,
+to perform context switch. This ISR is thus reserved when using ThreadX and the SWINT
+should not be manipulated in any way by the application. The port will setup the 
+interrupt within _tx_initialize_low_level and the compiler will automatically install
+the necessary interrupt vector. As such no additional initialization is necessary by the
+application.
+
+The following defines the saved context stack frame used by the ThreadX port. The
+state of the CPU registers at the time of a context switch is saved on the running 
+thread's stack The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+    Offset        Interrupted Stack Frame
+
+     0x00                   1
+     0x04                   ACC0
+     0x08                   ACC1
+     0x0C                   R6
+     0x10                   R7
+     0x14                   R8
+     0x18                   R9
+     0x1C                   R10
+     0x20                   R11
+     0x24                   R12
+     0x28                   R13
+     0x2C                   FPSW
+     0x30                   R14
+     0x34                   R15
+     0x38                   R3
+     0x3C                   R4
+     0x40                   R5
+     0x44                   R1
+     0x48                   R2
+     0x4C                   PC - return address
+     0x50                   PSW
+     
+Note: By default ccrx does not save the state of the accumulator registers ACC0 and ACC1
+when entering an ISR. This means that if the ISR uses any of the DSP instructions the
+content of those registers could be corrupted. Saving and restoring of the acummulators
+can be enabled by adding the -save_acc command line option.
+
+     
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations.  This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself.  Of course, this costs some 
+performance.  To make ThreadX run faster, you can change the ThreadX Library 
+project to disable debug information and enable the desired optimizations.  
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined before tx_api.h is included. 
+
+
+6. Timer Processing
+
+Timer processign is performed by calling __tx_timer_interrupt(). This should usually be done
+from within the callback of a periodic timer with a period of 100Hz. In the sample projects
+a Renesas Fit CMT periodic timer module (rx_cmt) is used as the timer source.
+
+
+7.  Interrupt Handling
+
+Interrupt handling is unaffected by the ThreadX port as such user interrupts can be 
+written according to the toolchain's documentation. It is recommended not to use interrupt
+priority 15 as this is the priority of the context switch interrupt. However using interrupt
+priority 15 won't cause any negative side effectd but doing so may may slightly reduce 
+performance. Please refer to the toolchain documentation for additional details on how to
+define interupt service routines.
+
+
+8. Execution Profiling
+
+The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists 
+of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation 
+of the EPK for generic usage details.
+
+To add the EPK to your RXv2 release make the following modifications:
+
+* Enable the following define for both the Threadx library and the application
+TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+* in tx_port.h, change around line 183
+change #define TX_THREAD_EXTENSION_3     
+into #include "tx_execution_profile.h"   
+
+* Setup CMT1 as a free running 16 bit timer.
+
+* In tx_execution_profile.h, change following around line 74:
+
+#ifdef TX_EXECUTION_64BIT_TIME
+typedef unsigned long long              EXECUTION_TIME;
+#define TX_THREAD_EXTENSION_3           unsigned long long  tx_thread_execution_time_total; \
+                                        unsigned long long  tx_thread_execution_time_last_start; 
+#define TX_EXECUTION_MAX_TIME_SOURCE    0xFFFFFFFFFFFFFFFF
+#else
+typedef unsigned long                   EXECUTION_TIME;
+#define TX_THREAD_EXTENSION_3           unsigned long   tx_thread_execution_time_total; \
+                                        unsigned long   tx_thread_execution_time_last_start; 
+#define TX_EXECUTION_MAX_TIME_SOURCE    0xFFFF
+#endif
+                                        
+/* Define basic constants for the execution profile kit.  */
+
+#define TX_EXECUTION_TIME_SOURCE         (EXECUTION_TIME)  *((USHORT *) 0x8800A)
+
+Rebuild the Threadx library and the application.
+Refer to the EPK documentation how to interpret the results.
+
+
+9.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+
+12-31-2020  Initial ThreadX release for the RXv2 using CC-RXX tools, version 6.1.3
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
+
+
+www.expresslogic.com
\ No newline at end of file
diff --git a/ports/rxv2/ccrx/src/tx_initialize_low_level.src b/ports/rxv2/ccrx/src/tx_initialize_low_level.src
new file mode 100644
index 00000000..72b297bf
--- /dev/null
+++ b/ports/rxv2/ccrx/src/tx_initialize_low_level.src
@@ -0,0 +1,101 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+
+    .GLB __tx_initialize_unused_memory
+
+    IPR03    .EQU  87303H
+    IEN03    .EQU  87203H
+
+    .SECTION P,CODE
+    
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_low_level                             RX/CCRX        */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function is responsible for any low-level processor            */ 
+;/*    initialization, including setting up interrupt vectors, setting     */ 
+;/*    up a periodic timer interrupt source, saving the system stack       */ 
+;/*    pointer for use in ISR processing later, and finding the first      */ 
+;/*    available RAM memory address for tx_application_define.             */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+
+    .GLB __tx_initialize_low_level
+__tx_initialize_low_level:
+;
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) &free_mem_start;
+;
+    MOV.L    #free_mem_start, R1                ; Pickup unused memory address
+    MOV.L    #__tx_initialize_unused_memory,R2
+    MOV.L    R1,[R2]                            ; Save first free memory address
+
+;   /* Set priority of SWINT to 1. */
+    MOV.L    #IPR03, r1
+    MOV.L    #1, r2
+    MOV.B    r2, [r1]
+
+;   /* Enable SWINT. */
+    MOV.L    #IEN03,r1
+    MOV.B    [r1], r2
+    OR       #(1 << 3), r2
+    MOV.B    r2, [r1]
+
+    RTS                                    
+
+    .SECTION    FREEMEM ,DATA, ALIGN=4
+free_mem_start:
+    .BLKL 8              ; this section is last in the link map so we can access the end of RAM memory
+
+    .END
diff --git a/ports/rxv2/ccrx/src/tx_thread_context_restore.src b/ports/rxv2/ccrx/src/tx_thread_context_restore.src
new file mode 100644
index 00000000..9601dfda
--- /dev/null
+++ b/ports/rxv2/ccrx/src/tx_thread_context_restore.src
@@ -0,0 +1,207 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    .GLB     __tx_thread_system_state
+    .GLB     __tx_thread_current_ptr
+    .GLB     __tx_thread_system_stack_ptr
+    .GLB     __tx_thread_execute_ptr
+    .GLB     __tx_timer_time_slice
+    .GLB     __tx_thread_schedule
+    .GLB     __tx_thread_preempt_disable
+;
+    .SECTION    P,CODE
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_restore                           RX/CCRX        */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function restores the interrupt context if it is processing a  */ 
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+;/*    if no thread was running, the function returns to the scheduler.    */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                  Interrupt Service Routines    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    .GLB __tx_thread_context_restore
+__tx_thread_context_restore:
+;
+;    /* Lockout interrupts.  */
+
+     CLRPSW I                                 ; disable interrupts
+
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+
+     MOV.L    #__tx_thread_system_state, R1
+     MOV.L    [R1], R2
+     SUB      #1, R2
+     MOV.L    R2,[R1]
+     BEQ      __tx_thread_not_nested_restore 
+
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Recover the saved registers from the interrupt stack
+;       and return to the point of interrupt.  */
+;
+__tx_thread_nested_restore:
+     POPC    FPSW                                ; restore FPU status   
+     POPM    R14-R15             ; restore R14-R15
+     POPM    R3-R5               ; restore R3-R5
+     POPM    R1-R2               ; restore R1-R2
+     RTE                         ; return to point of interrupt, restore PSW including IPL
+;    }
+
+__tx_thread_not_nested_restore:
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+;               || (_tx_thread_preempt_disable))
+;    {
+    
+     MOV.L    #__tx_thread_current_ptr, R1       ; Pickup current thread ptr address
+     MOV.L    [R1], R2
+     CMP      #0, R2
+     BEQ      __tx_thread_idle_system_restore 
+     
+     MOV.L    #__tx_thread_preempt_disable, R3   ; pick up preempt disable flag
+     MOV.L    [R3], R3
+     CMP      #0, R3
+     BNE      __tx_thread_no_preempt_restore     ; if pre-empt disable flag set, we simply return to the original point of interrupt regardless
+     
+     MOV.L    #__tx_thread_execute_ptr, R3       ; (_tx_thread_current_ptr != _tx_thread_execute_ptr)
+     CMP      [R3], R2
+     BNE      __tx_thread_preempt_restore        ; jump to pre-empt restoring
+;
+__tx_thread_no_preempt_restore:
+     SETPSW  U                   ; user stack
+	 POPC    FPSW                ; restore FPU status
+     POPM    R14-R15             ; restore R14-R15
+     POPM    R3-R5               ; restore R3-R5
+     POPM    R1-R2               ; restore R1-R2
+     RTE                         ; return to point of interrupt, restore PSW including IPL
+
+;    }
+;    else
+;    {
+
+__tx_thread_preempt_restore:
+
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+
+     MOV.L    #__tx_timer_time_slice, R3        ; Pickup time-slice address
+     MOV.L    [R3],R4                           ; Pickup actual time-slice
+     CMP      #0, R4
+     BEQ      __tx_thread_dont_save_ts          ; no time slice to save
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0;
+;
+     MOV.L    R4,24[R2]                         ; Save thread's time slice
+     MOV.L    #0,R4                             ; Clear value
+     MOV.L    R4,[R3]                           ; Disable global time slice flag
+;    }
+__tx_thread_dont_save_ts:
+;
+;   /* Now store the remaining registers!   */
+
+     SETPSW   U                                 ; user stack
+     PUSHM    R6-R13
+
+     MVFACGU   #0, A1, R4                       ; Save accumulators.
+     MVFACHI   #0, A1, R5
+     MVFACLO   #0, A1, R6
+     PUSHM     R4-R6
+     MVFACGU   #0, A0, R4
+     MVFACHI   #0, A0, R5
+     MVFACLO   #0, A0, R6
+     PUSHM     R4-R6
+
+     MOV.L    #1, R3                            ; indicate interrupt stack frame
+     PUSH.L   R3
+
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;    R1 ->  _tx_thread_current_ptr
+;    R2 -> *_tx_thread_current_ptr
+
+     MOV.L   R0,8[R2]                        ; Save thread's stack pointer in thread control block
+     MOV.L   #0,R2                           ; Build NULL value
+     MOV.L   R2,[R1]                         ; Set current thread to NULL
+
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+
+__tx_thread_idle_system_restore:
+     MVTC    #0, PSW                          ; reset interrupt priority level to 0
+     BRA     __tx_thread_schedule             ; jump to scheduler
+;    }
+;
+;}
+;
+    .END
+
diff --git a/ports/rxv2/ccrx/src/tx_thread_context_save.src b/ports/rxv2/ccrx/src/tx_thread_context_save.src
new file mode 100644
index 00000000..26e94078
--- /dev/null
+++ b/ports/rxv2/ccrx/src/tx_thread_context_save.src
@@ -0,0 +1,171 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+    .GLB     __tx_thread_system_state
+    .GLB     __tx_thread_current_ptr
+    .GLB     __tx_thread_system_stack_ptr
+
+    .SECTION    P,CODE
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_save                              RX/CCRX        */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;VOID   _tx_thread_context_save(VOID)
+;{
+    .GLB __tx_thread_context_save
+__tx_thread_context_save:
+;
+;    /* Upon entry to this routine, it is assumed that interrupts are locked
+;       out and the (interrupt) stack frame looks like the following:
+;
+;           (lower address) SP   ->     [return address of this call]
+;                           SP+4 ->     Saved R1
+;                           SP+8 ->     Saved R2
+;                           SP+12->     Interrupted PC
+;                           SP+16->     Interrupted PSW
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+
+    MOV.L   #__tx_thread_system_state, R1     ; pick up address of system state
+    MOV.L   [R1], R2                           ; pick up system state
+    CMP     #0, R2                             ; 0 -> no nesting
+    BEQ     __tx_thread_not_nested_save
+;
+;    /* Nested interrupt condition.  */
+;   
+    ADD   #1, r2                             ; _tx_thread_system_state++
+    MOV.L   r2, [r1]
+
+;
+;   /* Save the rest of the scratch registers on the interrupt stack and return to the
+;       calling ISR.  */
+    POP R1                                      ; recuperate return address from stack
+    PUSHM   R3-R5
+    PUSHM   R14-R15
+    PUSHC   FPSW                                ; (top) FPSW, R14, R15, R3, R4, R5, R1, R2, PC, PSW (bottom)
+    JMP     R1                                  ; return address was preserved in R1
+
+;
+__tx_thread_not_nested_save:
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     #1, R2                                ; _tx_thread_system_state++
+    MOV.L   R2, [R1]
+
+    MOV.L   #__tx_thread_current_ptr, R2         ; Pickup current thread pointer
+    MOV.L   [R2], R2
+    CMP     #0,R2                                ; Is it NULL?  
+    BEQ      __tx_thread_idle_system_save        ; Yes, idle system is running - idle restore
+;
+;    /* Move stack frame over to the current threads stack.  */
+;    /* complete stack frame with registers not saved yet (R3-R5, R14-R15, FPSW)   */
+;
+    MVFC    USP, R1                               ; pick up user stack pointer
+    MOV.L   16[R0], R2
+    MOV.L   R2, [-R1]                             ; save PSW on thread stack
+    MOV.L   12[R0], R2
+    MOV.L   R2, [-R1]                             ; save PC on thread stack
+    MOV.L   8[R0], R2
+    MOV.L   R2, [-R1]                             ; save R2 on thread stack 
+    MOV.L   4[R0], R2
+    MOV.L   R2, [-R1]                             ; save R1 on thread stack 
+    MOV.L   R5, [-R1]                             ; save R5 on thread stack
+    MOV.L   R4, [-R1]                             ; save R4 on thread stack
+    MOV.L   R3, [-R1]                             ; save R3 on thread stack
+    MOV.L   R15, [-R1]                            ; save R15 on thread stack
+    MOV.L   R14, [-R1]                            ; save R14 on thread stack
+    MVFC    FPSW, R3
+    MOV.L   R3, [-R1]                             ; save FPSW on thread stack
+	
+    POP     R2                                    ; pick up return address from interrupt stack
+    ADD     #16, R0, R0                           ; correct interrupt stack pointer back to the bottom   
+    MVTC    R1, USP                               ; set user/thread stack pointer
+    JMP     R2                                    ; return to ISR
+
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save:
+;
+;        /* Interrupt occurred in the scheduling loop.  */
+;
+    POP     R1                                   ; pick up return address
+    ADD     #16, R0, R0                          ; correct interrupt stack pointer back to the bottom (PC), don't care about saved registers
+    JMP     R1                                   ; return to caller
+;
+;    }
+;}
+    .END
+
diff --git a/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src b/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src
new file mode 100644
index 00000000..39168c1d
--- /dev/null
+++ b/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src
@@ -0,0 +1,96 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    .SECTION    P,CODE
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_control                         RX/CCRX        */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function is responsible for changing the interrupt lockout     */ 
+;/*    posture of the system.                                              */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    new_posture                           New interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+
+.GLB __tx_thread_interrupt_control
+__tx_thread_interrupt_control:
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    
+    MVFC      PSW, R2           ; Save PSW to R2
+    MOV.L     R2, R3            ; Make a copy of PSW in r3
+    
+;
+;    /* Apply the new interrupt posture.  */
+;
+    
+    BTST    #16, R1             ; test I bit of PSW of "new posture"
+    BMNE    #16, R2             ; conditionally set I bit of intermediate posture 
+    
+    MVTC    R2, PSW             ; save intermediate posture to PSW
+    
+    MOV.L   R3,R1               ; Get original SR 
+    RTS                         ; Return to caller
+;}
+    .END
+
diff --git a/ports/rxv2/ccrx/src/tx_thread_schedule.src b/ports/rxv2/ccrx/src/tx_thread_schedule.src
new file mode 100644
index 00000000..a34c12f5
--- /dev/null
+++ b/ports/rxv2/ccrx/src/tx_thread_schedule.src
@@ -0,0 +1,180 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    .GLB     __tx_thread_execute_ptr
+    .GLB     __tx_thread_current_ptr
+    .GLB     __tx_timer_time_slice
+;
+    .SECTION    P,CODE
+
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                                  RX/CCRX        */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function waits for a thread control block pointer to appear in */ 
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+;/*    in the variable, the corresponding thread is resumed.               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+;/*    _tx_thread_system_return             Return to system from thread   */ 
+;/*    _tx_thread_context_restore           Restore thread's context       */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;VOID   _tx_thread_schedule(VOID)
+;{
+    .GLB __tx_thread_schedule
+__tx_thread_schedule:
+;
+;    /* Enable interrupts.  */
+;
+    SETPSW I
+;
+;    /* Wait for a thread to execute.  */
+;    do
+;    {
+    MOV.L    #__tx_thread_execute_ptr, R1     ; Address of thread to executer ptr
+__tx_thread_schedule_loop:
+    MOV.L    [R1],R2                          ; Pickup next thread to execute
+    CMP      #0,R2                            ; Is it NULL?
+    BEQ      __tx_thread_schedule_loop        ; Yes, idle system, keep checking
+;
+;    }
+;    while(_tx_thread_execute_ptr == TX_NULL);
+;    
+;    /* Yes! We have a thread to execute.  Lockout interrupts and
+;       transfer control to it.  */
+;
+    CLRPSW I                                  ; disable interrupts
+;
+;    /* Setup the current thread pointer.  */
+;    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+;
+    MOV.L    #__tx_thread_current_ptr, R3
+    MOV.L    R2,[R3]                          ; Setup current thread pointer
+;
+;    /* Increment the run count for this thread.  */
+;    _tx_thread_current_ptr -> tx_thread_run_count++;
+;
+    MOV.L    4[R2],R3                      ; Pickup run count  
+    ADD      #1,R3                         ; Increment run counter
+    MOV.L    R3,4[R2]                      ; Store it back in control block
+;
+;    /* Setup time-slice, if present.  */
+;    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+;
+    MOV.L    24[R2],R3                     ; Pickup thread time-slice
+    MOV.L    #__tx_timer_time_slice,R4     ; Pickup pointer to time-slice
+    MOV.L    R3, [R4]                      ; Setup time-slice                        
+;
+;    /* Switch to the thread's stack.  */
+;    SP =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+    SETPSW U                               ; user stack mode
+    MOV.L   8[R2],R0                       ; Pickup stack pointer
+;
+;    /* Determine if an interrupt frame or a synchronous task suspension frame
+;   is present.  */
+;
+    POP    R1                               ; Pickup stack type
+    CMP    #1, R1                           ; Is it an interrupt stack?
+    BNE    __tx_thread_synch_return         ; No, a synchronous return frame is present.
+
+    POPM    R1-R3                           ; Restore accumulators.
+    MVTACLO R3, A0
+    MVTACHI R2, A0
+    MVTACGU R1, A0
+    POPM    R1-R3
+    MVTACLO R3, A1
+    MVTACHI R2, A1
+    MVTACGU R1, A1
+
+    POPM   R6-R13                           ; Recover interrupt stack frame
+    POPC   FPSW 
+    POPM   R14-R15
+    POPM   R3-R5
+    POPM   R1-R2    
+    RTE                                     ; return to point of interrupt, this restores PC and PSW
+  
+__tx_thread_synch_return:
+   POPC    PSW
+   POPM    R6-R13                           ; Recover solicited stack frame
+   RTS
+;
+;}
+
+
+.GLB __tx_thread_context_save
+.GLB __tx_thread_context_restore
+
+; Software triggered interrupt used to perform context switches.
+; The priority of this interrupt is set to the lowest priority within
+; tx_initialize_low_level() and triggered by ThreadX when calling
+; _tx_thread_system_return().
+.RVECTOR 27, _tx_software_interrupt_entry
+.GLB _tx_software_interrupt_entry
+_tx_software_interrupt_entry:
+
+    PUSHM R1-R2
+
+    BSR __tx_thread_context_save
+
+    BRA __tx_thread_context_restore
+
+    .END
diff --git a/ports/rxv2/ccrx/src/tx_thread_stack_build.src b/ports/rxv2/ccrx/src/tx_thread_stack_build.src
new file mode 100644
index 00000000..38da71c9
--- /dev/null
+++ b/ports/rxv2/ccrx/src/tx_thread_stack_build.src
@@ -0,0 +1,155 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    .SECTION    P,CODE
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_stack_build                               RX/CCRX        */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    .GLB __tx_thread_stack_build
+__tx_thread_stack_build:
+;
+;       
+;    /* Build an interrupt frame.  The form of the fake interrupt stack
+;       on the Renesas RX should look like the following after it is built:
+;       
+;  Stack Top:           1       Interrupt stack frame type
+;                       ACC0
+;                       ACC1
+;                       R6
+;                       R7
+;                       R8
+;                       R9
+;                       R10
+;                       R11
+;                       R12
+;                       R13
+;                       FPSW
+;                       R14
+;                       R15
+;                       R3
+;                       R4
+;                       R5
+;                       R1
+;                       R2
+;                       PC
+;                       PSW
+
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    MOV.L   16[R1],R3               ; Pickup end of stack area
+    BCLR    #0, R3                  ; mask for 4-byte alignment
+    BCLR    #1, R3
+;
+;    /* Build the stack frame.  */
+;
+    MOV.L #30000h, R4
+    MOV.L R4, [-R3]                         ; initial PSW (SVC mode, U flag set)
+    MOV.L R2, [-R3]                         ; initial PC
+    MOV.L #0, R4
+    MOV.L R4,[-R3]                          ; initial R2 ...
+    MOV.L R4,[-R3]                          ; initial R1 ...    
+    MOV.L R4,[-R3]                          ; initial R5 ...
+    MOV.L R4,[-R3]                          ; initial R4 ...
+    MOV.L R4,[-R3]                          ; initial R3 ...    
+    MOV.L R4,[-R3]                          ; initial R15 ...
+    MOV.L R4,[-R3]                          ; initial R14 ...
+    MVFC  FPSW, r4
+    MOV.L R4, [-R3]                         ; initial FPSW
+    MOV.L #0, R4
+    MOV.L R4,[-R3]                          ; initial R13 ...   
+    MOV.L R4,[-R3]                          ; initial R12 ...
+    MOV.L R4,[-R3]                          ; initial R11 ...
+    MOV.L R4,[-R3]                          ; initial R10 ...   
+    MOV.L R4,[-R3]                          ; initial R9 ...
+    MOV.L R4,[-R3]                          ; initial R8 ...
+    MOV.L R4,[-R3]                          ; initial R7 ...    
+    MOV.L R4,[-R3]                          ; initial R6 ...
+
+    MOV.L R4,[-R3]                          ; Accumulator 1
+    MOV.L R4,[-R3]
+    MOV.L R4,[-R3]
+
+    MOV.L R4,[-R3]                          ; Accumulator 0
+    MOV.L R4,[-R3]
+    MOV.L R4,[-R3]
+
+    MOV.L #1, R4
+    MOV.L R4,[-R3]                           ; indicate interrupt stack frame
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  R1;   
+    MOV.L R3, 8[R1]
+                                            ; store initial SP in thread control block
+    RTS
+                                 
+;}
+    .END
+
diff --git a/ports/rxv2/ccrx/src/tx_thread_system_return.src b/ports/rxv2/ccrx/src/tx_thread_system_return.src
new file mode 100644
index 00000000..fb70a970
--- /dev/null
+++ b/ports/rxv2/ccrx/src/tx_thread_system_return.src
@@ -0,0 +1,127 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    .GLB     __tx_thread_current_ptr
+    .GLB     __tx_timer_time_slice
+    .GLB     __tx_thread_schedule
+
+    .SECTION    P,CODE
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_system_return                             RX/CCRX        */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function is target processor specific.  It is used to transfer */ 
+;/*    control from a thread back to the system.  Only a minimal context   */ 
+;/*    is saved since the compiler assumes temp registers are going to get */ 
+;/*    slicked by a function call anyway.                                  */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling loop        */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ThreadX components                                                  */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;VOID   _tx_thread_system_return(VOID)
+;{
+    .GLB __tx_thread_system_return
+__tx_thread_system_return:
+;
+;    /* Save call save registers on the stack.  */
+;
+      PUSHM    R6-R13
+      PUSHC    PSW
+      MOV.L    #0, R1
+      PUSH.L   R1              ; solicited stack frame    
+;   
+;   /* Lockout interrupts.  */
+;
+      CLRPSW   I               ; Lockout interrupts
+;
+;    /* Save current stack in current Thread controle block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  SP;
+     MOV.L   #__tx_thread_current_ptr, R2
+     MOV.L   [R2], R3
+     MOV.L   R0, 8[R3]
+    
+     MOV.L   #__tx_timer_time_slice, R4
+     MOV.L   [R4], R5
+
+;    /* Determine if the time-slice is active.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+     CMP     #0,R5                       ; Is a time-slice present?
+     BEQ     __tx_thread_dont_save_ts    ; No, don't save the time-slice
+;
+;   /* Save time-slice for the thread and clear the current time-slice.  */
+    ;   _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+     MOV.L   R5,24[R3]  
+;   _tx_timer_time_slice =  0;
+;
+     MOV.L   R1, [R4] ; Disable the time-slice         
+;
+;    }
+__tx_thread_dont_save_ts:
+;
+;    /* Clear the current thread pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    MOV.L   R1, [R2]
+    BRA  __tx_thread_schedule
+;}
+    .END
+
diff --git a/ports/rxv2/ccrx/src/tx_timer_interrupt.src b/ports/rxv2/ccrx/src/tx_timer_interrupt.src
new file mode 100644
index 00000000..cf88b6c1
--- /dev/null
+++ b/ports/rxv2/ccrx/src/tx_timer_interrupt.src
@@ -0,0 +1,251 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    .GLB     __tx_timer_time_slice
+    .GLB     __tx_timer_system_clock
+    .GLB     __tx_timer_current_ptr
+    .GLB     __tx_timer_list_start
+    .GLB     __tx_timer_list_end
+    .GLB     __tx_timer_expired_time_slice
+    .GLB     __tx_timer_expired
+    .GLB     __tx_timer_expiration_process
+    .GLB     __tx_thread_context_save
+    .GLB     __tx_thread_time_slice
+    .GLB     __tx_thread_context_restore
+;
+    .SECTION    P,CODE
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_timer_interrupt                                  RX/CCRX        */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function processes the hardware timer interrupt.  This         */ 
+;/*    processing includes incrementing the system clock and checking for  */ 
+;/*    time slice and/or timer expiration.  If either is found, the        */ 
+;/*    interrupt context save/restore functions are called along with the  */ 
+;/*    expiration functions.                                               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_save               Save interrupted context      */ 
+;/*    _tx_timer_expiration_process          Timer expiration processing   */ 
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */ 
+;/*    _tx_thread_context_restore            Restore interrupted context   */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    interrupt vector                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    .GLB __tx_timer_interrupt
+__tx_timer_interrupt:
+;
+;    /* Upon entry to this routine, it is assumed that all interrupts are locked
+;       out and the stack looks like the following:
+;                            SP+4 ->    Interrupted PC
+;                            SP+8->    Interrupted SR
+;   */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    PUSHM    R14-R15
+    PUSHM    R1-R5
+
+    MOV.L    #__tx_timer_system_clock, R1    ; Pickup address of system clock
+    MOV.L    [R1], R2                        ; Pickup system clock
+    ADD      #1, R2                          ; Increment system clock
+    MOV.L    R2,[R1]                         ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV.L   #__tx_timer_time_slice, R1       ; Pickup address of time slice
+    MOV.L   [R1], R2                         ; Pickup the current time slice
+    CMP     #0, R2                           ; Is a time slice active?
+    BEQ     __tx_timer_no_time_slice         ; No, skip timer slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     #1, R2                           ; Decrement the time-slice
+    MOV.L   R2, [R1]                         ; Store time-slice
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CMP     #0, R2                           ; Has it expired?
+    BNE     __tx_timer_no_time_slice         ; No, time-slice has not expired
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV.L   #__tx_timer_expired_time_slice, R1  ; Pickup address of expired time-slice
+    MOV.L   #1, R2                           ; Build expired value
+    MOV.L   R2, [R1]                         ; Set expired time slice variable
+;    }
+;
+__tx_timer_no_time_slice:
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV.L   #__tx_timer_current_ptr, R1     ; Pickup address of current timer ptr
+    MOV.L   [R1], R2                        ; Pickup current pointer
+    MOV.L   [R2+], R1                       ; pickup timer list entry, _tx_timer_current_ptr++
+    CMP     #0, R1                          ; Is timer pointer NULL?
+    BEQ     __tx_timer_no_timer            ; Yes, no timer has expired
+        
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV.L   #__tx_timer_expired,R2          ; Build address of expired flag
+    MOV.L   #1, R1                          ; Build expired value
+    MOV.L   R1, [R2]    
+    BRA     __tx_timer_done                 ; Finished with timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer:
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+;       /* R2 already contains __tx_timer_current_ptr++ */                         
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV.L   #__tx_timer_list_end, R1          ; Pickup the timer list end ptr
+    MOV.L   [R1], R1                          ; Pickup actual timer list end
+    CMP     R1, R2                            ; Are we at list end?
+    BNE     __tx_timer_skip_wrap              ; No, don't move pointer to the
+                                              ;   top of the list
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV.L   #__tx_timer_list_start, R2        ; Pickup the timer list start ptr
+    MOV.L   [R2], R2                          ; Pickup the start of the list
+;    }
+;
+__tx_timer_skip_wrap:
+    MOV.L   #__tx_timer_current_ptr,R1     
+    MOV.L   R2, [R1]                          ; store in updated pointer in  _tx_timer_current_ptr  
+    
+__tx_timer_done:
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV.L  #__tx_timer_expired_time_slice, R1    ; Pickup expired time slice addr
+    MOV.L  [R1], R1                           ; Pickup expired time slice
+    MOV.L   #__tx_timer_expired, R2           ; Pickup expired timer flag address
+    MOV.L   [R2], R2                          ; Pickup actual flag
+    OR      R1, R2                            ; Or flags together
+    BEQ     __tx_timer_nothing_expired        ; If Z set, nothing has expired
+
+__tx_something_expired:
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+    MOV.L   #__tx_timer_expired,R1            ; Pickup expired flag address
+    MOV.L   [R1], R1                          ; Pickup expired flag
+    CMP     #0,R1                             ; Is the expired timer flag set?
+    BEQ     __tx_timer_dont_activate          ; No, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BSR    __tx_timer_expiration_process      ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate:
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+; 
+    MOV.L   #__tx_timer_expired_time_slice, R1   ; Pickup time-slice expired flag addr
+    MOV.L   [R1], R1                           ; Pickup actual flag
+    CMP     #0,R1                              ; Has time-slice expired?
+    BEQ      __tx_timer_not_ts_expiration      ; No, skip time-slice expiration
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BSR     __tx_thread_time_slice             ; Call time-slice processing
+;    }
+;
+__tx_timer_not_ts_expiration:
+
+__tx_timer_nothing_expired:
+
+    POPM R1-R5
+    POPM R14-R15
+;
+    RTS                                       ; return to point of interrupt
+;
+;}
+
+    .END
+
diff --git a/ports/rxv2/gnu/inc/tx_port.h b/ports/rxv2/gnu/inc/tx_port.h
new file mode 100644
index 00000000..57841625
--- /dev/null
+++ b/ports/rxv2/gnu/inc/tx_port.h
@@ -0,0 +1,264 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                            RX/GNURX       */
+/*                                                           6.1.3        */
+/*                                                                        */
+/*  AUTHOR                                                                */ 
+/*                                                                        */ 
+/*    William E. Lamie, Express Logic, Inc.                               */ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+#include <string.h>
+//#include <intrinsics.h>
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        256         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          0
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2          
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  UCHAR interrupt_save;
+#define TX_DISABLE                              {interrupt_save = ((UCHAR)__builtin_rx_mvfc(0u) && 0x8u); __builtin_rx_clrpsw(8u);};
+#define TX_RESTORE                              {if(interrupt_save != 0u) {__builtin_rx_setpsw(8u);}};
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+static void _tx_thread_system_return_inline(void)
+{
+    TX_INTERRUPT_SAVE_AREA
+
+    TX_DISABLE
+
+    *((volatile UCHAR *)(0x872E0u)) = 1u;
+
+    TX_RESTORE
+}
+
+#endif
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RX/GNURX Version 6.1.3 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+#endif
+
diff --git a/ports/rxv2/gnu/readme_threadx.txt b/ports/rxv2/gnu/readme_threadx.txt
new file mode 100644
index 00000000..5baf5961
--- /dev/null
+++ b/ports/rxv2/gnu/readme_threadx.txt
@@ -0,0 +1,168 @@
+                     Microsoft's Azure RTOS ThreadX for Renesas RXv2
+
+                            Using the GNU Tools
+
+
+1.  Building the ThreadX run-time Library
+
+Please see the Samples repository on GitHub for the Azure RTOS demonstrations
+for the RXv2.
+
+
+2.  Demonstration System
+
+
+Please see the Samples repository on GitHub for the Azure RTOS demonstrations
+for the RXv2.
+
+
+3.  System Initialization
+
+The system entry point using the GNU tools is at the label _PowerON_Reset. 
+
+The vector area is setup in the file tx_initialize_low_level.S. This file is also 
+responsible for setting up various system data structures, interrupt vectors, and 
+the periodic timer interrupt. This file is also an ideal place to add additional hardware 
+initialization code.
+
+The ThreadX demonstration for the RXv2 utilizes CMT0 as a periodic timer interrupt 
+source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the 
+interrupt priority level is set to level 7. You may change any of the timer 
+parameters as needed. Increasing the timer interrupt frequency increases the overhead
+of the timer handling code on the system.
+
+In addition, _tx_initialize_low_level determines the first available address for use 
+by the application, which is supplied as the sole input parameter to your application 
+definition function, tx_application_define. The first available memory is determined 
+by the location of the '_end' label the is defined in the linker script.
+'_end' should reference the first memory AFTER all other RAM 
+sections in your linker control file.
+
+
+4.  Context Switch, Register Usage and Stack Frames
+
+The RXv2 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #17,
+to perform context switch. This ISR is thus reserved when using ThreadX and the SWINT
+should not be manipulated in any way by the application. The port will setup the 
+interrupt within _tx_initialize_low_level and the compiler will automatically install
+the necessary interrupt vector. As such no additional initialization is necessary by the
+application.
+
+The following defines the saved context stack frame used by the ThreadX port. The
+state of the CPU registers at the time of a context switch is saved on the running 
+thread's stack The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+    Offset        Interrupted Stack Frame
+
+     0x00                   1
+     0x04                   ACC0
+     0x08                   ACC1
+     0x0C                   R6
+     0x10                   R7
+     0x14                   R8
+     0x18                   R9
+     0x1C                   R10
+     0x20                   R11
+     0x24                   R12
+     0x28                   R13
+     0x2C                   FPSW
+     0x30                   R14
+     0x34                   R15
+     0x38                   R3
+     0x3C                   R4
+     0x40                   R5
+     0x44                   R1
+     0x48                   R2
+     0x4C                   PC - return address
+     0x50                   PSW
+     
+Note: By default GNURX does not save the state of the accumulator registers ACC0 and ACC1
+when entering an ISR. This means that if the ISR uses any of the DSP instructions the
+content of those registers could be corrupted. Saving and restoring of the acummulators
+can be enabled by adding the -msave-acc-in-interrupts command line option.
+
+     
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler optimizations.  This 
+makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself.  
+Of course, this costs some performance. To make ThreadX run faster, you can change the 
+ThreadX Library project to disable debug information and enable the desired optimizations.  
+
+In addition, you can eliminate the ThreadX basic API error checking by compiling your 
+application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h 
+is included. 
+
+
+6. Timer Processing
+
+Timer processign is performed by calling __tx_timer_interrupt(). This should usually be done
+from within the callback of a periodic timer with a period of 100Hz. In the sample projects
+a Renesas Fit CMT periodic timer module (rx_cmt) is used as the timer source.
+
+
+7.  Interrupt Handling
+
+Interrupt handling is unaffected by the ThreadX port as such user interrupts can be 
+written according to the toolchain's documentation. It is recommended not to use interrupt
+priority 15 as this is the priority of the context switch interrupt. However using interrupt
+priority 15 won't cause any negative side effectd but doing so may may slightly reduce 
+performance. Please refer to the toolchain documentation for additional details on how to
+define interupt service routines.
+
+
+8. Execution Profiling
+
+The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists 
+of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation 
+of the EPK for generic usage details.
+
+To add the EPK to your RXv2 release make the following modifications:
+
+* Enable the following define for both the Threadx library and the application
+TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+* in tx_port.h, change around line 183
+change #define TX_THREAD_EXTENSION_3     
+into #include "tx_execution_profile.h"   
+
+* Setup CMT1 as a free running 16 bit timer.
+
+* In tx_execution_profile.h, change following around line 74:
+
+#ifdef TX_EXECUTION_64BIT_TIME
+typedef unsigned long long              EXECUTION_TIME;
+#define TX_THREAD_EXTENSION_3           unsigned long long  tx_thread_execution_time_total; \
+                                        unsigned long long  tx_thread_execution_time_last_start; 
+#define TX_EXECUTION_MAX_TIME_SOURCE    0xFFFFFFFFFFFFFFFF
+#else
+typedef unsigned long                   EXECUTION_TIME;
+#define TX_THREAD_EXTENSION_3           unsigned long   tx_thread_execution_time_total; \
+                                        unsigned long   tx_thread_execution_time_last_start; 
+#define TX_EXECUTION_MAX_TIME_SOURCE    0xFFFF
+#endif
+                                        
+/* Define basic constants for the execution profile kit.  */
+
+#define TX_EXECUTION_TIME_SOURCE         (EXECUTION_TIME)  *((USHORT *) 0x8800A)
+
+Rebuild the Threadx library and the application.
+Refer to the EPK documentation how to interpret the results.
+
+
+9.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+
+12-31-2020  Initial ThreadX release for the RXv2 using GNURX tools, version 6.1.3
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/rxv2/gnu/src/tx_initialize_low_level.S b/ports/rxv2/gnu/src/tx_initialize_low_level.S
new file mode 100644
index 00000000..197ae936
--- /dev/null
+++ b/ports/rxv2/gnu/src/tx_initialize_low_level.S
@@ -0,0 +1,93 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+
+    .text
+
+;
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_initialize_low_level                             RX/GNURX       */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for any low-level processor            */
+;/*    initialization, including setting up interrupt vectors, setting     */
+;/*    up a periodic timer interrupt source, saving the system stack       */
+;/*    pointer for use in ISR processing later, and finding the first      */
+;/*    available RAM memory address for tx_application_define.             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+    .global __tx_initialize_low_level
+__tx_initialize_low_level:
+
+;
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) &free_mem_start;
+;
+    MOV.L    #_end, R1                ; Pickup unused memory address
+    MOV.L    #__tx_initialize_unused_memory, R2
+    MOV.L    R1,[R2]                            ; Save first free memory address
+
+;   /* Set priority of SWINT to 1. */
+    MOV.L    #0x87303, r1
+    MOV.L    #1, r2
+    MOV.B    r2, [r1]
+
+;   /* Enable SWINT. */
+    MOV.L    #0x87203,r1
+    MOV.B    [r1], r2
+    OR       #(1 << 3), r2
+    MOV.B    r2, [r1]
+
+    RTS
+
+
+    .end
diff --git a/ports/rxv2/gnu/src/tx_thread_context_restore.S b/ports/rxv2/gnu/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..c2799838
--- /dev/null
+++ b/ports/rxv2/gnu/src/tx_thread_context_restore.S
@@ -0,0 +1,207 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    .global     __tx_thread_system_state
+    .global     __tx_thread_current_ptr
+    .global     __tx_thread_system_stack_ptr
+    .global     __tx_thread_execute_ptr
+    .global     __tx_timer_time_slice
+    .global     __tx_thread_schedule
+    .global     __tx_thread_preempt_disable
+
+    .text
+
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_restore                           RX/GNURX       */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function restores the interrupt context if it is processing a  */
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+;/*    if no thread was running, the function returns to the scheduler.    */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling routine     */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                  Interrupt Service Routines    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    .global __tx_thread_context_restore
+__tx_thread_context_restore:
+;
+;    /* Lockout interrupts.  */
+
+     CLRPSW I                                 ; disable interrupts
+
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+
+     MOV.L    #__tx_thread_system_state, R1
+     MOV.L    [R1], R2
+     SUB      #1, R2
+     MOV.L    R2,[R1]
+     BEQ      __tx_thread_not_nested_restore
+
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Recover the saved registers from the interrupt stack
+;       and return to the point of interrupt.  */
+;
+__tx_thread_nested_restore:
+     POPC    FPSW                                ; restore FPU status
+     POPM    R14-R15             ; restore R14-R15
+     POPM    R3-R5               ; restore R3-R5
+     POPM    R1-R2               ; restore R1-R2
+     RTE                         ; return to point of interrupt, restore PSW including IPL
+;    }
+
+__tx_thread_not_nested_restore:
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
+;               || (_tx_thread_preempt_disable))
+;    {
+
+     MOV.L    #__tx_thread_current_ptr, R1       ; Pickup current thread ptr address
+     MOV.L    [R1], R2
+     CMP      #0, R2
+     BEQ      __tx_thread_idle_system_restore
+
+     MOV.L    #__tx_thread_preempt_disable, R3   ; pick up preempt disable flag
+     MOV.L    [R3], R3
+     CMP      #0, R3
+     BNE      __tx_thread_no_preempt_restore     ; if pre-empt disable flag set, we simply return to the original point of interrupt regardless
+
+     MOV.L    #__tx_thread_execute_ptr, R3       ; (_tx_thread_current_ptr != _tx_thread_execute_ptr)
+     CMP      [R3], R2
+     BNE      __tx_thread_preempt_restore        ; jump to pre-empt restoring
+;
+__tx_thread_no_preempt_restore:
+     SETPSW  U                   ; user stack
+     POPC    FPSW                ; restore FPU status
+     POPM    R14-R15             ; restore R14-R15
+     POPM    R3-R5               ; restore R3-R5
+     POPM    R1-R2               ; restore R1-R2
+     RTE                         ; return to point of interrupt, restore PSW including IPL
+
+;    }
+;    else
+;    {
+
+__tx_thread_preempt_restore:
+
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+
+     MOV.L    #__tx_timer_time_slice, R3        ; Pickup time-slice address
+     MOV.L    [R3],R4                           ; Pickup actual time-slice
+     CMP      #0, R4
+     BEQ      __tx_thread_dont_save_ts          ; no time slice to save
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0;
+;
+     MOV.L    R4,24[R2]                         ; Save thread's time slice
+     MOV.L    #0,R4                             ; Clear value
+     MOV.L    R4,[R3]                           ; Disable global time slice flag
+;    }
+__tx_thread_dont_save_ts:
+;
+;   /* Now store the remaining registers!   */
+
+     SETPSW   U                                 ; user stack
+     PUSHM    R6-R13
+
+     MVFACGU   #0, A1, R4                       ; Save accumulators.
+     MVFACHI   #0, A1, R5
+     MVFACLO   #0, A1, R6
+     PUSHM     R4-R6
+     MVFACGU   #0, A0, R4
+     MVFACHI   #0, A0, R5
+     MVFACLO   #0, A0, R6
+     PUSHM     R4-R6
+
+     MOV.L    #1, R3                            ; indicate interrupt stack frame
+     PUSH.L   R3
+
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;    R1 ->  _tx_thread_current_ptr
+;    R2 -> *_tx_thread_current_ptr
+
+     MOV.L   R0,8[R2]                        ; Save thread's stack pointer in thread control block
+     MOV.L   #0,R2                           ; Build NULL value
+     MOV.L   R2,[R1]                         ; Set current thread to NULL
+
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+
+__tx_thread_idle_system_restore:
+     MVTC    #0, PSW                          ; reset interrupt priority level to 0
+     BRA     __tx_thread_schedule             ; jump to scheduler
+;    }
+;
+;}
+;
+    .end
diff --git a/ports/rxv2/gnu/src/tx_thread_context_save.S b/ports/rxv2/gnu/src/tx_thread_context_save.S
new file mode 100644
index 00000000..cae38615
--- /dev/null
+++ b/ports/rxv2/gnu/src/tx_thread_context_save.S
@@ -0,0 +1,171 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+    .global     __tx_thread_system_state
+    .global     __tx_thread_current_ptr
+    .global     __tx_thread_system_stack_ptr
+
+    .text
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_save                              RX/GNURX       */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function saves the context of an executing thread in the       */
+;/*    beginning of interrupt processing.  The function also ensures that  */
+;/*    the system stack is used upon return to the calling ISR.            */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                                                */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    .global __tx_thread_context_save
+__tx_thread_context_save:
+;
+;    /* Upon entry to this routine, it is assumed that interrupts are locked
+;       out and the (interrupt) stack frame looks like the following:
+;
+;           (lower address) SP   ->     [return address of this call]
+;                           SP+4 ->     Saved R1
+;                           SP+8 ->     Saved R2
+;                           SP+12->     Interrupted PC
+;                           SP+16->     Interrupted PSW
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+
+    MOV.L   #__tx_thread_system_state, R1     ; pick up address of system state
+    MOV.L   [R1], R2                           ; pick up system state
+    CMP     #0, R2                             ; 0 -> no nesting
+    BEQ     __tx_thread_not_nested_save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD   #1, r2                             ; _tx_thread_system_state++
+    MOV.L   r2, [r1]
+
+;
+;   /* Save the rest of the scratch registers on the interrupt stack and return to the
+;       calling ISR.  */
+    POP R1                                      ; recuperate return address from stack
+    PUSHM   R3-R5
+    PUSHM   R14-R15
+    PUSHC   FPSW                                ; (top) FPSW, R14, R15, R3, R4, R5, R1, R2, PC, PSW (bottom)
+    JMP     R1                                  ; return address was preserved in R1
+
+;
+__tx_thread_not_nested_save:
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     #1, R2                                ; _tx_thread_system_state++
+    MOV.L   R2, [R1]
+
+    MOV.L   #__tx_thread_current_ptr, R2         ; Pickup current thread pointer
+    MOV.L   [R2], R2
+    CMP     #0,R2                                ; Is it NULL?
+    BEQ      __tx_thread_idle_system_save        ; Yes, idle system is running - idle restore
+;
+;    /* Move stack frame over to the current threads stack.  */
+;    /* complete stack frame with registers not saved yet (R3-R5, R14-R15, FPSW)   */
+;
+    MVFC    USP, R1                               ; pick up user stack pointer
+    MOV.L   16[R0], R2
+    MOV.L   R2, [-R1]                             ; save PSW on thread stack
+    MOV.L   12[R0], R2
+    MOV.L   R2, [-R1]                             ; save PC on thread stack
+    MOV.L   8[R0], R2
+    MOV.L   R2, [-R1]                             ; save R2 on thread stack
+    MOV.L   4[R0], R2
+    MOV.L   R2, [-R1]                             ; save R1 on thread stack
+    MOV.L   R5, [-R1]                             ; save R5 on thread stack
+    MOV.L   R4, [-R1]                             ; save R4 on thread stack
+    MOV.L   R3, [-R1]                             ; save R3 on thread stack
+    MOV.L   R15, [-R1]                            ; save R15 on thread stack
+    MOV.L   R14, [-R1]                            ; save R14 on thread stack
+    MVFC    FPSW, R3
+    MOV.L   R3, [-R1]                             ; save FPSW on thread stack
+
+    POP     R2                                    ; pick up return address from interrupt stack
+    ADD     #16, R0, R0                           ; correct interrupt stack pointer back to the bottom
+    MVTC    R1, USP                               ; set user/thread stack pointer
+    JMP     R2                                    ; return to ISR
+
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save:
+;
+;        /* Interrupt occurred in the scheduling loop.  */
+;
+    POP     R1                                   ; pick up return address
+    ADD     #16, R0, R0                          ; correct interrupt stack pointer back to the bottom (PC), don't care about saved registers
+    JMP     R1                                   ; return to caller
+;
+;    }
+;}
+    .end
+
diff --git a/ports/rxv2/gnu/src/tx_thread_interrupt_control.S b/ports/rxv2/gnu/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..096c0568
--- /dev/null
+++ b/ports/rxv2/gnu/src/tx_thread_interrupt_control.S
@@ -0,0 +1,96 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    .text
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_control                         RX/GNURX       */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for changing the interrupt lockout     */
+;/*    posture of the system.                                              */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    new_posture                           New interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+
+    .global __tx_thread_interrupt_control
+__tx_thread_interrupt_control:
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+
+    MVFC      PSW, R2           ; Save PSW to R2
+    MOV.L     R2, R3            ; Make a copy of PSW in r3
+
+;
+;    /* Apply the new interrupt posture.  */
+;
+
+    BTST    #16, R1             ; test I bit of PSW of "new posture"
+    BMNE    #16, R2             ; conditionally set I bit of intermediate posture
+
+    MVTC    R2, PSW             ; save intermediate posture to PSW
+
+    MOV.L   R3,R1               ; Get original SR
+    RTS                         ; Return to caller
+;}
+    .end
+
diff --git a/ports/rxv2/gnu/src/tx_thread_schedule.S b/ports/rxv2/gnu/src/tx_thread_schedule.S
new file mode 100644
index 00000000..c48840e7
--- /dev/null
+++ b/ports/rxv2/gnu/src/tx_thread_schedule.S
@@ -0,0 +1,180 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    .global     __tx_thread_execute_ptr
+    .global     __tx_thread_current_ptr
+    .global     __tx_timer_time_slice
+;
+    .text
+
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_schedule                                  RX/GNURX       */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function waits for a thread control block pointer to appear in */
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+;/*    in the variable, the corresponding thread is resumed.               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+;/*    _tx_thread_system_return             Return to system from thread   */
+;/*    _tx_thread_context_restore           Restore thread's context       */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+    .global __tx_thread_schedule
+__tx_thread_schedule:
+;
+;    /* Enable interrupts.  */
+;
+    SETPSW I
+;
+;    /* Wait for a thread to execute.  */
+;    do
+;    {
+    MOV.L    #__tx_thread_execute_ptr, R1     ; Address of thread to executer ptr
+__tx_thread_schedule_loop:
+    MOV.L    [R1],R2                          ; Pickup next thread to execute
+    CMP      #0,R2                            ; Is it NULL?
+    BEQ      __tx_thread_schedule_loop        ; Yes, idle system, keep checking
+;
+;    }
+;    while(_tx_thread_execute_ptr == TX_NULL);
+;
+;    /* Yes! We have a thread to execute.  Lockout interrupts and
+;       transfer control to it.  */
+;
+    CLRPSW I                                  ; disable interrupts
+;
+;    /* Setup the current thread pointer.  */
+;    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+;
+    MOV.L    #__tx_thread_current_ptr, R3
+    MOV.L    R2,[R3]                          ; Setup current thread pointer
+;
+;    /* Increment the run count for this thread.  */
+;    _tx_thread_current_ptr -> tx_thread_run_count++;
+;
+    MOV.L    4[R2],R3                      ; Pickup run count
+    ADD      #1,R3                         ; Increment run counter
+    MOV.L    R3,4[R2]                      ; Store it back in control block
+;
+;    /* Setup time-slice, if present.  */
+;    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+;
+    MOV.L    24[R2],R3                     ; Pickup thread time-slice
+    MOV.L    #__tx_timer_time_slice,R4     ; Pickup pointer to time-slice
+    MOV.L    R3, [R4]                      ; Setup time-slice
+;
+;    /* Switch to the thread's stack.  */
+;    SP =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+    SETPSW U                               ; user stack mode
+    MOV.L   8[R2],R0                       ; Pickup stack pointer
+;
+;    /* Determine if an interrupt frame or a synchronous task suspension frame
+;   is present.  */
+;
+    POP    R1                               ; Pickup stack type
+    CMP    #1, R1                           ; Is it an interrupt stack?
+    BNE    __tx_thread_synch_return         ; No, a synchronous return frame is present.
+
+    POPM    R1-R3                           ; Restore accumulators.
+    MVTACLO R3, A0
+    MVTACHI R2, A0
+    MVTACGU R1, A0
+    POPM    R1-R3
+    MVTACLO R3, A1
+    MVTACHI R2, A1
+    MVTACGU R1, A1
+
+    POPM   R6-R13                           ; Recover interrupt stack frame
+    POPC   FPSW
+    POPM   R14-R15
+    POPM   R3-R5
+    POPM   R1-R2
+    RTE                                     ; return to point of interrupt, this restores PC and PSW
+
+__tx_thread_synch_return:
+   POPC    PSW
+   POPM    R6-R13                           ; Recover solicited stack frame
+   RTS
+;
+;}
+
+
+.global __tx_thread_context_save
+.global __tx_thread_context_restore
+
+
+; Software triggered interrupt used to perform context switches.
+; The priority of this interrupt is set to the lowest priority within
+; tx_initialize_low_level() and triggered by ThreadX when calling
+; _tx_thread_system_return().
+.global $tableentry$27$.rvectors
+$tableentry$27$.rvectors:
+
+    PUSHM R1-R2
+
+    BSR __tx_thread_context_save
+
+    BRA __tx_thread_context_restore
+
+    .end
diff --git a/ports/rxv2/gnu/src/tx_thread_stack_build.S b/ports/rxv2/gnu/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..752372bf
--- /dev/null
+++ b/ports/rxv2/gnu/src/tx_thread_stack_build.S
@@ -0,0 +1,155 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    .text
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_stack_build                               RX/GNURX       */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    .global __tx_thread_stack_build
+__tx_thread_stack_build:
+;
+;
+;    /* Build an interrupt frame.  The form of the fake interrupt stack
+;       on the Renesas RX should look like the following after it is built:
+;
+;  Stack Top:           1       Interrupt stack frame type
+;                       ACC0
+;                       ACC1
+;                       R6
+;                       R7
+;                       R8
+;                       R9
+;                       R10
+;                       R11
+;                       R12
+;                       R13
+;                       FPSW
+;                       R14
+;                       R15
+;                       R3
+;                       R4
+;                       R5
+;                       R1
+;                       R2
+;                       PC
+;                       PSW
+
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    MOV.L   16[R1],R3               ; Pickup end of stack area
+    BCLR    #0, R3                  ; mask for 4-byte alignment
+    BCLR    #1, R3
+;
+;    /* Build the stack frame.  */
+;
+    MOV.L #30000h, R4
+    MOV.L R4, [-R3]                         ; initial PSW (SVC mode, U flag set)
+    MOV.L R2, [-R3]                         ; initial PC
+    MOV.L #0, R4
+    MOV.L R4,[-R3]                          ; initial R2 ...
+    MOV.L R4,[-R3]                          ; initial R1 ...
+    MOV.L R4,[-R3]                          ; initial R5 ...
+    MOV.L R4,[-R3]                          ; initial R4 ...
+    MOV.L R4,[-R3]                          ; initial R3 ...
+    MOV.L R4,[-R3]                          ; initial R15 ...
+    MOV.L R4,[-R3]                          ; initial R14 ...
+    MVFC  FPSW, r4
+    MOV.L R4, [-R3]                         ; initial FPSW
+    MOV.L #0, R4
+    MOV.L R4,[-R3]                          ; initial R13 ...
+    MOV.L R4,[-R3]                          ; initial R12 ...
+    MOV.L R4,[-R3]                          ; initial R11 ...
+    MOV.L R4,[-R3]                          ; initial R10 ...
+    MOV.L R4,[-R3]                          ; initial R9 ...
+    MOV.L R4,[-R3]                          ; initial R8 ...
+    MOV.L R4,[-R3]                          ; initial R7 ...
+    MOV.L R4,[-R3]                          ; initial R6 ...
+
+    MOV.L R4,[-R3]                          ; Accumulator 1
+    MOV.L R4,[-R3]
+    MOV.L R4,[-R3]
+
+    MOV.L R4,[-R3]                          ; Accumulator 0
+    MOV.L R4,[-R3]
+    MOV.L R4,[-R3]
+
+    MOV.L #1, R4
+    MOV.L R4,[-R3]                           ; indicate interrupt stack frame
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  R1;
+    MOV.L R3, 8[R1]
+                                            ; store initial SP in thread control block
+    RTS
+
+;}
+    .end
+
diff --git a/ports/rxv2/gnu/src/tx_thread_system_return.S b/ports/rxv2/gnu/src/tx_thread_system_return.S
new file mode 100644
index 00000000..baa5314a
--- /dev/null
+++ b/ports/rxv2/gnu/src/tx_thread_system_return.S
@@ -0,0 +1,127 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    .global     __tx_thread_current_ptr
+    .global     __tx_timer_time_slice
+    .global     __tx_thread_schedule
+
+    .text
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_system_return                             RX/GNURX       */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is target processor specific.  It is used to transfer */
+;/*    control from a thread back to the system.  Only a minimal context   */
+;/*    is saved since the compiler assumes temp registers are going to get */
+;/*    slicked by a function call anyway.                                  */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling loop        */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ThreadX components                                                  */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    .GLB __tx_thread_system_return
+__tx_thread_system_return:
+;
+;    /* Save call save registers on the stack.  */
+;
+      PUSHM    R6-R13
+      PUSHC    PSW
+      MOV.L    #0, R1
+      PUSH.L   R1              ; solicited stack frame
+;
+;   /* Lockout interrupts.  */
+;
+      CLRPSW   I               ; Lockout interrupts
+;
+;    /* Save current stack in current Thread controle block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  SP;
+     MOV.L   #__tx_thread_current_ptr, R2
+     MOV.L   [R2], R3
+     MOV.L   R0, 8[R3]
+
+     MOV.L   #__tx_timer_time_slice, R4
+     MOV.L   [R4], R5
+
+;    /* Determine if the time-slice is active.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+     CMP     #0,R5                       ; Is a time-slice present?
+     BEQ     __tx_thread_dont_save_ts    ; No, don't save the time-slice
+;
+;   /* Save time-slice for the thread and clear the current time-slice.  */
+    ;   _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+     MOV.L   R5,24[R3]
+;   _tx_timer_time_slice =  0;
+;
+     MOV.L   R1, [R4] ; Disable the time-slice
+;
+;    }
+__tx_thread_dont_save_ts:
+;
+;    /* Clear the current thread pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    MOV.L   R1, [R2]
+    BRA  __tx_thread_schedule
+;}
+    .end
+
diff --git a/ports/rxv2/gnu/src/tx_timer_interrupt.S b/ports/rxv2/gnu/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..3511e2c8
--- /dev/null
+++ b/ports/rxv2/gnu/src/tx_timer_interrupt.S
@@ -0,0 +1,251 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    .global     __tx_timer_time_slice
+    .global     __tx_timer_system_clock
+    .global     __tx_timer_current_ptr
+    .global     __tx_timer_list_start
+    .global     __tx_timer_list_end
+    .global     __tx_timer_expired_time_slice
+    .global     __tx_timer_expired
+    .global     __tx_timer_expiration_process
+    .global     __tx_thread_context_save
+    .global     __tx_thread_time_slice
+    .global     __tx_thread_context_restore
+;
+    .SECTION    P,CODE
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_timer_interrupt                                  RX/GNURX       */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function processes the hardware timer interrupt.  This         */
+;/*    processing includes incrementing the system clock and checking for  */
+;/*    time slice and/or timer expiration.  If either is found, the        */
+;/*    interrupt context save/restore functions are called along with the  */
+;/*    expiration functions.                                               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_context_save               Save interrupted context      */
+;/*    _tx_timer_expiration_process          Timer expiration processing   */
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */
+;/*    _tx_thread_context_restore            Restore interrupted context   */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    interrupt vector                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    .global __tx_timer_interrupt
+__tx_timer_interrupt:
+;
+;    /* Upon entry to this routine, it is assumed that all interrupts are locked
+;       out and the stack looks like the following:
+;                            SP+4 ->    Interrupted PC
+;                            SP+8->    Interrupted SR
+;   */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    PUSHM    R14-R15
+    PUSHM    R1-R5
+
+    MOV.L    #__tx_timer_system_clock, R1    ; Pickup address of system clock
+    MOV.L    [R1], R2                        ; Pickup system clock
+    ADD      #1, R2                          ; Increment system clock
+    MOV.L    R2,[R1]                         ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV.L   #__tx_timer_time_slice, R1       ; Pickup address of time slice
+    MOV.L   [R1], R2                         ; Pickup the current time slice
+    CMP     #0, R2                           ; Is a time slice active?
+    BEQ     __tx_timer_no_time_slice         ; No, skip timer slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     #1, R2                           ; Decrement the time-slice
+    MOV.L   R2, [R1]                         ; Store time-slice
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CMP     #0, R2                           ; Has it expired?
+    BNE     __tx_timer_no_time_slice         ; No, time-slice has not expired
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV.L   #__tx_timer_expired_time_slice, R1  ; Pickup address of expired time-slice
+    MOV.L   #1, R2                           ; Build expired value
+    MOV.L   R2, [R1]                         ; Set expired time slice variable
+;    }
+;
+__tx_timer_no_time_slice:
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV.L   #__tx_timer_current_ptr, R1     ; Pickup address of current timer ptr
+    MOV.L   [R1], R2                        ; Pickup current pointer
+    MOV.L   [R2+], R1                       ; pickup timer list entry, _tx_timer_current_ptr++
+    CMP     #0, R1                          ; Is timer pointer NULL?
+    BEQ     __tx_timer_no_timer            ; Yes, no timer has expired
+
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV.L   #__tx_timer_expired,R2          ; Build address of expired flag
+    MOV.L   #1, R1                          ; Build expired value
+    MOV.L   R1, [R2]
+    BRA     __tx_timer_done                 ; Finished with timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer:
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+;       /* R2 already contains __tx_timer_current_ptr++ */
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV.L   #__tx_timer_list_end, R1          ; Pickup the timer list end ptr
+    MOV.L   [R1], R1                          ; Pickup actual timer list end
+    CMP     R1, R2                            ; Are we at list end?
+    BNE     __tx_timer_skip_wrap              ; No, don't move pointer to the
+                                              ;   top of the list
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV.L   #__tx_timer_list_start, R2        ; Pickup the timer list start ptr
+    MOV.L   [R2], R2                          ; Pickup the start of the list
+;    }
+;
+__tx_timer_skip_wrap:
+    MOV.L   #__tx_timer_current_ptr,R1
+    MOV.L   R2, [R1]                          ; store in updated pointer in  _tx_timer_current_ptr
+
+__tx_timer_done:
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV.L  #__tx_timer_expired_time_slice, R1    ; Pickup expired time slice addr
+    MOV.L  [R1], R1                           ; Pickup expired time slice
+    MOV.L   #__tx_timer_expired, R2           ; Pickup expired timer flag address
+    MOV.L   [R2], R2                          ; Pickup actual flag
+    OR      R1, R2                            ; Or flags together
+    BEQ     __tx_timer_nothing_expired        ; If Z set, nothing has expired
+
+__tx_something_expired:
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+    MOV.L   #__tx_timer_expired,R1            ; Pickup expired flag address
+    MOV.L   [R1], R1                          ; Pickup expired flag
+    CMP     #0,R1                             ; Is the expired timer flag set?
+    BEQ     __tx_timer_dont_activate          ; No, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BSR    __tx_timer_expiration_process      ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate:
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    MOV.L   #__tx_timer_expired_time_slice, R1   ; Pickup time-slice expired flag addr
+    MOV.L   [R1], R1                           ; Pickup actual flag
+    CMP     #0,R1                              ; Has time-slice expired?
+    BEQ      __tx_timer_not_ts_expiration      ; No, skip time-slice expiration
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice();
+
+    BSR     __tx_thread_time_slice             ; Call time-slice processing
+;    }
+;
+__tx_timer_not_ts_expiration:
+
+__tx_timer_nothing_expired:
+
+    POPM R1-R5
+    POPM R14-R15
+;
+    RTS                                       ; return to point of interrupt
+;
+;}
+
+    .end
+
diff --git a/ports/rxv2/iar/inc/tx_port.h b/ports/rxv2/iar/inc/tx_port.h
new file mode 100644
index 00000000..14b9728f
--- /dev/null
+++ b/ports/rxv2/iar/inc/tx_port.h
@@ -0,0 +1,273 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                            RX/IAR         */
+/*                                                           6.1.3        */
+/*                                                                        */
+/*  AUTHOR                                                                */ 
+/*                                                                        */ 
+/*    William E. Lamie, Express Logic, Inc.                               */ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+#include <string.h>
+#include <intrinsics.h>
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        256         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          0
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2          
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  __istate_t interrupt_save;
+#define TX_DISABLE                              {interrupt_save = __get_interrupt_state();__disable_interrupt();};
+#define TX_RESTORE                              {__set_interrupt_state(interrupt_save);};
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+static void _tx_thread_system_return_inline(void)
+{
+    TX_INTERRUPT_SAVE_AREA
+
+    TX_DISABLE
+
+    *((volatile UCHAR *)(0x872E0u)) = 1u;
+
+    TX_RESTORE
+}
+
+#endif
+
+
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+
+extern volatile ULONG  _tx_thread_system_state;
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | ((~__get_PSW_register()) & (1u << 17u)))
+#endif
+
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RX/IAR Version 6.1.3 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
+
diff --git a/ports/rxv2/iar/readme_threadx.txt b/ports/rxv2/iar/readme_threadx.txt
new file mode 100644
index 00000000..0c0afd29
--- /dev/null
+++ b/ports/rxv2/iar/readme_threadx.txt
@@ -0,0 +1,163 @@
+                    Microsoft's Azure RTOS ThreadX for Renesas RXv2
+
+                                Using the IAR Tools
+
+
+1.  Building the ThreadX run-time Library
+
+Please see the Samples repository on GitHub for the Azure RTOS demonstrations
+for the RXv2.
+
+
+2.  Demonstration System
+
+Please see the Samples repository on GitHub for the Azure RTOS demonstrations
+for the RXv2.
+
+
+3.  System Initialization
+
+The system entry point using the IAR tools is at the label __iar_program_start. 
+
+The vector area is setup in the file tx_initialize_low_level.s. This file is also 
+responsible for setting up various system data structures, interrupt vectors, and 
+the periodic timer interrupt. This file is also an ideal place add hardware 
+initialization code.
+
+The ThreadX demonstration for the RXv2 utilizes CMT0 as a periodic timer interrupt 
+source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the 
+interrupt priority level is set to level 7. You may change any of the timer 
+parameters as needed.
+
+In addition, _tx_initialize_low_level determines the first available address for use 
+by the application, which is supplied as the sole input parameter to your application 
+definition function, tx_application_define. The first available memory is determined 
+by the location of the FREEMEM section so it should be placed AFTER all other RAM 
+sections in your linker control file.
+
+
+4.  Context Switch, Register Usage and Stack Frames
+
+The RXv2 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #17,
+to perform context switch. This ISR is thus reserved when using ThreadX and the SWINT
+should not be manipulated in any way by the application. The port will setup the 
+interrupt within _tx_initialize_low_level and the compiler will automatically install
+the necessary interrupt vector. As such no additional initialization is necessary by the
+application.
+
+The following defines the saved context stack frame used by the ThreadX port. The
+state of the CPU registers at the time of a context switch is saved on the running 
+thread's stack The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+    Offset        Interrupted Stack Frame
+
+     0x00                   1
+     0x04                   ACC0
+     0x08                   ACC1
+     0x0C                   R6
+     0x10                   R7
+     0x14                   R8
+     0x18                   R9
+     0x1C                   R10
+     0x20                   R11
+     0x24                   R12
+     0x28                   R13
+     0x2C                   FPSW
+     0x30                   R14
+     0x34                   R15
+     0x38                   R3
+     0x3C                   R4
+     0x40                   R5
+     0x44                   R1
+     0x48                   R2
+     0x4C                   PC - return address
+     0x50                   PSW
+     
+Note: By default IAR does not save the state of the accumulator registers ACC0 and ACC1
+when entering an ISR. This means that if the ISR uses any of the DSP instructions the
+content of those registers could be corrupted. Saving and restoring of the acummulators
+can be enabled by adding the --save_acc command line option.
+     
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler optimizations.  This 
+makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself.  
+Of course, this costs some performance. To make ThreadX run faster, you can change the 
+ThreadX Library project to disable debug information and enable the desired optimizations.  
+
+In addition, you can eliminate the ThreadX basic API error checking by compiling your 
+application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h 
+is included. 
+
+
+6. Timer Processing
+
+Timer processign is performed by calling __tx_timer_interrupt(). This should usually be done
+from within the callback of a periodic timer with a period of 100Hz. In the sample projects
+a Renesas Fit CMT periodic timer module (rx_cmt) is used as the timer source.
+
+
+7.  Interrupt Handling
+
+Interrupt handling is unaffected by the ThreadX port as such user interrupts can be 
+written according to the toolchain's documentation. It is recommended not to use interrupt
+priority 15 as this is the priority of the context switch interrupt. However using interrupt
+priority 15 won't cause any negative side effectd but doing so may may slightly reduce 
+performance. Please refer to the toolchain documentation for additional details on how to
+define interupt service routines.
+
+
+8. Execution Profiling
+
+The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists 
+of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation 
+of the EPK for generic usage details.
+
+To add the EPK to your RXv2 release make the following modifications:
+
+* Enable the following define for both the Threadx library and the application
+TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+* in tx_port.h, change around line 183
+change #define TX_THREAD_EXTENSION_3     
+into #include "tx_execution_profile.h"   
+
+* Setup CMT1 as a free running 16 bit timer.
+
+* In tx_execution_profile.h, change following around line 74:
+
+#ifdef TX_EXECUTION_64BIT_TIME
+typedef unsigned long long              EXECUTION_TIME;
+#define TX_THREAD_EXTENSION_3           unsigned long long  tx_thread_execution_time_total; \
+                                        unsigned long long  tx_thread_execution_time_last_start; 
+#define TX_EXECUTION_MAX_TIME_SOURCE    0xFFFFFFFFFFFFFFFF
+#else
+typedef unsigned long                   EXECUTION_TIME;
+#define TX_THREAD_EXTENSION_3           unsigned long   tx_thread_execution_time_total; \
+                                        unsigned long   tx_thread_execution_time_last_start; 
+#define TX_EXECUTION_MAX_TIME_SOURCE    0xFFFF
+#endif
+                                        
+/* Define basic constants for the execution profile kit.  */
+
+#define TX_EXECUTION_TIME_SOURCE         (EXECUTION_TIME)  *((USHORT *) 0x8800A)
+
+Rebuild the Threadx library and the application.
+Refer to the EPK documentation how to interpret the results.
+
+
+9.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+12-31-2020  Initial ThreadX release for the RXv2using IAR tools, version 6.1.3
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
\ No newline at end of file
diff --git a/ports/rxv2/iar/src/tx_initialize_low_level.s b/ports/rxv2/iar/src/tx_initialize_low_level.s
new file mode 100644
index 00000000..49336a57
--- /dev/null
+++ b/ports/rxv2/iar/src/tx_initialize_low_level.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+
+    extern __tx_initialize_unused_memory
+
+    section .text:CODE:ROOT
+
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_low_level                             RX/IAR         */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function is responsible for any low-level processor            */ 
+;/*    initialization, including setting up interrupt vectors, setting     */ 
+;/*    up a periodic timer interrupt source, saving the system stack       */ 
+;/*    pointer for use in ISR processing later, and finding the first      */ 
+;/*    available RAM memory address for tx_application_define.             */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+    public __tx_initialize_low_level
+
+__tx_initialize_low_level:
+
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) &free_mem_start;
+;
+    MOV.L    #__tx_free_memory_start, R1        ; Pickup unused memory address
+    MOV.L    #__tx_initialize_unused_memory,R2                
+    MOV.L    R1,[R2]                            ; Save first free memory address
+
+;   /* Set priority of SWINT to 1. */
+    MOV.L    #0x87303, r1
+    MOV.L    #1, r2
+    MOV.B    r2, [r1]
+
+;   /* Enable SWINT. */
+    MOV.L    #0x87203, r1
+    MOV.B    [r1], r2
+    OR       #(1 << 3), r2
+    MOV.B    r2, [r1]
+
+    RTS
+
+    section FREEMEM:DATA
+    public __tx_free_memory_start
+__tx_free_memory_start
+    DS32    4
+
+    END
diff --git a/ports/rxv2/iar/src/tx_thread_context_restore.s b/ports/rxv2/iar/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..491dae82
--- /dev/null
+++ b/ports/rxv2/iar/src/tx_thread_context_restore.s
@@ -0,0 +1,205 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    extern __tx_thread_system_state
+    extern __tx_thread_current_ptr
+    extern __tx_thread_preempt_disable
+    extern __tx_thread_execute_ptr
+    extern __tx_timer_time_slice
+    extern __tx_thread_schedule
+
+    section .text:CODE:ROOT
+
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_restore                           RX/IAR         */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function restores the interrupt context if it is processing a  */ 
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+;/*    if no thread was running, the function returns to the scheduler.    */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                  Interrupt Service Routines    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+    public __tx_thread_context_restore
+
+__tx_thread_context_restore:
+;
+;    /* Lockout interrupts.  */
+
+     CLRPSW I                                 ; disable interrupts
+
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+
+     MOV.L    #__tx_thread_system_state, R1
+     MOV.L    [R1], R2
+     SUB      #1, R2
+     MOV.L    R2,[R1]
+     BEQ      __tx_thread_not_nested_restore 
+
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Recover the saved registers from the interrupt stack
+;       and return to the point of interrupt.  */
+;
+__tx_thread_nested_restore:
+     POPC    FPSW                                ; restore FPU status   
+     POPM    R14-R15             ; restore R14-R15
+     POPM    R3-R5               ; restore R3-R5
+     POPM    R1-R2               ; restore R1-R2
+     RTE                         ; return to point of interrupt, restore PSW including IPL
+;    }
+
+__tx_thread_not_nested_restore:
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+;               || (_tx_thread_preempt_disable))
+;    {
+    
+     MOV.L    #__tx_thread_current_ptr, R1       ; Pickup current thread ptr address
+     MOV.L    [R1], R2
+     CMP      #0, R2
+     BEQ      __tx_thread_idle_system_restore 
+     
+     MOV.L    #__tx_thread_preempt_disable, R3   ; pick up preempt disable flag
+     MOV.L    [R3], R3
+     CMP      #0, R3
+     BNE      __tx_thread_no_preempt_restore     ; if pre-empt disable flag set, we simply return to the original point of interrupt regardless
+     
+     MOV.L    #__tx_thread_execute_ptr, R3       ; (_tx_thread_current_ptr != _tx_thread_execute_ptr)
+     CMP      [R3], R2
+     BNE      __tx_thread_preempt_restore        ; jump to pre-empt restoring
+;
+__tx_thread_no_preempt_restore:
+     SETPSW  U                   ; user stack
+	 POPC    FPSW                ; restore FPU status
+     POPM    R14-R15             ; restore R14-R15
+     POPM    R3-R5               ; restore R3-R5
+     POPM    R1-R2               ; restore R1-R2
+     RTE                         ; return to point of interrupt, restore PSW including IPL
+
+;    }
+;    else
+;    {
+
+__tx_thread_preempt_restore:
+
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+
+     MOV.L    #__tx_timer_time_slice, R3        ; Pickup time-slice address
+     MOV.L    [R3],R4                           ; Pickup actual time-slice
+     CMP      #0, R4
+     BEQ      __tx_thread_dont_save_ts          ; no time slice to save
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0;
+;
+     MOV.L    R4,24[R2]                         ; Save thread's time slice
+     MOV.L    #0,R4                             ; Clear value
+     MOV.L    R4,[R3]                           ; Disable global time slice flag
+;    }
+__tx_thread_dont_save_ts:
+;
+;   /* Now store the remaining registers!   */
+
+     SETPSW   U                                 ; user stack
+     PUSHM    R6-R13
+     
+     MVFACGU   #0, A1, R4                       ; Save accumulators.
+     MVFACHI   #0, A1, R5
+     MVFACLO   #0, A1, R6
+     PUSHM     R4-R6
+     MVFACGU   #0, A0, R4
+     MVFACHI   #0, A0, R5
+     MVFACLO   #0, A0, R6
+     PUSHM     R4-R6
+     
+     MOV.L    #1, R3                            ; indicate interrupt stack frame
+     PUSH.L   R3
+
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;    R1 ->  _tx_thread_current_ptr
+;    R2 -> *_tx_thread_current_ptr
+
+     MOV.L   R0,8[R2]                        ; Save thread's stack pointer in thread control block
+     MOV.L   #0,R2                           ; Build NULL value
+     MOV.L   R2,[R1]                         ; Set current thread to NULL
+
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+
+__tx_thread_idle_system_restore:
+     MVTC    #0, PSW                          ; reset interrupt priority level to 0
+     BRA     __tx_thread_schedule             ; jump to scheduler
+;    }
+;
+;}
+;
+    END
diff --git a/ports/rxv2/iar/src/tx_thread_context_save.s b/ports/rxv2/iar/src/tx_thread_context_save.s
new file mode 100644
index 00000000..218f65cd
--- /dev/null
+++ b/ports/rxv2/iar/src/tx_thread_context_save.s
@@ -0,0 +1,170 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+    extern __tx_thread_system_state
+    extern __tx_thread_current_ptr
+
+    section .text:CODE:ROOT
+    ;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_save                              RX/IAR         */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;VOID   _tx_thread_context_save(VOID)
+;{
+    public __tx_thread_context_save
+
+__tx_thread_context_save:
+;
+;    /* Upon entry to this routine, it is assumed that interrupts are locked
+;       out and the (interrupt) stack frame looks like the following:
+;
+;           (lower address) SP   ->     [return address of this call]
+;                           SP+4 ->     Saved R1
+;                           SP+8 ->     Saved R2
+;                           SP+12->     Interrupted PC
+;                           SP+16->     Interrupted PSW
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+
+    MOV.L   #__tx_thread_system_state, R1     ; pick up address of system state
+    MOV.L   [R1], R2                           ; pick up system state
+    CMP     #0, R2                             ; 0 -> no nesting
+    BEQ     __tx_thread_not_nested_save
+;
+;    /* Nested interrupt condition.  */
+;   
+    ADD   #1, r2                             ; _tx_thread_system_state++
+    MOV.L   r2, [r1]
+
+;
+;   /* Save the rest of the scratch registers on the interrupt stack and return to the
+;       calling ISR.  */
+    POP R1                                      ; recuperate return address from stack
+    PUSHM   R3-R5
+    PUSHM   R14-R15
+    PUSHC   FPSW                                ; (top) FPSW, R14, R15, R3, R4, R5, R1, R2, PC, PSW (bottom)
+    JMP     R1                                  ; return address was preserved in R1
+
+;
+__tx_thread_not_nested_save:
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     #1, R2                                ; _tx_thread_system_state++
+    MOV.L   R2, [R1]
+
+    MOV.L   #__tx_thread_current_ptr, R2         ; Pickup current thread pointer
+    MOV.L   [R2], R2
+    CMP     #0,R2                                ; Is it NULL?  
+    BEQ      __tx_thread_idle_system_save        ; Yes, idle system is running - idle restore
+;
+;    /* Move stack frame over to the current threads stack.  */
+;    /* complete stack frame with registers not saved yet (R3-R5, R14-R15, FPSW)   */
+;
+    MVFC    USP, R1                               ; pick up user stack pointer
+    MOV.L   16[R0], R2
+    MOV.L   R2, [-R1]                             ; save PSW on thread stack
+    MOV.L   12[R0], R2
+    MOV.L   R2, [-R1]                             ; save PC on thread stack
+    MOV.L   8[R0], R2
+    MOV.L   R2, [-R1]                             ; save R2 on thread stack 
+    MOV.L   4[R0], R2
+    MOV.L   R2, [-R1]                             ; save R1 on thread stack 
+    MOV.L   R5, [-R1]                             ; save R5 on thread stack
+    MOV.L   R4, [-R1]                             ; save R4 on thread stack
+    MOV.L   R3, [-R1]                             ; save R3 on thread stack
+    MOV.L   R15, [-R1]                            ; save R15 on thread stack
+    MOV.L   R14, [-R1]                            ; save R14 on thread stack
+    MVFC    FPSW, R3
+    MOV.L   R3, [-R1]                             ; save FPSW on thread stack
+	
+    POP     R2                                    ; pick up return address from interrupt stack
+    ADD     #16, R0, R0                           ; correct interrupt stack pointer back to the bottom   
+    MVTC    R1, USP                               ; set user/thread stack pointer
+    JMP     R2                                    ; return to ISR
+
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save:
+;
+;        /* Interrupt occurred in the scheduling loop.  */
+;
+    POP     R1                                   ; pick up return address
+    ADD     #16, R0, R0                          ; correct interrupt stack pointer back to the bottom (PC), don't care about saved registers
+    JMP     R1                                   ; return to caller
+;
+;    }
+;}    
+    END
diff --git a/ports/rxv2/iar/src/tx_thread_interrupt_control.s b/ports/rxv2/iar/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..bd8474df
--- /dev/null
+++ b/ports/rxv2/iar/src/tx_thread_interrupt_control.s
@@ -0,0 +1,93 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+    section .text:CODE:ROOT
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_control                         RX/IAR         */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function is responsible for changing the interrupt lockout     */ 
+;/*    posture of the system.                                              */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    new_posture                           New interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    public __tx_thread_interrupt_control
+__tx_thread_interrupt_control:
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    
+    MVFC      PSW, R2           ; Save PSW to R2
+    MOV.L     R2, R3            ; Make a copy of PSW in r3
+    
+;
+;    /* Apply the new interrupt posture.  */
+;
+    
+    BTST    #16, R1             ; test I bit of PSW of "new posture"
+    BMNE    #16, R2             ; conditionally set I bit of intermediate posture 
+    
+    MVTC    R2, PSW             ; save intermediate posture to PSW
+    
+    MOV.L   R3,R1               ; Get original SR 
+    RTS                         ; Return to caller
+;}
+    END
diff --git a/ports/rxv2/iar/src/tx_thread_schedule.s b/ports/rxv2/iar/src/tx_thread_schedule.s
new file mode 100644
index 00000000..9de14be1
--- /dev/null
+++ b/ports/rxv2/iar/src/tx_thread_schedule.s
@@ -0,0 +1,179 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    extern __tx_thread_execute_ptr
+    extern __tx_thread_current_ptr
+    extern __tx_timer_time_slice
+
+    section .text:CODE:ROOT
+
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                                  RX/IAR         */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */ 
+;/*                                                                        */ 
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */ 
+;/*  DESCRIPTION                                                           */ 
+;/*                                                                        */ 
+;/*    This function waits for a thread control block pointer to appear in */ 
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+;/*    in the variable, the corresponding thread is resumed.               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+;/*    _tx_thread_system_return             Return to system from thread   */ 
+;/*    _tx_thread_context_restore           Restore thread's context       */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */ 
+;/*                                                                        */ 
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */ 
+;/**************************************************************************/ 
+;VOID   _tx_thread_schedule(VOID)
+;{
+    public __tx_thread_schedule
+
+__tx_thread_schedule:
+;
+;    /* Enable interrupts.  */
+;
+    SETPSW I
+;
+;    /* Wait for a thread to execute.  */
+;    do
+;    {
+    MOV.L    #__tx_thread_execute_ptr, R1     ; Address of thread to executer ptr
+__tx_thread_schedule_loop:
+    MOV.L    [R1],R2                          ; Pickup next thread to execute
+    CMP      #0,R2                            ; Is it NULL?
+    BEQ      __tx_thread_schedule_loop        ; Yes, idle system, keep checking
+;
+;    }
+;    while(_tx_thread_execute_ptr == TX_NULL);
+;    
+;    /* Yes! We have a thread to execute.  Lockout interrupts and
+;       transfer control to it.  */
+;
+    CLRPSW I                                  ; disable interrupts
+;
+;    /* Setup the current thread pointer.  */
+;    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+;
+    MOV.L    #__tx_thread_current_ptr, R3
+    MOV.L    R2,[R3]                          ; Setup current thread pointer
+;
+;    /* Increment the run count for this thread.  */
+;    _tx_thread_current_ptr -> tx_thread_run_count++;
+;
+    MOV.L    4[R2],R3                      ; Pickup run count  
+    ADD      #1,R3                         ; Increment run counter
+    MOV.L    R3,4[R2]                      ; Store it back in control block
+;
+;    /* Setup time-slice, if present.  */
+;    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+;
+    MOV.L    24[R2],R3                     ; Pickup thread time-slice
+    MOV.L    #__tx_timer_time_slice,R4     ; Pickup pointer to time-slice
+    MOV.L    R3, [R4]                      ; Setup time-slice                        
+;
+;    /* Switch to the thread's stack.  */
+;    SP =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+    SETPSW U                               ; user stack mode
+    MOV.L   8[R2],R0                       ; Pickup stack pointer
+;
+;    /* Determine if an interrupt frame or a synchronous task suspension frame
+;   is present.  */
+;
+    POP    R1                               ; Pickup stack type
+    CMP    #1, R1                           ; Is it an interrupt stack?
+    BNE    __tx_thread_synch_return         ; No, a synchronous return frame is present.
+
+    POPM    R1-R3                           ; Restore accumulators.
+    MVTACLO R3, A0
+    MVTACHI R2, A0
+    MVTACGU R1, A0
+    POPM    R1-R3
+    MVTACLO R3, A1
+    MVTACHI R2, A1
+    MVTACGU R1, A1
+    
+    POPM   R6-R13                           ; Recover interrupt stack frame
+    POPC   FPSW 
+    POPM   R14-R15
+    POPM   R3-R5
+    POPM   R1-R2    
+    RTE                                         ; return to point of interrupt, this restores PC and PSW
+  
+__tx_thread_synch_return:
+   POPC    PSW
+   POPM    R6-R13                           ; Recover solicited stack frame
+   RTS
+;
+;}
+
+    extern __tx_thread_context_save
+    extern __tx_thread_context_restore
+
+; Software triggered interrupt used to perform context switches.
+; The priority of this interrupt is set to the lowest priority within
+; tx_initialize_low_level() and triggered by ThreadX when calling
+; _tx_thread_system_return().
+    public ___interrupt_27
+___interrupt_27:
+
+    PUSHM R1-R2
+
+    BSR __tx_thread_context_save
+
+    BRA __tx_thread_context_restore
+
+    END
diff --git a/ports/rxv2/iar/src/tx_thread_stack_build.s b/ports/rxv2/iar/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..688f0bc8
--- /dev/null
+++ b/ports/rxv2/iar/src/tx_thread_stack_build.s
@@ -0,0 +1,147 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+
+    section .text:CODE:ROOT
+
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_stack_build                               RX/IAR         */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+
+    public __tx_thread_stack_build
+
+__tx_thread_stack_build:
+;
+;       
+;    /* Build an interrupt frame.  The form of the fake interrupt stack
+;       on the Renesas RX should look like the following after it is built:
+;       
+;  Stack Top:           1       Interrupt stack frame type
+;                       ACC0
+;                       ACC1
+;                       R6
+;                       R7
+;                       R8
+;                       R9
+;                       R10
+;                       R11
+;                       R12
+;                       R13
+;                       FPSW
+;                       R14
+;                       R15
+;                       R3
+;                       R4
+;                       R5
+;                       R1
+;                       R2
+;                       PC
+;                       PSW
+
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    MOV.L   16[R1],R3               ; Pickup end of stack area
+    BCLR    #0, R3                  ; mask for 4-byte alignment
+    BCLR    #1, R3
+;
+;    /* Build the stack frame.  */
+;
+    MOV.L #30000h, R4
+    MOV.L R4, [-R3]                         ; initial PSW (SVC mode, U flag set)
+    MOV.L R2, [-R3]                         ; initial PC
+    MOV.L #0, R4
+    MOV.L R4,[-R3]                          ; initial R2 ...
+    MOV.L R4,[-R3]                          ; initial R1 ...    
+    MOV.L R4,[-R3]                          ; initial R5 ...
+    MOV.L R4,[-R3]                          ; initial R4 ...
+    MOV.L R4,[-R3]                          ; initial R3 ...    
+    MOV.L R4,[-R3]                          ; initial R15 ...
+    MOV.L R4,[-R3]                          ; initial R14 ...
+    MVFC  FPSW, r4
+    MOV.L R4, [-R3]                         ; initial FPSW
+    MOV.L #0, R4
+    MOV.L R4,[-R3]                          ; initial R13 ...   
+    MOV.L R4,[-R3]                          ; initial R12 ...
+    MOV.L R4,[-R3]                          ; initial R11 ...
+    MOV.L R4,[-R3]                          ; initial R10 ...   
+    MOV.L R4,[-R3]                          ; initial R9 ...
+    MOV.L R4,[-R3]                          ; initial R8 ...
+    MOV.L R4,[-R3]                          ; initial R7 ...    
+    MOV.L R4,[-R3]                          ; initial R6 ...
+
+    MOV.L R4,[-R3]                          ; Accumulator 1
+    MOV.L R4,[-R3]
+    MOV.L R4,[-R3]
+
+    MOV.L R4,[-R3]                          ; Accumulator 0
+    MOV.L R4,[-R3]
+    MOV.L R4,[-R3]
+
+    MOV.L #1, R4
+    MOV.L R4,[-R3]                           ; indicate interrupt stack frame
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  R1;   
+    MOV.L R3, 8[R1]
+                                            ; store initial SP in thread control block
+    RTS
+                                 
+;}
+
+    END
diff --git a/ports/rxv2/iar/src/tx_thread_system_return.s b/ports/rxv2/iar/src/tx_thread_system_return.s
new file mode 100644
index 00000000..808e345e
--- /dev/null
+++ b/ports/rxv2/iar/src/tx_thread_system_return.s
@@ -0,0 +1,74 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+
+    section .text:CODE:ROOT
+    
+    ;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_system_return                             RX/IAR         */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is target processor specific.  It is used to transfer */
+;/*    control from a thread back to the system.  Only a minimal context   */
+;/*    is saved since the compiler assumes temp registers are going to get */
+;/*    slicked by a function call anyway.                                  */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling loop        */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ThreadX components                                                  */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+
+    public __tx_thread_system_return
+
+__tx_thread_system_return:
+
+    BRA __tx_thread_system_return
+
+    RTS
+
+    END
diff --git a/ports/rxv2/iar/src/tx_timer_interrupt.s b/ports/rxv2/iar/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..645f73b4
--- /dev/null
+++ b/ports/rxv2/iar/src/tx_timer_interrupt.s
@@ -0,0 +1,235 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+
+    extern __tx_timer_expiration_process
+    extern __tx_timer_system_clock
+    extern __tx_timer_expired_time_slice
+    extern __tx_timer_current_ptr
+    extern __tx_timer_expired
+    extern __tx_timer_list_start
+    extern __tx_timer_time_slice
+    extern __tx_timer_list_end
+    extern __tx_thread_time_slice
+
+    section .text:CODE:ROOT
+
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_timer_interrupt                                  RX/IAR         */
+;/*                                                           6.1.3        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function processes the hardware timer interrupt.  This         */
+;/*    processing includes incrementing the system clock and checking for  */
+;/*    time slice and/or timer expiration.  If either is found, the        */
+;/*    interrupt context save/restore functions are called along with the  */
+;/*    expiration functions.                                               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_context_save               Save interrupted context      */
+;/*    _tx_timer_expiration_process          Timer expiration processing   */
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */
+;/*    _tx_thread_context_restore            Restore interrupted context   */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    interrupt vector                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+;/*                                                                        */
+;/**************************************************************************/
+
+    public __tx_timer_interrupt
+__tx_timer_interrupt:
+;
+;    /* Upon entry to this routine, it is assumed that all interrupts are locked
+;       out and the stack looks like the following:
+;                            SP+4 ->    Interrupted PC
+;                            SP+8->    Interrupted SR
+;   */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    PUSHM    R14-R15
+    PUSHM    R1-R5
+
+    MOV.L    #__tx_timer_system_clock, R1    ; Pickup address of system clock
+    MOV.L    [R1], R2                        ; Pickup system clock
+    ADD      #1, R2                          ; Increment system clock
+    MOV.L    R2,[R1]                         ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV.L   #__tx_timer_time_slice, R1       ; Pickup address of time slice
+    MOV.L   [R1], R2                         ; Pickup the current time slice
+    CMP     #0, R2                           ; Is a time slice active?
+    BEQ     __tx_timer_no_time_slice         ; No, skip timer slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     #1, R2                           ; Decrement the time-slice
+    MOV.L   R2, [R1]                         ; Store time-slice
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CMP     #0, R2                           ; Has it expired?
+    BNE     __tx_timer_no_time_slice         ; No, time-slice has not expired
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV.L   #__tx_timer_expired_time_slice, R1  ; Pickup address of expired time-slice
+    MOV.L   #1, R2                           ; Build expired value
+    MOV.L   R2, [R1]                         ; Set expired time slice variable
+;    }
+;
+__tx_timer_no_time_slice:
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV.L   #__tx_timer_current_ptr, R1     ; Pickup address of current timer ptr
+    MOV.L   [R1], R2                        ; Pickup current pointer
+    MOV.L   [R2+], R1                       ; pickup timer list entry, _tx_timer_current_ptr++
+    CMP     #0, R1                          ; Is timer pointer NULL?
+    BEQ     __tx_timer_no_timer            ; Yes, no timer has expired
+        
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV.L   #__tx_timer_expired,R2          ; Build address of expired flag
+    MOV.L   #1, R1                          ; Build expired value
+    MOV.L   R1, [R2]    
+    BRA     __tx_timer_done                 ; Finished with timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer:
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+;       /* R2 already contains __tx_timer_current_ptr++ */                         
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV.L   #__tx_timer_list_end, R1          ; Pickup the timer list end ptr
+    MOV.L   [R1], R1                          ; Pickup actual timer list end
+    CMP     R1, R2                            ; Are we at list end?
+    BNE     __tx_timer_skip_wrap              ; No, don't move pointer to the
+                                              ;   top of the list
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV.L   #__tx_timer_list_start, R2        ; Pickup the timer list start ptr
+    MOV.L   [R2], R2                          ; Pickup the start of the list
+;    }
+;
+__tx_timer_skip_wrap:
+    MOV.L   #__tx_timer_current_ptr,R1     
+    MOV.L   R2, [R1]                          ; store in updated pointer in  _tx_timer_current_ptr  
+    
+__tx_timer_done:
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV.L  #__tx_timer_expired_time_slice, R1    ; Pickup expired time slice addr
+    MOV.L  [R1], R1                           ; Pickup expired time slice
+    MOV.L   #__tx_timer_expired, R2           ; Pickup expired timer flag address
+    MOV.L   [R2], R2                          ; Pickup actual flag
+    OR      R1, R2                            ; Or flags together
+    BEQ     __tx_timer_nothing_expired        ; If Z set, nothing has expired
+
+__tx_something_expired:
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+    MOV.L   #__tx_timer_expired,R1            ; Pickup expired flag address
+    MOV.L   [R1], R1                          ; Pickup expired flag
+    CMP     #0,R1                             ; Is the expired timer flag set?
+    BEQ     __tx_timer_dont_activate          ; No, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BSR    __tx_timer_expiration_process      ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate:
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+; 
+    MOV.L   #__tx_timer_expired_time_slice, R1   ; Pickup time-slice expired flag addr
+    MOV.L   [R1], R1                           ; Pickup actual flag
+    CMP     #0,R1                              ; Has time-slice expired?
+    BEQ      __tx_timer_not_ts_expiration      ; No, skip time-slice expiration
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BSR     __tx_thread_time_slice             ; Call time-slice processing
+;    }
+;
+__tx_timer_not_ts_expiration:
+
+__tx_timer_nothing_expired:
+
+    POPM R1-R5
+    POPM R14-R15
+;
+    RTS                                       ; return to point of interrupt
+;
+;}
+    END
\ No newline at end of file
diff --git a/ports/xtensa/xcc/CMakeLists.txt b/ports/xtensa/xcc/CMakeLists.txt
new file mode 100644
index 00000000..31768e58
--- /dev/null
+++ b/ports/xtensa/xcc/CMakeLists.txt
@@ -0,0 +1,36 @@
+
+target_sources(${PROJECT_NAME}
+    PRIVATE
+    # {{BEGIN_TARGET_SOURCES}}
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_clib_lock.c
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.c
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.c
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_xtensa_stack_error_handler.c
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_context.S
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_coproc_handler.S
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_init.c
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_intr_asm.S
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_intr.c
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_intr_wrapper.c
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_overlay_os_hook.c
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_vectors.S
+	${CMAKE_CURRENT_LIST_DIR}/src/xtensa_vectors_xea3.S
+
+    # {{END_TARGET_SOURCES}}
+)
+
+target_include_directories(${PROJECT_NAME}
+    PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}/inc
+)
+
+set_source_files_properties(${CMAKE_CURRENT_LIST_DIR}/src/xtensa_vectors_xea3.S
+                            TARGET_DIRECTORY ${PROJECT_NAME}
+                            PROPERTIES COMPILE_OPTIONS "-mtext-section-literals")
+
diff --git a/ports/xtensa/xcc/example_build/demo_threadx.c b/ports/xtensa/xcc/example_build/demo_threadx.c
new file mode 100644
index 00000000..5bec9cc8
--- /dev/null
+++ b/ports/xtensa/xcc/example_build/demo_threadx.c
@@ -0,0 +1,377 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include <stdio.h>
+#include <xtensa/xtutil.h>
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+UCHAR                   memory_area[DEMO_BYTE_POOL_SIZE];
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Print something to show we are making progress. This should use the print
+           function from libxtutil which is thread-safe.  */
+        printf("%u %u %u\n", thread_0_counter, thread_1_counter, thread_2_counter);
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/xtensa/xcc/inc/tx_api_asm.h b/ports/xtensa/xcc/inc/tx_api_asm.h
new file mode 100644
index 00000000..1840ffce
--- /dev/null
+++ b/ports/xtensa/xcc/inc/tx_api_asm.h
@@ -0,0 +1,67 @@
+
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains macro constants for ThreadX API structures       */
+/*    and enums that need to be used in assembly coded port sources.      */
+/*    Most of these constants are derived from definitions in tx_api.h.   */
+/*    Only the constants that are needed are included here to reduce      */
+/*    the maintenance required when the structures or enums change.       */
+/*    Structure offsets depend on the compiler, so are tools-specific,    */
+/*    which usually means port-specific since a compiler's struct         */
+/*    packing rules depend on properties of the target architecture.      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_API_ASM_H
+#define TX_API_ASM_H
+
+#include "tx_port.h"
+
+/* API input parameters and general constants.  */
+
+#define TX_TRUE                         1
+#define TX_FALSE                        0
+#define TX_NULL                         0
+
+/* ThreadX thread control block structure.  */
+//  typedef struct TX_THREAD_STRUCT
+//  {
+
+#define tx_thread_run_count             0x04
+#define tx_thread_stack_ptr             0x08
+#define tx_thread_stack_end             0x10
+#define tx_thread_time_slice            0x18
+#define tx_thread_new_time_slice        0x1C
+#define tx_thread_solicited             0x28
+
+#ifdef TX_THREAD_SAFE_CLIB
+  #define tx_real_thread_entry          0x2C
+  #define tx_thread_clib_ptr            0x30
+  #define tx_thread_cp_state            0x34
+#else
+  #define tx_thread_cp_state            0x2C
+#endif
+
+//  }
+
+#endif /* TX_API_ASM_H */
+
diff --git a/ports/xtensa/xcc/inc/tx_port.h b/ports/xtensa/xcc/inc/tx_port.h
new file mode 100644
index 00000000..9438a7c8
--- /dev/null
+++ b/ports/xtensa/xcc/inc/tx_port.h
@@ -0,0 +1,479 @@
+
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+#include "tx_user.h"
+#endif
+
+/* Comment this out to disable thread-safe C library support. */
+#define TX_THREAD_SAFE_CLIB    1
+
+/* Include the glue to Xtensa-generic parts of this ThreadX port. */
+#include "xtensa_rtos.h"
+
+/* Parts of this file should not been seen by assembler sources. */
+#ifndef __ASSEMBLER__
+
+/* Some generic C sources call memset() and need this (else compiler warns).
+   Until the generic sources take care of this, do it here. */
+   
+#include <string.h>
+
+
+/* Define compiler library include files and library-specific macros. */
+
+/*
+    Thread-safety support for the supported C libraries. At this time
+    only the newlib and Xtensa C libraries are supported.
+
+    The C library reent structure can be quite large so it is placed
+    at the end of TX_THREAD, and a pointer to it is defined near the
+    beginning of TX_THREAD where assembly code can easily get to it 
+    at a fixed offset.
+*/
+
+#ifdef TX_THREAD_SAFE_CLIB
+struct TX_THREAD_STRUCT;
+
+extern char *_tx_clib_heap_start, *_tx_clib_heap_end;
+extern void _tx_clib_reent_init (struct TX_THREAD_STRUCT *thread_ptr);
+extern void _tx_clib_reent_cleanup (struct TX_THREAD_STRUCT *thread_ptr, int partial);
+extern void _tx_clib_thread_setup(struct TX_THREAD_STRUCT *thread_ptr);
+
+#include    <sys/reent.h>
+
+#define TX_CLIB_THREAD_EXTENSION \
+    VOID                (*tx_real_thread_entry)(ULONG id);  /* Actual entry point */ \
+    struct _reent *     tx_thread_clib_ptr;                 /* C lib reentrancy ptr */
+#define TX_CLIB_THREAD_EXTENSION_END \
+    struct _reent       tx_thread_clib_reent;               /* C lib reentrancy struct */
+#define TX_CLIB_THREAD_CREATE_EXTENSION(thread_ptr)
+#define TX_CLIB_THREAD_DELETE_EXTENSION(thread_ptr)
+#define TX_CLIB_THREAD_EXIT_EXTENSION(thread_ptr)
+#define TX_THREAD_CLIB_EXTENSION(thread_ptr) \
+    _tx_clib_thread_setup(thread_ptr);
+#else
+#define TX_CLIB_THREAD_EXTENSION
+#define TX_CLIB_THREAD_EXTENSION_END
+#define TX_CLIB_THREAD_CREATE_EXTENSION(thread_ptr)
+#define TX_CLIB_THREAD_DELETE_EXTENSION(thread_ptr)
+#define TX_CLIB_THREAD_EXIT_EXTENSION(thread_ptr)
+#define TX_THREAD_CLIB_EXTENSION(thread_ptr)
+#endif
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+#endif /* #ifndef __ASSEMBLER__ */
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/*
+    Define the minimum stack size for a thread on this processor.
+    If the size supplied during thread creation is less than TX_MINIMUM_STACK,
+    the thread create call will return an error. The minimum allows for a 
+    thread whose entry function makes no calls and needs no local frame.
+    TX_MINIMUM_STACK_BASIC allows the entry function to at least call 
+    tx_thread_relinquish(). An extra 0x10 bytes is allowed in all cases to 
+    allow for stack pointer alignment to 16 bytes. There is an additional premium 
+    for the stack checking functionality of TX_ENABLE_STACK_CHECKING.
+    In Xtensa, all these amounts depend on the function call ABI used by the
+    configuration (in general, Call0 ABI needs about 0x20 bytes less stack space
+    per function call frame). These amounts assume no compiler optimization (-O0).
+    Optimization usually requires less stack.
+
+    TX_MINIMUM_STACK_BASIC is a MINIMUM for threads that call tx_thread_relinquish()
+    only. Threads that do more, and in particular call C library functions such as 
+    printf(), need much more stack space and it is up to the application developer 
+    to determine how much.
+*/
+
+#ifdef __XTENSA_CALL0_ABI__
+        /* Call0 ABI */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        (XT_STK_FRMSZ + 0x10)
+#endif
+#ifdef  TX_ENABLE_STACK_CHECKING
+#define TX_STACK_CHECK_PREMIUM                  0x30
+#else
+#define TX_STACK_CHECK_PREMIUM                  0
+#endif
+#ifndef TX_MINIMUM_STACK_BASIC
+#define TX_MINIMUM_STACK_BASIC                  (XT_STK_FRMSZ + 0x70 + TX_STACK_CHECK_PREMIUM)
+#endif
+
+#else   /* Windowed ABI */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        (XT_STK_FRMSZ + 0x20)
+#endif
+#ifdef  TX_ENABLE_STACK_CHECKING
+#define TX_STACK_CHECK_PREMIUM                  0x50
+#else
+#define TX_STACK_CHECK_PREMIUM                  0
+#endif
+#ifndef TX_MINIMUM_STACK_BASIC
+#define TX_MINIMUM_STACK_BASIC                  (XT_STK_FRMSZ + 0x100 + TX_STACK_CHECK_PREMIUM)
+#endif
+
+#endif
+
+/*
+    Minimum stack size for the ThreadX system stack on this processor.
+    This is just a useful starting point for an application, it is not
+    checked by ThreadX. The minimum system stack size allows for the 
+    possible depth of interrupt nesting (XCHAL_EXCM_LEVEL-1 interrupt 
+    stack frames and XCHAL_EXCM_LEVEL interrupt handlers including timer),
+    assuming very basic interrupt handlers (allows 1 call12). It needs to 
+    be increased to support the application's real interrupt handlers (and 
+    timer interrupt if TX_TIMER_PROCESS_IN_ISR). The system stack is located 
+    where the stack pointer is inside tx_kernel_enter() which is usually from 
+    main(), and so is determined by the development tools. It grows downward 
+    toward the first available memory pointer passed to tx_application_define(). 
+    An application should allow sufficient space for the system stack.
+
+    For XEA3, allow a minimum of XCHAL_NUM_INTLEVELS nested interrupts. The stack
+    frames are minimal-sized and may need to be increased to support real applications.
+*/
+
+#if XCHAL_HAVE_XEA3
+#define TX_SYSTEM_STACK_MINIMUM                 (XCHAL_NUM_INTLEVELS * 0x40)
+#ifndef TX_SYSTEM_STACK_SIZE
+#if TX_SYSTEM_STACK_MINIMUM > 2048
+#define TX_SYSTEM_STACK_SIZE                    TX_SYSTEM_STACK_MINIMUM
+#else
+#define TX_SYSTEM_STACK_SIZE                    2048
+#endif
+#endif
+#else
+#define TX_SYSTEM_STACK_MINIMUM                 (((XCHAL_EXCM_LEVEL-1) * (0x40 + XT_STK_FRMSZ)) + 0x40)
+#ifndef TX_SYSTEM_STACK_SIZE
+#define TX_SYSTEM_STACK_SIZE                    4096
+#endif
+#endif
+
+/*
+    Define the system timer thread's default stack size and priority.
+    These are only applicable if TX_TIMER_PROCESS_IN_ISR is not defined.
+*/
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#ifdef __XTENSA_CALL0_ABI__
+#define TX_TIMER_THREAD_STACK_SIZE              (TX_MINIMUM_STACK_BASIC + 0x100)
+#else
+#define TX_TIMER_THREAD_STACK_SIZE              (TX_MINIMUM_STACK_BASIC + 0x200)
+#endif
+#endif
+
+
+/* Parts of this file should not been seen by assembler sources. */
+#ifndef __ASSEMBLER__
+
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX Xtensa port.  */ 
+
+#if XCHAL_HAVE_XEA3
+#define TX_INT_DISABLE                          0x8               /* Disable interrupts value */
+#define TX_INT_ENABLE                           0x0               /* Enable interrupt value   */
+#else
+#define TX_INT_DISABLE                          XCHAL_EXCM_LEVEL  /* Disable interrupts value */
+#define TX_INT_ENABLE                           0x0               /* Enable interrupt value   */
+#endif
+
+
+/*
+    Define the clock source for trace event entry time stamp. The following 
+    two item are port specific. For example, if the time source is at the 
+    address 0x0a800024 and is 16-bits in size, the clock source constants 
+    would be:
+
+    #define TX_TRACE_TIME_SOURCE                *((ULONG *) 0x0a800024)
+    #define TX_TRACE_TIME_MASK                  0x0000FFFFUL
+*/
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/*
+    Define the port specific options for the _tx_build_options variable.
+    This variable indicates how the ThreadX library was built.
+*/
+
+#if defined(XT_SIMULATOR) || !defined(XT_BOARD)
+#define TX_XT_OPT_SIMULATOR                     (1UL << 0)
+#else
+#define TX_XT_OPT_SIMULATOR                     0
+#endif
+
+#if defined(XT_BOARD)
+#define TX_XT_OPT_BOARD                         (1UL << 1)
+#else
+#define TX_XT_OPT_BOARD                         0
+#endif
+
+#if defined(XT_INTEXC_HOOKS)
+#define TX_XT_OPT_INTEXC_HOOKS                  (1UL << 2)
+#else
+#define TX_XT_OPT_INTEXC_HOOKS                  0
+#endif
+
+#if defined(TX_THREAD_SAFE_CLIB)
+#define TX_XT_OPT_CLIB                          (1UL << 3)
+#else
+#define TX_XT_OPT_CLIB                          0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (TX_XT_OPT_SIMULATOR | TX_XT_OPT_BOARD \
+                                                | TX_XT_OPT_INTEXC_HOOKS | TX_XT_OPT_CLIB)
+
+
+/*
+    Define the in-line initialization constant so that modules with in-line
+    initialization capabilities can prevent their initialization from being
+    a function call.
+*/
+
+#define TX_INLINE_INITIALIZATION
+
+
+/*
+    Determine whether or not stack checking is enabled. By default, ThreadX
+    stack checking is disabled. When the following is defined, ThreadX thread 
+    stack checking is enabled. If enabled (TX_ENABLE_STACK_CHECKING is defined),
+    the TX_DISABLE_STACK_FILLING define is canceled, thereby forcing the stack 
+    fill which is necessary for the stack checking logic.
+*/
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/*
+    Define the TX_THREAD control block extensions for this port. The main
+    reason for the multiple macros is so that backward compatibility can 
+    be maintained with existing ThreadX kernel awareness modules.
+*/
+
+#if XCHAL_CP_NUM > 0
+#define TX_CP_THREAD_EXTENSION  \
+    /* Co-proc state save areas, with padding for alignment: */ \
+    UINT                tx_thread_cp_state[(XT_CP_SIZE+3)/4];
+#else
+#define TX_CP_THREAD_EXTENSION
+#endif
+
+#define TX_THREAD_EXTENSION_0 \
+    /* These extensions needs to be accessed from assembly code at context switches */ \
+    UINT                tx_thread_solicited;    /* Non-zero indicates solicited entry */ \
+    TX_CLIB_THREAD_EXTENSION                    /* Ptr to C library re-ent struct */ \
+    TX_CP_THREAD_EXTENSION          /* Coprocessor state save areas */
+
+#define TX_THREAD_EXTENSION_1 \
+    TX_CLIB_THREAD_EXTENSION_END
+
+#define TX_THREAD_EXTENSION_2
+
+/* Execution profile related */
+#define TX_THREAD_EXTENSION_3 \
+    unsigned long long  tx_thread_execution_time_total; \
+    unsigned long       tx_thread_execution_time_last_start;
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+#if XCHAL_CP_NUM > 0
+extern void _xt_coproc_release(void * coproc_sa_base);
+
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \
+        _xt_coproc_release(&thread_ptr->tx_thread_cp_state);
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \
+        _xt_coproc_release(&thread_ptr->tx_thread_cp_state);
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) \
+        _xt_coproc_release(&thread_ptr->tx_thread_cp_state);
+#define TX_THREAD_CP_EXTENSION(thread_ptr) \
+    /* Initialize XT_CP_ASA ptr to aligned save area: */ \
+    /* NOTE: keep this matched with xtensa_context.h. */ \
+    thread_ptr->tx_thread_cp_state[0] = 0; \
+    thread_ptr->tx_thread_cp_state[1] = 0; \
+    thread_ptr->tx_thread_cp_state[2] = \
+        ((((UINT)thread_ptr->tx_thread_cp_state)+12+XCHAL_TOTAL_SA_ALIGN-1) \
+            & -XCHAL_TOTAL_SA_ALIGN);
+#else
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_CP_EXTENSION(thread_ptr)
+#endif
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \
+    TX_THREAD_CLIB_EXTENSION(thread_ptr) \
+    TX_THREAD_CP_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/*
+    Define ThreadX interrupt lockout and restore macros for protection
+    on access of critical kernel information. The restore interrupt macro
+    must restore the interrupt posture of the running thread prior to the
+    value present prior to the disable macro. In most cases, the save area
+    macro is used to define a local function save area for the disable and
+    restore macros.
+*/
+
+extern unsigned int                 _tx_thread_interrupt_control(unsigned int new_posture);
+
+#define TX_INTERRUPT_SAVE_AREA      register unsigned int interrupt_save;
+
+#ifdef TX_DISABLE_INLINE_MACROS
+#define TX_DISABLE                  interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
+#define TX_RESTORE                  _tx_thread_interrupt_control(interrupt_save);
+#else
+#define TX_DISABLE                  interrupt_save = xthal_disable_interrupts();
+#define TX_RESTORE                  xthal_restore_interrupts(interrupt_save);
+#endif
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+#if XCHAL_HAVE_XEA3
+/* Variables that keep track of the timer and software interrupt numbers in use. */
+extern int xt_sw_intnum;
+extern int xt_timer_intnum;
+#endif
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. * Azure RTOS Xtensa Version 6.1.3 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+#endif /* #ifndef __ASSEMBLER__ */
+
+#endif
+
diff --git a/ports/xtensa/xcc/inc/tx_user.h b/ports/xtensa/xcc/inc/tx_user.h
new file mode 100644
index 00000000..db17d428
--- /dev/null
+++ b/ports/xtensa/xcc/inc/tx_user.h
@@ -0,0 +1,257 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   User Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_user.h                                           PORTABLE C      */ 
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This file contains user defines for configuring ThreadX in specific */ 
+/*    ways. This file will have an effect only if the application and     */ 
+/*    ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ 
+/*    Note that all the defines in this file may also be made on the      */ 
+/*    command line when building ThreadX library and application objects. */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_USER_H
+#define TX_USER_H
+
+
+/* Define various build options for the ThreadX port.  The application should either make changes
+   here by commenting or un-commenting the conditional compilation defined OR supply the defines 
+   though the compiler's equivalent of the -D option.  
+   
+   For maximum speed, the following should be defined:
+
+        TX_MAX_PRIORITIES                       32  
+        TX_DISABLE_PREEMPTION_THRESHOLD
+        TX_DISABLE_REDUNDANT_CLEARING
+        TX_DISABLE_NOTIFY_CALLBACKS
+        TX_NOT_INTERRUPTABLE
+        TX_TIMER_PROCESS_IN_ISR
+        TX_REACTIVATE_INLINE
+        TX_DISABLE_STACK_FILLING
+        TX_INLINE_THREAD_RESUME_SUSPEND
+   
+   For minimum size, the following should be defined:
+   
+        TX_MAX_PRIORITIES                       32  
+        TX_DISABLE_PREEMPTION_THRESHOLD
+        TX_DISABLE_REDUNDANT_CLEARING
+        TX_DISABLE_NOTIFY_CALLBACKS
+        TX_NOT_INTERRUPTABLE
+        TX_TIMER_PROCESS_IN_ISR
+   
+   Of course, many of these defines reduce functionality and/or change the behavior of the
+   system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR
+   results in faster and smaller code, however, it increases the amount of processing in the ISR.
+   In addition, some services that are available in timers are not available from ISRs and will
+   therefore return an error if this option is used. This may or may not be desirable for a 
+   given application.  */
+
+
+/* Override various options with default values already assigned in tx_port.h. Please also refer
+   to tx_port.h for descriptions on each of these options.  */
+
+/*
+#define TX_MAX_PRIORITIES                       32  
+#define TX_MINIMUM_STACK                        ????         
+#define TX_THREAD_USER_EXTENSION                ????
+#define TX_TIMER_THREAD_STACK_SIZE              ????
+#define TX_TIMER_THREAD_PRIORITY                ????
+*/
+
+/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls 
+   should be processed within the a system timer thread or directly in the timer ISR. 
+   By default, the timer thread is used. When the following is defined, the timer expiration 
+   processing is done directly from the timer ISR, thereby eliminating the timer thread control
+   block, stack, and context switching to activate it.  */
+
+/*
+#define TX_TIMER_PROCESS_IN_ISR
+*/
+
+/* Determine if in-line timer reactivation should be used within the timer expiration processing.
+   By default, this is disabled and a function call is used. When the following is defined,
+   reactivating is performed in-line resulting in faster timer processing but slightly larger
+   code size.  */ 
+
+/*
+#define TX_REACTIVATE_INLINE 
+*/
+
+/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled,
+   which places an 0xEF pattern in each byte of each thread's stack.  This is used by
+   debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature.  */
+
+/*
+#define TX_DISABLE_STACK_FILLING 
+*/
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+/*
+#define TX_ENABLE_STACK_CHECKING
+*/
+
+/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is 
+   enabled. If the application does not use preemption-threshold, it may be disabled to reduce
+   code size and improve performance.  */
+
+/*
+#define TX_DISABLE_PREEMPTION_THRESHOLD
+*/
+
+/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears 
+   the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary
+   clearing of ThreadX global variables.  */
+
+/*
+#define TX_DISABLE_REDUNDANT_CLEARING
+*/
+
+/* Determine if no timer processing is required. This option will help eliminate the timer 
+   processing when not needed. The user will also have to comment out the call to 
+   tx_timer_interrupt, which is typically made from assembly language in 
+   tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR
+   must also be used.  */
+
+/* 
+#define TX_NO_TIMER
+#ifndef TX_TIMER_PROCESS_IN_ISR
+#define TX_TIMER_PROCESS_IN_ISR
+#endif
+*/
+
+/* Determine if the notify callback option should be disabled. By default, notify callbacks are
+   enabled. If the application does not use notify callbacks, they may be disabled to reduce
+   code size and improve performance.  */
+
+/*
+#define TX_DISABLE_NOTIFY_CALLBACKS
+*/
+
+
+/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal 
+   code in-line. This results in a larger image, but improves the performance of the thread 
+   resume and suspend services.  */
+
+/*
+#define TX_INLINE_THREAD_RESUME_SUSPEND
+*/
+
+
+/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code 
+   size and less processing overhead, but increases the interrupt lockout time.  */
+
+/*
+#define TX_NOT_INTERRUPTABLE
+*/
+
+
+/* Determine if the trace event logging code should be enabled. This causes slight increases in 
+   code size and overhead, but provides the ability to generate system trace information which 
+   is available for viewing in TraceX.  */
+
+/*
+#define TX_ENABLE_EVENT_TRACE
+*/
+
+
+/* Determine if block pool performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various block pool performance information. */
+
+/*
+#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if byte pool performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various byte pool performance information. */
+
+/*
+#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if event flags performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various event flags performance information. */
+
+/*
+#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if mutex performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various mutex performance information. */
+
+/*
+#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if queue performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various queue performance information. */
+
+/*
+#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if semaphore performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various semaphore performance information. */
+
+/*
+#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if thread performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various thread performance information. */
+
+/*
+#define TX_THREAD_ENABLE_PERFORMANCE_INFO
+*/
+
+/* Determine if timer performance gathering is required by the application. When the following is
+   defined, ThreadX gathers various timer performance information. */
+
+/*
+#define TX_TIMER_ENABLE_PERFORMANCE_INFO
+*/
+
+#endif
+
diff --git a/ports/xtensa/xcc/inc/xtensa_api.h b/ports/xtensa/xcc/inc/xtensa_api.h
new file mode 100644
index 00000000..10255838
--- /dev/null
+++ b/ports/xtensa/xcc/inc/xtensa_api.h
@@ -0,0 +1,125 @@
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*     Xtensa-specific API for RTOS ports.                                */
+/**************************************************************************/
+
+#ifndef XTENSA_API_H
+#define XTENSA_API_H
+
+#include <xtensa/hal.h>
+
+#include "xtensa_context.h"
+
+
+/* Typedef for C-callable interrupt handler function */
+typedef void (*xt_handler)(void *);
+
+/* Typedef for C-callable exception handler function */
+typedef void (*xt_exc_handler)(XtExcFrame *);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified exception.
+
+    n        - Exception number (type)
+    f        - Handler function address, NULL to uninstall handler.
+
+  The handler will be passed a pointer to the exception frame, which is created
+  on the stack of the thread that caused the exception.
+
+  If the handler returns, the thread context will be restored and the faulting
+  instruction will be retried. Any values in the exception frame that are
+  modified by the handler will be restored as part of the context. For details
+  of the exception frame structure see xtensa_context.h.
+-------------------------------------------------------------------------------
+*/
+extern xt_exc_handler xt_set_exception_handler(uint32_t n, xt_exc_handler f);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified interrupt.
+ 
+    n        - Interrupt number.
+    f        - Handler function address, NULL to uninstall handler.
+    arg      - Argument to be passed to handler.
+-------------------------------------------------------------------------------
+*/
+extern xt_handler xt_set_interrupt_handler(uint32_t n, xt_handler f, void * arg);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to enable the specified interrupt.
+
+    intnum    - Interrupt number to be enabled.
+
+  Returns: Nothing.
+-------------------------------------------------------------------------------
+*/
+extern void xt_interrupt_enable(uint32_t intnum);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to disable the specified interrupt.
+
+    intnum    - Interrupt number to be disabled.
+
+  Returns: Nothing.
+-------------------------------------------------------------------------------
+*/
+extern void xt_interrupt_disable(uint32_t intnum);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to trigger the specified (s/w) interrupt.
+
+    intnum    - Interrupt number to be triggered.
+
+  Returns: Nothing.
+-------------------------------------------------------------------------------
+*/
+extern void xt_interrupt_trigger(uint32_t intnum);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to clear the specified (s/w or edge-triggered)
+  interrupt.
+
+    intnum    - Interrupt number to be cleared.
+
+Returns: Nothing.
+-------------------------------------------------------------------------------
+*/
+extern void xt_interrupt_clear(uint32_t intnum);
+
+
+#endif /* XTENSA_API_H */
+
diff --git a/ports/xtensa/xcc/inc/xtensa_context.h b/ports/xtensa/xcc/inc/xtensa_context.h
new file mode 100644
index 00000000..c2f76afa
--- /dev/null
+++ b/ports/xtensa/xcc/inc/xtensa_context.h
@@ -0,0 +1,561 @@
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************
+
+    XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
+
+    This header contains definitions and macros for use primarily by Xtensa
+    RTOS assembly source files. It includes and uses the Xtensa hardware
+    abstraction layer (HAL) to deal with config specifics. It may also be
+    included in C source files.
+
+    NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
+
+***************************************************************************/
+
+#ifndef XTENSA_CONTEXT_H
+#define XTENSA_CONTEXT_H
+
+#ifdef __ASSEMBLER__
+#include    <xtensa/coreasm.h>
+#endif
+
+#include    <xtensa/config/tie.h>
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+#if defined (__ASSEMBLER__)
+#include    "tx_api_asm.h"
+#endif
+
+
+/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
+
+
+/*
+-------------------------------------------------------------------------------
+  Macros that help define structures for both C and assembler.
+-------------------------------------------------------------------------------
+*/
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+
+#define XSTRUCT_BEGIN            .pushsection .text; .struct 0
+#define XSTRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
+#define XSTRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
+#define XSTRUCT_END(sname)       sname##Size:; .popsection
+
+#else
+
+#define XSTRUCT_BEGIN            typedef struct {
+#define XSTRUCT_FIELD(ctype,size,asname,name)    ctype   name;
+#define XSTRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
+#define XSTRUCT_END(sname)       } sname;
+
+#endif //_ASMLANGUAGE || __ASSEMBLER__
+
+
+/*
+-------------------------------------------------------------------------------
+  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
+
+  A stack frame of this structure is allocated for any interrupt or exception.
+  It goes on the current stack. If the RTOS has a system stack for handling 
+  interrupts, every thread stack must allow space for just one interrupt stack 
+  frame, then nested interrupt stack frames go on the system stack.
+
+  The frame includes basic registers (explicit) and "extra" registers introduced 
+  by user TIE or the use of the MAC16 option in the user's Xtensa config.
+  The frame size is minimized by omitting regs not applicable to user's config.
+
+  For Windowed ABI, this stack frame includes the interruptee's base save area,
+  another base save area to manage gcc nested functions, and a little temporary 
+  space to help manage the spilling of the register windows.
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_HAVE_XEA2
+
+XSTRUCT_BEGIN
+XSTRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
+XSTRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
+XSTRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
+XSTRUCT_FIELD (long, 4, XT_STK_A0,       a0)
+XSTRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
+XSTRUCT_FIELD (long, 4, XT_STK_A2,       a2)
+XSTRUCT_FIELD (long, 4, XT_STK_A3,       a3)
+XSTRUCT_FIELD (long, 4, XT_STK_A4,       a4)
+XSTRUCT_FIELD (long, 4, XT_STK_A5,       a5)
+XSTRUCT_FIELD (long, 4, XT_STK_A6,       a6)
+XSTRUCT_FIELD (long, 4, XT_STK_A7,       a7)
+XSTRUCT_FIELD (long, 4, XT_STK_A8,       a8)
+XSTRUCT_FIELD (long, 4, XT_STK_A9,       a9)
+XSTRUCT_FIELD (long, 4, XT_STK_A10,      a10)
+XSTRUCT_FIELD (long, 4, XT_STK_A11,      a11)
+XSTRUCT_FIELD (long, 4, XT_STK_A12,      a12)
+XSTRUCT_FIELD (long, 4, XT_STK_A13,      a13)
+XSTRUCT_FIELD (long, 4, XT_STK_A14,      a14)
+XSTRUCT_FIELD (long, 4, XT_STK_A15,      a15)
+XSTRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
+XSTRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+XSTRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+#if XCHAL_HAVE_LOOPS
+XSTRUCT_FIELD (long, 4, XT_STK_LBEG,     lbeg)
+XSTRUCT_FIELD (long, 4, XT_STK_LEND,     lend)
+XSTRUCT_FIELD (long, 4, XT_STK_LCOUNT,   lcount)
+#endif
+#if XCHAL_HAVE_EXCLUSIVE
+XSTRUCT_FIELD (long, 4, XT_STK_ATOMCTL,  atomctl)
+#endif
+#ifndef __XTENSA_CALL0_ABI__
+/* Temporary space for saving stuff during window spill */
+XSTRUCT_FIELD (long, 4, XT_STK_TMP0,     tmp0)
+XSTRUCT_FIELD (long, 4, XT_STK_TMP1,     tmp1)
+XSTRUCT_FIELD (long, 4, XT_STK_TMP2,     tmp2)
+#endif
+#ifdef XT_USE_SWPRI
+/* Storage for virtual priority mask */
+XSTRUCT_FIELD (long, 4, XT_STK_VPRI,     vpri)
+#endif
+#ifdef XT_USE_OVLY
+/* Storage for overlay state */
+XSTRUCT_FIELD (long, 4, XT_STK_OVLY,     ovly)
+#endif
+XSTRUCT_END(XtExcFrame)
+
+#endif /* XCHAL_HAVE_XEA2 */
+
+#if XCHAL_HAVE_XEA3
+
+XSTRUCT_BEGIN
+XSTRUCT_FIELD (long, 4, XT_STK_ATOMCTL,  atomctl)
+XSTRUCT_FIELD (long, 4, XT_STK_LCOUNT,   lcount)
+XSTRUCT_FIELD (long, 4, XT_STK_LEND,     lend)
+XSTRUCT_FIELD (long, 4, XT_STK_LBEG,     lbeg)
+XSTRUCT_FIELD (long, 4, XT_STK_PC,       pc)
+XSTRUCT_FIELD (long, 4, XT_STK_PS,       ps)
+XSTRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+XSTRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+#ifdef __XTENSA_CALL0_ABI__
+XSTRUCT_FIELD (long, 4, XT_STK_A0,     a0)
+XSTRUCT_FIELD (long, 4, XT_STK_A1,     a1)
+XSTRUCT_FIELD (long, 4, XT_STK_A2,     a2)
+XSTRUCT_FIELD (long, 4, XT_STK_A3,     a3)
+XSTRUCT_FIELD (long, 4, XT_STK_A4,     a4)
+XSTRUCT_FIELD (long, 4, XT_STK_A5,     a5)
+XSTRUCT_FIELD (long, 4, XT_STK_A6,     a6)
+XSTRUCT_FIELD (long, 4, XT_STK_A7,     a7)
+#endif
+XSTRUCT_FIELD (long, 4, XT_STK_A8,     a8)
+XSTRUCT_FIELD (long, 4, XT_STK_A9,     a9)
+XSTRUCT_FIELD (long, 4, XT_STK_A10,    a10)
+XSTRUCT_FIELD (long, 4, XT_STK_A11,    a11)
+XSTRUCT_FIELD (long, 4, XT_STK_A12,    a12)
+XSTRUCT_FIELD (long, 4, XT_STK_A13,    a13)
+XSTRUCT_FIELD (long, 4, XT_STK_A14,    a14)
+XSTRUCT_FIELD (long, 4, XT_STK_A15,    a15)
+#ifdef __XTENSA_WINDOWED_ABI__
+XSTRUCT_AFIELD(long, 4, XT_STK_SPILL,  spill, 8)
+#endif
+XSTRUCT_END(XtExcFrame)
+
+#endif /* XCHAL_HAVE_XEA3 */
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define XT_STK_NEXT1      XtExcFrameSize
+#else
+#define XT_STK_NEXT1      sizeof(XtExcFrame)
+#endif
+
+
+/* Allocate extra storage if needed for non-CP TIE state. Allow for alignment
+   padding as needed.
+ */
+#if XCHAL_EXTRA_SA_SIZE != 0
+
+#if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
+#else
+/* If need more alignment than stack, add space for dynamic alignment */
+#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
+#endif
+#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
+
+#else
+
+/* No extra storage required */
+#define XT_STK_NEXT2            XT_STK_NEXT1   
+
+#endif
+
+
+#if XCHAL_HAVE_XEA3
+
+/* Total frame size */
+#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2))
+
+/* Exception/interrupt frame size */
+#define XT_STK_XFRM_SZ          XT_STK_NEXT1
+
+/* Extra save area size (including alignment padding) */
+#define XT_STK_XTRA_SZ          (XT_STK_FRMSZ - XT_STK_XFRM_SZ)
+
+/* Alignment padding area size */
+#if XCHAL_EXTRA_SA_SIZE != 0
+#define XT_STK_ALIGN_SZ         (XT_STK_EXTRA - XT_STK_NEXT1)
+#endif
+
+#else
+
+/*
+-------------------------------------------------------------------------------
+  This is the frame size. Add space for 4 registers (interruptee's base save
+  area) and some space for gcc nested functions if any.
+-------------------------------------------------------------------------------
+*/
+#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
+
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+
+  The RTOS must provide an area per thread to save the state of co-processors
+  when that thread does not have control. Co-processors are context-switched
+  lazily (on demand) only when a new thread uses a co-processor instruction,
+  otherwise a thread retains ownership of the co-processor even when it loses
+  control of the processor. An Xtensa co-processor exception is triggered when
+  any co-processor instruction is executed by a thread that is not the owner,
+  and the context switch of that co-processor is then peformed by the handler.
+  Ownership represents which thread's state is currently in the co-processor.
+
+  Co-processors may not be used by interrupt or exception handlers. If an 
+  co-processor instruction is executed by an interrupt or exception handler,
+  the co-processor exception handler will trigger a kernel panic and freeze.
+  This restriction is introduced to reduce the overhead of saving and restoring
+  co-processor state (which can be quite large) and in particular remove that
+  overhead from interrupt handlers.
+
+  The co-processor state save area may be in any convenient per-thread location
+  such as in the thread control block or above the thread stack area. It need
+  not be in the interrupt stack frame since interrupts don't use co-processors.
+
+  Along with the save area for each co-processor, two bitmasks with flags per 
+  co-processor (laid out as in the CPENABLE reg) help manage context-switching
+  co-processors as efficiently as possible:
+
+  XT_CPENABLE
+    The contents of a non-running thread's CPENABLE register.
+    It represents the co-processors owned (and whose state is still needed)
+    by the thread. When a thread is preempted, its CPENABLE is saved here.
+    When a thread solicits a context-swtich, its CPENABLE is cleared - the
+    compiler has saved the (caller-saved) co-proc state if it needs to.
+    When a non-running thread loses ownership of a CP, its bit is cleared.
+    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+    Avoids co-processor exceptions when no change of ownership is needed.
+
+  XT_CPSTORED
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether the state of each co-processor is saved in the state 
+    save area. When a thread enters the kernel, only the state of co-procs
+    still enabled in CPENABLE is saved. When the co-processor exception 
+    handler assigns ownership of a co-processor to a thread, it restores 
+    the saved state only if this bit is set, and clears this bit.
+
+  XT_CP_CS_ST
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether callee-saved state is saved in the state save area.
+    Callee-saved state is saved by itself on a solicited context switch,
+    and restored when needed by the coprocessor exception handler.
+    Unsolicited switches will cause the entire coprocessor to be saved
+    when necessary.
+
+  XT_CP_ASA
+    Pointer to the aligned save area.  Allows it to be aligned more than
+    the overall save area (which might only be stack-aligned or TCB-aligned).
+    Especially relevant for Xtensa cores configured with a very large data
+    path that requires alignment greater than 16 bytes (ABI stack alignment).
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_CP_NUM > 0
+
+/*  Offsets of each coprocessor save area within the 'aligned save area':  */
+#define XT_CP0_SA   0
+#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
+#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
+#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
+#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
+#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
+#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
+#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
+#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
+
+/*  Offsets within the overall save area:  */
+#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
+/*  Overall size allows for dynamic alignment:  */
+#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
+#else
+#define XT_CP_SIZE  0
+#endif
+
+
+/*
+-------------------------------------------------------------------------------
+  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+
+  Convenient where the frame size requirements are the same for both ABIs.
+    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
+
+  where size = size of stack frame in bytes (must be >0 and aligned to 16).
+  For framed functions the frame is created and the return address saved at
+  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+  For frameless functions, there is no frame and return address remains in a0.
+  Note: Because CPP macros expand to a single line, macros requiring multi-line 
+  expansions are implemented as assembler macros.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef __ASSEMBLER__
+#ifdef __XTENSA_CALL0_ABI__
+  /* Call0 */
+  #define ENTRY(sz)     entry1  sz
+    .macro  entry1 size=0x10
+    addi    sp, sp, -\size
+    s32i    a0, sp, 0
+    .endm
+  #define ENTRY0      
+  #define RET(sz)       ret1    sz
+    .macro  ret1 size=0x10
+    l32i    a0, sp, 0
+    addi    sp, sp, \size
+    ret
+    .endm
+  #define RET0          ret
+#else
+  /* Windowed */
+#if XCHAL_HAVE_XEA3
+  #define ENTRY(sz)     entry   sp, (sz + 0x20)
+  #define ENTRY0        entry   sp, 0x20
+#else
+  #define ENTRY(sz)     entry   sp, (sz + 0x10)
+  #define ENTRY0        entry   sp, 0x10
+#endif
+  #define RET(sz)       retw
+  #define RET0          retw
+#endif
+#endif
+
+
+/*
+-------------------------------------------------------------------------------
+  This flag is meant for internal use. Have all interrupts be dispatched via a
+  common wrapper, which takes care of doing some OS-specific stuff common to
+  all interrupt handlers. Said stuff cannot safely be handled in the RTOS_ENTER
+  and RTOS_EXIT macros.
+-------------------------------------------------------------------------------
+*/
+#if (defined TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || (defined XT_INTEXC_HOOKS)
+#define XT_USE_INT_WRAPPER    1
+#else
+#define XT_USE_INT_WRAPPER    0
+#endif
+
+#if XCHAL_HAVE_XEA3
+#ifdef XT_USE_SWPRI
+//#warning "Software prioritization of interrupts (XT_USE_SWPRI) not supported for XEA3."
+#endif
+
+#ifdef __ASSEMBLER__
+
+    // RTOS-specific entry macro. Use only a8, a12-a14.
+
+    .macro  XT_RTOS_INT_ENTER
+
+    .endm
+
+    // RTOS-specific exit macro. Use only a8-a14.
+    // (In call0, a15 holds user SP, must be preserved)
+
+    .macro  XT_RTOS_INT_EXIT
+
+    // Check nesting count and branch on nest state.
+    movi     a8,  _tx_thread_system_state
+    movi     a9,  _tx_thread_execute_ptr        // a9  <- &_tx_thread_execute_ptr (new)
+    movi    a10,  _tx_thread_preempt_disable    // a10 <- &_tx_thread_preempt_disable
+    l32i     a8,  a8, 0
+    bnez     a8,  .Lnested                      // state != 0 means nested
+
+    movi     a8,  _tx_thread_current_ptr        // a8  <- &_tx_thread_current_ptr (old)
+    l32i     a9,  a9, 0                         // a9  <- _tx_thread_execute_ptr
+    l32i    a11,  a8, 0                         // a11 <- _tx_thread_current_ptr
+    beqz    a11,  .Lsched                       // no old thread, go to scheduler
+    l32i    a10, a10, 0                         // a10 <- _tx_thread_preempt_disable
+    beq     a11,  a9, .Lnested                  // no change, restore current thread
+    bgei    a10,  1, .Lnested                   // no preemption, restore current thread
+
+    // Preemption, save remaining state of current (outgoing) thread
+
+    movi    a12,  _tx_timer_time_slice          // a12 <- &_tx_timer_time_slice
+    addi    a10,  a1, -XT_STK_FRMSZ
+    s32i    a10, a11, tx_thread_stack_ptr       // save outgoing thread stack pointer
+    l32i    a10, a12, 0                         // a10 <- _tx_timer_time_slice
+    s32i    a10, a11, tx_thread_time_slice      // save outgoing time slice value
+    movi    a10,  0
+    s32i    a10, a12, 0                         // disable time slice
+    s32i    a10, a11, tx_thread_solicited       // mark as preempted
+    s32i    a10,  a8, 0                         // Clear _tx_thread_current_ptr
+#if XCHAL_CP_NUM > 0
+    rsr     a12,  CPENABLE                      // Save and clear CPENABLE
+    s16i    a12, a11, tx_thread_cp_state + XT_CPENABLE
+    wsr     a10,  CPENABLE
+#endif
+
+    // Save non-CP TIE state if any
+#if XCHAL_EXTRA_SA_SIZE > 0
+    addi    a10,  a1, -XT_STK_FRMSZ + XT_STK_ALIGN_SZ   // where to save
+#if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a12, -XCHAL_EXTRA_SA_ALIGN
+    and     a10, a10, a12                       // align dynamically >16 bytes
+#endif
+    xchal_ncp_store a10, a11, a12, a13, a14
+#endif
+
+    // If windowed ABI, a0-a7 was not saved by dispatch code.
+    // These don't go into the exception frame, but below the
+    // exception frame pointer.
+
+#ifdef __XTENSA_WINDOWED_ABI__
+    addi    a10,  a1, -XT_STK_FRMSZ -32
+    s32i     a0, a10, 0
+    s32i     a2, a10, 8
+    s32i     a3, a10, 12
+    s32i     a4, a10, 16
+    s32i     a5, a10, 20
+    s32i     a6, a10, 24
+    s32i     a7, a10, 28
+#endif
+
+.Lsched:
+    // When we get here, interrupts are disabled, a8 = &_tx_thread_current_ptr,
+    // a9 = _tx_thread_execute_ptr
+    movi     a9,  _tx_thread_execute_ptr        // a9  <- &_tx_thread_execute_ptr (new)
+    l32i     a9,  a9, 0                         // a9  <- _tx_thread_execute_ptr
+    s32i     a9,  a8, 0                         // _tx_thread_current_ptr = _tx_thread_execute_ptr
+    beqz     a9, _xt_idle                       // go idle if _tx_thread_execute_ptr == 0
+    l32i    a10,  a9, tx_thread_run_count
+    l32i    a11,  a9, tx_thread_time_slice
+    movi    a12, _tx_timer_time_slice
+    addi    a10, a10, 1
+    s32i    a10,  a9, tx_thread_run_count
+    s32i    a11, a12, 0                         // _tx_timer_time_slice = _tx_thread_current_ptr->tx_thread_time_slice
+
+#ifdef TX_THREAD_SAFE_CLIB
+    #if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    movi    a10,  _impure_ptr
+    #elif XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    movi    a10,  _reent_ptr
+    #else
+    #error TX_THREAD_SAFE_CLIB defined with unsupported C library.
+    #endif
+    l32i    a11,  a9, tx_thread_clib_ptr
+    s32i    a11, a10, 0
+#endif
+
+#if XCHAL_CP_NUM > 0
+    l16ui   a10,  a9, tx_thread_cp_state + XT_CPENABLE
+    wsr     a10,  CPENABLE                      // restore CPENABLE
+#endif
+
+    l32i     a1,  a9, tx_thread_stack_ptr       // SP = _tx_thread_execute_ptr->tx_thread_stack_ptr
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    // Call the thread entry function to indicate the thread is executing.
+    // SP should be pointing to a safe region at this point.
+#ifdef __XTENSA_CALL0_ABI__
+    call0    _tx_execution_thread_enter
+#else
+    call8    _tx_execution_thread_enter
+#endif
+#endif
+
+    l32i     a2,  a9, tx_thread_solicited       // a2 = solicited flag
+    beqz     a2, 1f
+
+    // Solicited restore
+    addi     a1,  a1, XT_STK_FRMSZ              // restore original SP
+    addi     a2,  a1, -XT_STK_XFRM_SZ
+    l32i     a3,  a2, XT_STK_PC                 // a3 = return PC
+
+    movi     a2, PS_DI
+    xps  a2, a2                                 // disable interrupts
+    movi     a2, 0
+    wsr.ms   a2                                 // restore normal DISPST
+    rsync
+    jx   a3                                     // return to yield point
+
+1:
+    // Preempt restore
+#if XCHAL_EXTRA_SA_SIZE > 0
+    addi    a10,  a1, XT_STK_ALIGN_SZ           // where to restore from
+#if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a12, -XCHAL_EXTRA_SA_ALIGN
+    and     a10, a10, a12                       // align dynamically >16 bytes
+#endif
+    xchal_ncp_load a10, a11, a12, a13, a14
+#endif
+
+#ifdef __XTENSA_WINDOWED_ABI__
+    // Restore a0-a7 for windowed ABI
+    addi     a8,  a1, -32
+    l32i     a0,  a8, 0
+    l32i     a2,  a8, 8
+    l32i     a3,  a8, 12
+    l32i     a4,  a8, 16
+    l32i     a5,  a8, 20
+    l32i     a6,  a8, 24
+    l32i     a7,  a8, 28
+#else
+    // For call0, dispatch exit code expects a15 = original SP
+    addi    a15,  a1, XT_STK_FRMSZ
+#endif
+
+    addi     a1,  a1, XT_STK_FRMSZ              // set up SP for dispatch exit
+
+.Lnested:
+    // Return to the current saved context.
+
+    .endm
+
+#endif /* __ASSEMBLER__ */
+#endif /* XCHAL_HAVE_XEA3 */
+
+#endif /* XTENSA_CONTEXT_H */
+
diff --git a/ports/xtensa/xcc/inc/xtensa_rtos.h b/ports/xtensa/xcc/inc/xtensa_rtos.h
new file mode 100644
index 00000000..03db1849
--- /dev/null
+++ b/ports/xtensa/xcc/inc/xtensa_rtos.h
@@ -0,0 +1,204 @@
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************
+
+    RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
+
+    This header is the primary glue between generic Xtensa RTOS support
+    sources and a specific RTOS port for Xtensa.  It contains definitions
+    and macros for use primarily by Xtensa assembly coded source files.
+
+    Macros in this header map callouts from generic Xtensa files to specific
+    RTOS functions. It may also be included in C source files.
+
+    Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 
+    architecture, using the Xtensa hardware abstraction layer (HAL) to deal 
+    with configuration specifics.
+
+    Should be included by all Xtensa generic and RTOS port-specific sources.
+
+***************************************************************************/
+
+#ifndef XTENSA_RTOS_H
+#define XTENSA_RTOS_H
+
+#ifdef __ASSEMBLER__
+#include    <xtensa/coreasm.h>
+#else
+#include    <stdint.h>
+#include    <xtensa/config/core.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+#include    <xtensa/simcall.h>
+
+/*
+Include any RTOS specific definitions that are needed by this header.
+*/
+#include "tx_user.h"
+
+/*
+Name of RTOS (for messages).
+*/
+#define XT_RTOS_NAME    ThreadX
+
+/*
+Check some Xtensa configuration requirements and report error if not met.
+Error messages can be customize to the RTOS port.
+*/
+
+#if !XCHAL_HAVE_XEA2 && !XCHAL_HAVE_XEA3
+#error "ThreadX/Xtensa requires Xtensa Exception Architecture v2 (XEA2) or higher."
+#endif
+
+
+/***************************************************************************
+
+RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+
+Define callout macros used in generic Xtensa code to interact with the RTOS.
+The macros are simply the function names for use in calls from assembler code.
+Some of these functions may call back to generic functions in xtensa_context.h .
+
+***************************************************************************/
+
+/*
+Inform RTOS of entry into an interrupt handler that will affect it. 
+Allows RTOS to manage switch to any system stack and count nesting level.
+Called after minimal context has been saved, with interrupts disabled.
+RTOS port can call0 _xt_context_save to save the rest of the context.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_ENTER(void)
+#define XT_RTOS_INT_ENTER   _tx_thread_context_save
+
+/*
+Inform RTOS of completion of an interrupt handler, and give control to
+RTOS to perform thread/task scheduling, switch back from any system stack
+and restore the context, and return to the exit dispatcher saved in the
+stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+leaving only a minimal part of the context to be restored by the exit
+dispatcher. This function does not return to the place it was called from.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_EXIT(void)
+#define XT_RTOS_INT_EXIT    _tx_thread_context_restore
+
+/*
+Convenience macros to disable and enable interrupts.
+*/
+#if XCHAL_HAVE_XEA3
+#define XT_INTS_DISABLE(reg)    movi reg, PS_DI; xps  reg, reg
+#define XT_INTS_ENABLE(reg)     wsr  reg, PS; rsync
+#else
+#define XT_INTS_DISABLE(reg)    rsil reg, XCHAL_EXCM_LEVEL
+#define XT_INTS_ENABLE(reg)     wsr  reg, PS; rsync
+#endif
+
+/*
+Inform RTOS of the occurrence of a tick timer interrupt.
+If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+May be coded in or called from C or assembly, per ABI conventions.
+*/
+#ifndef TX_NO_TIMER
+// void XT_RTOS_TIMER_INT(void)
+#define XT_RTOS_TIMER_INT   _tx_timer_interrupt
+#endif
+
+/*
+Return in a15 the base address of the co-processor state save area for the 
+thread that triggered a co-processor exception, or 0 if no thread was running.
+The state save area is structured as defined in xtensa_context.h and has size 
+XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+in interrupt handlers or the RTOS kernel. May only be called from assembly code
+and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 
+The implementation may use only a2-4, a15 (all other regs must be preserved).
+*/
+// void* XT_RTOS_CP_STATE(void)
+#define XT_RTOS_CP_STATE    _tx_thread_coproc_state
+
+
+/***************************************************************************
+
+HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+
+This Xtensa RTOS port provides hooks for dynamically installing exception
+and interrupt handlers to facilitate automated testing where each test
+case can install its own handler for user exceptions and each interrupt
+priority (level). This consists of an array of function pointers indexed
+by interrupt priority, with index 0 being the user exception handler hook.
+Each entry in the array is initially 0, and may be replaced by a function 
+pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+
+The handler for low and medium priority obeys ABI conventions so may be coded
+in C. For the exception handler, the cause is the contents of the EXCCAUSE
+reg, and the result is -1 if handled, else the cause (still needs handling).
+For interrupt handlers, the cause is a mask of pending enabled interrupts at
+that level, and the result is the same mask with the bits for the handled
+interrupts cleared (those not cleared still need handling). This allows a test
+case to either pre-handle or override the default handling for the exception
+or interrupt level (see xtensa_vectors.S).
+
+High priority handlers (including NMI) must be coded in assembly, are always
+called by 'call0' regardless of ABI, must preserve all registers except a0,
+and must not use or modify the interrupted stack. The hook argument 'cause'
+is not passed and the result is ignored, so as not to burden the caller with
+saving and restoring a2 (it assumes only one interrupt per level - see the
+discussion in high priority interrupts in xtensa_vectors.S). The handler
+therefore should be coded to prototype 'void h(void)' even though it plugs
+into an array of handlers of prototype 'uint32_t h(uint32_t)'.
+
+To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+
+***************************************************************************/
+
+#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
+
+#ifndef __ASSEMBLER__
+typedef uint32_t (*XT_INTEXC_HOOK)(uint32_t cause);
+extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
+#endif
+
+
+/***************************************************************************
+
+CONVENIENCE INCLUSIONS.
+
+Ensures RTOS specific files need only include this one Xtensa-generic header.
+These headers are included last so they can use the RTOS definitions above.
+
+***************************************************************************/
+
+#include    "xtensa_context.h"
+
+#ifdef XT_RTOS_TIMER_INT
+#include    "xtensa_timer.h"
+#endif
+
+
+#endif /* XTENSA_RTOS_H */
+
diff --git a/ports/xtensa/xcc/inc/xtensa_timer.h b/ports/xtensa/xcc/inc/xtensa_timer.h
new file mode 100644
index 00000000..d5a29ed5
--- /dev/null
+++ b/ports/xtensa/xcc/inc/xtensa_timer.h
@@ -0,0 +1,157 @@
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************
+    XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
+
+    This header contains timer related definitions and macros for use by
+    Xtensa RTOS source files. It includes and uses the Xtensa hardware
+    abstraction layer (HAL) to deal with config specifics.
+
+    If the RTOS has no timer interrupt, then there is no tick timer and the
+    clock frequency is irrelevant, so all of these macros are left undefined
+    and the Xtensa core configuration need not have a timer.
+***************************************************************************/
+
+#ifndef XTENSA_TIMER_H
+#define XTENSA_TIMER_H
+
+#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
+
+#ifdef XT_RTOS_TIMER_INT        /* skip all this stuff if no timer int */
+
+#ifdef __ASSEMBLER__
+#include    <xtensa/coreasm.h>
+#else
+#include    <xtensa/tie/xt_timer.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+
+#if XCHAL_HAVE_XEA3
+
+/*
+If the user has not specified a timer by defining XT_TIMER_INDEX, then
+select timer 0.
+*/
+#ifndef XT_TIMER_INDEX
+#define XT_TIMER_INDEX    0
+#endif
+
+#else /* XEA2 */
+
+/*
+Select timer to use for periodic tick, and determine its interrupt number 
+and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+in which case its validity is checked (it must exist in this core and must 
+not be on a high priority interrupt - an error will be reported in invalid).
+Otherwise select the first low or medium priority interrupt timer available.
+*/  
+#ifndef XT_TIMER_INDEX
+  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    3
+    #endif
+  #endif
+  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    2
+    #endif
+  #endif
+  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    1
+    #endif
+  #endif
+  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    0
+    #endif
+  #endif
+#endif
+
+#endif /* XCHAL_HAVE_XEA3 */
+
+#ifndef XT_TIMER_INDEX
+  #error "There is no suitable timer in this Xtensa configuration."
+#endif
+
+#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
+#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
+#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
+
+#if XCHAL_HAVE_XEA2
+#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
+#endif
+
+#if XT_TIMER_INDEX == 0
+#define XT_WSR_CCOMPARE         XT_WSR_CCOMPARE0
+#elif XT_TIMER_INDEX == 1
+#define XT_WSR_CCOMPARE         XT_WSR_CCOMPARE1
+#elif XT_TIMER_INDEX == 2
+#define XT_WSR_CCOMPARE         XT_WSR_CCOMPARE2
+#endif
+
+#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+#elif !XCHAL_HAVE_XEA3 && (XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL)
+  #error "The timer interrupt cannot be high priority (use medium or low)."
+#endif
+
+/*
+Default number of timer ticks per second. This can be redefined as required
+either by editing here or by overriding from the command line during build.
+*/
+#ifndef XT_TICK_PER_SEC
+#define XT_TICK_PER_SEC     100
+#endif
+
+/*
+Set processor clock frequency and determine clock divisor for timer tick.
+If using a supported board via the board-independent API defined in xtbsp.h,
+this may be left undefined but XT_BOARD must be defined. The frequency and
+tick divisor will be computed during run-time initialization.
+*/
+#ifndef XT_BOARD
+#ifndef XT_CLOCK_FREQ
+#define XT_CLOCK_FREQ       1000000
+#endif
+#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
+#else
+#ifndef __ASSEMBLER__
+extern uint32_t xt_tick_divisor;
+extern void     xt_tick_divisor_init(void);
+#endif
+#define XT_TICK_DIVISOR     xt_tick_divisor
+#endif  /* XT_BOARD */
+
+#endif  /* XT_RTOS_TIMER_INT */
+#endif  /* XTENSA_TIMER_H */
+
diff --git a/ports/xtensa/xcc/readme_threadx.txt b/ports/xtensa/xcc/readme_threadx.txt
new file mode 100644
index 00000000..90fc92d7
--- /dev/null
+++ b/ports/xtensa/xcc/readme_threadx.txt
@@ -0,0 +1,1015 @@
+           Microsoft's ThreadX for Xtensa Configurable Processors
+
+                            Using the Xtensa Tools
+
+1.  Xtensa Configuration Requirements and Restrictions
+
+The Xtensa configurable architecture supports a vast space of processor
+features. This port of ThreadX to the Xtensa architecture is based on
+a Cadence Design Systems RTOS porting layer that takes care of Xtensa specifics 
+that are common to most embedded real-time operating systems. It supports all
+Xtensa features (including context-switching custom processor extensions
+defined in the TIE language) with certain minimum requirements. You
+must use Xtensa Tools to compile and link ThreadX for your particular
+configuration. ThreadX uses the Xtensa Hardware Abstraction Layer (HAL)
+to adapt your ThreadX compilation to your particular Xtensa processor
+configuration. ThreadX also provides optional thread-safe support for
+the Xtensa C library and the newlib C library distributed with Xtensa Tools
+(for use in threads only, not in interrupt handlers).
+
+ThreadX for Xtensa configurable processors requires the following minimum 
+processor configuration options:
+- Timer interrupt option with at least one interruptible timer for ThreadX.
+- Interrupt option (implied by the timer interrupt option).
+- Xtensa Exception Architecture 2 (XEA2) or Exception Architecture 3 (XEA3).
+  Please note that XEA1 is NOT supported.
+
+Minimal support for certain evaluation boards is provided via a board
+independent "XTBSP" API implemented by a board specific library. This
+provides the board clock frequency and basic polled drivers for the display
+and console I/O device (usually a UART), and ThreadX can be built to
+take advantage of these (note: it is not specific to ThreadX and is not a
+traditional RTOS "board support package" with RTOS specific interrupt-driven
+drivers). Note that ThreadX can run on any Xtensa board without
+this board support (a "raw" platform), but you will have to provide the
+clock frequency and drivers for any on-board devices you want to use.
+
+
+2.  Building the ThreadX run-time Library
+
+By default, you will build for the Xtensa instruction set simulator. If
+you have a supported emulation board, you can build to run on that. You
+can also build to run on a raw Xtensa core with no "board support", a
+good starting point for supporting your own target platform. Cadence Design Systems
+recommends doing functional development on the simulator because it
+is easier to debug with, then move to a board if/when you need to test
+hardware drivers or real-time performance.
+
+ThreadX/Xtensa comes with a Makefile as well as DOS .bat file, taking
+advantage of xt-make, a version of GNU make that comes with Xtensa Tools
+(you can just as well use generic GNU make if you have it installed).
+The Makefile works on any host platform and provides for incremental builds.
+The .bat file works on DOS/Windows only and always cleans before building.
+The build for each target platform is placed in a sub-directory so several
+platform builds can coexist even with incremental rebuilds.
+
+First, make sure you have installed Xtensa Tools and your processor
+configuration, and be sure that Xtensa Tools are in your search path.
+
+If you wish to build for an evaluation board that is supported by an
+external package, be sure the appropriate package is installed. See the
+introduction (section 0) to determine if you need an external package.
+If you are using an external board package, set the environment variable
+XTENSA_BOARDS to the absolute path of the root of the installed support 
+package (or you can pass this to xt-make commands on the command line).
+eg. XTENSA_BOARDS = C:\usr\xtensa\RB-2007.1-xtav60 for Avnet LX60 board.
+You do not need to set XTENSA_BOARDS if using a Cadence Design Systems supported 
+board with Xtensa Tools RB-2007.2 and up (support is bundled with the tools).
+
+Next, change directories to the ThreadX installation directory, as follows:
+
+> cd c:\threadx\xtensa\gnu
+
+Now build the ThreadX library (tx.a) by executing the build_threadx.bat
+batch file (or using the Makefile directly) while inside the threadx
+directory, as follows:
+
+> build_threadx.bat
+
+which always builds for the simulator (but you can edit it), or
+
+> xt-make
+
+which by default builds for the simulator (PLATFORM=sim), or either of
+
+> xt-make PLATFORM=board BOARD=<board>
+or
+> xt-make BOARD=<board>
+
+which builds for a specified supported board (note PLATFORM=board is
+default when BOARD is defined). eg. BOARD=xtav60 for the Avnet LX60
+(XT-AV60) board.
+
+> xt-make PLATFORM=raw
+ 
+which builds for a raw Xtensa core with no "board support".
+
+> xt-make PLATFORM=gdbio
+
+Provides some very slow I/O support through the xt-gdb debugger.
+For GDBIO to work, xt-gdb must remain connected to the target.
+
+If you are building for an Xtensa processor configuration that is not the
+default you selected when you installed Xtensa Tools, you need to define the 
+environment variable XTENSA_CORE. If your configuration is not in the 
+default registry you selected when you installed Xtensa Tools, you also
+need to define the environment variable XTENSA_SYSTEM. See tools manuals.
+You can avoid defining these in your environment if you pass the variables 
+you need to redefine into xt-make as follows:
+
+> xt-make XTENSA_CORE=<your_config_name> XTENSA_SYSTEM=<your_registry> ...
+
+There are more details about build options in the comment in the Makefile.
+
+At this point, all the ThreadX objects are located in a library file: tx.a .
+This file must be linked with your application in order to use ThreadX.
+This library and all the intermediate object files are placed in a platform
+specific sub-directory named the same as BOARD or PLATFORM (if BOARD is not
+defined), for example "sim", "xtkc705".
+
+To build ThreadX with thread-safe C library support, define TX_THREAD_SAFE_CLIB
+in your build, as described in section 5 and in the Makefile. Please note
+that the C library is only safe for use in threads, not in interrupt handlers.
+It may also safely be used in tx_application_define (after tx_kernel_enter, 
+before threads are running).
+
+
+3.  Demonstration System
+
+The ThreadX demonstration is designed to execute under Xtensa instruction set
+simulator (ISS) or on a supported evaluation board programmed with your Xtensa
+processor configuration.
+
+Building the demonstration is easy, simply execute the build_threadx_demo.bat 
+batch file while inside threadx directory, as follows:
+
+> build_threadx_demo.bat 
+
+or
+
+> xt-make demo
+
+Be sure to set or pass into xt-make the variables described in section 2 above
+for building the ThreadX library, including the PLATFORM or BOARD you want to
+run on.
+
+This compiles demo_threadx.c (which is the demonstration application) and links 
+it with the ThreadX objects in tx.a. The resulting file demo_threadx.out is a 
+ELF binary file that can be downloaded and executed on the target.
+
+The demo binary appears in the platform specific sub-directory described earlier.
+For the following commands, change to that directory or prepend it as the path
+of demo_threadx.out.
+
+
+To execute on the simulator:
+
+> xt-run [--turbo] demo_threadx.out
+
+The option --turbo provides much faster, but non-cycle-accurate simulation.
+Refer to the Xtensa simulator user manual for further simulator options.
+
+
+To execute on the simulator using the Xplorer GUI based debugger:
+
+> xplorer --debug demo_threadx.out
+
+
+To execute on a supported evaluation board, download demo_threadx.out per
+instructions in the tools manuals. Be sure the board has been programmed
+with the correct configuration and is set up to boot from RAM and debug
+a downloaded program!  Optionally you may connect a terminal or terminal
+emulator to the serial port on the board with settings as described in
+the board user manual, and see the output of printf on the terminal (if
+the demo was compiled with DEMO_USE_PRINTF or DEMO_USE_XTUTIL).
+
+To obtain I/O on a "raw" platform such as an unsupported board, you need
+to provide low level I/O drivers (eg. inbyte() and outbyte() for character
+I/O if you want to use printf etc.).  You can run "raw" executables on
+any Xtensa platform, including simulator and any board, but you will not
+see any behavior specific to the platform (eg. display, printed output,
+stopping simulation at end of program). You can, while debugging, use a
+debugger mechanism called GDBIO to obtain basic I/O. Use PLATFORM=GDBIO
+on your xt-make command line - this is the same as "raw" except it links
+some stubs that communicate through the debugger. It is very slow!
+
+WARNING: It is tempting to add printf calls to other threads in the demo.
+If you modify the code in any way, you may need adjust affected threads' 
+stack sizes. This is especially true if you add a printf call. See 4.5.
+
+
+4.  System Initialization
+
+4.1 ThreadX Kernel
+
+ThreadX uses the reset vector and low level initialization from the Xtensa
+libraries provided by the linker support package (LSP). It does not provide
+its own reset vector (which would have to be maintained with tools upgrades).
+
+ThreadX is initialized by tx_kernel_enter which is usually called from
+main. The primary initialization function is _tx_initialize_low_level
+and is located in the file tx_initialize_low_level.c. This function is
+responsible for setting up various system data structures. Interrupt and
+exception vectors are linked into your program and installed at load time
+(they are not dynamically installed). The interrupt and exception vectors
+for the ThreadX Xtensa port are defined in xtensa_vectors.S (for XEA2) and
+xtensa_vectors_xea3.S (for XEA3).
+
+4.2 Memory Allocation
+
+In addition, _tx_initialize_low_level also determines the first available 
+address for use by the application. By default, the first available address 
+is assumed to be above all linker-allocated sections at symbol _end. This 
+is passed to the application definition function, tx_application_define.
+This is a convenience to the application developer. Ultimately the developer
+has full control over memory allocation and can choose to use this or not.
+The top of available memory is not provided and should be obtained from the
+tools if needed.
+
+4.3 Location and Extent of System (Interrupt) Stack
+
+ThreadX/Xtensa supports a user-definable system stack. By default, the
+top of the system stack is defined by the symbol _xt_interrupt_stack_top.
+See the file xtensa_intr_asm.S for the default system stack definition.
+This stack may be resized and/or relocated according to the application
+needs. The application developer must ensure that the system stack is
+sized appropriately for the application. All interrupts handled by 
+ThreadX will use the system stack. Handlers written in assembly must
+not switch to the system stack, since it will not be possible to detect
+whether the stack is currently in use.
+
+The macro TX_SYSTEM_STACK_SIZE defines the size of the system stack.
+As a convenience, a macro TX_MINIMUM_STACK_SYSTEM is provided with the
+minimum size required for the system stack. This is based on the maximum
+possible interrupt nesting level per the Xtensa processor configuration,
+assuming very simple C handlers that do not call deeper than one or two 
+levels.  If the application uses more complex handlers, it will be
+necessary to add to this value (accounting for nesting) to determine 
+the space required for the system stack.
+
+4.4 Location and Extent of C Library Heap
+
+If the optional thread-safe support for the C library is used, memory
+for the heap is allocated like this: by default, half the space between
+the first available memory address and the end of system memory is
+made available to the heap.
+
+The heap location and limit are available in two global variables, and 
+can be fully customized in tx_application_define by assigning to them:
+
+    _tx_clib_heap_start     Base address of heap.
+    _tx_clib_heap_end       Upper limit address to which heap can grow.
+
+This must be done BEFORE any C library calls. It is advised that it be
+done at the beginning of tx_application_define.
+
+Please note that when the thread-safe C library support is used, the heap
+is not initialized before tx_kernel_enter has been called, so malloc will 
+fail. It is recommended to avoid C library calls that use the heap (such
+as printf) outside of ThreadX (eg. in main). The C library is NOT safe 
+for use in interrupt or exception handlers, so this should be avoided.
+
+4.5 Thread Stack Sizes
+
+The application must ensure that every thread has enough space for its
+stack. This must account for the deepest call depth and allow for one
+interrupt stack frame as defined in xtensa_context.h . Several factors
+influence the size of the stack required, including compiler optimization
+level (-O0 is worst), use of TX_ENABLE_STACK_CHECKING option, and of 
+course your Xtensa configuration. Some stack size guidelines and macros 
+are provided in tx_port.h assuming no optimization (default, -O0).
+
+Threads that call C library functions may need larger stacks than those
+that don't. In particular, use of printf requires a very large stack and
+will usually cause a stack overflow if inserted in a thread without 
+enlarging its stack size. See DEMO_STACK_SIZE_PRINTF in demo_threadx.c
+for a guideline. Use printf with care!
+
+
+5.  Assembler / Compiler Switches
+
+The following are compiler switches used in building the ThreadX library
+and demonstration system. These can be supplied by editing the Makefile
+or by overriding the COPT or CFLAGS variables in the make command line
+(eg. make COPT="-O2 -DTX_THREAD_SAFE_CLIB"). More details in Makefile.
+
+Compiler Switch                 Meaning
+
+    -g                      Specifies debug information.
+    -c                      Specifies object code generation.
+    -On                     Sets compiler optimization level n (default -O0).
+    -mlongcalls             Allows assembler and linker to convert call 
+                            instructions to longer indirect call sequences 
+                            when target is out of range.
+    -x assembler-with-cpp   Passes .s and .S files through C preprocessor.
+    -Dmacro                 Define a preprocessor macro with no value.
+    -Dmacro=value           Define a preprocessor macro with a value.
+
+Application Defines (preprocessor macros definable with the -D option):
+
+    TX_THREAD_SAFE_CLIB     Enable support for thread-safe C library.
+                            Only the Xtensa C library and the newlib library
+                            are supported for thread-safe operation.
+                            When this is enabled, half the available memory 
+                            space is allocated by default, below the system 
+                            stack, for the heap. The heap size and location 
+                            can be customized in tx_application_define.
+                            Default off.
+
+    NOTE: Thread safe support for Xtensa C library requires Xtensa Tools
+          version RF-2015.2 or later.
+
+    TX_ENABLE_STACK_CHECKING Enable generic ThreadX support for stack 
+                            overflow checking. This can help avoid long
+                            debugging sessions or customer support calls
+                            by identifying many crashes caused by stack
+                            overflow. Use of this option adds a small
+                            premium to the required thread stack sizes
+                            (the premium is included by the stack size
+                            convenience macros defined in tx_port.h).
+
+    TX_NO_TIMER             Enable generic ThreadX footprint reduction when
+                            no periodic tick is needed. The Xtensa port also
+                            reduces footprint by removing all code related
+                            to timer interrupts. Related XT_* options below
+                            (XT_CLOCK_FREQ, XT_TICK_PER_SEC, XT_TIMER_INDEX)
+                            have no effect under TX_NO_TIMER.
+
+    All generic ThreadX options in tx_user.h may also be defined with -D.
+
+    Note, the above defines are not specific to Xtensa processors, so 
+    their names begin with "TX_". Defines below are unique to the Xtensa
+    port so have names beginning with "XT_".
+
+    XT_SIMULATOR            Set this if building to run on the simulator.
+                            Takes advantage of certain simulator control
+                            and reporting facilities, and adjusts timing 
+                            of periodic tick to provide a more acceptable
+                            performance in simulation (see XT_CLOCK_FREQ).
+                            Set by default unless PLATFORM is overridden.
+
+    XT_BOARD=board          Set this if building for a supported board.
+                            The value should be the identifier of a board
+                            supported in the Xtensa Tools or an external
+                            package (eg. XT_BOARD=xtkc705 for the Xilinx
+                            KC705 board). If the board is supported by an
+                            external package, the variable XTENSA_BOARDS
+                            should point to the root of the package. Set by
+                            provided Makefile when PLATFORM=board and BOARD
+                            is defined (eg. PLATFORM=board BOARD=xtkc705).
+
+    XT_CLOCK_FREQ=freq      Specifies the target processor's clock 
+                            frequency in Hz. Used primarily to set the 
+                            timer that generates the periodic interrupt.
+                            Defaults are provided and may be edited in
+                            xtensa_timer.h (see comments there also).
+                            Default for simulator provides more acceptable
+                            performance, but cannot provide real-time
+                            performance due to variation in simulation
+                            speed per host platform and insufficient 
+                            cycles between interrupts to process them.
+                            Supported board platforms by default leave 
+                            this undefined and compute the clock frequency 
+                            at initialization unless this is explicitly 
+                            defined.
+
+    XT_TICK_PER_SEC=n       Specifies the frequency of the periodic tick.
+
+    XT_TIMER_INDEX=n        Specifies which timer to use for ThreadX.
+                            Set this if your Xtensa processor configuration 
+                            provides more than one suitable timer and you 
+                            want to override the default. See xtensa_timer.h.
+
+    XT_INTEXC_HOOKS         Enables hooks in interrupt vector handlers
+                            to support dynamic installation of exception
+                            and interrupt handlers. Used by automatic 
+                            regression test programs. Disabled by default.
+                            
+    XT_USE_OVLY             Enable code overlay support.
+
+    XT_USE_SWPRI            Enable software prioritization of interrupts.
+                            Enabling this will prioritize interrupts with
+                            higher bit numbers over those with lower bit
+                            numbers at the same level. This works only for
+                            low and medium priority interrupts that can be
+                            dispatched to C handlers.
+
+    TX_SYSTEM_STACK_SIZE=n  Specify the size of the interrupt stack, which
+                            is the stack that all interrupt handlers switch
+                            to while handling interrupts. See the section
+                            describing the interrupt stack for more details.
+
+
+6.  Register Usage and Stack Frames
+
+The Xtensa architecture specifies two ABIs that determine how the general
+purpose registers a0-a15 are used: the windowed ABI, and the Call0 ABI.
+The choice of ABI is made when configuring the processor or its associated
+software. Xtensa processors may have other special registers (including
+coprocessor registers and other TIE "states") that are independent of this
+choice of ABI. See Xtensa documentation for more details.
+
+In the windowed ABI the registers of the current window are used as follows:
+    a0      = return address
+    a1      = stack pointer (alias sp)
+    a2      = first argument and result of call (in simple cases)
+    a3-7    = second through sixth arguments of call (in simple cases).
+              Note that complex or large arguments are passed on the
+              stack. Details are in the Xtensa Tools manuals.
+    a8-a15  = available for use as temporaries.
+
+There are no callee-save registers. The windowed hardware automatically
+saves registers a0-a3 on a call4, a0-a8 on a call8, a0-a12 on a call12,
+by rotating the register window. Hardware triggers window overflow and
+underflow exceptions as necessary when registers outside the current 
+window need to be spilled to preallocated space in the stack frame, or
+restored. Complete details are in the Xtensa manuals. The entire windowed
+register file is saved and restored on interrupt or thread context switch.
+Note that only call0 and call8 are available in XEA3 Windowed ABI.
+
+The Call0 ABI does not make use of register windows, relying instead
+on a fixed set of 16 registers without window rotation.
+The Call0 ABI is more conventional and uses registers as follows:
+    a0      = return address
+    a1      = stack pointer (alias sp)
+    a2      = first argument and result of call (in simple cases)
+    a3-7    = second through sixth arguments of call (in simple cases).
+              Note that complex or large arguments are passed on the
+              stack. Details are in the Xtensa Tools manuals.
+    a8-a11  = scratch.
+    a12-a15 = callee-save (a function must preserve these for its caller).
+
+On a ThreadX API call, callee-save registers are saved only when a thread
+context switch occurs, and other registers are not saved at all (the caller
+does not expect them to be preserved). On an interrupt, callee-saved
+registers might only be saved and restored when a thread context-switch
+occurs, but all other registers are always saved and restored.
+
+An Xtensa processor has other special registers independent of the ABI,
+depending on the configuration (including coprocessor registers and other
+TIE state) that are part of the thread context. ThreadX preserves all such
+registers over an unsolicited context-switch triggered by an interrupt
+(including time-slice expiry). However it does NOT preserve these over
+a solicited context-switch during a ThreadX API call. This bears some
+explanation. These special registers are either ignored by the compiler
+or treated as caller-saved, meaning that if kept "live" over a function
+call (ie. need to be preserved) they must be saved and restored by the
+caller. Since solicited entry to ThreadX is always made by a function
+call, ThreadX assumes the caller has saved any of these registers that are
+"live". ThreadX avoids a lot of overhead by not having to save and restore
+every special register (there can be many) on every solicited context switch.
+
+As a consequence, the application developer should NOT assume that special
+registers are preserved over a ThreadX API call such as tx_thread_sleep.
+If multiple threads use a register, the caller must save and restore it.
+
+The saved context stack frames for context switches that occur as a result 
+of interrupt handling (interrupt frame) or from thread-level API calls 
+(solicited frame) are described in human readable form in xtensa_context.h .
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD. An Xtensa architecture port-specific
+extension to the thread control block tx_thread_solicited contains 1 for a
+thread that is currently suspended from an API call, otherwise contains 0.
+
+
+7.  Improving Performance, Footprint, or Ease of Debugging
+
+The distribution version of ThreadX is built with debug (-g) and without
+compiler optimizations (-O0). This makes debugging easier inside ThreadX
+itself. Of course, -O0 costs some performance. To make ThreadX run faster,
+you can change the Makefile to enable the desired optimizations or set
+a predefined optimization level (-O<level>) .
+
+Maximum performance is achieved with -O3, but that might increase footprint
+substantially. A good compromise is -O2. If code size is a concern, -Os may
+yield better results. See the compiler manual for details.
+
+You can eliminate the ThreadX basic API error checking by compiling your
+application code with the symbol TX_DISABLE_ERROR_CHECKING defined before
+tx_api.h is included. 
+
+The Xtensa architecture port-specific assembly files are coded with no
+file-scope labels inside functions (all labels inside functions begin with
+".L"). This allows a profiler to accurately associate an address with a
+function, and also allows the debugger's stack trace to show the correct
+function wherever the program counter is within that function. However
+there are some tradeoffs in debugging. Local (".L") labels are not
+visible to the debugger, so the following limitations may be observed
+during debugging:
+- You cannot set a breakpoint on a local label inside a function.
+- Disassembly will show the entire function, but will get out of sync and
+  show incorrect opcodes if it crosses any padding before an aligned local
+  branch target (".L" label, not ".Ln"). Restart disassembly specifying an
+  address range explicitly between points where there is padding.
+Since ThreadX is provided in source form, it is not difficult to remove
+the ".L" and ".Ln" prefixes from local labels if you want them visible.
+They can also be made visible by passing the '-L' option to the assembler
+and linker (see the assembler and linker manuals for details).
+
+
+8.  Interrupt and Exception Handling
+
+NOTE: The material in this section is mostly an overview. For a more
+detailed explanation please refer to the Xtensa ISA manual and the System
+Software manual.
+
+ThreadX provides a complete set of efficient exception and first-level
+interrupt handlers installed at the appropriate exception and interrupt
+vector locations. The XEA2 architecture supports several different
+classes of exceptions and interrupts. Being a configurable architecture,
+many of these are optional, and the vector locations are determined by
+your processor configuration. The handlers provided use conditional
+compilation to adapt to your processor configuration and include only 
+the code that is needed.
+
+Xtensa vector locations may reside almost anywhere, including in ROM.
+And the amount of code space available at each of these locations is
+often very small (e.g. due to following vectors). A small stub of code
+installed at the vector jumps to the corresponding handler, usually in RAM.
+The exception and interrupt handlers are defined in xtensa_vectors.S .
+They are not specific to ThreadX, but call into ThreadX where appropriate
+via macros defined in xtensa_rtos.h .
+
+Interrupt/Exception Handling in XEA2
+------------------------------------
+
+The handlers provided for low and medium priority interrupts are just
+dispatchers that save relevant state and call user-definable handlers.
+See the files xtensa_vectors.S and xtensa_api.h for more details of how
+to create and install application-specific user interrupt handlers.
+Similarly, user-defined handlers can be installed for exceptions (other
+than a few which are always handled by the OS).
+
+The high priority interrupt handlers provided may be considered templates
+into which the application adds code to service specific interrupts.
+The places where application handlers should be inserted are tagged with
+the comment "USER_EDIT" in xtensa_vectors.S.
+
+This ThreadX port supports strict priority-based nesting of interrupts.
+An interrupt may only nest on top of one of strictly lower priority.
+Equal priority interrupts concurrently pending are handled in an
+application-defined sequence before any lower priority interrupts
+are handled. During interrupt and exception handling, the processor's
+interrupt level (PS.INTLEVEL) is used to control the interrupt priority
+level that can be accepted; interrupt sources are not controlled
+individually by ThreadX (the application is free to access the INTENABLE
+register directly to enable/disable individual interrupts, e.g. using
+Xtensa HAL services). This approach provides the most deterministic
+bounds on interrupt latency (for a given priority) and system stack depth.
+
+Software prioritization of interrupts at the same priority is controlled
+by the definition of XT_USE_SWPRI. See above for a description of this
+parameter.
+
+Interrupt and Exception Handling in XEA3
+----------------------------------------
+
+In XEA3 no distinction is made between low, medium and high priority interrupt
+levels. Interrupts at all levels up to the highest (NMI) level can be dispatched
+to handlers written in C. Interrupts are dispatched by the XEA3 dispatcher and
+the handlers are found from a handler table. Handlers are installed into the
+handler table by calling xt_set_interrupt_handler. As there is no concept of
+a high priority interrupt any longer, handlers can only be specified per
+interrupt, not per level. Since all levels can be handled in C, the value of
+EXCM_LEVEL is set to the highest possible level (NMI level).
+Software prioritization is not available for XEA3.
+
+
+The following subsections describe the handling of each class of exception
+and interrupt in more detail. Many have nothing to do with ThreadX but are
+mentioned because there is code to handle them in xtensa_vectors.S.
+
+8.1 User Exception and Interrupt Handler (Low/Medium Priority)
+
+    All Xtensa 'general exceptions' come to the user, kernel, or double
+    exception vector.  The exception type is identified by the EXCCAUSE
+    special register (level 1 interrupts are one particular cause of a
+    general exception). This port sets up PS to direct all such exceptions
+    to the user vector. Exceptions taken at the other two vectors usually
+    indicate a kernel or application bug.
+
+    In XEA3, everything except a double exception will come to a common
+    vector. This vector saves the requisite processor state and then checks
+    for the highest priority interrupt to dispatch. If no interrupts are
+    pending then a check is made for exceptions.
+
+    Level 1 interrupts are identified at the beginning of the handler
+    and are dispatched to a dedicated handler. Then, syscall and alloca
+    exceptions are identified and dispatched to special handlers described
+    below. After this, coprocessor exceptions are identified and dispatched
+    to the coprocessor handler.
+
+    Any remaining exceptions are processed as follows:
+
+    Having allocated the exception stack frame, the user exception handler
+    calls _tx_thread_context_save, which saves the rest of the interrupt
+    context. After this the handler sets up a C environment and enables
+    the high-priority class of interrupts (which do not interact with
+    ThreadX), then reads EXCCAUSE and uses the cause (number) to index 
+    into a table of user-specified handlers. The correct handler is then
+    called. If the handler returns, the context is restored and control
+    is returned to the code that caused the exception. The user-defined
+    handler may alter the saved context, or any other system state, that
+    allows the faulting instruction to be retried.
+
+    If the cause is a level 1 (low-priority) or medium-priority interrupt,
+    the handler enables all interrupts above that priority level after
+    saving the thread context and switching to the interrupt stack if it
+    is not a nested interrupt. It then sets up the environment for C code
+    and then calls the handler (found in the handler table) for the 
+    interrupt number. If the user has not specified a handler, then the
+    default handler will be called, which will terminate the program.
+
+    If the interrupt is for the system timer, it calls a special interrupt
+    handler for the system timer tick, which calls _tx_timer_interrupt then
+    clears its bit from the mask. This interrupt cannot be hooked by the
+    user-defined handler.
+
+    Finally, the handler calls _tx_thread_context_restore to allow ThreadX
+    to perform any scheduling necessary and return either to the interrupted
+    thread or another.
+
+    If software prioritization is enabled, the handler will re-enable all
+    interrupts at the same level that are numerically higher than the current
+    one, before calling the user handler. This allows a higher priority
+    interrupt to pre-empt the lower priority handler.
+
+8.2 Medium Priority Interrupt Handlers (XEA2)
+
+    Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL, 
+    a configuration-specific maximum interrupt level affected by the global 
+    'exception mode' bit in the processor status word (PS.EXCM).
+    Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class.
+    The Xtensa hardware documentation considers medium priority interrupts
+    to be a special case of high-priority interrupts, but from a software
+    perspective they are very different.
+
+    Dispatch of medium-priority interrupts is discussed in the section
+    above.
+
+8.3 High Priority Interrupt Handlers (XEA2)
+
+    High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, 
+    a configuration-specific maximum interrupt level affected by the 
+    global 'exception mode' bit in the processor status word (PS.EXCM).
+    High priority handlers may not directly interact with ThreadX at all,
+    and are described here only for the sake of completeness. They must
+    be coded in assembler (may not be coded in C) and are intended to be 
+    used for handling extremely high frequency hardware events that need
+    to be handled in only a few cycles. A high priority interrupt handler
+    may trigger a software interrupt at a medium or low priority level to
+    occasionally signal ThreadX. Please see Xtensa documentation.
+
+    There is a separate vector and a few special registers for each high
+    priority interrupt, providing for fast dispatch and efficient nesting
+    on top of lower priority interrupts. Handlers are templates included
+    only for the vectors that exist in your Xtensa processor configuration.
+    These templates are written for only one interrupt per high priority 
+    level to minimize latency servicing very fast time-critical interrupts.
+    The vector code jumps to the corresponding first-level interrupt handler,
+    which then executes application-provided assembler code before returning
+    quickly to the interrupted thread or lower priority handler.
+
+8.4 Kernel Exception Handler (XEA2)
+
+    Kernel mode is not used in this port of ThreadX, and therefore kernel
+    exceptions should not happen. A stub is provided for the vector that
+    triggers the debugger (if connected) or calls _xt_panic to freeze the 
+    processor should a kernel exception occur.
+
+8.5 Alloca Exception Handler
+
+    Alloca exceptions are generated by the 'movsp' instruction, which
+    is used only in the windowed ABI. Its purpose is to allocate some
+    space on top of the stack. Because the window hardware may have
+    spilled some registers to the 16 byte "base save" area below the
+    stack pointer, it is necessary to protect those values. The alloca
+    handler accomplishes this quickly without setting up an interrupt
+    frame or entering ThreadX, by emulating a register underflow and
+    re-executing 'movsp'.
+
+8.6 Syscall Exception Handler
+
+    Syscall exceptions are generated by a 'syscall' instruction.
+    The windowed ABI specifies that executing this instruction with
+    a value of zero in register a2 must spill any unsaved registers
+    in the windowed register file to their pre-determined locations
+    on the caller's stack. The handler does exactly that, and skips
+    over the 'syscall' instruction before returning to the caller.
+    If a2 is non-zero, the handler returns a2 == -1 to the caller.
+
+8.7 Co-Processor Exception Handler
+
+    A coprocessor exception is generated when a thread accesses a
+    coprocessor that it does not "own". Ownership represents which 
+    thread's state is currently in the coprocessor. Co-processors are 
+    context-switched "lazily" (on demand) only when a non-owning thread 
+    uses a coprocessor instruction, otherwise a thread retains ownership 
+    even when it is preempted from the main processor. The coprocessor
+    exception handler performs the context-switch and manages ownership.
+
+    Co-processors may not be used by any code outside the context of a
+    thread. A coprocessor exception triggered by code that is not part
+    of a running thread is a fatal error and ThreadX/Xtensa will panic.
+    This restriction is intended to reduce the overhead of saving and 
+    restoring coprocessor state (which can be quite large) and in 
+    particular remove that overhead from interrupt handlers. It also
+    reduces the thread stack size requirement by allowing coprocessor
+    state to be saved in the thread control block rather than the stack.
+
+8.8 Debug Exception Handler
+
+    A debug exception is caused as a result of running code, such as by
+    a 'break' instruction or hardware breakpoints and watchpoints, or
+    as a result of an external debug interrupt, such as from an OCD based
+    debugger or multiprocessor debug events ("breakin/breakout"). If the
+    processor is running in OCD mode under control of an OCD-based debugger,
+    the trigger event immediately halts the processor and gives control to
+    the OCD debugger. Otherwise control is transferred to the debug vector.
+    The debug vector handler calls the simulator if running on the ISS,
+    which then takes control and interacts with any attached debugger.
+    If running on hardware and not in OCD mode, debug exceptions are not
+    expected, so the debug handler calls _xt_panic to freeze the processor.
+
+8.9 Double Exception Handler
+
+    A double exception is a general exception that happens while the
+    processor is in exception mode (PS.EXCM set), and thus indicates a
+    bug in kernel code. The double exception vector handler triggers
+    the debugger (if connected) or calls _xt_panic to freeze the 
+    processor.
+
+8.10 Window Overflow and Underflow Exception Handlers
+
+    Window overflow and underflow handlers are required for use of the
+    windowed ABI. Each has its own dedicated vector and highly optimized
+    code that is independent of OS. See Xtensa documentation for details.
+
+8.11 Hooks for Dynamic Installation of Handlers
+
+    Optional hooks are provided in the user exception and low level
+    interrupt handler and all medium and high priority interrupt handlers,
+    to dynamically install a handler function (which may be coded in C,
+    unless in a high-priority interrupt handler). These hooks are enabled
+    and used by automatic regression tests, they are not part of a normal
+    ThreadX build. However an application is free to take advantage of
+    them. The interrupt/exception hooks are described in xtensa_rtos.h .
+
+    It is recommended that the application not make use of these hooks, but
+    rather use xt_set_interrupt_handler() and xt_set_exception_handler()
+    to install application-specific handlers. This method is more convenient
+    and allows arguments to be passed to the handlers. Software prioritization
+    of interrupts works only with this method. See xtensa_api.h for details.
+
+9.  Overlay Support (XEA2 only)
+
+ThreadX supports the overlay feature of the Xtensa toolsuite. To enable overlay support,
+the ThreadX library should be built with XT_USE_OVLY defined. In addition, the linker 
+command line must use the overlay library via the -loverlay linker option and the 
+xtensa_overlay_os_hook.o object file must be explicitly specified in order to override
+the overlay libary version.
+
+You will also need to generate a custom LSP for overlay use. Please reference the 
+Xtensa System Software Reference and Xtenas Linker Support Packages (LSPs) for more 
+information on using overlays.
+
+
+10.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+04/26/2019  ThreadX Xtensa version 5.12. This release adds support for the Xtensa XEA3
+            exception architecture and the Xtensa NX processor family. The following
+            changes/enhancements are included:
+
+            Makefile                            Changes to support building for Xtensa
+                                                XEA3 configurations.
+            xtensa_vectors_xea3.S               New file added, interrupt and exception
+                                                dispatch code for XEA3.
+
+            tx_api_asm.h                        Changes and additions to support the Xtensa
+            tx_port.h                           XEA3 exception architecture.
+            xtensa_api.h
+            xtensa_context.h
+            xtensa_rtos.h
+            xtensa_timer.h
+            tx_initialize_low_level.c
+            tx_thread_context_restore.S
+            tx_thread_context_save.S
+            tx_thread_interrupt_control.c
+            tx_thread_schedule.S
+            tx_thread_stack_build.S
+            tx_thread_system_return.S
+            tx_timer_interrupt.S
+            tx_xtensa_stack_error_handler.c
+            xtensa_context.S
+            xtensa_coproc_handler.S
+            xtensa_init.c
+            xtensa_intr.c
+            xtensa_intr_asm.S
+            xtensa_intr_wrapper.c
+            xtensa_vectors.S
+
+08/01/2017  ThreadX Xtensa version 5.11. This release includes the following changes
+            and enhancements/modifications: 
+
+            Makefile                            Build execution profile module only
+                                                if the module has been selected.
+            tx_api_asm.h                        Changed field offsets for Xtensa-
+                                                specific fields in TCB.
+            tx_clib_lock.c                      Added thread wrapper function to handle
+                                                C library setup and cleanup properly.
+            tx_port.h                           Redefined macros as required as part of
+                                                the redesigned C library thread safety support.
+            tx_xtensa_stack_error_handler.c     Included required headers.
+            xtensa_intr_asm.S                   Placed interrupt stack explicitly in .data
+                                                section.
+            xtensa_intr.c                       Fixed return values for set exception handler
+                                                and set interrupt handler functions.
+            xtensa_overlay_os_hook.c            Added conditions so that code is now compiled
+                                                only if overlay option is selected.
+            xtensa_timer.h                      Include TIE header files conditionally.
+            *.h                                 Modified comment(s).
+            *.S                                 Modified comment(s).
+ 
+03/22/2016  ThreadX Xtensa version 5.10. This release includes the following changes
+            and enhancements: separate user-configurable interrupt stack, support for
+            Xtensa C library (xclib) thread safety, minor changes to the support for
+            the Execution Profile kit, and minor changes to remove some compiler warnings.
+            This release includes the following modifications:
+
+            tx_port.h                           Added support for XCLIB C library thread safety, 
+                                                added support for separate interrupt stack, 
+                                                added support Execution Profile Kit (EPK), and 
+                                                updated version string.
+            tx_initialize_low_level.S           Replaced by tx_initialize_low_level.c, added
+                                                support for XCLIB C library thread safety, 
+                                                added support for separate interrupt stack and 
+                                                moved setup of thread stack check callback in here 
+                                                from demo program.
+            tx_thread_context_restore.S         Added support for Execution Profile Kit (EPK).
+            tx_thread_schedule.S                Added support for Execution Profile Kit (EPK), and
+                                                added support for XCLIB C library thread safety.
+            tx_thread_system_return.S           Added support for Execution Profile Kit (EPK).
+            tx_api_asm.h                        Added support for XCLIB C library thread safety.
+            tx_clib_lock.c                      Added support for XCLIB C library thread safety.
+            xtensa_api.h                        Corrected issues with function declarations.
+            xtensa_context.h                    Corrected build errors when TX_NO_TIMER defined.
+            xtensa_intr_asm.S                   Added support for separate interrupt stack.
+            xtensa_overlay_os_hook.c            Corrected compiler warnings.
+            xtensa_vectors.S                    Added support for Execution Profile Kit (EPK), and
+                                                added compiler warnings.
+            xtensa_timer.h                      Added timer related defines to simplify timer setup code.
+            Makefile                            Various misc updates, removed some obsolete targets.
+            tx_intr_demo.c                      Added support for XCLIB C library thread safety.
+            *.h                                 Modified comment(s).
+            *.S                                 Modified comment(s).
+
+06/01/2015  ThreadX Xtensa version 5.9. This release includes the following modifications:
+
+            tx_port.h                           Changed default timer thread stack size logic, 
+                                                updated coprocessor support, and updated 
+                                                version string.
+            tx_initialize_low_level.S           Modified timer setup.
+            tx_thread_schedule.S                Added setup for timing test option.                                    
+            tx_thread_stack_build.S             Added virtual priority mask setup.
+            tx_thread_system_return.S           Added support for coprocessor save.
+            xtensa_context.h                    Added additional interrupt support, including 
+                                                coprocessor save/restore.
+            xtensa_context.S                    Added additional interrupt support, including
+                                                coprocessor save/restore.
+            xtensa_overlay_os_hook.c            Added include of overlay.h.
+            xtensa_vectors.S                    Added new interrupt support and functionality.
+            xtensa_api.h                        Added new file for this release.
+            xtensa_intr.c                       Added new file for this release.
+            xtensa_intr_asm.S                   Added new file for this release.
+            *.h                                 Modified comment(s).
+            *.S                                 Modified comment(s).
+
+07/31/2014  ThreadX Xtensa version 5.8. This release includes the following modifications:
+
+            tx_port.h                           Added in-line interrupt disable and 
+                                                restore macros, and updated version string.
+            tx_thread_system_return.S           Added context save optimization.
+            xtensa_context.h                    Added overlay support.
+            xtensa_context.S                    Added overlay support.
+            xtensa_overlay_os_hook.c            Added new file for overlay support.
+            *.h                                 Modified comment(s).
+            *.S                                 Modified comment(s).
+
+10/01/2011  ThreadX Xtensa version 5.7. This release includes the following modifications:
+
+            tx_port.h                           Updated version string.
+            tx_thread_context_restore.S         Changed to 16-bit save of tx_thread_cp_state.
+            tx_thread_schedule.S                Changed to 16-bit restore of tx_thread_cp_state.
+            tx_thread_system_return.S           Changed to 16-bit save of tx_thread_cp_state.
+            xtensa_context.h                    Modified alignment constants and macros.
+            xtensa_context.S                    Removed initial alignment adjustment.
+            *.h                                 Modified comment(s).
+            *.S                                 Modified comment(s).
+
+07/15/2011  ThreadX Xtensa version 5.6. This release includes the following modifications:
+
+            tx_port.h                           Modified control block and thread processing 
+                                                extensions to be compatible with all cores, 
+                                                and updated version string.
+           
+            tx_clib_lock.c                      Added code to not use priority inheritance when
+                                                running the regression testsuite.
+            tx_timer_interrupt.S                Added code to optionally call user timer ISR.
+            xtensa_timer.h                      Adjusted timer for testsuite to pass under
+                                                simulation.            
+            xtensa_vectors.S                    Fixed several issues in coprocessor context
+                                                switch code.
+            *.S                                 Modified comment(s).
+
+01/28/2011  ThreadX Xtensa version 5.5. This release includes the following modifications:
+
+            tx_port.h                           Changed version ID and added alignment padding.            
+            tx_thread_stack_build.s             Added code to clear solicited stack frame flag.
+            xtensa_context.h                    Added logic to support Xtensa processors with 
+                                                load/store units wider than 128-bits
+            xtensa_context.s                    Added logic to support Xtensa processors with
+                                                load/store units wider than 128-bits
+            xtensa_vectors.s                    Added logic to support Xtensa processors with
+                                                load/store units wider than 128-bits
+            *.s                                 Modified comment(s).
+
+05/01/2010  ThreadX Xtensa version 5.4. This release includes the following modifications:
+
+            tx_port.h                           Changed version ID.            
+            tx_thread_system_return.s           Changed code to preserve current time-slice value.
+            *.s                                 Modified comment(s).
+
+07/15/2009  ThreadX Xtensa version 5.3. It includes the following modifications:
+
+            tx_port.h                           Added include of string.h, added GDBIO 
+                                                constants, and modified version ID string.
+            tx_clib_lock.c                      Added include of stdlib.h.
+            tx_thread_context_save.S            Added "XCHAL_CP_NUM > 0" conditional around
+                                                _tx_thread_coproc_state function definition.
+            tx_thread_schedule.S                Removed #else conditional and replaced RET
+                                                macro with assembly code.
+            tx_thread_system_return.S           Replaced ENTRY macro with assembly code.
+            xtensa_context.h                    Modified call frame offsets.
+            xtensa_timer.h                      Modified timer constants and added extern
+                                                for _xt_tick_diviso_init function.
+            xtensa_vectors.S                    Replaced exit macros.
+            tx*.h                               Modified comment(s).
+            tx*.c                               Modified comment(s).
+            tx*.S                               Modified comment(s).
+
+06/18/2008  ThreadX Xtensa version 5.2. It includes the following modifications:
+
+            tx_port.h                           Added "extern" to the interrupt control 
+                                                function prototype, and modified 
+                                                version ID string.
+            tx_api_asm.h                        Fixed bug whereby tx_thread_cp_state 
+                                                was off by 1 word and overlapped 
+                                                tx_thread_name if TX_THREAD_SAFE_CLIB
+                                                was not defined.
+            xtensa_vectors.S                    Strengthened syncs for strict ISA
+                                                conformance. Aligned exit dispatchers.
+            tx*.h                               Modified comment(s).
+            tx*.c                               Modified comment(s).
+            tx*.S                               Modified comment(s).
+
+04/02/2007  ThreadX Xtensa version 5.1. This release adds minor enhancements
+            and supports evaluation boards via a new board independent "XTBSP"
+            API (allowing ThreadX to take advantage of any supported board)
+            and deprecates board-specific code for the obsolete XT2000.
+            It includes the following modifications:
+
+            tx_port.h                           Co-proc check uses XCHAL_CP_NUM,
+                                                deprecated XT_XT2000 option, 
+                                                included tx_user.h first, and
+                                                made TX_MAX_PRIORITIES visible
+                                                to assembler code.
+            tx_xtensa_stack_error_handler.c     Accessed board's display via API
+                                                and deprecated XT_XT2000 option.
+            tx_initialize_low_level.S           Co-proc check uses XCHAL_CP_NUM,
+                                                modified timer setup and
+                                                supported TX_NO_TIMER.
+            tx_thread_context_restore.S         Co-proc check uses XCHAL_CP_NUM.
+            tx_thread_schedule.S                Co-proc check uses XCHAL_CP_NUM.
+            tx_thread_system_return.S           Co-proc check uses XCHAL_CP_NUM.
+            tx_timer_interrupt.S                Use tick divisor computed via
+                                                API and support TX_NO_TIMER.
+            xtensa_context.h                    Co-proc check uses XCHAL_CP_NUM.
+            xtensa_context.S                    Co-proc check uses XCHAL_CP_NUM.
+            xtensa_init.c                       Added new initialization code to
+                                                set tick timer using board API.
+            xtensa_rtos.h                       Allowed tx_user.h macros to 
+                                                affect Xtensa-generic macros and
+                                                supported TX_NO_TIMER.
+            xtensa_timer.h                      Updated timer configuration 
+                                                logic and supported TX_NO_TIMER.
+            xtensa_vectors.S                    Co-proc check uses XCHAL_CP_NUM
+                                                and updated logic for long jumps
+                                                and supported TX_NO_TIMER.
+            tx*.h                               Modified comment(s).
+            tx*.c                               Modified comment(s).
+            tx*.S                               Modified comment(s).
+
+10/10/2006  Initial ThreadX version for Xtensa configurable processors 
+            and Diamond pre-configured processors using Xtensa Tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/xtensa/xcc/src/tx_clib_lock.c b/ports/xtensa/xcc/src/tx_clib_lock.c
new file mode 100644
index 00000000..072cbd52
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_clib_lock.c
@@ -0,0 +1,406 @@
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains the interface functions to provide thread-safe   */
+/*    operation of the C library. Both newlib and the Xtensa C Library    */
+/*    are supported.                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#include "tx_api.h"     /* TX_THREAD_SAFE_CLIB may be defined by tx_port.h */
+#include "tx_thread.h"
+#include "tx_initialize.h"
+
+/* Xtensa specific */
+#include <xtensa/config/system.h>
+
+#ifdef TX_THREAD_SAFE_CLIB    /* this file is only needed if using C lib */
+
+#include <errno.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+
+
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+
+#include <malloc.h>
+
+/* NOTE: should have been declared in reent.h... */
+extern void _wrapup_reent(struct _reent * ptr);
+
+/* Mutex used for all C library protection */
+TX_MUTEX  clib_lock_mutex;
+
+
+/**************************************************************************/
+/*    __malloc_lock - called by the malloc() family of routines when they */
+/*    need to lock the memory pool. A call to malloc() may call this      */
+/*    function recursively.                                               */
+/**************************************************************************/
+void
+__malloc_lock (struct _reent * ptr)
+{
+    if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) {
+        return;
+    }
+
+    tx_mutex_get (&clib_lock_mutex, TX_WAIT_FOREVER);
+}
+
+/**************************************************************************/
+/*    __malloc_unlock - called by the malloc() family of routines when    */
+/*    need to unlock the memory pool.                                     */
+/**************************************************************************/
+void
+__malloc_unlock (struct _reent * ptr)
+{
+    if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) {
+        return;
+    }
+
+#ifndef THREADX_TESTSUITE   /* see THREADX_TESTSUITE comments below */
+    tx_mutex_prioritize (&clib_lock_mutex);    /* is this at all necessary? */
+#endif
+    tx_mutex_put (&clib_lock_mutex);
+}
+
+
+/**************************************************************************/
+/*    __env_lock - called by the setenv() family of routines when they    */
+/*    need to modify the environment. A call to setenv() may call this    */
+/*    function recursively.                                               */
+/**************************************************************************/
+void
+__env_lock (struct _reent * ptr)
+{
+    if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) {
+        return;
+    }
+
+    tx_mutex_get (&clib_lock_mutex, TX_WAIT_FOREVER);
+}
+
+/**************************************************************************/
+/*    __env_unlock - called by the setenv() family of routines when they  */
+/*    need to unlock the environment.                                     */
+/**************************************************************************/
+void
+__env_unlock (struct _reent * ptr)
+{
+    if (_tx_thread_system_state != TX_INITIALIZE_IS_FINISHED) {
+        return;
+    }
+
+    tx_mutex_prioritize (&clib_lock_mutex);
+    tx_mutex_put (&clib_lock_mutex);
+}
+
+#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
+
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+
+#include <errno.h>
+#include <sys/reent.h>
+    
+#define XT_NUM_CLIB_LOCKS      (_MAX_LOCK + FOPEN_MAX)
+
+typedef TX_MUTEX * _Rmtx;
+
+static TX_MUTEX xclib_locks[XT_NUM_CLIB_LOCKS];
+static uint32_t lcnt;
+
+/* Override this and set to nonzero to enable locking. */
+int32_t _xclib_use_mt = 1;
+
+
+/**************************************************************************/
+/*    _Mtxinit - initialize a lock. Called once for each lock.            */
+/**************************************************************************/
+void
+_Mtxinit (_Rmtx * mtx)
+{
+    TX_MUTEX * lock;
+
+    if (lcnt >= XT_NUM_CLIB_LOCKS) {
+        /* Fatal error */
+    }
+
+    lock = &(xclib_locks[lcnt]);
+    lcnt++;
+
+    /* See notes for newlib case below. */
+#ifdef THREADX_TESTSUITE
+    tx_mutex_create (lock, "Clib lock", 0);
+#else
+    tx_mutex_create (lock, "Clib lock", TX_INHERIT);
+#endif
+
+    *mtx = lock;
+}
+
+/**************************************************************************/
+/*    _Mtxdst - destroy a lock. Called once for each lock.                */
+/**************************************************************************/
+void
+_Mtxdst (_Rmtx * mtx)
+{
+    if ((mtx) && (*mtx)) {
+        tx_mutex_delete (*mtx);
+    }
+}
+
+/**************************************************************************/
+/*    _Mtxlock - acquire lock.                                            */
+/**************************************************************************/
+void
+_Mtxlock (_Rmtx * mtx)
+{
+    if ((mtx) && (*mtx)) {
+        tx_mutex_get (*mtx, TX_WAIT_FOREVER);
+    }
+}
+
+/**************************************************************************/
+/*    _Mtxunlock - release a lock.                                        */
+/**************************************************************************/
+void
+_Mtxunlock (_Rmtx * mtx)
+{
+    if ((mtx) && (*mtx)) {
+        tx_mutex_put (*mtx);
+    }
+}
+
+#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+
+
+/**************************************************************************/
+/*    _sbrk_r - heap allocator. This function is called when the memory   */
+/*    allocator needs a new chunk of memory.                              */
+/*    The bounds of the heap area are global variables so that customer   */
+/*    startup code can easily override them if needed.                    */
+/*                                                                        */
+/*    _tx_clib_heap_start    is the start of memory assigned to the heap  */
+/*                           or 0 (NULL) if no memory is assigned (in     */
+/*                           that case all calls to malloc will fail).    */
+/*                                                                        */
+/*   _tx_clib_heap_end       is the end of memory assigned to the heap    */
+/*                           or 0 (NULL) if no memory is assigned. If a   */
+/*                           nonzero start value is set then a nonzero    */
+/*                           end value must be set.                       */
+/**************************************************************************/
+
+char * _tx_clib_heap_start = NULL;
+char * _tx_clib_heap_end   = NULL;
+
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    static char * heap_ptr;
+    char * new_heap_ptr;
+    char * alloc_ptr;
+
+    /* The heap is bound by _tx_clib_heap_{start,end}. */
+    if (heap_ptr == NULL) {
+        heap_ptr = _tx_clib_heap_start;
+    }
+
+    new_heap_ptr = heap_ptr + incr;
+    if ((heap_ptr == NULL) ||                   /* no heap        */
+        (new_heap_ptr >= _tx_clib_heap_end) ||  /* heap exhausted */
+        (new_heap_ptr < heap_ptr)) {            /* wraparound     */
+        reent->_errno = ENOMEM;
+        return (void *) -1;
+    }
+
+    alloc_ptr = heap_ptr;
+    heap_ptr = new_heap_ptr;
+    return (void *) alloc_ptr;
+}
+
+
+/**************************************************************************/
+/*    _tx_clib_init - initialize C library thread safety support.         */
+/*    Called by _tx_initialize_low_level().                               */
+/**************************************************************************/
+void
+_tx_clib_init (void)
+{
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+#ifdef THREADX_TESTSUITE
+  /*  Priority inheritance causes printf() (which calls malloc()
+      which calls __malloc_unlock() which calls tx_mutex_put()
+      which calls _tx_mutex_priority_change() if TX_INHERIT is set)
+      which causes the task to suspend and resume which sometimes
+      changes execution order in the very sensitive testsuite
+      and makes it fail.  So, for the testsuite, don't request
+      priority inheritance (it doesn't need it in any case).  */
+    tx_mutex_create (&clib_lock_mutex, "Clib lock", 0);
+#else
+    tx_mutex_create (&clib_lock_mutex, "Clib lock", TX_INHERIT);
+#endif
+#endif /* NEWLIB */
+
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    /* Nothing. */
+#endif /* XCLIB */
+}
+
+
+/**************************************************************************/
+/*    _tx_clib_reent_init - initialize C library thread reent structure.  */
+/*    Called by tx_thread_create() to init per-thread C library state.    */
+/**************************************************************************/
+void
+_tx_clib_reent_init (TX_THREAD * thread_ptr)
+{
+    if (thread_ptr == NULL) {
+        /* Should never happen */
+        return;
+    }
+
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    struct _reent * reent = &(thread_ptr->tx_thread_clib_reent);
+
+    memset (reent, 0, sizeof(struct _reent));
+    _REENT_INIT_PTR (reent);
+    thread_ptr->tx_thread_clib_ptr = reent;
+#endif
+
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    thread_ptr->tx_thread_clib_ptr = &(thread_ptr->tx_thread_clib_reent);
+    _init_reent (thread_ptr->tx_thread_clib_ptr);
+#endif
+}
+
+
+/**************************************************************************/
+/*    _tx_clib_reent_cleanup - clean up C library thread reent structure. */
+/*    Called by tx_thread_delete() to clean up per-thread C library state */
+/*    and free any allocated memory (partial = 0).                        */
+/*    Called by tx_thread_shell_entry and tx_thread_terminate to perform  */
+/*    "atexit" processing and clean up stdio, but leaving the rest of the */
+/*    structure intact so the thread can be restarted (partial = 1).      */
+/**************************************************************************/
+void
+_tx_clib_reent_cleanup (TX_THREAD * thread_ptr, int32_t partial)
+{
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    struct _reent * reent = &(thread_ptr->tx_thread_clib_reent);
+    FILE * fp = &(reent->__sf[0]);
+    int32_t i;
+
+  /* Avoid closing stdin,stdout,stderr so other threads can still use them. */
+    for (i = 0; i < 3; i++) {
+        fp->_close = NULL;
+        fp++;
+    }
+
+    if (partial != 0) {
+        /* Perform "atexit" processing and clean up stdio. */
+        _wrapup_reent (reent);
+    }
+    else {
+        /* Free all the heap memory allocated in the reent structure.
+           ThreadX requires that the thread has either exited or been
+           terminated before it can be deleted so we can assume that
+           _wrapup_reent has already been called for this thread. */
+        _reclaim_reent (reent);
+    }
+#endif
+
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+  /* Unused, keep compiler happy */
+  (void) partial;
+
+  /* File handle table is global; no allocated memory in struct. */
+  thread_ptr->tx_thread_clib_ptr = 0;
+#endif
+}
+
+
+/**************************************************************************/
+/*    _xt_wrapper - thread wrapper to handle C library init/cleanup.      */
+/*    If C library thread safety is enabled, every thread is invoked      */
+/*    via this wrapper in order to handle thread context setup/cleanup.   */
+/**************************************************************************/
+void
+_xt_thread_wrapper (ULONG arg)
+{
+    TX_INTERRUPT_SAVE_AREA
+    TX_THREAD * thread_ptr = _tx_thread_current_ptr;
+
+    /* No use for this parameter */
+    (void) arg;
+
+    /* Init the C library thread context */
+    _tx_clib_reent_init (thread_ptr);
+
+    /* Disable interrupts around the global context ptr update */
+    TX_DISABLE
+
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    _impure_ptr = thread_ptr->tx_thread_clib_ptr;
+#endif
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    _reent_ptr = thread_ptr->tx_thread_clib_ptr;
+#endif
+
+    TX_RESTORE
+
+    /* Call actual thread entry point */
+    (thread_ptr->tx_real_thread_entry)(thread_ptr->tx_thread_entry_parameter);
+
+    /* Clean up C library thread context */
+    _tx_clib_reent_cleanup(thread_ptr, 1);
+    _tx_clib_reent_cleanup(thread_ptr, 0);
+}
+
+
+/**************************************************************************/
+/*    _tx_clib_thread_setup - Xtensa-specific thread setup actions.       */
+/*    This function will be called only if thread safe C library usage    */
+/*    is enabled. It inserts the wrapper as the thread entry point and    */
+/*    saves the actual entry point for later use.                         */
+/**************************************************************************/
+void
+_tx_clib_thread_setup (TX_THREAD * thread_ptr)
+{
+    thread_ptr->tx_real_thread_entry = thread_ptr->tx_thread_entry;
+    thread_ptr->tx_thread_entry      = &(_xt_thread_wrapper);
+}
+
+#endif /* TX_THREAD_SAFE_CLIB */
+
diff --git a/ports/xtensa/xcc/src/tx_initialize_low_level.c b/ports/xtensa/xcc/src/tx_initialize_low_level.c
new file mode 100644
index 00000000..d7082db0
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_initialize_low_level.c
@@ -0,0 +1,187 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+
+#include "tx_api.h"
+#include "tx_port.h"
+#include "xtensa_api.h"
+
+#if XCHAL_HAVE_ISL || XCHAL_HAVE_KSL || XCHAL_HAVE_PSL
+#include <xtensa/tie/xt_exception_dispatch.h>
+#endif
+
+
+#if XCHAL_HAVE_XEA3
+int32_t xt_sw_intnum    = -1;
+int32_t xt_timer_intnum = -1;
+#endif
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for any low-level processor            */
+/*    initialization, including setting up interrupt vectors, setting     */
+/*    up a periodic timer interrupt source, saving the system stack       */
+/*    pointer for use in ISR processing later, and finding the first      */
+/*    available RAM memory address for tx_application_define.             */
+/*    It also sets the default heap region for the optional C library.    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_initialize_low_level(VOID)
+{
+    extern char   _xt_interrupt_stack_top;
+    extern void   _tx_timer_interrupt(void *);
+    extern void * _tx_thread_system_stack_ptr;
+    extern void * _tx_initialize_unused_memory;
+    extern char   _end;
+
+    #ifdef TX_THREAD_SAFE_CLIB
+    extern char __stack;
+    extern void _tx_clib_init(void);
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    extern void _xt_coproc_init(void);
+    extern void _xt_coproc_exc(XtExcFrame * fp);
+    #endif
+
+    #ifdef TX_ENABLE_STACK_CHECKING
+    extern VOID _tx_xtensa_stack_error_handler(TX_THREAD * thread);
+    #endif
+
+    #if XCHAL_HAVE_XEA3
+    extern void xt_sched_handler(void * arg);
+    int32_t i;
+    #endif
+
+    TX_INTERRUPT_SAVE_AREA
+
+    /* Disable interrupts - don't want any that interact with ThreadX yet. */
+    TX_DISABLE
+
+    /*
+    Disable stack limit checking if present. Whatever was set up earlier
+    is not going to work for us.
+    */
+#if XCHAL_HAVE_KSL
+    XT_WSR_KSL(0);
+#endif
+#if XCHAL_HAVE_ISL
+    XT_WSR_ISL(0);
+#endif
+
+    /* Save the system stack pointer.  */
+    _tx_thread_system_stack_ptr = &(_xt_interrupt_stack_top);
+
+    /* Save the first available memory address.  */
+    _tx_initialize_unused_memory = (void *)(((UINT)&_end + 15) & ~0xF);
+
+    #ifdef TX_THREAD_SAFE_CLIB
+    /*
+    Pre-allocate default memory region for the C library heap.
+    Bisect the region from first available memory to end of system memory,
+    align to 16 byte boundary, and allocate the heap in the upper half.
+    */
+    _tx_clib_heap_end   = &(__stack);
+    _tx_clib_heap_start =
+        (void *)(((UINT)_tx_initialize_unused_memory/2 + (UINT)_tx_clib_heap_end/2) & ~0xF);
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    /*
+    Initialize co-processor management for threads. Leave CPENABLE alone.
+    This is called from a normal Xtensa single-threaded run-time environment
+    before multi-threading has commenced. All co-processors are enabled.
+    It is important NOT to clear CPENABLE yet because tx_application_define() 
+    is user code which might use a co-processor. The co-processor exception 
+    handler does not expect to be called outside a thread.
+    */
+    _xt_coproc_init();
+
+    #if XCHAL_HAVE_XEA3
+    /* Install the coprocessor exception handler. */
+    xt_set_exception_handler(EXCCAUSE_CP_DISABLED, _xt_coproc_exc);
+    #endif
+    #endif
+
+    #if XCHAL_HAVE_XEA3
+    /* Select a software interrupt to use for scheduling. */
+    for (i = 0; i < XCHAL_NUM_INTERRUPTS; i++) {
+        if ((Xthal_inttype[i] == XTHAL_INTTYPE_SOFTWARE) && (Xthal_intlevel[i] == 1)) {
+            xt_sw_intnum = i;
+            break;
+        }
+    }
+
+    if (xt_sw_intnum == -1) {
+        __asm__ volatile ("break 1, 1");
+    }
+
+    /* Set the interrupt handler and enable the interrupt. */
+    xt_set_interrupt_handler(xt_sw_intnum, xt_sched_handler, 0);
+    xt_interrupt_enable(xt_sw_intnum);
+    #endif
+
+    #ifndef TX_NO_TIMER
+
+    /* Compute tick divisor if clock freq is not compile-time constant. */
+    #ifndef XT_CLOCK_FREQ
+    _xt_tick_divisor_init();
+    #endif
+
+    /* Set up the periodic tick timer (assume enough time to complete init). */
+    #ifdef XT_CLOCK_FREQ
+    XT_WSR_CCOMPARE(XT_RSR_CCOUNT() + XT_TICK_DIVISOR);
+    #else
+    XT_WSR_CCOMPARE(XT_RSR_CCOUNT() + _xt_tick_divisor);
+    #endif
+
+    #if XCHAL_HAVE_XEA3
+    xt_timer_intnum = XT_TIMER_INTNUM;
+    xt_set_interrupt_handler(xt_timer_intnum, _tx_timer_interrupt, 0);
+    #endif
+
+    /* Enable the timer interrupt at the device level. */
+    xt_interrupt_enable(XT_TIMER_INTNUM);
+
+    #endif /* TX_NO_TIMER */
+
+    /* Initialize C library thread safety support. */
+    #ifdef TX_THREAD_SAFE_CLIB
+    _tx_clib_init();
+    #endif
+
+    /* Install stack overflow notification callback. */
+    #ifdef TX_ENABLE_STACK_CHECKING
+    tx_thread_stack_error_notify(_tx_xtensa_stack_error_handler);
+    #endif
+}
+
diff --git a/ports/xtensa/xcc/src/tx_thread_context_restore.S b/ports/xtensa/xcc/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..aa628751
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_thread_context_restore.S
@@ -0,0 +1,216 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#include "xtensa_rtos.h"
+#include "tx_api_asm.h"
+
+
+#if XCHAL_HAVE_XEA2
+
+    .text
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This function restores the interrupt context if it is processing a  */ 
+/*    nested interrupt. If not, it returns to the interrupt thread if no  */ 
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+/*    if no thread was running, the function returns to the scheduler.    */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/ 
+
+//  VOID   _tx_thread_context_restore(VOID)
+//  {
+    .globl  _tx_thread_context_restore
+    .type   _tx_thread_context_restore,@function
+    .align  4
+_tx_thread_context_restore:
+
+    /*
+    Please note: Control flow might seem strange. This is because it has been 
+    optimized to avoid taken branches in the longest normal path (the critical 
+    one for worst-case latency), presumed to be a non-nested interrupt that 
+    preempts) and to hide pipeline interlock cycles where possible.
+    */
+
+    /* Lockout interrupts.  */
+    XT_INTS_DISABLE(a0)
+
+    #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the ISR exit function to indicate an ISR is complete. */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   _tx_execution_isr_exit
+    #else
+    call8   _tx_execution_isr_exit
+    #endif
+    #endif
+
+    /* Determine if interrupts are nested.  */
+    //  if (--_tx_thread_system_state)
+    //  {
+
+    movi    a2, _tx_thread_system_state /* a2 = & interrupt nesting count */
+    l32i    a3, a2, 0                   /* decrement interrupt nesting count */
+    addi    a3, a3, -1
+    s32i    a3, a2, 0
+    bnez    a3, .L_tx_thread_nested_restore
+
+    //  }
+
+.Ln_tx_thread_not_nested_restore:
+
+    /* Determine if a thread was interrupted and no preemption is required.  */
+    //  else if (((_tx_thread_current_ptr) 
+    //              && (_tx_thread_current_ptr == _tx_thread_execute_ptr))
+    //           || (_tx_thread_preempt_disable))
+    //  {
+
+    movi    a0, _tx_thread_current_ptr  /* a0 = &_tx_thread_current_ptr */
+    l32i    a2, a0, 0                   /* a2 =  _tx_thread_current_ptr (old) */
+    movi    a3, _tx_thread_execute_ptr
+    beqz    a2, .L_tx_thread_idle_system_restore
+
+    l32i    a3, a3, 0                   /* a3 = _tx_thread_execute_ptr (new) */
+    beq     a3, a2, .L_tx_thread_no_preempt_restore
+
+    movi    a3, _tx_thread_preempt_disable
+    l32i    a3, a3, 0                   /* a3 = _tx_thread_preempt_disable */
+
+    //      /* the no-preempt case has moved down so we fall-thru to preempt */
+    bgei    a3, 1, .L_tx_thread_no_preempt_restore
+    
+    //  }
+    //  else
+    //  {
+
+.Ln_tx_thread_preempt_restore:
+
+    /* Save remaining context on the thread's stack.  */
+    l32i    a3, a2, tx_thread_stack_ptr /* a3 = thread's stack ptr */
+
+    /* Store standard preserved registers.  */
+    /*
+    Call0 ABI callee-saved regs a12-15 need to be saved before preemption.
+    However a12-13 were saved for scratch by _tx_thread_context_save(). 
+    */
+    #ifdef __XTENSA_CALL0_ABI__         /* Call0: now save callee-save regs  */
+    s32i    a14, a3, XT_STK_A14
+    s32i    a15, a3, XT_STK_A15
+    #endif
+
+    /* Save the remaining time-slice and disable it.  */
+    //      if (_tx_timer_time_slice)
+    //      {
+    movi    a3, _tx_timer_time_slice    /* a3 = &_tx_timer_time_slice */
+    l32i    a4, a3, 0                   /* a4 =  _tx_timer_time_slice */
+    beqz    a4, .L_tx_thread_dont_save_ts
+
+    //          _tx_thread_current_ptr -> tx_thread_time_slice 
+    //              =  _tx_timer_time_slice;
+    //          _tx_timer_time_slice =  0;  */
+    s32i    a4, a2, tx_thread_time_slice
+    movi    a4, 0
+    s32i    a4, a3, 0
+
+    //      }
+
+.L_tx_thread_dont_save_ts:
+
+    /* Clear the current task pointer.  */
+    //      _tx_thread_current_ptr =  TX_NULL;
+    s32i    a4, a0, 0                   /* a4 == 0 == TX_NULL */
+
+    #if XCHAL_CP_NUM > 0
+    /* Save CPENABLE in thread's co-processor save area, and clear CPENABLE. */
+    rsr     a3, CPENABLE
+    s16i    a3, a2, tx_thread_cp_state + XT_CPENABLE
+    wsr     a4, CPENABLE                /* disable all co-processors */
+    #endif
+
+.L_tx_thread_idle_system_restore:
+
+    /* 
+    Return via the scheduler.
+    Scheduler returns eventually to this function's caller as if called by it.
+    At this point we are still on the system stack.
+    */
+    //      _tx_thread_schedule();
+    call0   _tx_thread_schedule         /* never returns here */
+
+    //  }
+
+    /* Flow never falls through here. */
+
+.L_tx_thread_no_preempt_restore:
+
+    /* Restore interrupted thread.  */
+
+    /* Pickup the saved stack pointer.  */
+    //      SP =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+    l32i    sp, a2, tx_thread_stack_ptr
+
+.L_tx_thread_nested_restore:
+
+    /* Recover the saved context and return to the point of interrupt.  */
+
+    call0   _xt_context_restore
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint 
+    from which this was called. Interruptee's A0, A1, PS, PC are restored 
+    and the interrupt stack frame is deallocated in the exit dispatcher.
+    At this point we are on the thread's stack.
+    */
+    l32i    a0, sp, XT_STK_EXIT
+    ret
+
+//  }
+
+#endif /* XCHAL_HAVE_XEA2 */
+
diff --git a/ports/xtensa/xcc/src/tx_thread_context_save.S b/ports/xtensa/xcc/src/tx_thread_context_save.S
new file mode 100644
index 00000000..4025ea66
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_thread_context_save.S
@@ -0,0 +1,157 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#include "xtensa_rtos.h"
+#include "tx_api_asm.h"
+
+
+#if XCHAL_HAVE_XEA2
+
+    .text
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This function saves the context of an executing thread in the       */ 
+/*    beginning of interrupt processing.  The function also ensures that  */ 
+/*    the system stack is used upon return to the calling ISR.            */ 
+/*                                                                        */ 
+/*    Interrupts remain disabled and no exceptions are triggered!         */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+//  VOID   _tx_thread_context_save(VOID)
+//  {
+    .globl  _tx_thread_context_save
+    .type   _tx_thread_context_save,@function
+    .align  4
+_tx_thread_context_save:
+
+    /*
+    Please note: Control flow might seem strange. This is because it has been
+    optimized to avoid taken branches in the longest normal path (the critical
+    one for worst-case latency), presumed to be a non-nested interrupt and 
+    non-idle) and to hide pipeline interlock cycles where possible.
+    */
+
+    /*
+    Save a couple of scratch regs to work with that are preserved over the
+    call to _xt_context_save. The latter assumes the interruptee's values 
+    of these are already saved and these regs contain different data to be
+    preserved, so doesn't save them in the stack frame, and thereby requires
+    that its caller have already saved them in the interrupt stack frame.
+    We end up with a12 = return address, a13 and a0 are scratch.
+    */
+    s32i    a12, sp, XT_STK_A12
+    s32i    a13, sp, XT_STK_A13
+
+    /* Check for a nested interrupt condition and increment nesting count.  */
+    //  if (_tx_thread_system_state++)
+    //  {
+    movi    a13, _tx_thread_system_state /* a13 = & interrupt nesting count */
+    mov     a12, a0                      /* a12 = save ret addr (free a0) */
+    l32i    a0,  a13, 0                  /* increment interrupt nesting count */
+    addi    a0,  a0,  1
+    s32i    a0,  a13, 0
+    bnei    a0,  1,   .L_tx_thread_nested_save  /* was !=0 before increment? */
+
+    //  }
+
+.Ln_tx_thread_not_nested_save:
+
+    /* Otherwise, not nested, check to see if a thread was running. */
+    //  else 
+    //  {
+    //      if (_tx_thread_current_ptr)
+    //      {
+    movi    a0,  _tx_thread_current_ptr
+    l32i    a13, a0,  0                  /* a13 = current thread ctrl blk */
+    beqz    a13, .L_tx_thread_idle_system_save
+
+    /* Save the rest of the interrupted context. */
+    call0   _xt_context_save
+
+    /* Save the current stack pointer in the thread's control block. */
+    //          _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+    s32i    sp,  a13, tx_thread_stack_ptr
+
+    //      }
+    /* Switch to the system stack and return to ISR. */
+
+.L_tx_thread_idle_system_save:
+
+    /* 
+    If interrupted in the idle state, it's not necessary to save any context.
+    But even in the idle case where we are already on the system stack, it is 
+    necessary to reset the (system) stack pointer so a series of consecutive 
+    interrupts in the idle state do not keep moving the SP downward.
+    */
+
+    //      sp =  _tx_thread_system_stack_ptr;
+    movi    a13, _tx_thread_system_stack_ptr
+    mov     a0,  a12                     /* retrieve return address */
+    l32i    sp,  a13, 0
+
+    ret
+    //  }
+
+.L_tx_thread_nested_save:
+    /* Nested interrupt condition. */
+    /* Save the rest of the interrupted context and return to ISR. */
+    call0   _xt_context_save
+    
+    mov     a0,  a12                     /* retrieve return address */
+    ret
+
+//  }
+
+#endif /* XCHAL_HAVE_XEA2 */
+
diff --git a/ports/xtensa/xcc/src/tx_thread_interrupt_control.c b/ports/xtensa/xcc/src/tx_thread_interrupt_control.c
new file mode 100644
index 00000000..1a9d42c3
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_thread_interrupt_control.c
@@ -0,0 +1,81 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#include "tx_api.h"
+#include "xtensa_rtos.h"
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This function is responsible for changing the interrupt lockout     */ 
+/*    posture of the system.                                              */ 
+/*    NOTE: In earlier versions this was implemented in assembly.         */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+UINT   _tx_thread_interrupt_control(UINT new_posture)
+{
+#if XCHAL_HAVE_XEA2
+    UINT ret = XT_RSIL(15);
+
+    XT_WSR_PS((ret & ~0xF) | (new_posture & 0xF));
+    XT_RSYNC();
+    return ret & 0xF;
+#else
+    UINT ret = xthal_disable_interrupts();
+
+    xthal_restore_interrupts(new_posture);
+    return ret;
+#endif
+}
+
diff --git a/ports/xtensa/xcc/src/tx_thread_schedule.S b/ports/xtensa/xcc/src/tx_thread_schedule.S
new file mode 100644
index 00000000..287c3530
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_thread_schedule.S
@@ -0,0 +1,253 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#include "tx_port.h"
+#include "xtensa_rtos.h"
+#include "tx_api_asm.h"
+
+    .text
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This function waits for a thread control block pointer to appear in */ 
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+/*    in the variable, the corresponding thread is resumed.               */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+//  VOID   _tx_thread_schedule(VOID)
+//  {
+    .globl  _tx_thread_schedule
+    .type   _tx_thread_schedule,@function
+    .align  4
+_tx_thread_schedule:
+
+#if XCHAL_HAVE_XEA3
+
+    /* Skip "entry" - nothing to save, never returns. */
+
+    movi    a2, PS_STACK_KERNEL | PS_DI     /* Set PS.STACK = Kernel and    */
+    movi    a3, PS_STACK_MASK | PS_DI_MASK  /* disable interrupts.          */
+    xps     a2, a3
+
+#ifdef __XTENSA_CALL0_ABI__
+    mov    a15,  a1                         /* Dispatch code expects a15 = old SP */
+#endif
+
+    movi    a0, _xt_dispatch + 3            /* Jump to dispatch code. It will */
+    ret                                     /* check for ready thread or idle */
+                                            /* and handle accordingly.        */
+
+    ill                                     /* Should never get back here. */
+
+#else
+
+    /*
+    Note on Windowed ABI:
+    Callers of this don't expect it to return to them. Most use 'call0'.
+    The only windowed (C) caller is _tx_initialize_kernel_enter().
+    There are no args or results to pass. So we don't really care if the 
+    window gets rotated. We can omit the 'entry' altogether and avoid the 
+    need for a special "no entry" entrypoint to this function.
+    */
+
+    #ifdef XT_ENABLE_TIMING_TEST_HACK
+    /* For timing_test "TS" numbers. INTERNAL USE ONLY. */
+    /* Always use CALL0. We may be here with windowing disabled. */
+    .extern scheduler_return
+    call0   scheduler_return
+    #endif
+
+    /* 
+    Wait for a thread to execute (Idle Loop).
+    First ensure interrupts (except hi-pri) are disabled so result 
+    of reading _tx_thread_execute_ptr can't change before testing.
+    While there's no thread ready, enable interrupts and wait in a 
+    low power state, then disable interrupts and repeat the test.
+    */
+    //  do
+    //  {
+    movi    a3, _tx_thread_execute_ptr
+.L_tx_thread_schedule_loop:             /* Idle Loop. */
+    XT_INTS_DISABLE(a2)                 /* disable interrupts if not already */
+    l32i    a2, a3, 0                   /* a2 = _tx_thread_execute_ptr */
+    bnez    a2, .L_tx_thread_schedule_ready
+    waiti   0                           /* enable interrupts and wait for */
+                                        /*   interrupt in low power state */
+    j       .L_tx_thread_schedule_loop
+
+    //  }
+    //  while(_tx_thread_execute_ptr == TX_NULL);
+
+.L_tx_thread_schedule_ready:
+    
+    /* Yes! We have a thread to execute.  Lockout interrupts and
+       transfer control to it. Interrupts are already disabled. */
+
+    /* Setup the current thread pointer.  */
+    //  _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+    movi    a3, _tx_thread_current_ptr
+    l32i    a0, a2, tx_thread_run_count
+    s32i    a2, a3, 0                   /* a2 = _tx_thread_current_ptr (TCB) */
+
+    /* Increment the run count for this thread.  */
+    //  _tx_thread_current_ptr -> tx_thread_run_count++;
+    addi    a3, a0, 1
+    movi    a0, _tx_timer_time_slice
+    s32i    a3, a2, tx_thread_run_count
+
+    /* Setup time-slice, if present.  */
+    //  _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+    l32i    a3, a2, tx_thread_time_slice
+    s32i    a3, a0, 0
+
+    #ifdef TX_THREAD_SAFE_CLIB
+    //  Load library-specific global context ptr address.  */
+
+    #if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    movi    a0, _impure_ptr
+    #elif XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    movi    a0, _reent_ptr
+    #else
+    #error TX_THREAD_SAFE_CLIB defined with unsupported C library.
+    #endif
+
+    l32i    a3, a2, tx_thread_clib_ptr
+    s32i    a3, a0, 0                   /* point to thread's reent struct */
+    #endif
+
+    /* Switch to the thread's stack.  */
+    //  SP =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+    l32i    sp, a2, tx_thread_stack_ptr
+
+    #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the thread entry function to indicate the thread is executing. */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   _tx_execution_thread_enter
+    #else
+    call8   _tx_execution_thread_enter
+    #endif
+    #endif
+
+    /* Determine if an interrupt frame or a synchronous task suspension frame
+       is present.  */
+    l32i    a3, a2, tx_thread_solicited
+    bnez    a3, .L_tx_thread_synch_return
+
+.Ln_tx_thread_asynch_return:
+
+    #if XCHAL_CP_NUM > 0
+    /* Restore thread's CPENABLE (enable co-processors this thread owns). */
+    l16ui   a3, a2, tx_thread_cp_state + XT_CPENABLE
+    wsr     a3, CPENABLE
+    #endif
+
+    /* Here we return from unsolicited entry with an interrupt stack frame. */
+    call0   _xt_context_restore
+
+    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14   
+    l32i    a15, sp, XT_STK_A15   
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    rsync                               /* ensure wsr.CPENABLE has completed */
+    #endif
+
+    /*
+    This does not return to its caller, but to the selected thread.
+    Must return via the exit dispatcher corresponding to the entrypoint 
+    from which this was called. Interruptee's A0, A1, PS, PC are restored 
+    and the interrupt stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0,  sp, XT_STK_EXIT   
+    ret
+
+.L_tx_thread_synch_return:
+
+    /* Here we return from a solicited entry with a solicited stack frame. */
+    movi    a0,  TX_FALSE
+    l32i    a3,  sp, XT_STK_PS   
+    s32i    a0,  a2, tx_thread_solicited
+
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a12, sp, XT_STK_A12   
+    l32i    a13, sp, XT_STK_A13   
+    l32i    a14, sp, XT_STK_A14   
+    l32i    a15, sp, XT_STK_A15   
+    #endif
+
+    l32i    a0,  sp, XT_STK_PC          /* return address */
+
+    #if XCHAL_CP_NUM > 0
+    /* CPENABLE should already be clear (it was cleared on entry to kernel). */
+    rsync                               /* ensure wsr.CPENABLE has completed */
+    #endif
+
+    wsr     a3,  PS                     /* no need to sync PS, delay is OK */
+
+    /* This does not return to its caller, but to the selected thread. */
+    #ifdef __XTENSA_CALL0_ABI__
+    /* 'addi sp, sp, imm' could turn into 'addmi, addi' sequence and make */
+    /* the sp briefly point to an illegal stack location. Avoid that.     */
+    addi    a2,  sp, XT_STK_FRMSZ
+    mov     sp,  a2
+    ret
+    #else
+    retw
+    #endif
+
+#endif /* XCHAL_HAVE_XEA3 */
+//  }
+
diff --git a/ports/xtensa/xcc/src/tx_thread_stack_build.S b/ports/xtensa/xcc/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..688e947d
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_thread_stack_build.S
@@ -0,0 +1,158 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#include "xtensa_rtos.h"
+#include "tx_api_asm.h"
+
+    .text
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame looks like an interrupt frame or a solicited frame  */
+/*    depending on the exception architecture of the target hardware.     */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+//  VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+//  {
+    .globl  _tx_thread_stack_build
+    .type   _tx_thread_stack_build,@function
+    .align  4
+_tx_thread_stack_build:
+
+    ENTRY0
+
+    /* Get logical base of stack area (top). */
+    l32i    a5, a2, tx_thread_stack_end /* get top-1 of stack area */
+    addi    a5, a5, 1                   /* undo the -1 */
+    srli    a5, a5, 4                   /* force 16-byte alignment */
+    slli    a5, a5, 4                   /* a5 = post-dispatch SP (frame top) */
+
+    /* Allocate space for the frame (frame size is already 16-byte aligned). */
+    addi    a4, a5, -XT_STK_FRMSZ       /* a4 = pre-dispatch SP (frame base) */
+
+    /* Set the thread's SP. */
+    s32i    a4, a2, tx_thread_stack_ptr
+
+#if !XCHAL_HAVE_XEA2
+    addi    a4, a4, XT_STK_XTRA_SZ      /* a4 = base of exception frame */
+#endif
+
+    /* Clear the entire frame. (XEA3: only exception frame) */
+    movi    a6, 0                       /* a6 = 0 */
+    mov     a7, a4                      /* a7 = ptr to current word */
+1:  s32i    a6, a7, 0                   /* clear current word */
+    addi    a7, a7, 4                   /* point to next word */
+    bltu    a7, a5, 1b                  /* repeat until frame top */
+
+#if XCHAL_HAVE_XEA2
+    s32i    a5, a4, XT_STK_A1           /* save post-dispatch SP in frame */
+#endif
+
+    /* Indicate a solicited or interrupted stack frame. */
+#if XCHAL_HAVE_XEA2
+    movi    a7, 0                       /* interrupted */
+#else
+    movi    a7, 0                       /* solicited */
+#endif
+    s32i    a7, a2, tx_thread_solicited
+
+    /*
+    Terminate GDB backtrace in this thread at the "return function" by ensuring
+    it's A0 == 0. Since frame was cleared, don't need to do this explicitly.
+    s32i    a6, a4, XT_STK_A0
+    */
+
+    /* Set the return address to the return function. */
+    /* Start thread via user exception exit dispatcher (could use any). */
+#if XCHAL_HAVE_XEA2
+    movi    a5, _xt_user_exit
+    s32i    a5, a4, XT_STK_EXIT
+#else
+    movi    a5, 0
+    s32i    a5, a4, XT_STK_ATOMCTL
+#endif
+
+    s32i    a3, a4, XT_STK_PC
+
+    /*
+    Set thread's initial PS for C code, all int levels enabled.
+    XEA2: Since we dispatch via level 1 (_xt_user_exit), must set PS.EXCM,
+      which will be cleared by 'rfe' after the dispatcher, to prevent
+      interrupts happening when PS is restored during the exit dispatcher.
+    XEA3: nothing special, other than setting the thread stack type.
+    */
+#if XCHAL_HAVE_XEA2
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a6, PS_UM | PS_EXCM
+    #else
+    movi    a6, PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1)  /* pretend 'call4' */
+    #endif
+#else
+    movi    a6, PS_STACK_FIRSTKER
+#endif
+    s32i    a6, a4, XT_STK_PS
+
+#if XCHAL_HAVE_XEA2
+    #ifdef XT_USE_SWPRI
+    /* Set the initial virtual priority mask value to all 1's */
+    movi    a3, -1
+    s32i    a3, a4, XT_STK_VPRI
+    #endif
+#endif
+
+    RET0
+
+//  }
+
diff --git a/ports/xtensa/xcc/src/tx_thread_system_return.S b/ports/xtensa/xcc/src/tx_thread_system_return.S
new file mode 100644
index 00000000..e90109c1
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_thread_system_return.S
@@ -0,0 +1,287 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#include "xtensa_rtos.h"
+#include "tx_api_asm.h"
+
+    .text
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This function is target processor specific.  It is used to transfer */ 
+/*    control from a thread back to the system.  Only a minimal context   */ 
+/*    is saved since the compiler assumes temp registers are going to get */ 
+/*    slicked by a function call anyway.                                  */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+//  VOID   _tx_thread_system_return(VOID)
+//  {
+    .globl  _tx_thread_system_return
+    .type   _tx_thread_system_return,@function
+    .align  4
+_tx_thread_system_return:
+    /*
+    Set up solicited stack frame and save minimal context (including a0).
+    Since this is solicited, no need to save regs compiler doesn't preserve.
+    */
+
+#if XCHAL_HAVE_XEA3
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp, sp, -16
+    #else
+    entry   sp, 48
+    #endif
+    s32i    a0, sp, 0                       /* save return address */
+#else
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    a2, sp, -XT_STK_FRMSZ           /* avoid addi/addmi relaxation that */
+    mov     sp, a2                          /* might temporarily move sp up     */
+    #else
+    entry   sp, XT_STK_FRMSZ
+    #endif
+#endif
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the thread exit function to indicate the thread is no longer executing. */
+#ifdef __XTENSA_CALL0_ABI__
+    call0   _tx_execution_thread_exit
+#else
+    call8   _tx_execution_thread_exit
+#endif
+#endif
+
+#if XCHAL_HAVE_XEA3
+
+#ifdef __XTENSA_CALL0_ABI__
+
+#else
+    ssai    0
+    spillw                                  /* spill all registers          */
+#endif
+
+    /*
+    Save register state into exception frame. This is safe to do with
+    interrupts enabled, but we will have to revert SP to point above
+    the exception frame because that is what the dispatch code expects.
+    Must disable interrupts before that.
+    */
+
+    movi    a0, .Lret
+    rsr.ps  a2
+    addi    sp, sp, -XT_STK_XFRM_SZ
+    s32i    a0, sp, XT_STK_PC               /* save return PC               */
+    s32i    a2, sp, XT_STK_PS               /* save PS                      */
+#ifdef __XTENSA_CALL0_ABI__
+    s32i    a12, sp, XT_STK_A12             /* callee-saved registers       */
+    s32i    a13, sp, XT_STK_A13
+    s32i    a14, sp, XT_STK_A14
+    s32i    a15, sp, XT_STK_A15
+#endif
+
+    movi    a2, PS_STACK_KERNEL | PS_DI     /* Set PS.STACK = Kernel and    */
+    movi    a8, PS_STACK_MASK | PS_DI_MASK  /* disable interrupts.          */
+    xps     a2, a8
+
+    movi    a3, _tx_thread_current_ptr      /* a3 = &_tx_thread_current_ptr */
+    movi    a2, TX_TRUE
+    l32i    a4, a3, 0                       /* a4 = _tx_thread_current_ptr  */
+    movi    a5, 0
+    s32i    a2, a4, tx_thread_solicited     /* mark as solicited switch     */
+
+#if XCHAL_CP_NUM > 0
+    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
+    /* should still reflect which CPs were in use (enabled).                */
+    call0   _xt_coproc_savecs
+
+    /* Clear CPENABLE and give up all co-procs. */
+    s16i    a5, a4, tx_thread_cp_state + XT_CPENABLE 
+    wsr     a5, CPENABLE                    /* disable all co-processors    */
+#endif
+
+    addi    sp, sp, XT_STK_XFRM_SZ          /* restore SP                   */
+    addi    a2, sp, -XT_STK_FRMSZ
+    s32i    a2, a4, tx_thread_stack_ptr     /* Save SP in TCB               */
+
+#ifdef __XTENSA_CALL0_ABI__
+    mov     a15, sp                         /* Dispatch code expects a15 = old a1 */
+#endif
+
+    s32i    a5, a3, 0                       /* Clear _tx_thread_current_ptr */
+
+    movi    a0, _xt_dispatch + 3            /* Jump to dispatch code */
+    ret
+
+    /* Execution returns here. Interrupts should be disabled. */
+    /* NOTE: we expect original SP to have been restored. */
+
+    .align  4
+
+.Lret:
+    addi    sp, sp, -XT_STK_XFRM_SZ         /* Prepare to restore state        */
+    l32i    a2, sp, XT_STK_PS               /* Retrieve PS value               */
+#ifdef __XTENSA_CALL0_ABI__
+    l32i    a12, sp, XT_STK_A12             /* Callee-saved registers          */
+    l32i    a13, sp, XT_STK_A13
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+#endif
+    addi    sp, sp, XT_STK_XFRM_SZ
+    wsr.ps  a2                              /* Safe to enable interrupts       */
+    rsync
+
+#ifdef __XTENSA_CALL0_ABI__
+    l32i    a0, sp, 0
+    addi    sp, sp, 16
+    ret
+#else
+    l32i    a0, sp, 0
+    retw
+#endif
+
+#else /* XEA1 or XEA2 */
+
+    rsr     a2,  PS
+    s32i    a0,  sp, XT_STK_PC
+    s32i    a2,  sp, XT_STK_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a12, sp, XT_STK_A12
+    s32i    a13, sp, XT_STK_A13
+    s32i    a14, sp, XT_STK_A14
+    s32i    a15, sp, XT_STK_A15
+    #else
+    /*
+    Spill register windows. Calling xthal_window_spill() causes extra spills and
+    reloads, so we set things up to call the _nw version instead to save cycles.
+    */
+    movi    a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK)     // (using a6 ensures any window using this a4..a7 is spilled)
+    mov     a4, a0                                  // save a0
+    and     a2, a2, a6                              // clear WOE, INTLEVEL
+    addi    a2, a2, XCHAL_EXCM_LEVEL                // set INTLEVEL
+    wsr     a2, PS
+    rsync
+    call0   xthal_window_spill_nw
+    l32i    a0,  sp, XT_STK_PS
+    wsr     a0,  PS                                 // Restore PS value
+    rsync
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
+    /* should still reflect which CPs were in use (enabled).                */
+    call0   _xt_coproc_savecs
+    #endif
+
+    /*
+    We do not return directly from this function to its caller.
+    Register usage from here on:
+        a0  = scratch (return address has been saved in stack frame)
+        a1  = stack ptr (thread, then system)
+        a2  = &_tx_thread_current_ptr
+        a3  = _tx_thread_current_ptr (thread control block)
+        a4  = &_tx_timer_time_slice
+    */
+
+    /* Lock out interrupts (except hi-pri). */
+    /* Grab thread control block of current thread. */
+    movi    a2, _tx_thread_current_ptr      /* a2 = &_tx_thread_current_ptr */
+    XT_INTS_DISABLE(a0)
+    l32i    a3, a2, 0                       /* a3 points to TCB */
+
+    /* Mark as having solicited entry to kernel (used on exit). */
+    movi    a0, TX_TRUE
+    s32i    a0, a3, tx_thread_solicited
+
+    /* Save current stack and switch to system stack. */
+    //  _tx_thread_current_ptr -> tx_thread_stack_ptr =  SP;
+    //  SP = _tx_thread_system_stack_ptr;
+    movi    a5, _tx_thread_system_stack_ptr /* a5 = & system stack ptr */
+    s32i    sp, a3, tx_thread_stack_ptr
+    movi    a4, _tx_timer_time_slice        /* a4 = &_tx_timer_time_slice */
+    l32i    sp, a5, 0                       /* sp = system stack ptr */
+
+    /* Determine if the time-slice is active. */
+    //  if (_tx_timer_time_slice)
+    //  {
+    l32i    a0, a4, 0
+    beqz    a0, .L_tx_thread_dont_save_ts
+
+    /* Save time-slice for the thread and clear current time-slice. */
+    //      _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+    //      _tx_timer_time_slice =  0;
+    s32i    a0, a3, tx_thread_time_slice
+    movi    a0, 0                           /* a0 == 0 == TX_NULL */
+    s32i    a0, a4, 0
+
+    //  }
+
+.L_tx_thread_dont_save_ts:
+
+    /* Clear the current thread pointer. */
+    //  _tx_thread_current_ptr =  TX_NULL;
+    s32i    a0, a2, 0                       /* a0 == 0 == TX_NULL */
+
+    #if XCHAL_CP_NUM > 0
+    /* Clear CPENABLE and give up all co-procs. */
+    s16i    a0, a3, tx_thread_cp_state + XT_CPENABLE
+    wsr     a0, CPENABLE                /* disable all co-processors */
+    #endif
+
+    /* 
+    Return via the scheduler.
+    Scheduler returns eventually to this function's caller as if called by it.
+    */
+    call0   _tx_thread_schedule             /* never returns here */
+
+#endif /* XCHAL_HAVE_XEA3 */
+//  }
+
diff --git a/ports/xtensa/xcc/src/tx_timer_interrupt.S b/ports/xtensa/xcc/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..6fcc5d36
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_timer_interrupt.S
@@ -0,0 +1,277 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#include "xtensa_rtos.h"
+#include "tx_api_asm.h"
+
+#ifndef TX_NO_TIMER
+
+    .text
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    This function processes the hardware timer interrupt.  This         */ 
+/*    processing includes incrementing the system clock and checking for  */ 
+/*    time slice and/or timer expiration.  If either is found, the        */ 
+/*    interrupt context save/restore functions are called along with the  */ 
+/*    expiration functions.                                               */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+//  VOID   _tx_timer_interrupt(VOID)
+//  {
+    .globl  _tx_timer_interrupt
+    .type   _tx_timer_interrupt,@function
+    .align  4
+_tx_timer_interrupt:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Define local variable spill offsets in stack frame for Call0 ABI. */
+    #define __tx_timer_interrupt_a0     0   /* ENTRY()/RET() saves/restores */
+    #define __tx_timer_interrupt_a2     4   /* preserve a2 */
+    #define __tx_timer_interrupt_a3     8   /* preserve a3 */
+    #endif
+
+    ENTRY(16)
+
+    .globl  tx_timer_user_isr
+    .weak   tx_timer_user_isr
+    movi    a2, tx_timer_user_isr
+    beqz    a2, 1f
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a2
+    #else
+    callx8  a2
+    #endif
+1:
+
+    /*
+    Xtensa timers work by comparing a cycle counter with a preset value.
+    Once the match occurs an interrupt is generated, and the handler has 
+    to set a new cycle count into the comparator. To avoid clock drift
+    due to interrupt latency, the new cycle count is computed from the old,
+    not the time the interrupt was serviced. However if a timer interrupt 
+    is ever serviced more than one tick late, it is necessary to process
+    multiple ticks until the new cycle count is in the future, otherwise 
+    the next timer interrupt would not occur until after the cycle counter 
+    had wrapped (2^32 cycles later).
+
+    do {
+        ticks++;
+        old_ccompare = read_ccompare_i();
+        write_ccompare_i( old_ccompare + divisor );
+        service one tick;
+        diff = read_ccount() - old_ccompare;
+    } while ( diff > divisor );
+    */
+
+.L_tx_timer_catchup:
+
+    /* Increment the system clock.  */
+    //  _tx_timer_system_clock++;
+    movi    a2, _tx_timer_system_clock  /* a2 = &_tx_timer_system_clock */
+    l32i    a3, a2, 0                   /* a3 =  _tx_timer_system_clock++ */
+    addi    a3, a3, 1
+    s32i    a3, a2, 0
+
+    /* Update the timer comparator for the next tick. */
+    #ifdef XT_CLOCK_FREQ
+    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment */
+    #else
+    movi    a3, _xt_tick_divisor
+    l32i    a2, a3, 0                   /* a2 = comparator increment */
+    #endif
+    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value */
+    add     a4, a3, a2                  /* a4 = new comparator value */
+    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt */
+    esync
+
+    /* Test for time-slice expiration.  */
+    //  if (_tx_timer_time_slice)
+    //  {
+    movi    a4, _tx_timer_time_slice    /* a4 = &_tx_timer_time_slice */
+    l32i    a5, a4, 0                   /* a5 =  _tx_timer_time_slice */
+    beqz    a5, .L_tx_timer_no_time_slice
+
+    /* Decrement the time_slice.  */
+    //      _tx_timer_time_slice--;
+    addi    a5, a5, -1
+    s32i    a5, a4, 0
+
+    /* Check for expiration.  */
+    //      if (_tx_timer_time_slice == 0)
+    bnez    a5, .L_tx_timer_no_time_slice
+
+    /* Set the time-slice expired flag.  */
+    //          _tx_timer_expired_time_slice =  TX_TRUE;
+    movi    a4, _tx_timer_expired_time_slice
+    movi    a5, TX_TRUE
+    s32i    a5, a4, 0
+
+    //  }
+
+.L_tx_timer_no_time_slice:
+
+    /* Test for timer expiration.  */
+    //  if (*_tx_timer_current_ptr)
+    //  {
+    movi    a4, _tx_timer_current_ptr   /* a4 = &_tx_timer_current_ptr */
+    l32i    a5, a4, 0                   /* a5 =  _tx_timer_current_ptr */
+    l32i    a6, a5, 0                   /* a6 = *_tx_timer_current_ptr */
+    beqz    a6, .L_tx_timer_no_timer
+
+    /* Set expiration flag.  */
+    //      _tx_timer_expired =  TX_TRUE;
+    movi    a6, _tx_timer_expired
+    movi    a7, TX_TRUE
+    s32i    a7, a6, 0
+    j       .L_tx_timer_done
+
+    //  }
+    //  else
+    //  {
+
+.L_tx_timer_no_timer:
+
+    /* No timer expired, increment the timer pointer.  */
+    //      _tx_timer_current_ptr++;
+
+    /* Check for wrap-around.  */
+    //      if (_tx_timer_current_ptr == _tx_timer_list_end)
+    movi    a6, _tx_timer_list_end
+    l32i    a6, a6, 0                   /* a6 =  _tx_timer_list_end */
+    addi    a5, a5, 4                   /* a5 = ++_tx_timer_current_ptr */
+    bne     a5, a6, .L_tx_timer_skip_wrap
+
+    /* Wrap to beginning of list.  */
+    //          _tx_timer_current_ptr =  _tx_timer_list_start;
+    movi    a6, _tx_timer_list_start
+    l32i    a5, a6, 0                   /* a5 =  _tx_timer_list_start */
+
+.L_tx_timer_skip_wrap:
+
+    s32i    a5, a4, 0                   /* _tx_timer_current_ptr = a5 */
+    //  }
+
+.L_tx_timer_done:
+
+    /* See if anything has expired.  */
+    //  if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+    //  {
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Preserve a2 and a3 across calls. */
+    s32i    a2, sp, __tx_timer_interrupt_a2
+    s32i    a3, sp, __tx_timer_interrupt_a3
+    #endif
+
+    /* Did a timer expire?  */
+    //      if (_tx_timer_expired)
+    //      {
+    movi    a4, _tx_timer_expired
+    l32i    a5, a4, 0
+    beqz    a5, .L_tx_timer_dont_activate
+
+    /* Call the timer expiration processing.  */
+    //          _tx_timer_expiration_process();
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   _tx_timer_expiration_process
+    #else
+    call8   _tx_timer_expiration_process
+    #endif
+
+    //      }
+
+.L_tx_timer_dont_activate:
+
+    /* Did time slice expire?  */
+    //      if (_tx_timer_expired_time_slice)
+    //      {
+    movi    a4, _tx_timer_expired_time_slice
+    l32i    a5, a4, 0
+    beqz    a5, .L_tx_timer_not_ts_expiration
+
+    /* Time slice interrupted thread.  */
+    //          _tx_thread_time_slice();
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   _tx_thread_time_slice
+    #else
+    call8   _tx_thread_time_slice
+    #endif
+
+    //      }
+
+.L_tx_timer_not_ts_expiration:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Restore a2 and a3. */
+    l32i    a2, sp, __tx_timer_interrupt_a2
+    l32i    a3, sp, __tx_timer_interrupt_a3
+    #endif
+
+    //  }
+
+.Ln_tx_timer_nothing_expired:
+
+    /* Check if we need to process more ticks to catch up. */
+    esync                               /* ensure comparator update complete */
+    rsr     a4, CCOUNT                  /* a4 = cycle count */
+    sub     a4, a4, a3                  /* diff = ccount - old comparator */
+    blt     a2, a4, .L_tx_timer_catchup /* repeat while diff > divisor */
+
+    RET(16)
+
+//  }
+
+#endif /* TX_NO_TIMER */
+
diff --git a/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c b/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c
new file mode 100644
index 00000000..2d14dd7a
--- /dev/null
+++ b/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c
@@ -0,0 +1,123 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Support for Xtensa applications                                     */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#include "tx_user.h"
+
+#ifdef TX_ENABLE_STACK_CHECKING
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+
+#include "xtensa_rtos.h"
+#ifdef XT_BOARD
+#include <xtensa/xtbsp.h>
+#endif
+#ifdef XT_SIMULATOR
+#include <xtensa/simcall.h>
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  DESCRIPTION                                                           */ 
+/*                                                                        */ 
+/*    Callback to notify of a stack overflow when registered with         */
+/*    tx_stack_error_notify and stack checking is enabled (ThreadX        */
+/*    is compiled with TX_ENABLE_STACK_CHECKING defined).                 */
+/*                                                                        */
+/*    The handler notifies the user in any/all of the following ways:     */
+/*    - A message via the simulator (extremely reliable, simulator only). */
+/*    - A message on the board's display (emulation board only).          */
+/*    - A message to stdout (uses low-level write to avoid printf which   */
+/*      is large and would trash state the user might want to examine).   */
+/*    The most reliable methods are done first. Several might work.       */
+/*                                                                        */
+/*    After notifying the user as best it can, the handler stops the      */
+/*    application in the most reliable of the following ways:             */
+/*    - Passes control to the debugger (if attached).                     */
+/*    - Terminates the simulation (simulator only).                       */
+/*    - Panics.                                                           */
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */ 
+/*                                                                        */ 
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */ 
+/**************************************************************************/ 
+
+VOID  _tx_xtensa_stack_error_handler(TX_THREAD * thread)
+{
+    #ifdef XT_SIMULATOR
+    register int32_t sc  __asm__ ("a2") = SYS_log_msg;
+    register char *  msg __asm__ ("a3") 
+        = "**** Stack overflow in thread 0x%08x.\n";
+    register TX_THREAD * thd __asm__ ("a4") = thread;
+    __asm__ volatile ("simcall" :: "a" (sc), "a" (msg), "a" (thd) );
+    #endif
+
+    #ifdef XT_BOARD
+    xtbsp_display_string("StkOflow");
+    #endif
+
+    write(1, "**** Stack overflow in thread \"", 31);
+    write(1, thread->tx_thread_name, strlen(thread->tx_thread_name));
+    write(1, "\"\n", 2);
+
+    #ifdef XT_SIMULATOR
+    sc = SYS_gdb_abort;
+    __asm__ volatile ("simcall");           /* control to debugger or exit */
+    #else
+    __asm__ volatile ("break 1, 15");       /* control to debugger or panic */
+    #endif
+}
+
+#endif /* TX_ENABLE_STACK_CHECKING */
+
diff --git a/ports/xtensa/xcc/src/xtensa_context.S b/ports/xtensa/xcc/src/xtensa_context.S
new file mode 100644
index 00000000..af3138aa
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_context.S
@@ -0,0 +1,433 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    XTENSA CONTEXT SAVE AND RESTORE ROUTINES                            */
+/*                                                                        */
+/* Low-level functions for handling generic context save and restore of   */
+/* registers not specifically addressed by the interrupt vectors and      */
+/* handlers. Those registers (not handled by these functions) are PC, PS, */
+/* A0, A1 (SP). Except for the calls to RTOS functions, this code is      */
+/* generic to Xtensa.                                                     */
+/*                                                                        */
+/* Note that in Call0 ABI, interrupt handlers are expected to preserve    */
+/* the callee-save regs (A12-A15), which is always the case if the        */
+/* handlers are coded in C. However A12, A13 are made available as        */
+/* scratch registers for interrupt dispatch code, so are presumed saved   */
+/* anyway, and are always restored even in Call0 ABI. Only A14, A15 are   */
+/* truly handled as callee-save regs.                                     */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+
+#include "xtensa_rtos.h"
+
+#ifdef XT_USE_OVLY
+#include <xtensa/overlay_os_asm.h>
+#endif
+
+    .text
+
+#if XCHAL_HAVE_XEA2
+
+/***************************************************************************
+
+    _xt_context_save
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
+interrupt stack frame defined in xtensa_rtos.h.
+Its counterpart is _xt_context_restore (which also restores A12, A13).
+
+Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
+This function preserves A12 & A13 in order to provide the caller with 2 scratch 
+regs that need not be saved over the call to this function. The choice of which
+2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
+to avoid moving data more than necessary. Caller can assign regs accordingly.
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Original A12, A13 have already been saved in the interrupt stack frame.
+    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the 
+    point of interruption.
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    A12, A13 as at entry (preserved).
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+***************************************************************************/
+
+    .global _xt_context_save
+    .type   _xt_context_save,@function
+    .align  4
+_xt_context_save:
+
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a5,  sp, XT_STK_A5
+    s32i    a6,  sp, XT_STK_A6
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a8,  sp, XT_STK_A8
+    s32i    a9,  sp, XT_STK_A9
+    s32i    a10, sp, XT_STK_A10
+    s32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
+    a12-13 are the caller's responsibility so it can use them as scratch.
+    So only need to save a14-a15 here for Windowed ABI (not Call0).
+    */
+    #ifndef __XTENSA_CALL0_ABI__
+    s32i    a14, sp, XT_STK_A14
+    s32i    a15, sp, XT_STK_A15
+    #endif
+
+    rsr     a3,  SAR
+    s32i    a3,  sp, XT_STK_SAR
+
+    #if XCHAL_HAVE_LOOPS
+    rsr     a3,  LBEG
+    s32i    a3,  sp, XT_STK_LBEG
+    rsr     a3,  LEND
+    s32i    a3,  sp, XT_STK_LEND
+    rsr     a3,  LCOUNT
+    s32i    a3,  sp, XT_STK_LCOUNT
+    #endif
+
+    #if XCHAL_HAVE_EXCLUSIVE
+    /* Save and clear state of ATOMCTL */
+    movi    a3,  0
+    getex   a3
+    s32i    a3,  sp, XT_STK_ATOMCTL
+    #endif
+
+    #if XT_USE_SWPRI
+    /* Save virtual priority mask */
+    movi    a3,  _xt_vpri_mask
+    l32i    a3,  a3, 0
+    s32i    a3,  sp, XT_STK_VPRI
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a9,  a0                     /* preserve ret addr */
+    #endif
+
+    #ifndef __XTENSA_CALL0_ABI__
+    /*
+    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
+    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
+    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
+    and underflow exceptions disabled (assured by PS.EXCM == 1).
+    */
+    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
+    s32i    a13, sp, XT_STK_TMP1    
+    s32i    a9,  sp, XT_STK_TMP2    
+
+    /*
+    Save the overlay state if we are supporting overlays. Since we just saved
+    three registers, we can conveniently use them here. Note that as of now,
+    overlays only work for windowed calling ABI.
+    */
+    #ifdef XT_USE_OVLY
+    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
+    _xt_overlay_get_state    a9, a12, a13
+    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
+    #endif
+
+    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
+    l32i    a13, sp, XT_STK_A13
+    l32i    a9,  sp, XT_STK_A9
+    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
+    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
+    addi    sp,  sp, -XT_STK_FRMSZ
+    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
+    l32i    a13, sp, XT_STK_TMP1    
+    l32i    a9,  sp, XT_STK_TMP2    
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_save_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we assume a9,12,13 are preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a0, a9                      /* retrieve ret addr */
+    #endif
+
+    ret
+
+/*******************************************************************************
+
+_xt_context_restore
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
+ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt 
+stack frame defined in xtensa_rtos.h .
+Its counterpart is _xt_context_save (whose caller saved A12, A13).
+
+Caller is responsible to restore PC, PS, A0, A1 (SP).
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Other processor state except PC, PS, A0, A1 (SP), is as at the point 
+    of interruption.
+
+*******************************************************************************/
+
+    .global _xt_context_restore
+    .type   _xt_context_restore,@function
+    .align  4
+_xt_context_restore:
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_restore_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we only assume a13 is preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    mov     a13, a0                     /* preserve ret addr */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
+    mov     a0,  a13                    /* retrieve ret addr */
+    #endif
+
+    #if XCHAL_HAVE_LOOPS
+    l32i    a2,  sp, XT_STK_LBEG
+    l32i    a3,  sp, XT_STK_LEND
+    wsr     a2,  LBEG
+    l32i    a2,  sp, XT_STK_LCOUNT
+    wsr     a3,  LEND
+    wsr     a2,  LCOUNT
+    #endif
+
+    #if XCHAL_HAVE_EXCLUSIVE
+    /* Restore state of ATOMCTL */
+    l32i    a2,  sp, XT_STK_ATOMCTL
+    getex   a2
+    #endif
+
+    #ifdef XT_USE_OVLY
+    /*
+    If we are using overlays, this is a good spot to check if we need
+    to restore an overlay for the incoming task. Here we have a bunch
+    of registers to spare. Note that this step is going to use a few
+    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
+    to be restored.
+    */
+    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
+    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
+    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
+    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
+    _xt_overlay_check_map    a2, a3, a4, a5, a6
+    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
+    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Restore virtual interrupt priority and interrupt enable */
+    movi    a3,  _xt_intdata
+    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
+    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
+    and     a4,  a4, a5
+    wsr     a4,  INTENABLE              /* update INTENABLE */
+    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
+    #endif
+
+    l32i    a3,  sp, XT_STK_SAR
+    l32i    a2,  sp, XT_STK_A2
+    wsr     a3,  SAR
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a6,  sp, XT_STK_A6
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a8,  sp, XT_STK_A8
+    l32i    a9,  sp, XT_STK_A9
+    l32i    a10, sp, XT_STK_A10
+    l32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
+    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), 
+    so need to be restored anyway, despite being callee-saved in Call0.
+    */
+    l32i    a12, sp, XT_STK_A12
+    l32i    a13, sp, XT_STK_A13
+    #ifndef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    ret
+
+#endif /* XCHAL_HAVE_XEA3 */
+
+
+/*******************************************************************************
+
+_xt_coproc_init
+
+Initializes global co-processor management data, setting all co-processors
+to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
+
+Called during initialization of the RTOS, before any threads run.
+
+This may be called from normal Xtensa single-threaded application code which
+might use co-processors. The Xtensa run-time initialization enables all 
+co-processors. They must remain enabled here, else a co-processor exception
+might occur outside of a thread, which the exception handler doesn't expect.
+
+Entry Conditions:
+    Xtensa single-threaded run-time environment is in effect.
+    No thread is yet running.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_init(void)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_init
+    .type   _xt_coproc_init,@function
+    .align  4
+_xt_coproc_init:
+    ENTRY0
+
+    /* Initialize thread co-processor ownerships to 0 (unowned). */
+    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
+    addi    a3, a2, XCHAL_CP_MAX << 2       /* a3 = top+1 of owner array */
+    movi    a4, 0                           /* a4 = 0 (unowned) */
+1:  s32i    a4, a2, 0
+    addi    a2, a2, 4
+    bltu    a2, a3, 1b
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+
+_xt_coproc_release
+
+Releases any and all co-processors owned by a given thread. The thread is 
+identified by it's co-processor state save area defined in xtensa_context.h .
+
+Must be called before a thread's co-proc save area is deleted to avoid
+memory corruption when the exception handler tries to save the state.
+May be called when a thread terminates or completes but does not delete
+the co-proc save area, to avoid the exception handler having to save the 
+thread's co-proc state before another thread can use it (optimization).
+
+Entry Conditions:
+    A2  = Pointer to base of co-processor state save area.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_release(void * coproc_sa_base)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_release
+    .type   _xt_coproc_release,@function
+    .align  4
+_xt_coproc_release:
+    ENTRY0                                  /* a2 = base of save area */
+
+    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
+    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
+    movi    a5, 0                           /* a5 = 0 (unowned) */
+
+#if XCHAL_HAVE_XEA3
+    movi    a6, PS_DI
+    xps     a6, a6                          /* lock interrupts */
+#else
+    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
+#endif
+
+1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
+    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
+    s32i    a5, a3, 0                       /*   owner = unowned */
+2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
+    bltu    a3, a4, 1b                      /* repeat until end of array */
+
+3:
+    wsr     a6, PS                          /* restore interrupts */
+    rsync
+
+    RET0
+
+#endif
+
diff --git a/ports/xtensa/xcc/src/xtensa_coproc_handler.S b/ports/xtensa/xcc/src/xtensa_coproc_handler.S
new file mode 100644
index 00000000..ee55e471
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_coproc_handler.S
@@ -0,0 +1,578 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    Xtensa coprocessor handling routines. This code is only active if   */
+/*    one or more coprocessors are present.                               */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+
+#include <xtensa/config/specreg.h>
+#include <xtensa/coreasm.h>
+
+#include "xtensa_context.h"
+#include "xtensa_rtos.h"
+
+
+#if XCHAL_CP_NUM > 0
+
+//-----------------------------------------------------------------------------
+//  Coprocessor related state and precomputed values.
+//-----------------------------------------------------------------------------
+
+// Table of coprocessor owners, identified by thread's CP save area pointer.
+// Zero means coprocessor is not owned.
+
+        .data
+        .global _xt_coproc_owner_sa
+        .align  16,,XCHAL_CP_MAX << 2   //  minimize crossing cache boundaries
+_xt_coproc_owner_sa:
+        .rept   XCHAL_CP_MAX
+        .word   0
+        .endr
+
+// Bitmask table for CP n's enable bit, indexed by coprocessor number.
+
+        .section .rodata, "a"
+        .global  _xt_coproc_mask
+        .align   16,,8                  // try to keep it all in one cache line
+        .set     i, 0
+_xt_coproc_mask:
+        .rept   XCHAL_CP_MAX
+        .long   (i<<16) | (1<<i)        // upper 16-bits = i, lower = bitmask
+        .set    i, i+1
+        .endr
+
+// Offset to CP n save area in thread's CP save area.
+
+        .global _xt_coproc_sa_offset
+        .align  16                      // minimize crossing cache boundaries
+_xt_coproc_sa_offset:
+        .word   XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
+        .word   XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
+
+
+//-----------------------------------------------------------------------------
+// _xt_coproc_handler
+//
+// Handles coprocessor exceptions and manages lazy context switching between
+// multiple threads sharing the coprocessor(s).
+// Register use:
+//   a0 - on entry, return address (must have been called via call0).
+//   a1 - pointing to valid exception stack frame.
+//   a2 - on entry, must hold coprocessor index. On exit, 0 if OK.
+//   a3-a15 - may all be used and trashed by this routine.
+//-----------------------------------------------------------------------------
+
+        .text
+        .align  4
+        .global _xt_coproc_handler
+
+_xt_coproc_handler:
+
+        mov     a7,  a0                         // a7 = return address
+        mov     a5,  a2                         // a5 = CP index n
+
+        // Get coprocessor state save area of new owner thread
+        call0   XT_RTOS_CP_STATE                // a15 = new owner's save area
+        beqz    a15, .L_xt_coproc_invalid       // not in a thread (invalid)
+        l32i    a4,  a15, XT_CP_ASA             // actual save area address
+        beqz    a4,  .L_xt_coproc_invalid       // thread has no save area
+
+        // Enable the co-processor's bit in CPENABLE
+        movi    a0,  _xt_coproc_mask
+        rsr     a4,  CPENABLE                   // a4 = CPENABLE
+        addx4   a0,  a5, a0                     // a0 = &_xt_coproc_mask[n]
+        l32i    a0,  a0, 0                      // a0 = (n << 16) | (1 << n)
+        movi    a3,  _xt_coproc_owner_sa
+        extui   a2,  a0, 0, 16                  // coprocessor bitmask portion
+        or      a4,  a4, a2                     // a4 = CPENABLE | (1 << n)
+        wsr     a4,  CPENABLE
+
+        // Get old coprocessor owner thread (save area ptr) and assign new one
+        addx4   a3,  a5, a3                     // a3 = &_xt_coproc_owner_sa[n]
+        l32i    a2,  a3, 0                      // a2 = old owner's save area
+        s32i    a15, a3, 0                      // _xt_coproc_owner_sa[n] = new
+        rsync                                   // ensure wsr.CPENABLE is complete
+
+        // Do we need to context-switch this coprocessor ?
+        beq     a15, a2, .L_xt_coproc_done      // new owner == old, we're done
+
+        // if no old owner then nothing to save
+        beqz    a2,  .L_check_new
+
+        // If old owner not actively using CP then nothing to save.
+        l16ui   a4,  a2, XT_CPENABLE            // a4 = old owner's CPENABLE
+        bnone   a4,  a0, .L_check_new           // old owner not using CP
+
+.L_save_old:
+        // We need to save old owner's coprocessor state
+        movi    a5,  _xt_coproc_sa_offset
+
+        // Mark old owner state as no longer active (CPENABLE bit n clear)
+        xor     a4,  a4, a0                     // clear CP in old owner's CPENABLE
+        s16i    a4,  a2, XT_CPENABLE            // update old owner's CPENABLE
+
+        extui   a4,  a0, 16, 5                  // a4 = CP index = n
+        addx4   a5,  a4, a5                     // a5 = &_xt_coproc_sa_offset[n]
+
+        // Mark old owner state as saved (CPSTORED bit n set)
+        l16ui   a4,  a2, XT_CPSTORED            // a4 = old owner's CPSTORED
+        l32i    a5,  a5, 0                      // a5 = XT_CP[n]_SA offset
+        or      a4,  a4, a0                     // set CP in old owner's CPSTORED
+        s16i    a4,  a2, XT_CPSTORED            // update old owner's CPSTORED
+        l32i    a2,  a2, XT_CP_ASA              // ptr to actual (aligned) save area
+        extui   a3,  a0, 16, 5                  // a3 = CP index = n
+        add     a2,  a2, a5                     // a2 = old owner's area for CP n
+
+        // The config-specific HAL macro invoked below destroys a2-a6.
+        // It is theoretically possible for Xtensa processor designers to write TIE
+        // that causes more address registers to be affected, but it is generally
+        // unlikely. If that ever happens, more registers needs to be saved/restored
+        // around this macro invocation, and the value in a15 needs to be recomputed.
+
+        xchal_cpi_store_funcbody
+
+.L_check_new:
+        // Check if any state has to be restored for new owner.
+        // NOTE: a15 = new owner's save area, cannot be zero when we get here.
+
+        l16ui   a3,  a15, XT_CPSTORED           // a3 = new owner's CPSTORED
+        movi    a4,  _xt_coproc_sa_offset
+        bnone   a3,  a0,  .L_check_cs           // full CP not saved, check callee-saved
+        xor     a3,  a3,  a0                    // CPSTORED bit is set, clear it
+        s16i    a3,  a15, XT_CPSTORED           // update new owner's CPSTORED
+
+        // Adjust new owner's save area pointers to area for CP n.
+        extui   a3,  a0, 16, 5                  // a3 = CP index = n
+        addx4   a4,  a3, a4                     // a4 = &_xt_coproc_sa_offset[n]
+        l32i    a4,  a4, 0                      // a4 = XT_CP[n]_SA
+        l32i    a5, a15, XT_CP_ASA              // ptr to actual (aligned) save area
+        add     a2,  a4, a5                     // a2 = new owner's area for CP
+
+        // The config-specific HAL macro invoked below destroys a2-a6.
+        // It is theoretically possible for Xtensa processor designers to write TIE
+        // that causes more address registers to be affected, but it is generally
+        // unlikely. If that ever happens, more registers needs to be saved/restored
+        // around this macro invocation.
+
+        xchal_cpi_load_funcbody
+
+.L_xt_coproc_done:
+        movi    a2,  0                          // a2 <- 0 == OK
+.L_xt_coproc_err:
+        mov     a0,  a7                         // return address
+        ret
+
+.L_check_cs:
+        // a0 = CP mask in low bits, a15 = new owner's save area.
+        l16ui   a2, a15, XT_CP_CS_ST            // a2 = mask of CPs saved
+        bnone   a2,  a0, .L_xt_coproc_done      // if no match then done
+        and     a2,  a2, a0                     // a2 = which CPs to restore
+        extui   a2,  a2, 0, 8                   // extract low 8 bits
+        call0   _xt_coproc_restorecs            // restore CP registers
+        j       .L_xt_coproc_done
+
+.L_xt_coproc_invalid:
+        // Coprocessor exception occurred outside a thread or the thread
+        // did not allocate space to save coprocessor state. Return error.
+        movi    a2,  1
+        j       .L_xt_coproc_err
+
+
+//-----------------------------------------------------------------------------
+// _tx_thread_coproc_state
+//
+// Helper function to return the save area for the current thread, if any.
+// Returns, in a15, the pointer to the save area if any, else zero.
+// If in interrupt context, returns zero. Only uses a15.
+// Must be called only via call0.
+//-----------------------------------------------------------------------------
+
+        .global     _tx_thread_coproc_state
+        .type       _tx_thread_coproc_state,@function
+        .align      4
+
+_tx_thread_coproc_state:
+
+        // return ( _tx_thread_system_state == 0 && _tx_thread_current_ptr != 0 
+        //          ? (&_tx_thread_current_ptr->tx_thread_cp_state) : 0 )
+
+        movi    a15, _tx_thread_system_state    // check if interrupt state
+        l32i    a15, a15, 0
+        bnez    a15, 1f
+        movi    a15, _tx_thread_current_ptr     // check if thread running
+        l32i    a15, a15, 0
+        beqz    a15, 2f
+
+        // Return base address of current thread's co-prcoessor save area.
+        addi    a15, a15, tx_thread_cp_state
+        ret
+1:
+        movi    a15, 0                          // return error
+2:
+        ret
+
+
+//-----------------------------------------------------------------------------
+// _xt_coproc_savecs
+//
+// If there is a current thread and it has a coprocessor state save area, then
+// save all callee-saved state into this area. This function is called from the
+// solicited context switch handler. It calls a system-specific function to get
+// the coprocessor save area base address.
+//
+// Entry conditions:
+//    - The thread being switched out is still the current thread.
+//    - CPENABLE state reflects which coprocessors are active.
+//    - Registers have been saved/spilled already.
+//
+// Exit conditions:
+//    - All necessary CP callee-saved state has been saved.
+//    - Registers a7-a15 have been trashed.
+//
+// Must be called from assembly code only, using CALL0.
+//-----------------------------------------------------------------------------
+
+        .global     _xt_coproc_savecs
+        .type       _xt_coproc_savecs,@function
+        .align      4
+_xt_coproc_savecs:
+
+        // At entry, CPENABLE should be showing which CPs are enabled.
+
+        rsr     a11, CPENABLE                   // a11 = which CPs are enabled
+        beqz    a11, .Ldone                     // quick exit if none
+        mov     a14, a0                         // save return address
+        call0   XT_RTOS_CP_STATE                // get address of CP save area
+        mov     a0, a14                         // restore return address
+        beqz    a15, .Ldone                     // if none then nothing to do
+        l32i    a14, a15, XT_CP_ASA             // a14 = base of aligned save area
+        beqz    a14, .Ldone                     // no save area, nothing to do
+        s16i    a11, a15, XT_CP_CS_ST           // save mask of CPs being stored
+        movi    a13, _xt_coproc_sa_offset       // array of CP save offsets
+        l32i    a15, a15, XT_CP_ASA             // a15 = base of aligned save area
+
+#if XCHAL_CP0_SA_SIZE
+        bbci.l  a11, 0, 2f                      // CP 0 not enabled
+        l32i    a14, a13, 0                     // a14 = _xt_coproc_sa_offset[0]
+        add     a12, a14, a15                   // a12 = save area for CP 0
+        xchal_cp0_store a12, a7, a8, a9, a10 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+        bbci.l  a11, 1, 2f                      // CP 1 not enabled
+        l32i    a14, a13, 4                     // a14 = _xt_coproc_sa_offset[1]
+        add     a12, a14, a15                   // a12 = save area for CP 1
+        xchal_cp1_store a12, a7, a8, a9, a10 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+        bbci.l  a11, 2, 2f
+        l32i    a14, a13, 8
+        add     a12, a14, a15
+        xchal_cp2_store a12, a7, a8, a9, a10 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+        bbci.l  a11, 3, 2f
+        l32i    a14, a13, 12
+        add     a12, a14, a15
+        xchal_cp3_store a12, a7, a8, a9, a10 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+        bbci.l  a11, 4, 2f
+        l32i    a14, a13, 16
+        add     a12, a14, a15
+        xchal_cp4_store a12, a7, a8, a9, a10 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+        bbci.l  a11, 5, 2f
+        l32i    a14, a13, 20
+        add     a12, a14, a15
+        xchal_cp5_store a12, a7, a8, a9, a10 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+        bbci.l  a11, 6, 2f
+        l32i    a14, a13, 24
+        add     a12, a14, a15
+        xchal_cp6_store a12, a7, a8, a9, a10 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+        bbci.l  a11, 7, 2f
+        l32i    a14, a13, 28
+        add     a12, a14, a15
+        xchal_cp7_store a12, a7, a8, a9, a10 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone:
+        ret
+
+
+//-----------------------------------------------------------------------------
+// _xt_coproc_restorecs
+//
+// Restore any callee-saved coprocessor state for the incoming thread.
+// This function is called from coprocessor exception handling, when giving
+// ownership to a thread that solicited a context switch earlier. It calls a
+// system-specific function to get the coprocessor save area base address.
+//
+// Entry conditions:
+//    - The incoming thread is set as the current thread.
+//    - CPENABLE is set up correctly for all required coprocessors.
+//    - a2 = mask of coprocessors to be restored.
+//
+// Exit conditions:
+//    - All necessary CP callee-saved state has been restored.
+//    - CPENABLE - unchanged.
+//    - Registers a2, a8-a15 have been trashed.
+//
+// Must be called from assembly code only, using CALL0.
+//-----------------------------------------------------------------------------
+
+        .global     _xt_coproc_restorecs
+        .type       _xt_coproc_restorecs,@function
+        .align      4
+_xt_coproc_restorecs:
+
+        mov     a14, a0                         // save return address
+        call0   XT_RTOS_CP_STATE                // get address of CP save area
+        mov     a0, a14                         // restore return address
+        beqz    a15, .Ldone2                    // if none then nothing to do
+        l32i    a14, a15, XT_CP_ASA             // a14 = base of aligned save area
+        beqz    a14, .Ldone2                    // no save area, nothing to do
+        l16ui   a13, a15, XT_CP_CS_ST           // a13 = which CPs have been saved
+        xor     a13, a13, a2                    // clear the ones being restored
+        s16i    a13, a15, XT_CP_CS_ST           // update saved CP mask
+        movi    a13, _xt_coproc_sa_offset       // array of CP save offsets
+        l32i    a15, a15, XT_CP_ASA             // a15 = base of aligned save area
+
+#if XCHAL_CP0_SA_SIZE
+        bbci.l  a2, 0, 2f                       // CP 0 not enabled
+        l32i    a14, a13, 0                     // a14 = _xt_coproc_sa_offset[0]
+        add     a12, a14, a15                   // a12 = save area for CP 0
+        xchal_cp0_load a12, a8, a9, a10, a11 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+        bbci.l  a2, 1, 2f                       // CP 1 not enabled
+        l32i    a14, a13, 4                     // a14 = _xt_coproc_sa_offset[1]
+        add     a12, a14, a15                   // a12 = save area for CP 1
+        xchal_cp1_load a12, a8, a9, a10, a11 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+        bbci.l  a2, 2, 2f
+        l32i    a14, a13, 8
+        add     a12, a14, a15
+        xchal_cp2_load a12, a8, a9, a10, a11 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+        bbci.l  a2, 3, 2f
+        l32i    a14, a13, 12
+        add     a12, a14, a15
+        xchal_cp3_load a12, a8, a9, a10, a11 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+        bbci.l  a2, 4, 2f
+        l32i    a14, a13, 16
+        add     a12, a14, a15
+        xchal_cp4_load a12, a8, a9, a10, a11 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+        bbci.l  a2, 5, 2f
+        l32i    a14, a13, 20
+        add     a12, a14, a15
+        xchal_cp5_load a12, a8, a9, a10, a11 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+        bbci.l  a2, 6, 2f
+        l32i    a14, a13, 24
+        add     a12, a14, a15
+        xchal_cp6_load a12, a8, a9, a10, a11 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+        bbci.l  a2, 7, 2f
+        l32i    a14, a13, 28
+        add     a12, a14, a15
+        xchal_cp7_load a12, a8, a9, a10, a11 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone2:
+        ret
+
+
+#if XCHAL_HAVE_XEA3
+
+//-----------------------------------------------------------------------------
+//  For XEA3, coprocessor exceptions come here. This is a wrapper function that
+//  calls _xt_coproc_handler() to do the actual work. Since the handler can be
+//  interrupted make sure that no context switch occurs.
+//-----------------------------------------------------------------------------
+
+        .text
+        .global     _xt_coproc_exc
+        .type       _xt_coproc_exc,@function
+        .align      4
+
+_xt_coproc_exc:
+#ifdef __XTENSA_CALL0_ABI__
+    addi    a1,  a1, -16                    // reserve 16 bytes on stack
+    s32i    a0,  a1, 0                      // save return address
+    s32i    a2,  a1, 4                      // save a2
+    s32i   a15,  a1, 8                      // must save a15 (see dispatch)
+    l32i    a2,  a1, 4
+    l32i    a3,  a2, XT_STK_EXCCAUSE        // a3 <- exccause
+    extui   a2,  a3, 8, 4                   // a2 <- CP index
+    call0   _xt_coproc_handler
+    l32i    a0,  a1, 0                      // restore return address
+    l32i   a15,  a1, 8                      // restore a15
+    addi    a1,  a1, 16
+    ret
+#else
+    entry   a1,  48                         // reserve 16 bytes on stack
+    s32i    a0,  a1, 0                      // save return address
+    l32i    a3,  a2, XT_STK_EXCCAUSE        // a3 <- exccause
+    extui   a2,  a3, 8, 4                   // a2 <- CP index
+    call0   _xt_coproc_handler
+    l32i    a0,  a1, 0                      // restore return address
+    retw
+#endif
+
+#endif // XCHAL_HAVE_XEA3
+
+
+#if XCHAL_HAVE_XEA2
+
+//-----------------------------------------------------------------------------
+//  XEA2 coprocessor exception dispatcher. Save enough state to be able to call
+//  the coprocessor handler, then restore and return.
+//-----------------------------------------------------------------------------
+
+        .text
+        .global     _xt_coproc_exc
+        .type       _xt_coproc_exc,@function
+        .align      4
+  
+_xt_coproc_exc:
+    
+        mov     a0, sp                          // Allocate stack frame
+        addi    sp, sp, -XT_STK_FRMSZ
+        s32i    a0, sp, XT_STK_A1               // save SP
+#if XCHAL_HAVE_WINDOWED
+        s32e    a0, sp, -12                     // for debug backtrace
+#endif  
+        rsr     a0, PS
+        s32i    a0, sp, XT_STK_PS               // save PS
+        rsr     a0, EPC_1
+        s32i    a0, sp, XT_STK_PC               // save PC
+        rsr     a0, EXCSAVE_1
+        s32i    a0, sp, XT_STK_A0               // retrieve and save a0
+#if XCHAL_HAVE_WINDOWED
+        s32e    a0, sp, -16                     // for debug backtrace
+#endif
+        s32i    a2, sp, XT_STK_A2
+        s32i    a3, sp, XT_STK_A3
+        s32i    a4, sp, XT_STK_A4
+        s32i    a5, sp, XT_STK_A5
+        s32i    a6, sp, XT_STK_A6
+        s32i    a7, sp, XT_STK_A7
+        s32i    a8, sp, XT_STK_A8
+        s32i    a9, sp, XT_STK_A9
+        s32i    a10, sp, XT_STK_A10
+        s32i    a11, sp, XT_STK_A11
+        s32i    a12, sp, XT_STK_A12
+        s32i    a13, sp, XT_STK_A13
+        s32i    a14, sp, XT_STK_A14
+        s32i    a15, sp, XT_STK_A15
+
+        rsr     a3, EXCCAUSE                    // a3 <- exccause
+        addi    a2, a3, -EXCCAUSE_CP0_DISABLED  // a2 <- CP index
+        call0   _xt_coproc_handler
+
+        mov     a0, a2                          // save return value
+        l32i    a2, sp, XT_STK_A2
+        l32i    a3, sp, XT_STK_A3
+        l32i    a4, sp, XT_STK_A4
+        l32i    a5, sp, XT_STK_A5
+        l32i    a6, sp, XT_STK_A6
+        l32i    a7, sp, XT_STK_A7
+        l32i    a8, sp, XT_STK_A8
+        l32i    a9, sp, XT_STK_A9
+        l32i    a10, sp, XT_STK_A10
+        l32i    a11, sp, XT_STK_A11
+        l32i    a12, sp, XT_STK_A12
+        l32i    a13, sp, XT_STK_A13
+        l32i    a14, sp, XT_STK_A14
+        l32i    a15, sp, XT_STK_A15
+        bnez    a0, .Lfail                      // abort if failure
+        l32i    a0, sp, XT_STK_PC
+        wsr     a0, EPC_1                       // restore PC
+        l32i    a0, sp, XT_STK_PS
+        wsr     a0, PS                          // restore PS
+        l32i    a0, sp, XT_STK_A0
+        addi    a1, a1, XT_STK_FRMSZ            // deallocate stack frame
+        rfe
+
+.Lfail:
+        call0   _xt_panic
+
+#endif // XCHAL_HAVE_XEA2
+
+#endif // XCHAL_CP_NUM > 0
+
diff --git a/ports/xtensa/xcc/src/xtensa_init.c b/ports/xtensa/xcc/src/xtensa_init.c
new file mode 100644
index 00000000..0359028c
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_init.c
@@ -0,0 +1,67 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    Xtensa initialization routines.                                     */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+
+#ifdef XT_BOARD
+#include    <xtensa/xtbsp.h>
+#endif
+
+#include    "xtensa_rtos.h"
+
+
+#ifdef XT_RTOS_TIMER_INT
+#ifndef XT_CLOCK_FREQ
+
+uint32_t _xt_tick_divisor = 0;  /* cached number of cycles per tick */
+
+/*
+Compute and initialize at run-time the tick divisor (the number of 
+processor clock cycles in an RTOS tick, used to set the tick timer).
+Called when the processor clock frequency is not known at compile-time.
+*/
+void _xt_tick_divisor_init(void)
+{
+    #ifdef XT_BOARD
+    _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
+    #else
+    #error "No way to obtain processor clock frequency"
+    #endif  /* XT_BOARD */
+}
+
+#endif /* XT_CLOCK_FREQ */
+#endif /* XT_RTOS_TIMER_INT */
+
diff --git a/ports/xtensa/xcc/src/xtensa_intr.c b/ports/xtensa/xcc/src/xtensa_intr.c
new file mode 100644
index 00000000..c5f320cb
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_intr.c
@@ -0,0 +1,213 @@
+/*******************************************************************************
+Copyright (c) 2006-2019 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+******************************************************************************/
+
+/******************************************************************************
+  Xtensa-specific interrupt and exception functions for RTOS ports.
+  Also see xtensa_intr_asm.S.
+******************************************************************************/
+
+#include <stdlib.h>
+
+#include <xtensa/config/core.h>
+#include <xtensa/core-macros.h>
+
+#include "xtensa_api.h"
+
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
+
+
+/*
+  Default handler for unhandled exceptions.
+*/
+void xt_unhandled_exception(XtExcFrame *frame)
+{
+    (void) frame; /* Keep compiler happy */
+    exit(-1);
+}
+
+
+/*
+  This function registers a handler for the specified exception.
+  The function returns the address of the previous handler.
+  On error, it returns 0.
+*/
+xt_exc_handler xt_set_exception_handler(uint32_t n, xt_exc_handler f)
+{
+    xt_exc_handler old;
+
+    if (n >= XCHAL_EXCCAUSE_NUM) {
+        return 0;       /* invalid exception number */
+    }
+
+    old = _xt_exception_table[n];
+
+    if (f != NULL) {
+        _xt_exception_table[n] = f;
+    }
+    else {
+        _xt_exception_table[n] = &xt_unhandled_exception;
+    }
+
+    return old;
+}
+
+#endif
+
+#if XCHAL_HAVE_INTERRUPTS
+
+#if XCHAL_HAVE_XEA2
+/* Defined in xtensa_intr_asm.S */
+extern uint32_t _xt_intenable;
+extern uint32_t _xt_vpri_mask;
+#endif
+
+/* Handler table is in xtensa_intr_asm.S */
+
+typedef struct xt_handler_table_entry {
+    void * handler;
+    void * arg;
+} xt_handler_table_entry;
+
+#if (XT_USE_INT_WRAPPER || XCHAL_HAVE_XEA3)
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS + 1];
+#else
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];
+#endif
+
+
+/*
+  Default handler for unhandled interrupts.
+*/
+void xt_unhandled_interrupt(void * arg)
+{
+    (void) arg; /* Keep compiler happy */
+    exit(-1);
+}
+
+
+/*
+  This function registers a handler for the specified interrupt. The "arg"
+  parameter specifies the argument to be passed to the handler when it is
+  invoked. The function returns the address of the previous handler.
+  On error, it returns 0.
+*/
+xt_handler xt_set_interrupt_handler(uint32_t n, xt_handler f, void * arg)
+{
+    xt_handler_table_entry * entry;
+    xt_handler               old;
+
+    if (n >= XCHAL_NUM_INTERRUPTS) {
+        return 0;       /* invalid interrupt number */
+    }
+
+#if XCHAL_HAVE_XEA2
+    if (Xthal_intlevel[n] > XCHAL_EXCM_LEVEL) {
+        return 0;       /* priority level too high to safely handle in C */
+    }
+#endif
+
+#if (XT_USE_INT_WRAPPER || XCHAL_HAVE_XEA3)
+    entry = _xt_interrupt_table + n + 1;
+#else
+    entry = _xt_interrupt_table + n;
+#endif
+    old   = entry->handler;
+
+    if (f != NULL) {
+        entry->handler = f;
+        entry->arg     = arg;
+    }
+    else {
+        entry->handler = &xt_unhandled_interrupt;
+        entry->arg     = (void*)n;
+    }
+
+    return old;
+}
+
+
+/*
+  This function enables the interrupt whose number is specified as
+  the argument.
+*/
+void xt_interrupt_enable(uint32_t intnum)
+{
+#if XCHAL_HAVE_XEA2
+    uint32_t ps = XT_RSIL(15);
+
+    // New INTENABLE = (_xt_intenable | mask) & _xt_vpri_mask.
+    _xt_intenable |= (1 << intnum);
+    XT_WSR_INTENABLE(_xt_intenable & _xt_vpri_mask);
+    XT_WSR_PS(ps);
+    XT_RSYNC();
+#else
+    xthal_interrupt_enable(intnum);
+#endif
+}
+
+
+/*
+  This function disables the interrupt whose number is specified as
+  the argument.
+*/
+void xt_interrupt_disable(uint32_t intnum)
+{
+#if XCHAL_HAVE_XEA2
+    uint32_t ps = XT_RSIL(15);
+
+    // New INTENABLE = (_xt_intenable & ~mask) & _xt_vpri_mask.
+    _xt_intenable &= ~(1 << intnum);
+    XT_WSR_INTENABLE(_xt_intenable & _xt_vpri_mask);
+    XT_WSR_PS(ps);
+    XT_RSYNC();
+#else
+    xthal_interrupt_disable(intnum);
+#endif
+}
+
+
+/*
+  This function triggers the specified interrupt.
+*/
+void xt_interrupt_trigger(uint32_t intnum)
+{
+    xthal_interrupt_trigger(intnum);
+}
+
+
+/*
+  This function clears the specified interrupt.
+*/
+void xt_interrupt_clear(uint32_t intnum)
+{
+    xthal_interrupt_clear(intnum);
+}
+
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
+
diff --git a/ports/xtensa/xcc/src/xtensa_intr_asm.S b/ports/xtensa/xcc/src/xtensa_intr_asm.S
new file mode 100644
index 00000000..78fd8a70
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_intr_asm.S
@@ -0,0 +1,156 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    Xtensa interrupt handling data and assembly routines.               */
+/*    Also see xtensa_intr.c.                                             */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+
+#include "tx_port.h"
+#include "xtensa_context.h"
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/*
+-------------------------------------------------------------------------------
+  INTENABLE virtualization information.
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_HAVE_XEA2
+
+    .data
+    .global _xt_intdata
+    .align  8
+_xt_intdata:
+    .global _xt_intenable
+    .type   _xt_intenable,@object
+    .size   _xt_intenable,4
+    .global _xt_vpri_mask
+    .type   _xt_vpri_mask,@object
+    .size   _xt_vpri_mask,4
+
+_xt_intenable:     .word   0             /* Virtual INTENABLE     */
+_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
+
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  System interrupt stack.
+-------------------------------------------------------------------------------
+*/
+
+#if (XCHAL_HAVE_XEA2 || XCHAL_HAVE_ISB)
+    .data
+#else
+    .section    .intr.top, "aw"
+#endif
+
+    .global _xt_interrupt_stack
+    .global _xt_interrupt_stack_top
+    .align  16
+
+_xt_interrupt_stack:
+    .space  TX_SYSTEM_STACK_SIZE
+_xt_interrupt_stack_top:
+
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable interrupt handlers for each interrupt. For XEA2 configs,
+  not all slots can be filled, because interrupts at level > EXCM_LEVEL will
+  not be dispatched to a C handler by default.
+-------------------------------------------------------------------------------
+*/
+
+#if (XCHAL_HAVE_XEA2 || XCHAL_HAVE_ISB)
+    .data
+#else
+    .section    .intr.data, "aw"
+#endif
+
+    .global _xt_interrupt_table
+    .align  16
+
+_xt_interrupt_table:
+
+/*
+-------------------------------------------------------------------------------
+  If using the interrupt wrapper, make the first entry in the interrupt table
+  point to the wrapper (XEA3) or leave it empty (XEA2).
+-------------------------------------------------------------------------------
+*/
+#if XCHAL_HAVE_XEA3
+    .word   xt_interrupt_wrapper
+    .word   0
+#elif XT_USE_INT_WRAPPER
+    .word   0
+    .word   0
+#endif
+
+    .set    i, 0
+    .rept   XCHAL_NUM_INTERRUPTS
+    .word   xt_unhandled_interrupt      /* handler address               */
+    .word   i                           /* handler arg (default: intnum) */
+    .set    i, i+1
+    .endr
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
+
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable exception handlers for each exception. Note that not all
+  slots will be active, because some exceptions (e.g. coprocessor exceptions)
+  are always handled by the OS and cannot be hooked by user handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_exception_table
+    .align  4
+
+_xt_exception_table:
+    .rept   XCHAL_EXCCAUSE_NUM
+    .word   xt_unhandled_exception    /* handler address */
+    .endr
+
+#endif
+
diff --git a/ports/xtensa/xcc/src/xtensa_intr_wrapper.c b/ports/xtensa/xcc/src/xtensa_intr_wrapper.c
new file mode 100644
index 00000000..ff70f4ea
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_intr_wrapper.c
@@ -0,0 +1,125 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*  Xtensa-specific interrupt handler wrapper.                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+
+#include <xtensa/config/core.h>
+#include <xtensa/core-macros.h>
+
+#include "xtensa_rtos.h"
+#include "xtensa_api.h"
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+#include "tx_execution_profile.h"
+#endif
+
+
+#if (XCHAL_HAVE_XEA3 && XCHAL_HAVE_INTERRUPTS)
+
+/* Table of interrupt hooks. Used for testing ONLY. */
+#ifdef XT_INTEXC_HOOKS
+volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
+#endif
+
+
+/* Handler table is in xtensa_intr_asm.S */
+
+typedef struct xt_handler_table_entry {
+    void * handler;
+    void * arg;
+} xt_handler_table_entry;
+
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS + 1];
+extern int32_t xt_sw_intnum;
+
+static int32_t xt_wflag;
+
+
+/**************************************************************************/
+/*    Wrapper for interrupt handlers. Argument is (intnum << 2).          */
+/*    Execution comes here from the dispatch code if the wrapper is       */
+/*    enabled.                                                            */
+/**************************************************************************/
+void
+xt_interrupt_wrapper(void * arg)
+{
+    uint32_t                 intnum = (uint32_t)(arg) >> 2;
+    xt_handler_table_entry * entry;
+    xt_handler               handler;
+
+    /* Increment interrupt nest counter. */
+    _tx_thread_system_state++;
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the ISR enter function to indicate an ISR is executing. */
+    _tx_execution_isr_enter();
+#endif
+
+    /* Load handler address and argument from table. Note that the
+       first entry in the table points to this wrapper, so we have
+       to skip ahead one.
+     */
+    entry = _xt_interrupt_table + intnum + 1;
+    handler = (xt_handler) entry->handler;
+
+    (*handler)(entry->arg);
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the ISR exit function to indicate an ISR is complete. */
+    _tx_execution_isr_exit();
+#endif
+
+    /* If a context switch is pending, trigger the SW interrupt
+       to process the switch. Set an internal flag so we don't
+       trigger the sw interrupt again when handling it.
+     */
+    if (xt_wflag != 0) {
+        xt_wflag = 0;
+    }
+    else if (_tx_thread_current_ptr != _tx_thread_execute_ptr) {
+        xt_wflag = 1;
+        xt_interrupt_trigger(xt_sw_intnum);
+    }
+
+    /* Decrement interrupt nest counter. */
+    _tx_thread_system_state--;
+}
+
+#endif /* XCHAL_HAVE_XEA3 && XCHAL_HAVE_INTERRUPTS */
+
diff --git a/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c b/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c
new file mode 100644
index 00000000..8fd92701
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c
@@ -0,0 +1,109 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*  Xtensa overlay manager OS hooks for ThreadX. XEA2 only.               */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+
+#ifdef XT_USE_OVLY
+
+#include <xtensa/overlay.h>
+#include "tx_api.h"
+
+
+/* Required to work around a bug in the overlay header. */
+#ifdef XT_DISABLE_OVERLAYS
+#undef  xt_overlay_fatal_error
+#define xt_overlay_fatal_error(id)    
+#endif
+
+
+/* Mutex object that controls access to the overlay. Currently only one
+ * overlay region is supported so one mutex suffices.
+ */
+static TX_MUTEX xt_overlay_mutex;
+
+
+/**************************************************************************/
+/*  This function should be overridden to provide OS specific init such   */
+/*  as the creation of a mutex lock that can be used for overlay locking. */
+/*  Typically this mutex would be set up with priority inheritance. See   */
+/* overlay manager documentation for more details.                        */
+/**************************************************************************/
+void
+xt_overlay_init_os(void)
+{
+    /* Create the mutex for overlay access. Priority inheritance is
+     * required.
+     */
+    UINT status = 
+        tx_mutex_create (&xt_overlay_mutex, "xt_overlay_lock", TX_INHERIT);
+
+    if (status != TX_SUCCESS) {
+        xt_overlay_fatal_error (-1);
+    }
+}
+
+
+/**************************************************************************/
+/* This function locks access to shared overlay resources, typically      */
+/* by acquiring a mutex.                                                  */
+/**************************************************************************/
+void
+xt_overlay_lock(void)
+{
+    UINT status = tx_mutex_get (&xt_overlay_mutex, TX_WAIT_FOREVER);
+
+    if (status != TX_SUCCESS) {
+        xt_overlay_fatal_error (-1);
+    }
+}
+
+
+/**************************************************************************/
+/* This function releases access to shared overlay resources, typically   */
+/* by unlocking a mutex.                                                  */
+/**************************************************************************/
+void
+xt_overlay_unlock(void)
+{
+    UINT status = tx_mutex_put (&xt_overlay_mutex);
+
+    if (status != TX_SUCCESS) {
+        xt_overlay_fatal_error (-1);
+    }
+}
+
+#endif /* XT_USE_OVLY */
+
diff --git a/ports/xtensa/xcc/src/xtensa_vectors.S b/ports/xtensa/xcc/src/xtensa_vectors.S
new file mode 100644
index 00000000..b115abf5
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_vectors.S
@@ -0,0 +1,1696 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*  Xtensa exception and interrupt dispatch for XEA2.                     */
+/*                                                                        */
+/*  Interrupt handlers and user exception handlers support interaction    */
+/*  with the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT       */
+/*  before and after calling the user's specific interrupt handlers.      */
+/*                                                                        */
+/*  Users can install application-specific interrupt handlers for low and */
+/*  medium priority interrupts, by calling xt_set_interrupt_handler().    */
+/*  These handlers can be written in C and must follow the C calling      */
+/*  convention. The handler table is indexed by the interrupt number.     */
+/*  Each handler may be provided with an argument.                        */
+/*                                                                        */
+/*  Note that the system timer interrupt is handled specially, and is     */
+/*  dispatched to the RTOS-specific handler. This timer cannot be hooked  */
+/*  by application code.                                                  */
+/*                                                                        */
+/*  Optional hooks are also provided to install a handler per level at    */
+/*  run-time, made available by compiling this source file with           */
+/*  '-DXT_INTEXC_HOOKS' (useful for automated testing).                   */
+/*                                                                        */
+/*  Search for locations marked USER_EDIT for helpful comments on where   */
+/*  to insert application-specific code and how to write them.            */
+/*                                                                        */
+/*  Users can install application-specific exception handlers in the      */
+/*  same way, by calling xt_set_exception_handler(). One handler slot is  */
+/*  provided for each exception type. Note that some exceptions are       */
+/*  handled by the porting layer itself, and cannot be taken over by      */
+/*  application code. These are the alloca, syscall, and coprocessor      */
+/*  exceptions.                                                           */
+/*                                                                        */
+/*  Exception handlers can be written in C, and must follow C calling     */
+/*  convention. Each handler is passed a pointer to an exception frame as */
+/*  its single argument. The exception frame is created on the stack and  */
+/*  holds the saved context of the thread that took the exception. If the */
+/*  handler returns, the context will be restored and the instruction     */
+/*  that caused the exception will be retried. If the handler makes any   */
+/*  changes to the saved state in the exception frame, the changes will   */
+/*  be applied when restoring the context.                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+
+#include "xtensa_rtos.h"
+
+
+#if XCHAL_HAVE_XEA2
+
+/* Enable stack backtrace across exception/interrupt - see below */
+#define XT_DEBUG_BACKTRACE    1
+
+
+/*
+--------------------------------------------------------------------------------
+  Defines used to access _xtos_interrupt_table.
+--------------------------------------------------------------------------------
+*/
+#define XIE_HANDLER     0
+#define XIE_ARG         4
+#define XIE_SIZE        8
+
+/*
+--------------------------------------------------------------------------------
+  Macro extract_msb - return the input with only the highest bit set.
+
+  Input  : "ain"  - Input value, clobbered.
+  Output : "aout" - Output value, has only one bit set, MSB of "ain".
+  The two arguments must be different AR registers.
+--------------------------------------------------------------------------------
+*/
+
+    .macro  extract_msb     aout ain
+1:
+    addi    \aout, \ain, -1         /* aout = ain - 1        */
+    and     \ain, \ain, \aout       /* ain  = ain & aout     */
+    bnez    \ain, 1b                /* repeat until ain == 0 */
+    addi    \aout, \aout, 1         /* return aout + 1       */
+    .endm
+
+/*
+--------------------------------------------------------------------------------
+  Macro dispatch_c_isr - dispatch interrupts to user ISRs.
+  This will dispatch to user handlers (if any) that are registered in the
+  XTOS dispatch table (_xtos_interrupt_table). These handlers would have
+  been registered by calling _xtos_set_interrupt_handler(). There is one
+  exception - the timer interrupt used by the OS will not be dispatched
+  to a user handler - this must be handled by the caller of this macro.
+
+  Level triggered and software interrupts are automatically deasserted by
+  this code.
+
+  ASSUMPTIONS:
+    -- PS.INTLEVEL is set to "level" at entry
+    -- PS.EXCM = 0, C calling enabled
+
+  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
+
+  NOTE: This macro will use registers a0 and a2-a6. The arguments are:
+    level -- interrupt level
+    mask  -- interrupt bitmask for this level
+--------------------------------------------------------------------------------
+*/
+
+    .macro  dispatch_c_isr    level  mask
+
+    /* Get mask of pending, enabled interrupts at this level into a2. */
+
+.L_xt_user_int_&level&:
+    rsr     a2, INTENABLE
+    rsr     a3, INTERRUPT
+    movi    a4, \mask
+    and     a2, a2, a3
+    and     a2, a2, a4
+    beqz    a2, 9f                          /* nothing to do */
+
+    /* This bit of code provides a nice debug backtrace in the debugger.
+       It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
+       if you want to save the cycles.
+    */
+    #if XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EPC_1 + \level - 1          /* return address */
+    movi    a4, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    or      a0, a0, a4                      /* set top 2 bits */
+    addx2   a0, a4, a0                      /* clear top bit -- simulating call4 size   */
+    #endif
+    #endif
+
+    #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the ISR enter function to indicate an ISR is executing. */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   _tx_execution_isr_enter
+    #else
+    call4   _tx_execution_isr_enter
+    #endif
+    #endif
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, \level << 2
+    beqz    a4, 2f
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqz    a2, 9f
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqz    a6, 9f
+    mov     a2, a6
+    #endif
+2:
+    #endif
+
+    /* Now look up in the dispatch table and call user ISR if any. */
+    /* If multiple bits are set then MSB has highest priority.     */
+
+    extract_msb  a4, a2                     /* a4 = MSB of a2, a2 trashed */
+
+    #ifdef XT_USE_SWPRI
+    /* Enable all interrupts at this level that are numerically higher
+       than the one we just selected, since they are treated as higher
+       priority.
+    */
+    movi    a3, \mask                       /* a3 = all interrupts at this level */
+    add     a2, a4, a4                      /* a2 = a4 << 1 */
+    addi    a2, a2, -1                      /* a2 = mask of 1's <= a4 bit */
+    and     a2, a2, a3                      /* a2 = mask of all bits <= a4 at this level */
+    movi    a3, _xt_intdata
+    l32i    a6, a3, 4                       /* a6 = _xt_vpri_mask */
+    neg     a2, a2
+    addi    a2, a2, -1                      /* a2 = mask to apply */
+    and     a5, a6, a2                      /* mask off all bits <= a4 bit */
+    s32i    a5, a3, 4                       /* update _xt_vpri_mask */
+    rsr     a3, INTENABLE
+    and     a3, a3, a2                      /* mask off all bits <= a4 bit */
+    wsr     a3, INTENABLE
+    rsil    a3, \level - 1                  /* lower interrupt level by 1 */
+    #endif
+
+    wsr     a4, INTCLEAR                    /* clear sw or edge-triggered interrupt */
+
+    #ifndef TX_NO_TIMER
+    movi    a3, XT_TIMER_INTEN              /* a3 = timer interrupt bit */
+    beq     a3, a4, 7f                      /* if timer interrupt then skip table */
+    #endif
+
+    find_ms_setbit a3, a4, a3, 0            /* a3 = interrupt number */
+
+    movi    a4, _xt_interrupt_table
+    addx8   a3, a3, a4                      /* a3 = address of interrupt table entry */
+    l32i    a4, a3, XIE_HANDLER             /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6                         /* save in callee-saved reg */
+    l32i    a2, a3, XIE_ARG                 /* a2 = handler arg */
+    callx0  a4                              /* call handler */
+    mov     a2, a12
+    #else
+    mov     a2, a6                          /* save in windowed reg */
+    l32i    a6, a3, XIE_ARG                 /* a6 = handler arg */
+    callx4  a4                              /* call handler */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+7:
+
+    #ifndef TX_NO_TIMER
+    .ifeq XT_TIMER_INTPRI - \level
+.L_xt_user_int_timer_&level&:
+    /*
+    Interrupt handler for the RTOS tick timer if at this level.
+    We'll be reading the interrupt state again after this call
+    so no need to preserve any registers except a6 (vpri_mask).
+    */
+
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6
+    call0   XT_RTOS_TIMER_INT
+    mov     a2, a12
+    #else
+    mov     a2, a6
+    call4   XT_RTOS_TIMER_INT
+    #endif
+    .endif
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+8:
+    /*
+    Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
+    virtual _xt_intenable which _could_ have changed during interrupt
+    processing. But before that, raise the interrupt level back again.
+    */
+
+    rsil    a3, \level
+    movi    a3, _xt_intdata
+    l32i    a4, a3, 0                       /* a4 = _xt_intenable    */
+    s32i    a2, a3, 4                       /* update _xt_vpri_mask  */
+    and     a4, a4, a2                      /* a4 = masked intenable */
+    wsr     a4, INTENABLE                   /* update INTENABLE      */
+    #endif
+
+9:
+    /* done */
+
+    #if XCHAL_HAVE_EXCLUSIVE
+    /* Clear any local exclusive monitors. */
+    clrex
+    #endif
+
+    .endm
+
+
+/*
+--------------------------------------------------------------------------------
+  Panic handler.
+  Should be reached by call0 (preferable) or jump only. If call0, a0 says where 
+  from. If on simulator, display panic message and abort, else loop indefinitely.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+    .global     _xt_panic
+    .type       _xt_panic,@function
+    .align      4
+
+_xt_panic:
+    #ifdef XT_SIMULATOR
+    addi    a4, a0, -3                      /* point to call0 */
+    movi    a3, _xt_panic_message
+    movi    a2, SYS_log_msg
+    simcall
+    movi    a2, SYS_gdb_abort
+    simcall
+    #else
+    rsil    a2, XCHAL_EXCM_LEVEL            /* disable all low & med ints */
+1:  j       1b                              /* loop infinitely */
+    #endif
+
+    .section    .rodata, "a"
+    .align      4
+
+_xt_panic_message:
+    .string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n"
+
+
+/*
+--------------------------------------------------------------------------------
+    Hooks to dynamically install handlers for exceptions and interrupts.
+    Allows automated regression frameworks to install handlers per test.
+    Consists of an array of function pointers indexed by interrupt level, 
+    with index 0 containing the entry for user exceptions.
+    Initialized with all 0s, meaning no handler is installed at each level.
+    See comment in xtensa_rtos.h for more details.
+--------------------------------------------------------------------------------
+*/
+
+    #ifdef XT_INTEXC_HOOKS
+    .data
+    .global     _xt_intexc_hooks
+    .type       _xt_intexc_hooks,@object
+    .align      4
+
+_xt_intexc_hooks:
+    .fill       XT_INTEXC_HOOK_NUM, 4, 0
+    #endif
+
+
+/*
+--------------------------------------------------------------------------------
+  EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
+  (except window exception vectors).
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+--------------------------------------------------------------------------------
+*/
+
+
+/*
+--------------------------------------------------------------------------------
+Debug Exception.
+--------------------------------------------------------------------------------
+*/
+
+#if XCHAL_HAVE_DEBUG
+
+    .begin      literal_prefix .DebugExceptionVector
+    .section    .DebugExceptionVector.text, "ax"
+    .global     _DebugExceptionVector
+    .align      4
+
+_DebugExceptionVector:
+
+    #ifdef XT_SIMULATOR
+    /*
+    In the simulator, let the debugger (if any) handle the debug exception,
+    or simply stop the simulation:
+    */
+    wsr     a2, EXCSAVE+XCHAL_DEBUGLEVEL    /* save a2 where sim expects it */
+    movi    a2, SYS_gdb_enter_sktloop
+    simcall                                 /* have ISS handle debug exc. */
+    #elif 0 /* change condition to 1 to use the HAL minimal debug handler */
+    wsr     a3, EXCSAVE+XCHAL_DEBUGLEVEL
+    movi    a3, xthal_debugexc_defhndlr_nw  /* use default debug handler */
+    jx      a3
+    #else
+    wsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL    /* save original a0 somewhere */
+    call0   _xt_panic                       /* does not return */
+    rfi     XCHAL_DEBUGLEVEL                /* make a0 point here not later */
+    #endif
+
+    .end        literal_prefix
+
+#endif
+
+/*
+--------------------------------------------------------------------------------
+Double Exception.
+Double exceptions are not a normal occurrence. They indicate a bug of some kind.
+--------------------------------------------------------------------------------
+*/
+
+#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
+
+    .begin      literal_prefix .DoubleExceptionVector
+    .section    .DoubleExceptionVector.text, "ax"
+    .global     _DoubleExceptionVector
+    .align      4
+
+_DoubleExceptionVector:
+
+    #if XCHAL_HAVE_DEBUG
+    break   1, 4                            /* unhandled double exception */
+    #endif
+    call0   _xt_panic                       /* does not return */
+    rfde                                    /* make a0 point here not later */
+
+    .end        literal_prefix
+
+#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
+
+/*
+--------------------------------------------------------------------------------
+Kernel Exception (including Level 1 Interrupt from kernel mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .KernelExceptionVector
+    .section    .KernelExceptionVector.text, "ax"
+    .global     _KernelExceptionVector
+    .align      4
+
+_KernelExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_kernel_exc                  /* kernel exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .align      4
+
+_xt_kernel_exc:
+    #if XCHAL_HAVE_DEBUG
+    break   1, 0                            /* unhandled kernel exception */
+    #endif
+    call0   _xt_panic                       /* does not return */
+    rfe                                     /* make a0 point here not there */
+
+
+/*
+--------------------------------------------------------------------------------
+User Exception (including Level 1 Interrupt from user mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .UserExceptionVector
+    .section    .UserExceptionVector.text, "ax"
+    .global     _UserExceptionVector
+    .type       _UserExceptionVector,@function
+    .align      4
+
+_UserExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_user_exc                    /* user exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+/*
+--------------------------------------------------------------------------------
+  Insert some waypoints for jumping beyond the signed 8-bit range of
+  conditional branch instructions, so the conditional branchces to specific
+  exception handlers are not taken in the mainline. Saves some cycles in the
+  mainline.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+
+    #if XCHAL_HAVE_WINDOWED
+    .align      4
+_xt_to_alloca_exc:
+    call0   _xt_alloca_exc                  /* in window vectors section */
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+    .align      4
+_xt_to_syscall_exc:
+    call0   _xt_syscall_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    #if XCHAL_CP_NUM > 0
+    .align      4
+_xt_to_coproc_exc:
+    call0   _xt_coproc_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+
+/*
+--------------------------------------------------------------------------------
+  User exception handler.
+--------------------------------------------------------------------------------
+*/
+
+    .type       _xt_user_exc,@function
+    .align      4
+
+_xt_user_exc:
+
+    /* If level 1 interrupt then jump to the dispatcher */
+    rsr     a0, EXCCAUSE
+    beqi    a0, EXCCAUSE_LEVEL1_INTERRUPT, _xt_lowint1
+
+    /* Handle any coprocessor exceptions. Rely on the fact that exception
+       numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
+    */
+    #if XCHAL_CP_NUM > 0
+    bgeui   a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
+    #endif
+
+    /* Handle alloca and syscall exceptions */
+    #if XCHAL_HAVE_WINDOWED
+    beqi    a0, EXCCAUSE_ALLOCA,  _xt_to_alloca_exc
+    #endif
+    beqi    a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
+
+    /* Handle all other exceptions. All can have user-defined handlers. */
+    /* NOTE: we'll stay on the user stack for exception handling.       */
+
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save exc cause and vaddr into exception frame */
+    rsr     a0, EXCCAUSE
+    s32i    a0, sp, XT_STK_EXCCAUSE
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EPC_1                       /* return address for debug backtrace */
+    movi    a5, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    rsync                                   /* wait for WSR.PS to complete */
+    or      a0, a0, a5                      /* set top 2 bits */
+    addx2   a0, a5, a0                      /* clear top bit -- thus simulating call4 size */
+    #else
+    rsync                                   /* wait for WSR.PS to complete */
+    #endif
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+
+    #ifdef XT_INTEXC_HOOKS
+    /*
+    Call exception hook to pre-handle exceptions (if installed).
+    Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
+    */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, 0                       /* user exception hook index 0 */
+    beqz    a4, 1f
+.Ln_xt_user_exc_call_hook:
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqi    a2, -1, .L_xt_user_done
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqi    a6, -1, .L_xt_user_done
+    mov     a2, a6
+    #endif
+1:
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+    movi    a3, _xt_exception_table
+    addx4   a4, a2, a3                      /* a4 = address of exception table entry */
+    l32i    a4, a4, 0                       /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a2, sp                          /* a2 = pointer to exc frame */
+    callx0  a4                              /* call handler */
+    #else
+    mov     a6, sp                          /* a6 = pointer to exc frame */
+    callx4  a4                              /* call handler */
+    #endif
+
+.L_xt_user_done:
+
+    /* Restore context and return */
+    call0   _xt_context_restore
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+--------------------------------------------------------------------------------
+  Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+  on entry and used to return to a thread or interrupted interrupt handler.
+--------------------------------------------------------------------------------
+*/
+
+    .global     _xt_user_exit
+    .type       _xt_user_exit,@function
+    .align      4
+_xt_user_exit:
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+--------------------------------------------------------------------------------
+Syscall Exception Handler (jumped to from User Exception Handler).
+Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
+Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+    .type       _xt_syscall_exc,@function
+    .align      4
+_xt_syscall_exc:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /*
+    Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
+    Use a minimal stack frame (16B) to save A2 & A3 for scratch.
+    PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
+    rsr     a0, PS
+    addi    a0, a0, -PS_EXCM_MASK
+    wsr     a0, PS
+    */
+    addi    sp, sp, -16
+    s32i    a2, sp, 8
+    s32i    a3, sp, 12
+    #else   /* Windowed ABI */
+    /*
+    Save necessary context and spill the register windows.
+    PS.EXCM is still set and must remain set until after the spill.
+    Reuse context save function though it saves more than necessary.
+    For this reason, a full interrupt stack frame is allocated.
+    */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+    #endif
+
+    /*
+    Grab the interruptee's PC and skip over the 'syscall' instruction.
+    If it's at the end of a zero-overhead loop and it's not on the last
+    iteration, decrement loop counter and skip to beginning of loop.
+    */
+    rsr     a2, EPC_1                       /* a2 = PC of 'syscall' */
+    addi    a3, a2, 3                       /* ++PC                 */
+    #if XCHAL_HAVE_LOOPS
+    rsr     a0, LEND                        /* if (PC == LEND       */
+    bne     a3, a0, 1f
+    rsr     a0, LCOUNT                      /*     && LCOUNT != 0)  */
+    beqz    a0, 1f                          /* {                    */
+    addi    a0, a0, -1                      /*   --LCOUNT           */
+    rsr     a3, LBEG                        /*   PC = LBEG          */
+    wsr     a0, LCOUNT                      /* }                    */
+    #endif
+1:  wsr     a3, EPC_1                       /* update PC            */
+
+    /* Restore interruptee's context and return from exception. */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a2, sp, 8
+    l32i    a3, sp, 12
+    addi    sp, sp, 16
+    #else
+    call0   _xt_context_restore
+    addi    sp, sp, XT_STK_FRMSZ
+    #endif
+    movi    a0, -1
+    movnez  a2, a0, a2                      /* return -1 if not syscall 0 */
+    rsr     a0, EXCSAVE_1
+    rfe
+
+
+/*
+-------------------------------------------------------------------------------
+  Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet.
+-------------------------------------------------------------------------------
+*/
+
+    .text   
+    .type       _xt_lowint1,@function
+    .align      4
+
+_xt_lowint1:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_user_exit               /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */ 
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(1) | PS_UM
+    #else 
+    movi    a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+
+/*
+-------------------------------------------------------------------------------
+  MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS.
+
+  Medium priority interrupts are by definition those with priority greater
+  than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by
+  setting PS.EXCM and therefore can easily support a C environment for
+  handlers in C, and interact safely with an RTOS.
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_EXCM_LEVEL >= 2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   _xt_medint2                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint2,@function
+    .align      4
+_xt_medint2:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_2                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_2                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_2                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint2_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(2) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint2_exit
+    .type       _xt_medint2_exit,@function
+    .align      4
+_xt_medint2_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_2
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_2
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_EXCM_LEVEL >= 3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   _xt_medint3                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint3,@function
+    .align      4
+_xt_medint3:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_3                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_3                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_3                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint3_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(3) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint3_exit
+    .type       _xt_medint3_exit,@function
+    .align      4
+_xt_medint3_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_3
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_3
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_EXCM_LEVEL >= 4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   _xt_medint4                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint4,@function
+    .align      4
+_xt_medint4:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_4                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_4                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint4_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(4) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint4_exit
+    .type       _xt_medint4_exit,@function
+    .align      4
+_xt_medint4_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_4
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_4
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_EXCM_LEVEL >= 5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   _xt_medint5                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint5,@function
+    .align      4
+_xt_medint5:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_5                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_5                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_5                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint5_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(5) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint5_exit
+    .type       _xt_medint5_exit,@function
+    .align      4
+_xt_medint5_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_5
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_5
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     5
+
+#endif  /* Level 5 */
+
+#if XCHAL_EXCM_LEVEL >= 6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   _xt_medint6                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint6,@function
+    .align      4
+_xt_medint6:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_6                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_6                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_6                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint6_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(6) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint6_exit
+    .type       _xt_medint6_exit,@function
+    .align      4
+_xt_medint6_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_6
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_6
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     6
+
+#endif  /* Level 6 */
+
+
+/*******************************************************************************
+
+HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
+
+High priority interrupts are by definition those with priorities greater
+than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
+interrupts cannot interact with the RTOS, that is they must save all regs
+they use and not call any RTOS function.
+
+A further restriction imposed by the Xtensa windowed architecture is that
+high priority interrupts must not modify the stack area even logically
+"above" the top of the interrupted stack (they need to provide their
+own stack or static save area).
+
+Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
+and used for purposes requiring very short service times.
+
+Here are templates for high priority (level 2+) interrupt vectors.
+They assume only one interrupt per level to avoid the burden of identifying
+which interrupts at this level are pending and enabled. This allows for 
+minimum latency and avoids having to save/restore a2 in addition to a0.
+If more than one interrupt per high priority level is configured, this burden
+is on the handler which in any case must provide a way to save and restore
+registers it uses without touching the interrupted stack.
+
+Each vector goes at a predetermined location according to the Xtensa
+hardware configuration, which is ensured by its placement in a special
+section known to the Xtensa linker support package (LSP). It performs
+the minimum necessary before jumping to the handler in the .text section.
+
+*******************************************************************************/
+
+/*
+Currently only shells for high priority interrupt handlers are provided
+here. However a template and example can be found in the Cadence Design Systems tools
+documentation: "Microprocessor Programmer's Guide".
+*/
+
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   _xt_highint2                    /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint2,@function
+    .align      4
+_xt_highint2:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 2<<2
+    beqz    a0, 1f
+.Ln_xt_highint2_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint2_exit:
+    rsr     a0, EXCSAVE_2                   /* restore a0 */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   _xt_highint3                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint3,@function
+    .align      4
+_xt_highint3:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 3<<2
+    beqz    a0, 1f
+.Ln_xt_highint3_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint3_exit:
+    rsr     a0, EXCSAVE_3                   /* restore a0 */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   _xt_highint4                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint4,@function
+    .align      4
+_xt_highint4:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 4<<2
+    beqz    a0, 1f
+.Ln_xt_highint4_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint4_exit:
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   _xt_highint5                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint5,@function
+    .align      4
+_xt_highint5:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 5<<2
+    beqz    a0, 1f
+.Ln_xt_highint5_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint5_exit:
+    rsr     a0, EXCSAVE_5                   /* restore a0 */
+    rfi     5
+
+#endif  /* Level 5 */
+
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   _xt_highint6                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint6,@function
+    .align      4
+_xt_highint6:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 6<<2
+    beqz    a0, 1f
+.Ln_xt_highint6_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint6_exit:
+    rsr     a0, EXCSAVE_6                   /* restore a0 */
+    rfi     6
+
+#endif  /* Level 6 */
+
+#if XCHAL_HAVE_NMI
+
+    .begin      literal_prefix .NMIExceptionVector
+    .section    .NMIExceptionVector.text, "ax"
+    .global     _NMIExceptionVector
+    .type       _NMIExceptionVector,@function
+    .align      4
+_NMIExceptionVector:
+    wsr     a0, EXCSAVE + XCHAL_NMILEVEL  _ /* preserve a0 */
+    call0   _xt_nmi                         /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_nmi,@function
+    .align      4
+_xt_nmi:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, XCHAL_NMILEVEL<<2
+    beqz    a0, 1f
+.Ln_xt_nmi_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_nmi_exit:
+    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
+    rfi     XCHAL_NMILEVEL
+
+#endif  /* NMI */
+
+
+/*******************************************************************************
+
+WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
+
+Here is the code for each window overflow/underflow exception vector and 
+(interspersed) efficient code for handling the alloca exception cause.
+Window exceptions are handled entirely in the vector area and are very
+tight for performance. The alloca exception is also handled entirely in 
+the window vector area so comes at essentially no cost in code size.
+Users should never need to modify them and Cadence Design Systems recommends 
+they do not.
+
+Window handlers go at predetermined vector locations according to the
+Xtensa hardware configuration, which is ensured by their placement in a
+special section known to the Xtensa linker support package (LSP). Since
+their offsets in that section are always the same, the LSPs do not define
+a section per vector.
+
+These things are coded for XEA2 only (XEA1 is not supported).
+
+Note on Underflow Handlers:
+The underflow handler for returning from call[i+1] to call[i]
+must preserve all the registers from call[i+1]'s window.
+In particular, a0 and a1 must be preserved because the RETW instruction
+will be reexecuted (and may even underflow if an intervening exception
+has flushed call[i]'s registers).
+Registers a2 and up may contain return values.
+
+*******************************************************************************/
+
+#if XCHAL_HAVE_WINDOWED
+
+    .section .WindowVectors.text, "ax"
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call4.
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call4 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a3 are registers to be saved;
+        a4-a15 must be preserved;
+        a5 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x0
+    .global _WindowOverflow4
+_WindowOverflow4:
+
+    s32e    a0, a5, -16     /* save a0 to call[j+1]'s stack frame */
+    s32e    a1, a5, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a5,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a5,  -4     /* save a3 to call[j+1]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call4
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call4 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
+        a4-a15 must be preserved (they are call[i+1].reg[0..11]);
+        a5 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x40
+    .global _WindowUnderflow4
+_WindowUnderflow4:
+
+    l32e    a0, a5, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a5, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a5,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a3, a5,  -4     /* restore a3 from call[i+1]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Handle alloca exception generated by interruptee executing 'movsp'.
+This uses space between the window vectors, so is essentially "free".
+All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
+and PS.EXCM has been set by the exception hardware (can't be interrupted).
+The fact the alloca exception was taken means the registers associated with
+the base-save area have been spilled and will be restored by the underflow
+handler, so those 4 registers are available for scratch.
+The code is optimized to avoid unaligned branches and minimize cache misses.
+--------------------------------------------------------------------------------
+*/
+
+    .align  4
+    .global _xt_alloca_exc
+_xt_alloca_exc:
+
+    rsr     a0, WINDOWBASE  /* grab WINDOWBASE before rotw changes it */
+    rotw    -1              /* WINDOWBASE goes to a4, new a0-a3 are scratch */
+    rsr     a2, PS
+    extui   a3, a2, PS_OWB_SHIFT, PS_OWB_BITS
+    xor     a3, a3, a4      /* bits changed from old to current windowbase */
+    rsr     a4, EXCSAVE_1   /* restore original a0 (now in a4) */
+    slli    a3, a3, PS_OWB_SHIFT
+    xor     a2, a2, a3      /* flip changed bits in old window base */
+    wsr     a2, PS          /* update PS.OWB to new window base */
+    rsync
+
+    _bbci.l a4, 31, _WindowUnderflow4
+    rotw    -1              /* original a0 goes to a8 */
+    _bbci.l a8, 30, _WindowUnderflow8
+    rotw    -1
+    j               _WindowUnderflow12
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call8
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call8 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a7 are registers to be saved;
+        a8-a15 must be preserved;
+        a9 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x80
+    .global _WindowOverflow8
+_WindowOverflow8:
+
+    s32e    a0, a9, -16     /* save a0 to call[j+1]'s stack frame */
+    l32e    a0, a1, -12     /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1, a9, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a9,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a9,  -4     /* save a3 to call[j+1]'s stack frame */
+    s32e    a4, a0, -32     /* save a4 to call[j]'s stack frame */
+    s32e    a5, a0, -28     /* save a5 to call[j]'s stack frame */
+    s32e    a6, a0, -24     /* save a6 to call[j]'s stack frame */
+    s32e    a7, a0, -20     /* save a7 to call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call8
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call8 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
+        a8-a15 must be preserved (they are call[i+1].reg[0..7]);
+        a9 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0xC0
+    .global _WindowUnderflow8
+_WindowUnderflow8:
+
+    l32e    a0, a9, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a9, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a9,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a7, a1, -12     /* a7 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3, a9,  -4     /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4, a7, -32     /* restore a4 from call[i]'s stack frame */
+    l32e    a5, a7, -28     /* restore a5 from call[i]'s stack frame */
+    l32e    a6, a7, -24     /* restore a6 from call[i]'s stack frame */
+    l32e    a7, a7, -20     /* restore a7 from call[i]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call12
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call12 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a11 are registers to be saved;
+        a12-a15 must be preserved;
+        a13 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x100
+    .global _WindowOverflow12
+_WindowOverflow12:
+
+    s32e    a0,  a13, -16   /* save a0 to call[j+1]'s stack frame */
+    l32e    a0,  a1,  -12   /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1,  a13, -12   /* save a1 to call[j+1]'s stack frame */
+    s32e    a2,  a13,  -8   /* save a2 to call[j+1]'s stack frame */
+    s32e    a3,  a13,  -4   /* save a3 to call[j+1]'s stack frame */
+    s32e    a4,  a0,  -48   /* save a4 to end of call[j]'s stack frame */
+    s32e    a5,  a0,  -44   /* save a5 to end of call[j]'s stack frame */
+    s32e    a6,  a0,  -40   /* save a6 to end of call[j]'s stack frame */
+    s32e    a7,  a0,  -36   /* save a7 to end of call[j]'s stack frame */
+    s32e    a8,  a0,  -32   /* save a8 to end of call[j]'s stack frame */
+    s32e    a9,  a0,  -28   /* save a9 to end of call[j]'s stack frame */
+    s32e    a10, a0,  -24   /* save a10 to end of call[j]'s stack frame */
+    s32e    a11, a0,  -20   /* save a11 to end of call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call12
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call12 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
+        a12-a15 must be preserved (they are call[i+1].reg[0..3]);
+        a13 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org 0x140
+    .global _WindowUnderflow12
+_WindowUnderflow12:
+
+    l32e    a0,  a13, -16   /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1,  a13, -12   /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2,  a13,  -8   /* restore a2 from call[i+1]'s stack frame */
+    l32e    a11, a1,  -12   /* a11 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3,  a13,  -4   /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4,  a11, -48   /* restore a4 from end of call[i]'s stack frame */
+    l32e    a5,  a11, -44   /* restore a5 from end of call[i]'s stack frame */
+    l32e    a6,  a11, -40   /* restore a6 from end of call[i]'s stack frame */
+    l32e    a7,  a11, -36   /* restore a7 from end of call[i]'s stack frame */
+    l32e    a8,  a11, -32   /* restore a8 from end of call[i]'s stack frame */
+    l32e    a9,  a11, -28   /* restore a9 from end of call[i]'s stack frame */
+    l32e    a10, a11, -24   /* restore a10 from end of call[i]'s stack frame */
+    l32e    a11, a11, -20   /* restore a11 from end of call[i]'s stack frame */
+    rfwu
+
+#endif /* XCHAL_HAVE_WINDOWED */
+
+#endif /* XCHAL_HAVE_XEA2 */
+
diff --git a/ports/xtensa/xcc/src/xtensa_vectors_xea3.S b/ports/xtensa/xcc/src/xtensa_vectors_xea3.S
new file mode 100644
index 00000000..5596a75c
--- /dev/null
+++ b/ports/xtensa/xcc/src/xtensa_vectors_xea3.S
@@ -0,0 +1,392 @@
+/**************************************************************************/
+/*   Copyright (c) Cadence Design Systems, Inc.                           */
+/*                                                                        */
+/* Permission is hereby granted, free of charge, to any person obtaining  */
+/* a copy of this software and associated documentation files (the        */
+/* "Software"), to deal in the Software without restriction, including    */
+/* without limitation the rights to use, copy, modify, merge, publish,    */
+/* distribute, sublicense, and/or sell copies of the Software, and to     */
+/* permit persons to whom the Software is furnished to do so, subject to  */
+/* the following conditions:                                              */
+/*                                                                        */
+/* The above copyright notice and this permission notice shall be         */
+/* included in all copies or substantial portions of the Software.        */
+/*                                                                        */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
+/**************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*  Xtensa exception and interrupt dispatch for XEA3.                     */
+/*                                                                        */
+/*  Interrupt handlers and user exception handlers support interaction    */
+/*  with the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT       */
+/*  before and after calling the user's specific interrupt handlers.      */
+/*                                                                        */
+/*  Users can install application-specific interrupt handlers by calling  */
+/*  xt_set_interrupt_handler(). These handlers can be written in C and    */
+/*  must follow the C calling convention. The handler table is indexed by */
+/*  the interrupt number. Each handler may be provided with an argument.  */
+/*                                                                        */
+/*  Users can install application-specific exception handlers in the      */
+/*  same way, by calling xt_set_exception_handler(). One handler slot is  */
+/*  provided for each exception type. Note that some exceptions are       */
+/*  handled by the porting layer itself, and cannot be taken over by      */
+/*  application code. These are the alloca, syscall, and coprocessor      */
+/*  exceptions.                                                           */
+/*                                                                        */
+/*  Exception handlers can be written in C, and must follow C calling     */
+/*  convention. Each handler is passed a pointer to an exception frame as */
+/*  its single argument. The exception frame is created on the stack and  */
+/*  holds the saved context of the thread that took the exception. If the */
+/*  handler returns, the context will be restored and the instruction     */
+/*  that caused the exception will be retried. If the handler makes any   */
+/*  changes to the saved state in the exception frame, the changes will   */
+/*  be applied when restoring the context.                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+
+#include <xtensa/config/core.h>
+#include <xtensa/coreasm.h>
+
+#if XCHAL_HAVE_XEA3
+
+#include "xtensa_context.h"
+
+#if (XCHAL_HW_VERSION < XTENSA_HWVERSION_RH_2016_2)
+#error Xtensa HW earlier than RH_2016.2 not supported.
+#endif
+
+
+//-----------------------------------------------------------------------------
+// The entry point vectors are common for call0 and windowed configurations.
+//-----------------------------------------------------------------------------
+
+        .extern _DoubleExceptionHandler
+        .extern _xtos_exc_dispatch
+
+        .section .DispatchVector.text, "ax"
+#if XCHAL_HAVE_VECBASE
+        .align  64                      // 64-byte alignment needed when vecbase
+#else                                   // is relocatable
+        .align  4
+#endif
+
+        .org    0                       // Fixed offset for Reset Vector
+        .global _DispatchVector
+        .weak   _DispatchVector
+
+_DispatchVector:
+        j       _JumpToResetHandler
+
+        .org    3                       // Reserved
+        .local  _Reserved1
+
+_Reserved1:
+        ill
+
+        .org    6                       // Fixed offset for Double Exception Vector
+        .global _DoubleExceptionVector
+        .weak   _DoubleExceptionVector
+
+_DoubleExceptionVector:
+        j       _DoubleExceptionHandler
+
+        .org    9                       // Reserved
+        .local  _Reserved2
+
+_Reserved2:
+        ill
+
+//-----------------------------------------------------------------------------
+// Start of dispatch code.
+//-----------------------------------------------------------------------------
+
+        .org    12                      // Fixed offset for Tailchain entry point
+        .global _xt_dispatch
+
+_xt_dispatch:
+#ifdef __XTENSA_CALL0_ABI__
+
+        // NOTE: for call0, a15 is expected to be holding the previous stack pointer
+        // when we get to the Tailchain segment.
+
+        s32si.x4         a2, a15        // Select interrupt, a2 <- (intnum << 2)
+        movi             a0,   0
+        l32dis.it        a0,  a0        // a0 <- wrapper addr (handler_table[0])
+        s32stk           a9, a15, 96    // Set new stack pointer
+#if XT_STK_XTRA_SZ
+        addi             a1,  a1, -XT_STK_XTRA_SZ       // Adjust for extra save area
+#endif
+        s32dis.h         a0,  a0        // Jump to handler if interrupt else fall through
+                                        // Note this also clears local exclusive monitor
+
+#else // windowed
+
+        s32si.x4        a10,  a1        // Select interrupt, a10 <- (intnum << 2)
+        movi             a8,   0
+        l32dis.it        a8,  a8        // a8 <- wrapper addr (handler_table[0])
+        s32stk           a9,  a1, 96    // Set new stack pointer
+#if XT_STK_XTRA_SZ
+        addi             a9,  a9, -XT_STK_XTRA_SZ       // Adjust for extra save area
+#endif
+        s32dis.h         a8,  a8        // Jump to handler if interrupt else fall through
+                                        // Note this also clears local exclusive monitor
+
+#endif // __XTENSA_CALL0_ABI__
+
+.Lexit:
+        j       _xt_exit
+
+#ifndef __XTENSA_CALL0_ABI__
+        .org    36                      // Fixed offset for Underflow segment
+        .global _xt_underflow
+
+_xt_underflow:
+        l32e     a8,  a1, -64           //  a8 <- [a1-32]
+        l32e     a9,  a1, -64           //  a9 <- [a1-28]
+        l32e    a10,  a1, -64           // a10 <- [a1-24]
+        l32e    a11,  a1, -64           // a11 <- [a1-20]
+        l32e    a12,  a1, -64           // a12 <- [a1-16]
+        l32e    a13,  a1, -64           // a13 <- [a1-12]
+        l32e    a14,  a1, -64           // a14 <- [a1-8]
+        l32e    a15,  a1, -64           // a15 <- [a1-4] ; Return (branch to EPC)
+#endif
+
+        .org    60                      // Fixed offset for Save/Overflow segment
+        .global _xt_save
+
+_xt_save:
+#ifdef __XTENSA_CALL0_ABI__
+        s32e     a0,  a1, -64           // [a1-64] <-  a0
+        s32e     a2,  a1, -48           // [a1-56] <-  a2 ; a2 <- EPC
+        s32e     a3,  a1, -64           // [a1-52] <-  a3
+        s32e     a4,  a1, -64           // [a1-48] <-  a4
+        s32e     a5,  a1, -64           // [a1-44] <-  a5
+        s32e     a6,  a1, -64           // [a1-40] <-  a6
+        s32e     a7,  a1, -64           // [a1-36] <-  a7
+#else
+        .global _xt_overflow
+_xt_overflow:
+#endif
+        s32e     a8,  a1, -52           // [a1-32] <-  a8 ;  a8 <- ExcVAddr
+        s32e     a9,  a1, -28           // [a1-28] <-  a9 ;  a9 <- PS/SAR
+        s32e    a10,  a1, -48           // [a1-24] <- a10 ; a10 <- EPC
+        s32e    a11,  a1, -24           // [a1-20] <- a11 ; a11 <- ExcCause
+        s32e    a12,  a1, -44           // [a1-16] <- a12 ; a12 <- LBEG
+        s32e    a13,  a1, -40           // [a1-12] <- a13 ; a13 <- LEND
+        s32e    a14,  a1, -36           // [a1-8]  <- a14 ; a14 <- LCOUNT
+        s32e    a15,  a1, -32           // [a1-4]  <- a15 ; a15 <- a1
+                                        // If Overflow then return (branch to EPC)
+
+_xt_entry:
+        s32e     a8,  a1, -4            // [a1-68] <-  a8 (ExcVAddr)
+        s32e    a11,  a1, -8            // [a1-72] <- a11 (ExcCause)
+#if XCHAL_HAVE_LOOPS
+        s32e    a12,  a1, -20           // [a1-84] <- a12 (LBEG)
+        s32e    a13,  a1, -24           // [a1-88] <- a13 (LEND)
+        s32e    a14,  a1, -28           // [a1-92] <- a14 (LCOUNT)
+#endif
+#if XCHAL_HAVE_EXCLUSIVE
+        movi    a12,  0
+        getex   a12
+        s32e    a12,  a1, -32           // [a1-96] <- a12 (ATOMCTL)
+#endif
+
+        j       1f                      // make room for literals
+
+        .align  4
+        .literal_position
+
+.Le1:
+        .word   _xt_exception_table
+
+1:
+        // Call OS-specific code for additional work to be done. Stay on interruptee's
+        // stack in case more saves are required into stack frame.
+        // NOTE: OS-specific code can use a8, a12-a14, (+a2-a7: call0, a15: windowed).
+        // ALL other registers must be preserved.
+
+        XT_RTOS_INT_ENTER
+
+        // This sequence checks the interrupt controller and loads the interrupt
+        // number if available, and also loads the wrapper handler address.
+        // If there is an interrupt, execution will branch to the wrapper which
+        // will then forward to the correct handler.
+        // All this happens only if there is a pending interrupt. If not, execution
+        // falls through to exception handling.
+
+#ifdef __XTENSA_CALL0_ABI__
+
+        s32si.x4         a2,  a1        // [a1-80] <- a2 (EPC) ; a2 <- (intnum << 2)
+        movi             a0,   0
+        l32dis.it        a0,  a0        // a0 <- wrapper addr (handler_table[0])
+        s32stk           a9,  a1, 96    // [a1-76] <- a9 (PS/SAR) ; a1 = a1-96
+#if XT_STK_XTRA_SZ
+        addi             a1,  a1, -XT_STK_XTRA_SZ       // Adjust for extra save area
+#endif
+        s32dis.h         a0,  a0        // Jump to handler if interrupt else fall through
+
+#else // windowed
+
+        s32si.x4        a10,  a1        // [a1-80] <- a10 (EPC) ; a10 <- (intnum << 2)
+        movi             a8,   0
+        l32dis.it        a8,  a8        // a8 <- wrapper addr (handler_table[0])
+        s32stk           a9,  a1, 96    // [a1-76] <- a9 (PS/SAR) ; a9 = a1-96
+#if XT_STK_XTRA_SZ
+        addi             a9,  a9, -XT_STK_XTRA_SZ       // Adjust for extra save area
+#endif
+        s32dis.h         a8,  a8        // Jump to handler if interrupt else fall through
+
+#endif // __XTENSA_CALL0_ABI__
+
+        // At this point we have:
+        // (note window has rotated for windowed ABI)
+        //    a0 holds return address (Tailchain+3)
+        // For call0:
+        //   a11 holds ExcCause, also saved in [oldsp - 72]
+        //   a15 holds exception SP, a1 points to exception frame
+        // For windowed:
+        //    a3 holds ExcCause, also saved in [oldsp - 72]
+        //    a1 points to exception frame
+
+        .global _xt_exception
+
+_xt_exception:
+        l32r     a2,  .Le1                  // Load exc table address
+#ifdef __XTENSA_CALL0_ABI__
+        mov      a3, a11                    // Copy exception cause to a3
+#endif
+        extui    a4,  a3, 0, 4              // Extract exception cause
+        addx4    a2,  a4, a2                // Index into exc table
+        l32i     a4,  a2, 0                 // Load handler address
+#if XT_STK_XTRA_SZ
+        addi     a2,  a1, XT_STK_XTRA_SZ    // Argument = Exception frame ptr
+#else
+        mov      a2,  a1                    // Argument = Exception frame ptr
+#endif
+        jx       a4                         // Return directly from handler
+
+        // Exit/restore sequence
+
+        .global _xt_exit
+
+_xt_exit:
+#ifdef __XTENSA_CALL0_ABI__
+        mov      a1, a15                    // Restore stack pointer
+#endif
+
+        // Run OS-specific code to determine what to restore.
+        // Interrupts will remain disabled through this sequence.
+        // WARNING: stack pointer may change within this macro
+        // so all restores off the stack must happen afterwards.
+
+        XT_RTOS_INT_EXIT
+
+        .global _xt_restore
+
+_xt_restore:
+        // Some loads must happen before DISPST = Restore, as these
+        // will not be accessible via L32E once DISPST = Restore.
+
+#if XCHAL_HAVE_EXCLUSIVE
+        l32e    a12,  a1, -32           // a12 <- [a1-96] (ATOMCTL)
+        getex   a12
+#endif
+        l32e    a10,  a1, -12           // a10 <- [a1-76] (PS/SAR)
+        l32e    a12,  a1, -20           // a12 <- [a1-84] (LBEG)
+        l32e    a13,  a1, -24           // a13 <- [a1-88] (LEND)
+        l32e    a14,  a1, -28           // a14 <- [a1-92] (LCOUNT)
+        l32dis.epc  a11, a1             // a11 <- [a1-80] (EPC)
+                                        // If interrupt goto tailchain else fall through
+
+#ifdef __XTENSA_CALL0_ABI__
+        l32e     a0,  a1, -64           // a0 <- [a1-64]
+        l32e     a2,  a1, -64           // a2 <- [a1-56]
+        l32e     a3,  a1, -64           // a3 <- [a1-52]
+        l32e     a4,  a1, -64           // a4 <- [a1-48]
+        l32e     a5,  a1, -64           // a5 <- [a1-44]
+        l32e     a6,  a1, -64           // a6 <- [a1-40]
+        l32e     a7,  a1, -64           // a7 <- [a1-36]
+#endif
+
+        // Important: the following restrictions must be observed:
+        // 1) The LCOUNT register must be restored after LBEG/LEND.
+        // 2) There must be at least 3 instructions between the LCOUNT
+        //    restore and the last L32E (the one that branches).
+
+        l32e    a12,  a1, -44           // LBEG   <- a12, a12 <- [a1-16]
+        l32e    a13,  a1, -40           // LEND   <- a13, a13 <- [a1-12]
+        l32e    a14,  a1, -36           // LCOUNT <- a14, a14 <- [a1-8]
+        l32e     a8,  a1, -64           // a8 <- [a1-32]
+        l32e     a9,  a1, -64           // a9 <- [a1-28]
+        l32e    a10,  a1, -60           // PS/SAR <- a10, a10 <- [a1-24]
+        l32e    a11,  a1, -48           // EPC    <- a11, a11 <- [a1-20]
+        l32e    a15,  a1, -64           // a15 <- [a1-4], Branch to EPC if no interrupt
+                                        // If interrupt, branch to Tailchain
+
+
+//-----------------------------------------------------------------------------
+// Branch to reset handler code from here. Use CALL0 as a branch, will expand
+// to CALLX0 if needed when built with the -mlongcalls option.
+//-----------------------------------------------------------------------------
+
+        .align  4
+        .local  _JumpToResetHandler
+
+_JumpToResetHandler:
+        call0   _ResetHandler
+
+
+//-----------------------------------------------------------------------------
+// Idle loop. On interrupt, no state needs saving.
+//-----------------------------------------------------------------------------
+
+        .align  4
+        .global _xt_idle
+
+_xt_idle:
+        movi    a14, _xt_interrupt_stack_top
+        mov      a1, a14                // a1 <- Top of interrupt stack
+        movi    a14, 0                  // 0 = Normal
+        wsr.ms  a14                     // Set DISPST = Normal
+        rsync
+        waiti   0                       // Wait for interrupt
+        memw                            // HW erratum 569
+
+
+//-----------------------------------------------------------------------------
+// Scheduler interrupt handler. Triggered by context switch. At this time only
+// useful for windowed ABI to spill register windows.
+//-----------------------------------------------------------------------------
+
+        .align  4
+        .global xt_sched_handler
+
+xt_sched_handler:
+#ifdef __XTENSA_WINDOWED_ABI__
+        entry   a1, 32
+        ssai    1
+        spillw
+        retw
+#else
+        ret
+#endif
+
+#endif // XCHAL_HAVE_XEA3
+
diff --git a/ports_module/cortex-m7/ac5/example_build/build_threadx.bat b/ports_module/cortex-m7/ac5/example_build/build_threadx.bat
index caa281e3..c355a2f9 100644
--- a/ports_module/cortex-m7/ac5/example_build/build_threadx.bat
+++ b/ports_module/cortex-m7/ac5/example_build/build_threadx.bat
@@ -1,5 +1,7 @@
 del tx.a
+
 armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork tx_initialize_low_level.S
+
 armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/tx_thread_stack_build.S
 armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/tx_thread_schedule.S
 armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/tx_thread_system_return.S
@@ -9,6 +11,16 @@ armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/s
 armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/tx_timer_interrupt.S
 armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.S
 armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.S
+
+armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_alignment_adjust.c
+armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_external_memory_enable.c
+armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c
+armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c
+armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_mm_register_setup.c
+
+armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.S
+armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.S
+
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c
@@ -133,6 +145,7 @@ armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../..
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c
+
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c
@@ -193,6 +206,8 @@ armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../..
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c
+
+armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_absolute_load.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c
@@ -219,17 +234,10 @@ armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c
 armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c
-armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_alignment_adjust.c
-armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_external_memory_enable.c
-armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c
-armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c
-armcc -g -O0 --cpu=cortex-m7.fp.dp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_mm_register_setup.c
-armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.S
-armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.S
 
 armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o
 armar -r tx.a tx_event_flags_performance_system_info_get.o tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o  tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o 
 armar -r tx.a tx_semaphore_put_notify.o tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o  tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
 armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o 
 armar -r tx.a txe_queue_prioritize.o txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o txm_module_manager_in_place_load.o 
-armar -r tx.a txm_module_manager_initialize.o txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o txm_module_manager_internal_load.o txm_module_manager_object_allocate.o txm_module_manager_object_deallocate.o txm_module_manager_object_pointer_get_extended.o txm_module_manager_properties_get.o txm_module_manager_util.o txm_module_manager_user_mode_entry.o
+armar -r tx.a txm_module_manager_initialize.o txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o txm_module_manager_internal_load.o txm_module_manager_object_allocate.o txm_module_manager_object_deallocate.o txm_module_manager_object_pointer_get_extended.o txm_module_manager_properties_get.o txm_module_manager_util.o txm_module_manager_user_mode_entry.o txm_module_manager_absolute_load.o
diff --git a/ports_module/cortex-m7/ac5/example_build/build_threadx_demo.bat b/ports_module/cortex-m7/ac5/example_build/build_threadx_demo.bat
index da979bd9..ed8a78ef 100644
--- a/ports_module/cortex-m7/ac5/example_build/build_threadx_demo.bat
+++ b/ports_module/cortex-m7/ac5/example_build/build_threadx_demo.bat
@@ -1,4 +1,4 @@
-armasm -g --cpu=cortex-m7.fp.dp --apcs=/interwork tx_initialize_low_level.S
+armasm -g --cpreproc --cpu=cortex-m7.fp.dp --apcs=/interwork tx_initialize_low_level.S
 armcc -c -g --cpu=cortex-m7.fp.dp -O2 -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx.c
 armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a
 
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex-m7/ac6/example_build/sample_threadx/.cproject
index 9d81f0c7..fc1cb75e 100644
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx/.cproject
+++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/.cproject
@@ -55,8 +55,6 @@
                                 								
                                 <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
                                     									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx}&quot;"/>
-                                    									
                                     <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
                                     									
                                     <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
@@ -89,11 +87,7 @@
                                 								
                                 <option id="com.arm.tool.assembler.v6.base.options.debug.level.429021326" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
                                 								
-                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.incpath.2094427773" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
-                                    									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx}&quot;"/>
-                                    								
-                                </option>
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.incpath.2094427773" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath"/>
                                 								
                                 <inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>
                                 							
@@ -133,23 +127,7 @@
                 			
             </storageModule>
             			
-            <storageModule moduleId="org.eclipse.cdt.core.externalSettings">
-                				
-                <externalSettings containerId="tx;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier">
-                    					
-                    <externalSetting>
-                        						
-                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
-                        						
-                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
-                        						
-                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
-                        					
-                    </externalSetting>
-                    				
-                </externalSettings>
-                			
-            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
             		
         </cconfiguration>
         	
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/.project b/ports_module/cortex-m7/ac6/example_build/sample_threadx/.project
index 2a6b3cb1..725328bd 100644
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx/.project
+++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/.project
@@ -3,7 +3,6 @@
 	<name>sample_threadx</name>
 	<comment></comment>
 	<projects>
-		<project>tx</project>
 	</projects>
 	<buildSpec>
 		<buildCommand>
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.cproject
index ccfc3584..1e1ea739 100644
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.cproject
+++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.cproject
@@ -57,10 +57,6 @@
                                 								
                                 <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
                                     									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx}&quot;"/>
-                                    									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/txm}&quot;"/>
-                                    									
                                     <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
                                     									
                                     <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic_modules}&quot;"/>
@@ -115,13 +111,7 @@
                                 								
                                 <option id="com.arm.tool.assembler.v6.base.useMicroLib.555616131" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.assembler.v6.base.useMicroLib" useByScannerDiscovery="false" value="false" valueType="boolean"/>
                                 								
-                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.incpath.1292905054" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
-                                    									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx}&quot;"/>
-                                    									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/txm}&quot;"/>
-                                    								
-                                </option>
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.incpath.1292905054" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath"/>
                                 								
                                 <inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>
                                 							
@@ -185,29 +175,7 @@
                 			
             </storageModule>
             			
-            <storageModule moduleId="org.eclipse.cdt.core.externalSettings">
-                				
-                <externalSettings containerId="txm;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier">
-                    					
-                    <externalSetting>
-                        						
-                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
-                        						
-                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/>
-                        						
-                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
-                        						
-                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/>
-                        						
-                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
-                        						
-                        <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/>
-                        					
-                    </externalSetting>
-                    				
-                </externalSettings>
-                			
-            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
             		
         </cconfiguration>
         	
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.project b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.project
index 5f1f1fa6..17f6aba3 100644
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.project
+++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.project
@@ -3,7 +3,6 @@
 	<name>sample_threadx_module</name>
 	<comment></comment>
 	<projects>
-		<project>txm</project>
 	</projects>
 	<buildSpec>
 		<buildCommand>
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.cproject
index 0cf83cff..f6ca2712 100644
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.cproject
+++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.cproject
@@ -55,8 +55,6 @@
                                 								
                                 <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
                                     									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx}&quot;"/>
-                                    									
                                     <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
                                     									
                                     <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic_modules}&quot;"/>
@@ -91,11 +89,7 @@
                                 								
                                 <option id="com.arm.tool.assembler.v6.base.options.debug.level.429021326" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
                                 								
-                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.incpath.1361570371" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
-                                    									
-                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx}&quot;"/>
-                                    								
-                                </option>
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.incpath.1361570371" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath"/>
                                 								
                                 <inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>
                                 							
@@ -135,25 +129,7 @@
                 			
             </storageModule>
             			
-            <storageModule moduleId="org.eclipse.cdt.core.externalSettings">
-                				
-                <externalSettings containerId="sample_threadx_module;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier"/>
-                				
-                <externalSettings containerId="tx;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier">
-                    					
-                    <externalSetting>
-                        						
-                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
-                        						
-                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
-                        						
-                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
-                        					
-                    </externalSetting>
-                    				
-                </externalSettings>
-                			
-            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
             		
         </cconfiguration>
         	
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.project b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.project
index bddfb9ee..f1ca14fa 100644
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.project
+++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.project
@@ -3,8 +3,6 @@
 	<name>sample_threadx_module_manager</name>
 	<comment></comment>
 	<projects>
-		<project>sample_threadx_module</project>
-		<project>tx</project>
 	</projects>
 	<buildSpec>
 		<buildCommand>
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds
deleted file mode 100644
index b1993316..00000000
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds
+++ /dev/null
@@ -1,3 +0,0 @@
-wait
-load ..\sample_threadx_module\Debug\sample_threadx_module.axf
-wait
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
index d088487d..6cace9e2 100644
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
+++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
@@ -1,57 +1,69 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <launchConfiguration type="com.arm.debugger.launcher2">
+    <listAttribute key="7726568867342656373.viewid=2">
+        <listEntry value="module_location"/>
+        <listEntry value="code_alignment"/>
+        <listEntry value="status"/>
+    </listAttribute>
+    <mapAttribute key="7726568867342656373.viewid=2.ExpressionsData">
+        <mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
+        <mapEntry key="1" value=""/>
+        <mapEntry key="2" value=""/>
+    </mapAttribute>
+    <stringAttribute key="7726568867342656373.viewid=2:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;255&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;376&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
     <mapAttribute key="AverageDurationTracker">
-        <mapEntry key="*Fetching Data Model" value="2887558"/>
+        <mapEntry key="*Fetching Data Model" value="1447972"/>
         <mapEntry key="*FunctionLoader" value="214992700"/>
         <mapEntry key="*ListDynamicObjects" value="61100"/>
-        <mapEntry key="*list global low level symbols" value="9370891"/>
+        <mapEntry key="*list global low level symbols" value="1840075"/>
         <mapEntry key="*loading memory from target" value="1110358"/>
-        <mapEntry key="*loading values from target" value="8310340"/>
+        <mapEntry key="*loading values from target" value="5167565"/>
         <mapEntry key="*trace" value="38872798"/>
-        <mapEntry key="*updating expressions" value="61166027"/>
+        <mapEntry key="*updating expressions" value="53143906"/>
         <mapEntry key="*updating local_variables" value="6060821"/>
         <mapEntry key="*updating registers" value="3315038"/>
-        <mapEntry key="AddEventObserver" value="7229809"/>
-        <mapEntry key="Evaluate" value="2459191"/>
+        <mapEntry key="AddEventObserver" value="4901218"/>
+        <mapEntry key="Evaluate" value="4536197"/>
         <mapEntry key="SourceToAddress" value="1178100"/>
         <mapEntry key="areCachesAvailable" value="802125"/>
         <mapEntry key="backtrace" value="4840175"/>
-        <mapEntry key="break" value="47306816"/>
+        <mapEntry key="break" value="5325546"/>
         <mapEntry key="checking tracepoints" value="141269"/>
-        <mapEntry key="compute execution mode" value="2982244"/>
+        <mapEntry key="compute execution mode" value="5311716"/>
         <mapEntry key="console" value="2807900"/>
-        <mapEntry key="continue" value="70417515"/>
+        <mapEntry key="continue" value="67287632"/>
         <mapEntry key="core" value="6820750"/>
-        <mapEntry key="disassemble" value="62307917"/>
+        <mapEntry key="disassemble" value="41929939"/>
         <mapEntry key="evaluate address" value="758578"/>
         <mapEntry key="get byte order" value="322003"/>
-        <mapEntry key="get capabilities" value="2329837"/>
-        <mapEntry key="get execution addresss" value="1119951"/>
-        <mapEntry key="get source lines" value="1456512"/>
+        <mapEntry key="get capabilities" value="585052"/>
+        <mapEntry key="get execution addresss" value="387444"/>
+        <mapEntry key="get source lines" value="453685"/>
         <mapEntry key="getValidEncodings" value="2540450"/>
-        <mapEntry key="initialize command help" value="113682822"/>
+        <mapEntry key="initialize command help" value="53046776"/>
         <mapEntry key="interrupt" value="7691497"/>
-        <mapEntry key="list breakpoint options" value="251393"/>
-        <mapEntry key="list breakpoints" value="1729500"/>
-        <mapEntry key="list instruction sets" value="2446547"/>
-        <mapEntry key="list signals" value="7127146"/>
-        <mapEntry key="list watchpoint options" value="6289089"/>
-        <mapEntry key="list watchpoints" value="1080090"/>
-        <mapEntry key="loadfile" value="790923696"/>
-        <mapEntry key="next" value="45551172"/>
-        <mapEntry key="remove" value="2611023"/>
+        <mapEntry key="list breakpoint options" value="190256"/>
+        <mapEntry key="list breakpoints" value="1654130"/>
+        <mapEntry key="list instruction sets" value="1118577"/>
+        <mapEntry key="list signals" value="44653071"/>
+        <mapEntry key="list watchpoint options" value="3557205"/>
+        <mapEntry key="list watchpoints" value="730224"/>
+        <mapEntry key="loadfile" value="356525818"/>
+        <mapEntry key="next" value="31655516"/>
+        <mapEntry key="remove" value="2745078"/>
+        <mapEntry key="run script" value="27519512"/>
         <mapEntry key="select-frame" value="2720250"/>
-        <mapEntry key="set CWD" value="7691839"/>
-        <mapEntry key="set breakpoint properties" value="28197737"/>
-        <mapEntry key="set debug-from" value="11382151"/>
+        <mapEntry key="set CWD" value="4343514"/>
+        <mapEntry key="set breakpoint properties" value="6165571"/>
+        <mapEntry key="set debug-from" value="2007840"/>
         <mapEntry key="source sample_threadx_module_manager.ds" value="237787324"/>
         <mapEntry key="source sample_threadx_module_manager_debug.ds" value="145111082"/>
-        <mapEntry key="start" value="296844545"/>
-        <mapEntry key="step" value="41375081"/>
+        <mapEntry key="start" value="97315784"/>
+        <mapEntry key="step" value="47252310"/>
         <mapEntry key="synchronizing trace ranges" value="37187"/>
-        <mapEntry key="toggleBreakpoint" value="9917156"/>
+        <mapEntry key="toggleBreakpoint" value="9688552"/>
         <mapEntry key="updateBreakpointLocation" value="8450100"/>
-        <mapEntry key="waitForTargetToStop" value="41796648"/>
+        <mapEntry key="waitForTargetToStop" value="32104771"/>
     </mapAttribute>
     <intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
     <intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
@@ -73,11 +85,11 @@
     <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
     <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
     <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
-    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_DOWNLOAD_DIR"/>
     <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
     <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
     <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
-    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
     <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
     <intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
     <listAttribute key="FILES.DOWNLOAD_DEBUG"/>
@@ -87,11 +99,11 @@
     <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
     <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
     <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
-    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_DOWNLOAD_DIR"/>
     <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
     <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
     <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
-    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
     <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
     <intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
     <intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
@@ -125,8 +137,9 @@
     <stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
     <stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
     <booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
-    <booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="false"/>
-    <stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value=""/>
+    <booleanAttribute key="InstructionStepping" value="false"/>
+    <booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+    <stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="load ${workspace_loc:/sample_threadx_module/Debug/sample_threadx_module.axf}&#13;&#10;add-symbol-file ${workspace_loc:/sample_threadx_module/Debug/sample_threadx_module.axf}"/>
     <booleanAttribute key="KEY_COMMANDS_AS_CONNECT" value="false"/>
     <intAttribute key="Messages.POST_TRIGGER_CAPTURE_SIZE.getLocalisedValue().FMTrace" value="50"/>
     <booleanAttribute key="Messages.STOP_ON_TRIGGER.getLocalisedValue().FMTrace" value="false"/>
@@ -136,14 +149,15 @@
     <booleanAttribute key="VFS_ENABLED" value="true"/>
     <stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
     <stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+    <stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010CC4&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;112&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C7C&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;112&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010CCE&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;115&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C86&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;115&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010CDC&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;118&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C94&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;118&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010CEA&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;124&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010CA2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;124&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C3A&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;89&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010BF2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;89&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C68&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;97&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C20&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;97&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x0000A270&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/common_modules/module_manager/src/txm_module_manager_in_place_load.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\common_modules\module_manager\src\txm_module_manager_in_place_load.c&quot; line=&quot;119&quot; function=&quot;_txm_module_manager_in_place_load&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x0000A270&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/common_modules/module_manager/src/txm_module_manager_in_place_load.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\common_modules\module_manager\src\txm_module_manager_in_place_load.c&quot; line=&quot;119&quot; function=&quot;_txm_module_manager_in_place_load&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010CA4&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;103&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C5C&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;103&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x0000BD60&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/common_modules/module_manager/src/txm_module_manager_start.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\common_modules\module_manager\src\txm_module_manager_start.c&quot; line=&quot;225&quot; function=&quot;_txm_module_manager_start&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x0000BD18&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/common_modules/module_manager/src/txm_module_manager_start.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\common_modules\module_manager\src\txm_module_manager_start.c&quot; line=&quot;225&quot; function=&quot;_txm_module_manager_start&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010CB2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;106&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C6A&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;106&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010CBA&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;109&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;0x00010C72&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.c&quot; line=&quot;109&quot; function=&quot;module_manager_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
     <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
+        <listEntry value="&lt;Next Instruction&gt;"/>
         <listEntry value=""/>
         <listEntry value="0x00030F38"/>
-        <listEntry value="&lt;Next Instruction&gt;"/>
     </listAttribute>
     <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
-        <listEntry value=""/>
         <listEntry value="100"/>
+        <listEntry value=""/>
         <listEntry value="100"/>
     </listAttribute>
     <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.addresses">
@@ -165,8 +179,8 @@
     <stringAttribute key="config_file" value="CDB://cadi_config.xml"/>
     <booleanAttribute key="connectOnly" value="false"/>
     <listAttribute key="debugger.view.DisassemblyView:current">
-        <listEntry value=""/>
-        <listEntry value=""/>
+        <listEntry value="&lt;Next Instruction&gt;"/>
+        <listEntry value="100"/>
     </listAttribute>
     <listAttribute key="debugger.view.ExpressionsView">
         <listEntry value="thread_0_counter"/>
@@ -192,7 +206,7 @@
         <mapEntry key="8" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
         <mapEntry key="9" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
     </mapAttribute>
-    <stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;200&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;108&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;57&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;80&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;274&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;159&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;75&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;119&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
     <stringAttribute key="debugger.view.MemoryView" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;page&gt;&#10;&#9;&lt;memoryView/&gt;&#10;&lt;/page&gt;&#10;"/>
     <listAttribute key="debugger.view.MemoryView:current">
         <listEntry value=""/>
@@ -216,8 +230,6 @@
     <stringAttribute key="model_params" value=""/>
     <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
     <booleanAttribute key="runAfterConnect" value="false"/>
-    <stringAttribute key="runScriptAfterConnect" value="${workspace_loc:/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds}"/>
-    <stringAttribute key="runTargetInitializationScript" value="${workspace_loc:/sample_threadx_module_manager/sample_threadx_module_manager.ds}"/>
     <listAttribute key="setup">
         <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
         <listEntry value="&quot;FVP_MPS2_Cortex-M7&quot;"/>
diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds
deleted file mode 100644
index fc83a4f2..00000000
--- a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds
+++ /dev/null
@@ -1,3 +0,0 @@
-wait
-add-symbol-file ..\sample_threadx_module\Debug\sample_threadx_module.axf
-wait
diff --git a/ports_module/cortex-m7/gnu/example_build/build_threadx.bat b/ports_module/cortex-m7/gnu/example_build/build_threadx.bat
index b45a175f..4250db1e 100644
--- a/ports_module/cortex-m7/gnu/example_build/build_threadx.bat
+++ b/ports_module/cortex-m7/gnu/example_build/build_threadx.bat
@@ -1,5 +1,7 @@
 del tx.a
+
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb tx_initialize_low_level.S
+
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ..\module_manager\src\tx_thread_stack_build.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ..\module_manager\src\tx_thread_schedule.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ..\module_manager\src\tx_thread_system_return.S
@@ -9,6 +11,12 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ..\module_manager\src\tx_timer_interrupt.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ..\module_manager\src\txm_module_manager_thread_stack_build.S
 
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_alignment_adjust.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_external_memory_enable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_memory_fault_handler.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_mm_register_setup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_memory_fault_notify.c
+
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_allocate.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_cleanup.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_create.c
@@ -194,19 +202,16 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_delete.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_info_get.c
 
-arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_alignment_adjust.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_absolute_load.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_application_request.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_callback_request.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_event_flags_notify_trampoline.c
-arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_external_memory_enable.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_file_load.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_in_place_load.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_internal_load.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_initialize.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_kernel_dispatch.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_maximum_module_priority_set.c
-arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_memory_fault_handler.c
-arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_memory_fault_notify.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_memory_load.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_allocate.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_deallocate.c
@@ -216,7 +221,6 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_properties_get.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_queue_notify_trampoline.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_semaphore_notify_trampoline.c
-arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_mm_register_setup.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_start.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_stop.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_create.c
@@ -252,6 +256,7 @@ arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_perf
 arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
 arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
 arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+
 arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
 arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
 arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
@@ -265,16 +270,11 @@ arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_
 
 arm-none-eabi-ar -r tx.a txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o
 arm-none-eabi-ar -r tx.a txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o
-arm-none-eabi-ar -r tx.a txm_module_manager_in_place_load.o txm_module_manager_initialize.o
+arm-none-eabi-ar -r tx.a txm_module_manager_absolute_load.o txm_module_manager_in_place_load.o txm_module_manager_initialize.o txm_module_manager_internal_load.o
 arm-none-eabi-ar -r tx.a txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o
 arm-none-eabi-ar -r tx.a txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o
 arm-none-eabi-ar -r tx.a txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o
 arm-none-eabi-ar -r tx.a txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o
 arm-none-eabi-ar -r tx.a txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o
 arm-none-eabi-ar -r tx.a txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o
-arm-none-eabi-ar -r tx.a txm_module_manager_internal_load.o
-arm-none-eabi-ar -r tx.a txm_module_manager_object_allocate.o
-arm-none-eabi-ar -r tx.a txm_module_manager_object_deallocate.o
-arm-none-eabi-ar -r tx.a txm_module_manager_object_pointer_get_extended.o
-arm-none-eabi-ar -r tx.a txm_module_manager_properties_get.o
-arm-none-eabi-ar -r tx.a txm_module_manager_util.o
\ No newline at end of file
+arm-none-eabi-ar -r tx.a txm_module_manager_object_allocate.o txm_module_manager_object_deallocate.o txm_module_manager_object_pointer_get_extended.o txm_module_manager_properties_get.o txm_module_manager_util.o
\ No newline at end of file
diff --git a/ports_module/cortex-m7/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_library.bat
index 1b8f6a06..a6660a86 100644
--- a/ports_module/cortex-m7/gnu/example_build/build_threadx_module_library.bat
+++ b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_library.bat
@@ -1,5 +1,7 @@
 del txm.a
 
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c
+
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c
@@ -29,7 +31,6 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c
-arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c
@@ -98,21 +99,6 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c
 
-arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o
-arm-none-eabi-ar -r txm.a txm_block_pool_prioritize.o txm_block_release.o
-arm-none-eabi-ar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o
-arm-none-eabi-ar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o
-arm-none-eabi-ar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o
-arm-none-eabi-ar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o
-arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o
-arm-none-eabi-ar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o
-arm-none-eabi-ar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o
-arm-none-eabi-ar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o
-arm-none-eabi-ar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o
-arm-none-eabi-ar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o
-arm-none-eabi-ar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o
-arm-none-eabi-ar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o
-arm-none-eabi-ar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o
-arm-none-eabi-ar -r txm.a txm_time_get.o txm_time_set.o
-arm-none-eabi-ar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o
-arm-none-eabi-ar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o
+arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o  txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o  txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o  txm_time_get.o txm_time_set.o
+arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o
+arm-none-eabi-ar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o
diff --git a/ports_module/cortex-m7/gnu/example_build/build_threadx_module_manager_sample.bat b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_manager_sample.bat
index e361dfb2..244b7b73 100644
--- a/ports_module/cortex-m7/gnu/example_build/build_threadx_module_manager_sample.bat
+++ b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_manager_sample.bat
@@ -1,4 +1,4 @@
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module_manager.c
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb tx_simulator_startup.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb cortexm_crt0.S
-arm-none-eabi-ld -A cortex-m7 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx_module_manager.o tx.a  libc.a -o sample_threadx_module_manager.axf -M > sample_threadx_module_manager.map
+arm-none-eabi-gcc -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -nostartfiles -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx_module_manager.o tx.a -o sample_threadx_module_manager.axf -Wl,-Map=sample_threadx_module_manager.map
diff --git a/ports_module/cortex-m7/gnu/example_build/build_threadx_sample.bat b/ports_module/cortex-m7/gnu/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..5b008d0d
--- /dev/null
+++ b/ports_module/cortex-m7/gnu/example_build/build_threadx_sample.bat
@@ -0,0 +1,4 @@
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I..\inc -I..\..\..\..\common\inc sample_threadx.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb tx_simulator_startup.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb cortexm_crt0.S
+arm-none-eabi-gcc -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -nostartfiles -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx.o tx.a -lc -o sample_threadx.axf -Wl,-Map=sample_threadx.map
diff --git a/ports_module/cortex-m7/iar/example_build/tx.ewp b/ports_module/cortex-m7/iar/example_build/tx.ewp
index 0e44856f..7ff6209d 100644
--- a/ports_module/cortex-m7/iar/example_build/tx.ewp
+++ b/ports_module/cortex-m7/iar/example_build/tx.ewp
@@ -66,7 +66,7 @@
                 </option>
                 <option>
                     <name>OGLastSavedByProductVersion</name>
-                    <state>8.50.4.26131</state>
+                    <state>8.50.9.33458</state>
                 </option>
                 <option>
                     <name>GeneralEnableMisra</name>
@@ -481,7 +481,7 @@
             <name>AARM</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>10</version>
+                <version>11</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>1</debug>
                 <option>
@@ -637,6 +637,10 @@
                     <name>AsmNoLiteralPool</name>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -1050,7 +1054,7 @@
                 </option>
                 <option>
                     <name>IarchiveOutput</name>
-                    <state></state>
+                    <state>C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\iar\example_build\Debug\Exe\tx.a</state>
                 </option>
             </data>
         </settings>
@@ -1541,7 +1545,7 @@
             <name>AARM</name>
             <archiveVersion>2</archiveVersion>
             <data>
-                <version>10</version>
+                <version>11</version>
                 <wantNonLocal>1</wantNonLocal>
                 <debug>0</debug>
                 <option>
@@ -1697,6 +1701,10 @@
                     <name>AsmNoLiteralPool</name>
                     <state>0</state>
                 </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
             </data>
         </settings>
         <settings>
@@ -2766,6 +2774,9 @@
         <file>
             <name>$PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c</name>
         </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_absolute_load.c</name>
+        </file>
         <file>
             <name>$PROJ_DIR$\..\module_manager\src\txm_module_manager_alignment_adjust.c</name>
         </file>
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject
new file mode 100644
index 00000000..a49dadd2
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject
@@ -0,0 +1,174 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.1388095870" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6">
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.689426261" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.debug.level.1729514272" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.1388095870.857809581" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1944684744" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.259341383" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.cpu.96377009" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.defmac.1975445896" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1271571516" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1548640167" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                								
+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.815952161" superClass="com.arm.tool.c.compiler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.1091536604" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1962633763" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1147447905" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.cpu.269795998" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.options.debug.level.1521551718" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.defmac.281085002" name="Define macro (-D)" superClass="com.arm.tool.assembler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols"/>
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.1000911913" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1807144931" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.linker.option.entry.249327747" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="start64" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.scatter.1246240408" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="..\sample_threadx.scat" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.libs.2105481551" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="..\..\tx\Debug\tx.a"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.c.linker.option.imagemap.359605740" name="Generate image map (--map)" superClass="com.arm.tool.c.linker.option.imagemap" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.verbose.509554865" name="Verbose output (--verbose)" superClass="com.arm.tool.c.linker.option.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.totals.428431324" name="List total code and data sizes of output image (--info=totals)" superClass="com.arm.tool.c.linker.option.totals" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.redirectoutput.259431691" name="Redirect diagnostics output to file (--list)" superClass="com.arm.tool.c.linker.option.redirectoutput" useByScannerDiscovery="false" value="sample_threadx.map" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.elim.532237314" name="List unused sections that are eliminated (--info=unused)" superClass="com.arm.tool.c.linker.option.elim" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.compress.1449950796" name="Print RW compression information (--info=compression)" superClass="com.arm.tool.c.linker.option.compress" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.stack.1835435506" name="List stack usage of global symbols (--info=stack)" superClass="com.arm.tool.c.linker.option.stack" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.inlineinfo.1898593362" name="List functions inlined by linker (--info=inline)" superClass="com.arm.tool.c.linker.option.inlineinfo" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.callgraph.1505673040" name="Generate call graph (--callgraph)" superClass="com.arm.tool.c.linker.option.callgraph" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.graphfile.1311318964" name="Callgraph file (--callgraph_file)" superClass="com.arm.tool.c.linker.option.graphfile" useByScannerDiscovery="false" value="callgraph" valueType="string"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1243987688" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.1027551600" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/.project b/ports_module/cortex_a35/ac6/example_build/sample_threadx/.project
new file mode 100644
index 00000000..a1b15572
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/.project
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h
new file mode 100644
index 00000000..23bc7fd8
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h
@@ -0,0 +1,561 @@
+/*
+ * GICv3.h - data types and function prototypes for GICv3 utility routines
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_h
+#define GICV3_h
+
+#include <stdint.h>
+
+/*
+ * extra flags for GICD enable
+ */
+typedef enum
+{
+    gicdctlr_EnableGrp0 = (1 << 0),
+    gicdctlr_EnableGrp1NS = (1 << 1),
+    gicdctlr_EnableGrp1A = (1 << 1),
+    gicdctlr_EnableGrp1S = (1 << 2),
+    gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
+    gicdctlr_ARE_S = (1 << 4),	/* Enable Secure state affinity routing */
+    gicdctlr_ARE_NS = (1 << 5),	/* Enable Non-Secure state affinity routing */
+    gicdctlr_DS = (1 << 6),	/* Disable Security support */
+    gicdctlr_E1NWF = (1 << 7)	/* Enable "1-of-N" wakeup model */
+} GICDCTLRFlags_t;
+
+/*
+ * modes for SPI routing
+ */
+typedef enum
+{
+    gicdirouter_ModeSpecific = 0,
+    gicdirouter_ModeAny = (1 << 31)
+} GICDIROUTERBits_t;
+
+typedef enum
+{
+    gicdicfgr_Level = 0,
+    gicdicfgr_Edge = (1 << 1)
+} GICDICFGRBits_t;
+
+typedef enum
+{
+    gicigroupr_G0S = 0,
+    gicigroupr_G1NS = (1 << 0),
+    gicigroupr_G1S = (1 << 2)
+} GICIGROUPRBits_t;
+
+typedef enum
+{
+    gicrwaker_ProcessorSleep = (1 << 1),
+    gicrwaker_ChildrenAsleep = (1 << 2)
+} GICRWAKERBits_t;
+
+/**********************************************************************/
+
+/*
+ * Utility macros & functions
+ */
+#define RANGE_LIMIT(x)		((sizeof(x) / sizeof((x)[0])) - 1)
+
+static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
+					 uint32_t aff1, uint32_t aff0)
+{
+    /*
+     * only need to cast aff3 to get type promotion for all affinities
+     */
+    return ((((uint64_t)aff3 & 0xff) << 32) |
+	    ((aff2 & 0xff) << 16) |
+	    ((aff1 & 0xff) << 8) | aff0);
+}
+
+/**********************************************************************/
+
+/*
+ * GIC Distributor Function Prototypes
+ */
+
+/*
+ * ConfigGICD - configure GIC Distributor prior to enabling it
+ *
+ * Inputs:
+ *
+ *  control - control flags
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void ConfigGICD(GICDCTLRFlags_t flags);
+
+/*
+ * EnableGICD - top-level enable for GIC Distributor
+ *
+ * Inputs:
+ *
+ *  flags - new control flags to set
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void EnableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * DisableGICD - top-level disable for GIC Distributor
+ *
+ * Inputs
+ *
+ *  flags - control flags to clear
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void DisableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * SyncAREinGICD - synchronise GICD Address Routing Enable bits
+ *
+ * Inputs
+ *
+ *  flags - absolute flag bits to set in GIC Distributor
+ *
+ *  dosync - flag whether to wait for ARE bits to match passed
+ *      flag field (dosync = true), or whether to set absolute
+ *      flag bits (dosync = false)
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ * This function is used to resolve a race in an MP system whereby secondary
+ * CPUs cannot reliably program all Redistributor registers until the
+ * primary CPU has enabled Address Routing. The primary CPU will call this
+ * function with dosync = false, while the secondaries will call it with
+ * dosync = true.
+ */
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
+
+/*
+ * EnableSPI - enable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnableSPI(uint32_t id);
+
+/*
+ * DisableSPI - disable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisableSPI(uint32_t id);
+
+/*
+ * SetSPIPriority - configure the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetSPIPriority(uint32_t id, uint32_t priority);
+
+/*
+ * GetSPIPriority - determine the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  interrupt priority in the range 0 - 0xff
+ */
+uint32_t GetSPIPriority(uint32_t id);
+
+/*
+ * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  affinity - prepacked "dotted quad" affinity routing. NOTE: use the
+ *      gicv3PackAffinity() helper routine to generate this input
+ *
+ *  mode - select routing mode (specific affinity, or any recipient)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
+
+/*
+ * GetSPIRoute - read ARE-enabled interrupt routing information
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  routing configuration
+ */
+uint64_t GetSPIRoute(uint32_t id);
+
+/*
+ * SetSPITarget - configure the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ *  target - 8-bit target bitmap
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPITarget(uint32_t id, uint32_t target);
+
+/*
+ * GetSPITarget - read the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *  8-bit target bitmap
+ */
+uint32_t GetSPITarget(uint32_t id);
+
+/*
+ * ConfigureSPI - setup an interrupt as edge- or level-triggered
+ *
+ * Inputs
+ *
+ *   id - interrupt identifier
+ *
+ *   config - desired configuration
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
+
+/*
+ * SetSPIPending - mark an interrupt as pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetSPIPending(uint32_t id);
+
+/*
+ * ClearSPIPending - mark an interrupt as not pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearSPIPending(uint32_t id);
+
+/*
+ * GetSPIPending - query whether an interrupt is pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetSPIPending(uint32_t id);
+
+/*
+ * SetSPISecurity - mark a shared peripheral interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityBlock - mark a block of 32 shared peripheral
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  block - which block to mark (e.g. 1 = Ints 32-63)
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityAll - mark all shared peripheral interrupts
+ *     as security <group>
+ *
+ * Inputs:
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityAll(GICIGROUPRBits_t group);
+
+/**********************************************************************/
+
+/*
+ * GIC Re-Distributor Function Prototypes
+ *
+ * The model for calling Redistributor functions is that, rather than
+ * identifying the target redistributor with every function call, the
+ * SelectRedistributor() function is used to identify which redistributor
+ * is to be used for all functions until a different redistributor is
+ * explicitly selected
+ */
+
+/*
+ * WakeupGICR - wake up a Redistributor
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to wakeup
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void WakeupGICR(uint32_t gicr);
+
+/*
+ * EnablePrivateInt - enable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * DisablePrivateInt - disable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
+
+/*
+ * GetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *   Int priority
+ */
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
+
+#endif /* ndef GICV3_h */
+
+/* EOF GICv3.h */
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h
new file mode 100644
index 00000000..8e6f0acc
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h
@@ -0,0 +1,249 @@
+/*
+ * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_gicc_h
+#define GICV3_gicc_h
+
+/**********************************************************************/
+
+typedef enum
+{
+    sreSRE = (1 << 0),
+    sreDFB = (1 << 1),
+    sreDIB = (1 << 2),
+    sreEnable = (1 << 3)
+} ICC_SREBits_t;
+
+static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL2(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL2\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL3\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    igrpEnable = (1 << 0),
+    igrpEnableGrp1NS = (1 << 0),
+    igrpEnableGrp1S = (1 << 2)
+} ICC_IGRPBits_t;
+
+static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    ctlrCBPR = (1 << 0),
+    ctlrCBPR_EL1S = (1 << 0),
+    ctlrEOImode = (1 << 1),
+    ctlrCBPR_EL1NS = (1 << 1),
+    ctlrEOImode_EL3 = (1 << 2),
+    ctlrEOImode_EL1S = (1 << 3),
+    ctlrEOImode_EL1NS = (1 << 4),
+    ctlrRM = (1 << 5),
+    ctlrPMHE = (1 << 6)
+} ICC_CTLRBits_t;
+
+static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
+{
+    asm("msr  ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_CTLR_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
+{
+    asm("msr  ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_CTLR_EL3\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+static inline uint64_t getICC_IAR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_IAR0_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_IAR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_IAR1_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_EOIR0(uint32_t interrupt)
+{
+    asm("msr  ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_EOIR1(uint32_t interrupt)
+{
+    asm("msr  ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_DIR(uint32_t interrupt)
+{
+    asm("msr  ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_PMR(uint32_t priority)
+{
+    asm("msr  ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority));
+}
+
+static inline void setICC_BPR0(uint32_t binarypoint)
+{
+    asm("msr  ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline void setICC_BPR1(uint32_t binarypoint)
+{
+    asm("msr  ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline uint64_t getICC_BPR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_BPR0_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_BPR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_BPR1_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_RPR(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_RPR_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    sgirIRMTarget = 0,
+    sgirIRMAll = (1ull << 40)
+} ICC_SGIRBits_t;
+
+static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+#endif /* ndef GICV3_gicc_h */
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c
new file mode 100644
index 00000000..3bfb4a93
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c
@@ -0,0 +1,339 @@
+/*
+ * GICv3_gicd.c - generic driver code for GICv3 distributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include <stdint.h>
+
+#include "GICv3.h"
+
+typedef struct
+{
+        volatile uint32_t GICD_CTLR;              // +0x0000
+  const volatile uint32_t GICD_TYPER;             // +0x0004
+  const volatile uint32_t GICD_IIDR;              // +0x0008
+
+  const volatile uint32_t padding0;               // +0x000c
+
+        volatile uint32_t GICD_STATUSR;           // +0x0010
+
+  const volatile uint32_t padding1[3];            // +0x0014
+
+        volatile uint32_t IMP_DEF[8];             // +0x0020
+
+        volatile uint32_t GICD_SETSPI_NSR;        // +0x0040
+  const volatile uint32_t padding2;               // +0x0044
+        volatile uint32_t GICD_CLRSPI_NSR;        // +0x0048
+  const volatile uint32_t padding3;               // +0x004c
+        volatile uint32_t GICD_SETSPI_SR;         // +0x0050
+  const volatile uint32_t padding4;               // +0x0054
+        volatile uint32_t GICD_CLRSPI_SR;         // +0x0058
+
+  const volatile uint32_t padding5[3];            // +0x005c
+
+        volatile uint32_t GICD_SEIR;              // +0x0068
+
+  const volatile uint32_t padding6[5];            // +0x006c
+
+        volatile uint32_t GICD_IGROUPR[32];       // +0x0080
+
+        volatile uint32_t GICD_ISENABLER[32];     // +0x0100
+        volatile uint32_t GICD_ICENABLER[32];     // +0x0180
+        volatile uint32_t GICD_ISPENDR[32];       // +0x0200
+        volatile uint32_t GICD_ICPENDR[32];       // +0x0280
+        volatile uint32_t GICD_ISACTIVER[32];     // +0x0300
+        volatile uint32_t GICD_ICACTIVER[32];     // +0x0380
+
+        volatile uint8_t  GICD_IPRIORITYR[1024];  // +0x0400
+        volatile uint8_t  GICD_ITARGETSR[1024];   // +0x0800
+        volatile uint32_t GICD_ICFGR[64];         // +0x0c00
+        volatile uint32_t GICD_IGRPMODR[32];      // +0x0d00
+  const volatile uint32_t padding7[32];           // +0x0d80
+        volatile uint32_t GICD_NSACR[64];         // +0x0e00
+
+        volatile uint32_t GICD_SGIR;              // +0x0f00
+
+  const volatile uint32_t padding8[3];            // +0x0f04
+
+        volatile uint32_t GICD_CPENDSGIR[4];      // +0x0f10
+        volatile uint32_t GICD_SPENDSGIR[4];      // +0x0f20
+
+  const volatile uint32_t padding9[52];           // +0x0f30
+  const volatile uint32_t padding10[5120];        // +0x1000
+
+        volatile uint64_t GICD_IROUTER[1024];     // +0x6000
+} GICv3_distributor;
+
+/*
+ * use the scatter file to place GICD
+ */
+static GICv3_distributor __attribute__((section(".bss.distributor"))) gicd;
+
+void ConfigGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR = flags;
+}
+
+void EnableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR |= flags;
+}
+
+void DisableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR &= ~flags;
+}
+
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
+{
+    if (dosync)
+    {
+	const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
+	const uint32_t tval = flags & tmask;
+
+	while ((gicd.GICD_CTLR & tmask) != tval)
+	    continue;
+    }
+    else
+	gicd.GICD_CTLR = flags;
+}
+
+void EnableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ISENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void DisableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ICENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void SetSPIPriority(uint32_t id, uint32_t priority)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    gicd.GICD_IPRIORITYR[bank] = priority;
+}
+
+uint32_t GetSPIPriority(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
+}
+
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
+}
+
+uint64_t GetSPIRoute(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    return gicd.GICD_IROUTER[bank];
+}
+
+void SetSPITarget(uint32_t id, uint32_t target)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    gicd.GICD_ITARGETSR[bank] = target;
+}
+
+uint32_t GetSPITarget(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    /*
+     * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
+     * target bitmap per register
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
+}
+
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
+{
+    uint32_t bank, tmp;
+
+    /*
+     * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
+     * configuration per register
+     */
+    bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
+    config &= 3;
+
+    id = (id & 0xf) << 1;
+
+    tmp = gicd.GICD_ICFGR[bank];
+    tmp &= ~(3 << id);
+    tmp |= config << id;
+    gicd.GICD_ICFGR[bank] = tmp;
+}
+
+void SetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ISPENDR[bank] = 1 << id;
+}
+
+void ClearSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ICPENDR[bank] = 1 << id;
+}
+
+uint32_t GetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    return (gicd.GICD_ICPENDR[bank] >> id) & 1;
+}
+
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
+{
+    uint32_t bank, groupmod;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicd.GICD_IGROUPR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGROUPR[bank] &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicd.GICD_IGRPMODR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
+}
+
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
+{
+    uint32_t groupmod;
+    const uint32_t nbits = (sizeof group * 8) - 1;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
+
+    /*
+     * get each bit of group config duplicated over all 32-bits in a word
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicd.GICD_IGROUPR[block] = group;
+    gicd.GICD_IGRPMODR[block] = groupmod;
+}
+
+void SetSPISecurityAll(GICIGROUPRBits_t group)
+{
+    uint32_t block;
+
+    /*
+     * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
+     * want to iterate over all blocks excluding 0 (which are the
+     * SGI/PPI interrupts, and not relevant here)
+     */
+    for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
+	SetSPISecurityBlock(block, group);
+}
+
+/* EOF GICv3_gicd.c */
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c
new file mode 100644
index 00000000..7b437b18
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c
@@ -0,0 +1,308 @@
+/*
+ * GICv3_gicr.c - generic driver code for GICv3 redistributor
+ *
+ * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include "GICv3.h"
+
+/*
+ * physical LPI Redistributor register map
+ */
+typedef struct
+{
+        volatile uint32_t GICR_CTLR;             // +0x0000 - RW - Redistributor Control Register
+  const volatile uint32_t GICR_IIDR;             // +0x0004 - RO - Implementer Identification Register
+  const volatile uint32_t GICR_TYPER[2];         // +0x0008 - RO - Redistributor Type Register
+        volatile uint32_t GICR_STATUSR;          // +0x0010 - RW - Error Reporting Status Register, optional
+        volatile uint32_t GICR_WAKER;            // +0x0014 - RW - Redistributor Wake Register
+  const volatile uint32_t padding1[2];           // +0x0018 - RESERVED
+#ifndef USE_GIC600
+        volatile uint32_t IMPDEF1[8];            // +0x0020 - ?? - IMPLEMENTATION DEFINED
+#else
+        volatile uint32_t GICR_FCTLR;            // +0x0020 - RW - Function Control Register
+        volatile uint32_t GICR_PWRR;             // +0x0024 - RW - Power Management Control Register
+        volatile uint32_t GICR_CLASS;            // +0x0028 - RW - Class Register
+  const volatile uint32_t padding2[5];           // +0x002C - RESERVED
+#endif
+        volatile uint64_t GICR_SETLPIR;          // +0x0040 - WO - Set LPI Pending Register
+        volatile uint64_t GICR_CLRLPIR;          // +0x0048 - WO - Clear LPI Pending Register
+  const volatile uint32_t padding3[8];           // +0x0050 - RESERVED
+        volatile uint64_t GICR_PROPBASER;        // +0x0070 - RW - Redistributor Properties Base Address Register
+        volatile uint64_t GICR_PENDBASER;        // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
+  const volatile uint32_t padding4[8];           // +0x0080 - RESERVED
+        volatile uint64_t GICR_INVLPIR;          // +0x00A0 - WO - Redistributor Invalidate LPI Register
+  const volatile uint32_t padding5[2];           // +0x00A8 - RESERVED
+        volatile uint64_t GICR_INVALLR;          // +0x00B0 - WO - Redistributor Invalidate All Register
+  const volatile uint32_t padding6[2];           // +0x00B8 - RESERVED
+        volatile uint64_t GICR_SYNCR;            // +0x00C0 - RO - Redistributor Synchronize Register
+  const volatile uint32_t padding7[2];           // +0x00C8 - RESERVED
+  const volatile uint32_t padding8[12];          // +0x00D0 - RESERVED
+        volatile uint64_t IMPDEF2;               // +0x0100 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding9[2];           // +0x0108 - RESERVED
+        volatile uint64_t IMPDEF3;               // +0x0110 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding10[2];          // +0x0118 - RESERVED
+} GICv3_redistributor_RD;
+
+/*
+ * SGI and PPI Redistributor register map
+ */
+typedef struct
+{
+  const volatile uint32_t padding1[32];          // +0x0000 - RESERVED
+        volatile uint32_t GICR_IGROUPR0;         // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
+  const volatile uint32_t padding2[31];          // +0x0084 - RESERVED
+        volatile uint32_t GICR_ISENABLER;        // +0x0100 - RW - Interrupt Set-Enable Registers
+  const volatile uint32_t padding3[31];          // +0x0104 - RESERVED
+        volatile uint32_t GICR_ICENABLER;        // +0x0180 - RW - Interrupt Clear-Enable Registers
+  const volatile uint32_t padding4[31];          // +0x0184 - RESERVED
+        volatile uint32_t GICR_ISPENDR;          // +0x0200 - RW - Interrupt Set-Pending Registers
+  const volatile uint32_t padding5[31];          // +0x0204 - RESERVED
+        volatile uint32_t GICR_ICPENDR;          // +0x0280 - RW - Interrupt Clear-Pending Registers
+  const volatile uint32_t padding6[31];          // +0x0284 - RESERVED
+        volatile uint32_t GICR_ISACTIVER;        // +0x0300 - RW - Interrupt Set-Active Register
+  const volatile uint32_t padding7[31];          // +0x0304 - RESERVED
+        volatile uint32_t GICR_ICACTIVER;        // +0x0380 - RW - Interrupt Clear-Active Register
+  const volatile uint32_t padding8[31];          // +0x0184 - RESERVED
+        volatile uint8_t  GICR_IPRIORITYR[32];   // +0x0400 - RW - Interrupt Priority Registers
+  const volatile uint32_t padding9[504];         // +0x0420 - RESERVED
+        volatile uint32_t GICR_ICnoFGR[2];       // +0x0C00 - RW - Interrupt Configuration Registers
+  const volatile uint32_t padding10[62];         // +0x0C08 - RESERVED
+        volatile uint32_t GICR_IGRPMODR0;        // +0x0D00 - RW - ????
+  const volatile uint32_t padding11[63];         // +0x0D04 - RESERVED
+        volatile uint32_t GICR_NSACR;            // +0x0E00 - RW - Non-Secure Access Control Register
+} GICv3_redistributor_SGI;
+
+/*
+ * We have a multiplicity of GIC Redistributors; on the GIC-AEM and
+ * GIC-500 they are arranged as one 128KB region per redistributor: one
+ * 64KB page of GICR LPI registers, and one 64KB page of GICR Private
+ * Int registers
+ */
+typedef struct
+{
+    union
+    {
+        GICv3_redistributor_RD RD_base;
+        uint8_t padding[64 * 1024];
+    } RDblock;
+
+    union
+    {
+        GICv3_redistributor_SGI SGI_base;
+        uint8_t padding[64 * 1024];
+    } SGIblock;
+} GICv3_GICR;
+
+/*
+ * use the scatter file to place GIC Redistributor base address
+ *
+ * although this code doesn't know how many Redistributor banks
+ * a particular system will have, we declare gicrbase as an array
+ * to avoid unwanted compiler optimisations when calculating the
+ * base of a particular Redistributor bank
+ */
+static const GICv3_GICR gicrbase[2] __attribute__((section (".bss.redistributor")));
+
+/**********************************************************************/
+
+/*
+ * utility functions to calculate base of a particular
+ * Redistributor bank
+ */
+
+static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
+{
+    GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
+
+    return &((arraybase + gicr)->RDblock.RD_base);
+}
+
+static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
+{
+    GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
+
+    return &(arraybase[gicr].SGIblock.SGI_base);
+}
+
+/**********************************************************************/
+
+// This function walks a block of RDs to find one with the matching affinity
+uint32_t GetGICR(uint32_t affinity)
+{
+  GICv3_redistributor_RD* gicr;
+  uint32_t index = 0;
+
+  do
+  {
+    gicr = getgicrRD(index);
+    if (gicr->GICR_TYPER[1] == affinity)
+       return index;
+
+    index++;
+  }
+  while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block
+
+  return 0xFFFFFFFF; // return -1 to signal not RD found
+}
+
+void WakeupGICR(uint32_t gicr)
+{
+    GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
+#ifdef USE_GIC600
+    //Power up Re-distributor for GIC-600
+    gicrRD->GICR_PWRR = 0x2;
+#endif
+
+    /*
+     * step 1 - ensure GICR_WAKER.ProcessorSleep is off
+     */
+    gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
+
+    /*
+     * step 2 - wait for children asleep to be cleared
+     */
+    while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
+        continue;
+
+    /*
+     * OK, GICR is go
+     */
+    return;
+}
+
+void EnablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISENABLER = 1 << id;
+}
+
+void DisablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICENABLER = 1 << id;
+}
+
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    gicrSGI->GICR_IPRIORITYR[id] = priority;
+}
+
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
+}
+
+void SetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISPENDR = 1 << id;
+}
+
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ICPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICPENDR = 1 << id;
+}
+
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
+}
+
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    uint32_t groupmod;
+
+    /*
+     * GICR_IGROUPR0 is one 32-bit register
+     */
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+        gicrSGI->GICR_IGROUPR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+        gicrSGI->GICR_IGRPMODR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
+}
+
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    const uint32_t nbits = (sizeof group * 8) - 1;
+    uint32_t groupmod;
+
+    /*
+     * get each bit of group config duplicated over all 32 bits
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicrSGI->GICR_IGROUPR0 = group;
+    gicrSGI->GICR_IGRPMODR0 = groupmod;
+}
+
+/* EOF GICv3_gicr.c */
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S
new file mode 100644
index 00000000..e7f95aa7
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S
@@ -0,0 +1,133 @@
+//
+// Armv8-A AArch64 - Basic Mutex Example
+// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global _mutex_initialize
+    .global _mutex_acquire
+    .global _mutex_release
+
+//
+// These routines implement the mutex management functions required for running
+// the Arm C library in a multi-threaded environment.
+//
+// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
+//
+// **********************************************************************
+//
+
+    .type _mutex_initialize, "function"
+    .cfi_startproc
+_mutex_initialize:
+
+    //
+    // mark the mutex as unlocked
+    //
+    mov     w1, #0
+    str     w1, [x0]
+
+    //
+    // we are running multi-threaded, so set a non-zero return
+    // value (function prototype says use 1)
+    //
+    mov     w0, #1
+    ret
+    .cfi_endproc
+
+#if !defined(USE_LSE_ATOMIC)
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+
+    //
+    // send ourselves an event, so we don't stick on the wfe at the
+    // top of the loop
+    //
+    sevl
+
+    //
+    // wait until the mutex is available
+    //
+loop:
+    wfe
+    ldaxr   w1, [x0]
+    cbnz    w1, loop
+
+    //
+    // mutex is (at least, it was) available - try to claim it
+    //
+    mov     w1, #1
+    stxr    w2, w1, [x0]
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+
+    mov     w1, #0
+    stlr    w1, [x0]
+    ret
+    .cfi_endproc
+
+#else  // LSE version
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+    // This uses a "ticket lock".  The lock is stored as a 32-bit value: 
+    // - the upper 16-bits record the thread's ticket number ("take a ticket")
+    // - the lower 16-bits record the ticket being served    ("now serving")
+
+    // atomically load then increment the thread's ticket number ("take a ticket")
+    mov w3, #(1 << 16)
+    ldadda w3, w1, [x0]
+
+    // is the ticket now being served?
+    eor w2, w1, w1, ror #16
+    cbz w2, loop_exit
+
+    // no, so wait for the ticket to be served
+
+    // send a local event to avoid missing an unlock before the exclusive load
+    sevl
+
+loop:
+    wfe
+    ldaxrh  w3, [x0]
+    eor w2, w3, w1, lsr #16
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+loop_exit:
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+    mov     w1, #1
+    staddlh w1, [x0]
+    ret
+    .cfi_endproc
+#endif
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h
new file mode 100644
index 00000000..ec1a1d28
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h
@@ -0,0 +1,66 @@
+/*
+ * Armv8-A AArch64 - Basic Mutex Example
+ *
+ * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef MP_MUTEX_H
+#define MP_MUTEX_H
+
+/*
+ * The Arm C library calls-out to these functions to manage multithreading.
+ * They can also be called by user application code.
+ *
+ * Mutex type is specified by the Arm C library
+ *
+ * Declare function prototypes for libc mutex routines
+ */
+typedef signed int *mutex;
+
+/*
+ * int _mutex_initialize(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  0 - application is non-threaded
+ *  1 - application is threaded
+ *  The C library uses the return result to indicate whether it is being used in a multithreaded environment.
+ */
+int _mutex_initialize(mutex *m);
+
+/*
+ * void _mutex_acquire(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  <nothing>
+ *
+ * Side Effects
+ *  Routine does not return until the mutex has been claimed. A load-acquire
+ *  is used to guarantee that the mutex claim is properly ordered with
+ *  respect to any accesses to the resource protected by the mutex
+ */
+void _mutex_acquire(mutex *m);
+
+/*
+ * void _mutex_release(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  <nothing>
+ *
+ * Side Effects
+ *  A store-release is used to guarantee that the mutex release is properly
+ *  ordered with respect any accesses to the resource protected by the mutex
+ */
+void _mutex_release(mutex *m);
+
+#endif
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h
new file mode 100644
index 00000000..52c9a0fe
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h
@@ -0,0 +1,66 @@
+//
+// Private Peripheral Map for the v8 Architecture Envelope Model
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef PPM_AEM_H
+#define PPM_AEM_H
+
+//
+// Distributor layout
+//
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+//
+// CPU Interface layout
+//
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+
+#endif // PPM_AEM_H
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c
new file mode 100644
index 00000000..8898ff39
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c
@@ -0,0 +1,377 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+#include <stddef.h>
+
+#define DEMO_STACK_SIZE         2048
+#define DEMO_BYTE_POOL_SIZE     64000
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+UCHAR					memory_pool[DEMO_BYTE_POOL_SIZE];
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+void init_timer();
+
+/* Define main entry point.  */
+
+int main()
+{
+
+	/* Initialize timer for ThreadX.  */
+	init_timer();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+UCHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.launch b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.launch
new file mode 100644
index 00000000..b0d80e92
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.launch
@@ -0,0 +1,323 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+    <stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+    <stringAttribute key="ANDROID_APPLICATION" value=""/>
+    <stringAttribute key="ANDROID_APP_DIR" value=""/>
+    <stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+    <mapAttribute key="AverageDurationTracker">
+        <mapEntry key="*Fetching Data Model" value="2121447"/>
+        <mapEntry key="*list global low level symbols" value="2860801"/>
+        <mapEntry key="*loading memory from target" value="820184"/>
+        <mapEntry key="*loading values from target" value="15753616"/>
+        <mapEntry key="*trace" value="108193011"/>
+        <mapEntry key="*updating expressions" value="8499254"/>
+        <mapEntry key="*updating registers" value="44165495"/>
+        <mapEntry key="*updating variables" value="4261132"/>
+        <mapEntry key="Add Watchpoint" value="24597988"/>
+        <mapEntry key="AddEventObserver" value="4092335"/>
+        <mapEntry key="Evaluate" value="2222475"/>
+        <mapEntry key="GlobalsLoaderCommand" value="154351059"/>
+        <mapEntry key="Retrieving globals list" value="108099800"/>
+        <mapEntry key="areCachesAvailable" value="1362117"/>
+        <mapEntry key="backtrace" value="5112231"/>
+        <mapEntry key="break" value="38546780"/>
+        <mapEntry key="checking tracepoints" value="241976"/>
+        <mapEntry key="compute execution mode" value="516750"/>
+        <mapEntry key="continue" value="50416727"/>
+        <mapEntry key="core" value="6422300"/>
+        <mapEntry key="directory" value="1721303"/>
+        <mapEntry key="disable" value="1478680"/>
+        <mapEntry key="disassemble" value="47575372"/>
+        <mapEntry key="enable" value="1860234"/>
+        <mapEntry key="evaluate" value="2783965"/>
+        <mapEntry key="evaluate address" value="1323895"/>
+        <mapEntry key="get byte order" value="472733"/>
+        <mapEntry key="get capabilities" value="549106"/>
+        <mapEntry key="get cwd" value="199300"/>
+        <mapEntry key="get execution addresss" value="355530"/>
+        <mapEntry key="get source lines" value="298872"/>
+        <mapEntry key="get substitute paths" value="532537"/>
+        <mapEntry key="get value" value="402104"/>
+        <mapEntry key="getValidEncodings" value="1410473"/>
+        <mapEntry key="initialize command help" value="93797573"/>
+        <mapEntry key="interrupt" value="7684577"/>
+        <mapEntry key="list breakpoint options" value="177556"/>
+        <mapEntry key="list breakpoints" value="1044904"/>
+        <mapEntry key="list instruction sets" value="2271151"/>
+        <mapEntry key="list signals" value="3191996"/>
+        <mapEntry key="list source files" value="864344"/>
+        <mapEntry key="list watchpoint options" value="4854207"/>
+        <mapEntry key="list watchpoints" value="1079163"/>
+        <mapEntry key="loadfile" value="135174365"/>
+        <mapEntry key="next" value="25423704"/>
+        <mapEntry key="nexti" value="29780513"/>
+        <mapEntry key="remove" value="2942358"/>
+        <mapEntry key="run script" value="46791845"/>
+        <mapEntry key="set CWD" value="7797876"/>
+        <mapEntry key="set breakpoint properties" value="10976102"/>
+        <mapEntry key="set debug-from" value="1244377"/>
+        <mapEntry key="set substitute-path" value="103127531"/>
+        <mapEntry key="set watchpoint properties" value="1458988"/>
+        <mapEntry key="source use_model_semihosting.ds" value="9735717"/>
+        <mapEntry key="start" value="75890449"/>
+        <mapEntry key="step" value="30959584"/>
+        <mapEntry key="stepi" value="30815174"/>
+        <mapEntry key="synchronizing trace ranges" value="25240"/>
+        <mapEntry key="toggleBreakpoint" value="14043864"/>
+        <mapEntry key="waitForTargetToStop" value="1016641150"/>
+        <mapEntry key="write expression" value="5812240"/>
+    </mapAttribute>
+    <listAttribute key="DEBUG_TAB."/>
+    <stringAttribute key="DEBUG_TAB..RESOURCES.0.TYPE" value="SOURCE_DIR"/>
+    <stringAttribute key="DEBUG_TAB..RESOURCES.0.VALUE" value="${workspace_loc:/tx}"/>
+    <intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+    <intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+    <intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+    <listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+    <stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+    <stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+    <intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+    <listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+    <stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="APPLICATION_ON_TARGET"/>
+    <stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+    <stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+    <stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+    <intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+    <listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
+    <stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+    <intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+    <listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
+    <stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+    <intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+    <intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+    <listAttribute key="FILES.ICE_DEBUG">
+        <listEntry value="ON_DEMAND_LOAD"/>
+        <listEntry value="ALSO_LOAD_SYMBOLS"/>
+    </listAttribute>
+    <stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+    <stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value="${workspace_loc:/sample_threadx/Debug/sample_threadx.axf}"/>
+    <intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="1"/>
+    <listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+        <listEntry value="ON_DEMAND_LOAD"/>
+        <listEntry value="ALSO_LOAD_SYMBOLS"/>
+    </listAttribute>
+    <stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+    <stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+    <intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+    <listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+        <listEntry value="ON_DEMAND_LOAD"/>
+        <listEntry value="ALSO_LOAD_SYMBOLS"/>
+    </listAttribute>
+    <stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+    <stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+    <stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+    <stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+    <intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+    <stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+    <stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+    <booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+    <booleanAttribute key="InstructionStepping" value="false"/>
+    <booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+    <stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="set semihosting enabled off&#13;&#10;add-symbol-file &quot;${workspace_loc:/sample_threadx/Debug/sample_threadx.axf}&quot; EL1N:0"/>
+    <booleanAttribute key="KEY_COMMANDS_AS_CONNECT" value="false"/>
+    <intAttribute key="Messages.POST_TRIGGER_CAPTURE_SIZE.getLocalisedValue().FMTrace" value="50"/>
+    <booleanAttribute key="Messages.STOP_ON_TRIGGER.getLocalisedValue().FMTrace" value="false"/>
+    <booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+    <stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+    <booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+    <listAttribute key="TREE_NODE_PROPERTIES:debugger.view.ExpressionsView">
+        <listEntry value="NODE CACHE VERSION 1"/>
+        <listEntry value="EXPRESSION_GROUP:Expressions:VALUE:gic_dist:VALUE:(gic_dist)-&gt;padding0"/>
+        <listEntry value="1"/>
+        <listEntry value="element formatter"/>
+        <listEntry value="Unsigned Decimal"/>
+        <listEntry value="EXPRESSION_GROUP:Expressions:VALUE:_tx_thread_current_ptr-&gt;tx_thread_name"/>
+        <listEntry value="1"/>
+        <listEntry value="element formatter"/>
+        <listEntry value="Character"/>
+        <listEntry value="EXPRESSION_GROUP:Expressions:VALUE:$AARCH64::$Core::$SP"/>
+        <listEntry value="1"/>
+        <listEntry value="formatter"/>
+        <listEntry value="Hexadecimal"/>
+    </listAttribute>
+    <listAttribute key="TREE_NODE_PROPERTIES:debugger.view.NewRegisterView">
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+        <listEntry value="REGISTER_SET:$AARCH64"/>
+        <listEntry value="1"/>
+        <listEntry value="expanded"/>
+        <listEntry value="true"/>
+        <listEntry value="REGISTER_GROUP:$AARCH64::$Core"/>
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+        <listEntry value="true"/>
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+    <booleanAttribute key="VFS_ENABLED" value="true"/>
+    <stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+    <stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+    <stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot; hardwareBreakpoint=&quot;yes&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL3:0x0000000080009DC8&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL3:0x0000000080009DC8&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;1&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL1N:0x0000000080009DC8&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
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+    <stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;274&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;159&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;75&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;241&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.MemoryView" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;page&gt;&#10;&#9;&lt;memoryView/&gt;&#10;&lt;/page&gt;&#10;"/>
+    <listAttribute key="debugger.view.MemoryView:current">
+        <listEntry value=""/>
+        <listEntry value=""/>
+    </listAttribute>
+    <stringAttribute key="debugger.view.NewRegisterView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;49&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;false&#9;420&#9;-1&#9;true&#9;3&#9;false&#9;true&#9;41&#9;-1&#9;true&#9;4&#9;false&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;false&#9;37&#9;-1&#9;true&#9;6&#9;false&#9;true&#9;62&#9;-1&#9;true&#9;7&#9;true&#9;false&#9;53&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.NewRegisterView:_selectedRegisterSet" value="All registers"/>
+    <mapAttribute key="debugger.view.NewRegisterView_registerSets"/>
+    <stringAttribute key="debugger.view.StackView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;49&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;45&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;41&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;62&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
+    <listAttribute key="debugger.view.TraceView:TRACE_EXPORT_FILTERS"/>
+    <stringAttribute key="debugger.view.VariableTreeView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;197&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;159&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;75&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;242&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <listAttribute key="debugger.view.VariableTreeView:USER_ADDED_FILE_STATICS"/>
+    <listAttribute key="debugger.view.VariableTreeView:USER_ADDED_GLOBALS"/>
+    <listAttribute key="debugger.view.VariableTreeView:USER_ADDED_UNRESOLVED"/>
+    <booleanAttribute key="debugger.view.expression.DrawAsHex" value="false"/>
+    <booleanAttribute key="debugger.view.register.DrawAsHex" value="false"/>
+    <booleanAttribute key="debugger.view.variable.DrawAsHex" value="false"/>
+    <stringAttribute key="dtsl_config" value="DtslScript"/>
+    <stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
+    <stringAttribute key="dtsl_options_file" value="default"/>
+    <stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
+    <stringAttribute key="launch_configuration_version" value="2020.0"/>
+    <booleanAttribute key="linuxOS" value="false"/>
+    <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
+    <booleanAttribute key="runAfterConnect" value="false"/>
+    <mapAttribute key="scripts_view_script_links">
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
+    </mapAttribute>
+    <listAttribute key="setup">
+        <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
+        <listEntry value="&quot;FVP_Base_Cortex-A35x1&quot;"/>
+    </listAttribute>
+    <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
+    <stringAttribute key="substitutePath" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;tuplelist&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:\temp1702\tx\&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\temp1702\tx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&lt;/tuplelist&gt;&#10;"/>
+    <stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
+</launchConfiguration>
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat
new file mode 100644
index 00000000..e5783c7c
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat
@@ -0,0 +1,103 @@
+;********************************************************
+; Scatter file for Armv8-A Startup code on FVP Base model
+; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+; Use, modification and redistribution of this file is subject to your possession of a
+; valid End User License Agreement for the Arm Product of which these examples are part of 
+; and your compliance with all applicable terms and conditions of such licence agreement.
+;********************************************************
+
+LOAD 0x80000000
+{
+    EXEC +0
+    {
+        startup.o (StartUp, +FIRST)
+        * (+RO, +RW, +ZI)
+    }
+
+    ;
+    ; App stacks for all CPUs
+    ; All stacks and heap are aligned to a cache-line boundary
+    ;
+    ARM_LIB_STACK    +0 ALIGN 64 EMPTY 8 * 0x4000 {}
+
+    ;
+    ; Separate heap - import symbol __use_two_region_memory
+    ; in source code for this to work correctly
+    ;
+    ARM_LIB_HEAP     +0 ALIGN 64 EMPTY 0xA0000 {}
+    
+    ;
+    ; Handler stacks for all CPUs
+    ; All stacks and heap are aligned to a cache-line boundary
+    ;
+    HANDLER_STACK    +0 ALIGN 64 EMPTY 4 * 0x4000 {}
+
+    ;
+    ; Stacks for EL3
+    ;
+    EL3_STACKS       +0 ALIGN 64 EMPTY 8 * 0x1000 {}
+    ;
+    ; Strictly speaking, the L1 tables do not need to
+    ; be so strongly aligned, but no matter
+    ;
+    TTB0_L1          +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    ;
+    ; Various sets of L2 tables
+    ;
+    ; Alignment is 4KB, since the code uses a 4K page
+    ; granularity - larger granularities would require
+    ; correspondingly stricter alignment
+    ;
+    TTB0_L2_RAM      +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    TTB0_L2_PRIVATE  +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    TTB0_L2_PERIPH   +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    ;
+    ; The startup code uses the end of this region to calculate
+    ; the top of memory - do not place any RAM regions after it
+    ;
+    TOP_OF_RAM  +0 EMPTY 4 {}
+
+    ;
+    ; CS3 Peripherals is a 64MB region from 0x1c000000
+    ; that includes the following:
+    ; System Registers             at 0x1C010000
+    ; UART0 (PL011)                at 0x1C090000
+    ; Color LCD Controller (PL111) at 0x1C1F0000
+    ; plus a number of others.
+    ; CS3_PERIPHERALS is used by the startup code for page-table generation
+    ; This region is not truly empty, but we have no
+    ; predefined objects that live within it
+    ;
+    CS3_PERIPHERALS  0x1c000000 EMPTY 0x90000 {}
+
+    ;
+    ; Place the UART peripheral registers data structure
+    ; This is only really needed if USE_SERIAL_PORT is defined, but
+    ; the linker will remove unused sections if not needed
+;    PL011  0x1c090000 UNINIT 0x1000
+;    {
+;        uart.o (+ZI)
+;    }
+    ; Note that some other CS3_PERIPHERALS follow this
+
+    ;
+    ; GICv3 distributor
+    ;
+    GICD  0x2f000000 UNINIT 0x8000
+    {
+        GICv3_gicd.o (.bss.distributor)
+    }
+
+    ;
+    ; GICv3 redistributors
+    ; 128KB for each redistributor in the system
+    ;
+    GICR  0x2f100000 UNINIT 0x80000
+    {
+        GICv3_gicr.o (.bss.redistributor)
+    }
+}
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c
new file mode 100644
index 00000000..4dc009b2
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c
@@ -0,0 +1,122 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "sp804_timer.h"
+
+#define TIMER_SP804_CTRL_TIMEREN     (1 << 7)
+#define TIMER_SP804_CTRL_TIMERMODE   (1 << 6)        // Bit 6:
+#define TIMER_SP804_CTRL_INTENABLE   (1 << 5)
+#define TIMER_SP804_CTRL_TIMERSIZE   (1 << 1)        // Bit 1: 0=16-bit, 1=32-bit
+#define TIMER_SP804_CTRL_ONESHOT     (1 << 0)        // Bit 0: 0=wrapping, 1=one-shot
+
+#define TIMER_SP804_CTRL_PRESCALE_1  (0 << 2)        // clk/1
+#define TIMER_SP804_CTRL_PRESCALE_4  (1 << 2)        // clk/4
+#define TIMER_SP804_CTRL_PRESCALE_8  (2 << 2)        // clk/8
+
+struct sp804_timer
+{
+        volatile uint32_t Time1Load;     // +0x00
+  const volatile uint32_t Time1Value;    // +0x04 - RO
+        volatile uint32_t Timer1Control; // +0x08
+        volatile uint32_t Timer1IntClr;  // +0x0C - WO
+  const volatile uint32_t Timer1RIS;     // +0x10 - RO
+  const volatile uint32_t Timer1MIS;     // +0x14 - RO
+        volatile uint32_t Timer1BGLoad;  // +0x18
+
+        volatile uint32_t Time2Load;     // +0x20
+        volatile uint32_t Time2Value;    // +0x24
+        volatile uint8_t  Timer2Control; // +0x28
+        volatile uint32_t Timer2IntClr;  // +0x2C - WO
+  const volatile uint32_t Timer2RIS;     // +0x30 - RO
+  const volatile uint32_t Timer2MIS;     // +0x34 - RO
+        volatile uint32_t Timer2BGLoad;  // +0x38
+
+  // Not including ID registers
+
+};
+
+// Instance of the dual timer, will be placed using the scatter file
+struct sp804_timer* dual_timer;
+
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address)
+{
+  dual_timer = (struct sp804_timer*)address;
+  return;
+}
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
+{
+  uint32_t tmp = 0;
+
+  dual_timer->Time1Load = load_value;
+
+  // Fixed setting: 32-bit, no prescaling
+  tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
+
+  // Settings from parameters: interrupt generation & reload
+  tmp = tmp | interrupt | auto_reload;
+
+  // Write control register
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Starts the timer
+void startTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp | TIMER_SP804_CTRL_TIMEREN;      // Set TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Stops the timer
+void stopTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN;     // Clear TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void)
+{
+  return dual_timer->Time1Value;
+}
+
+
+void clearTimerIrq(void)
+{
+  // A write to this register, of any value, clears the interrupt
+  dual_timer->Timer1IntClr = 1;
+}
+
+
+// ------------------------------------------------------------
+// End of sp804_timer.c
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h
new file mode 100644
index 00000000..777062cc
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h
@@ -0,0 +1,53 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+// Header Filer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#ifndef _SP804_TIMER_
+#define _SP804_TIMER_
+
+#include <stdint.h>
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address);
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+
+#define SP804_AUTORELOAD   (0)
+#define SP804_SINGLESHOT   (1)
+#define SP804_GENERATE_IRQ (1 << 5)
+#define SP804_NO_IRQ       (0)
+
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
+
+
+// Starts the timer
+void startTimer(void);
+
+
+// Stops the timer
+void stopTimer(void);
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void);
+
+
+// Clears the timer interrupt
+void clearTimerIrq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of sp804_timer.h
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S
new file mode 100644
index 00000000..de100e56
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S
@@ -0,0 +1,779 @@
+// ------------------------------------------------------------
+// Armv8-A MPCore EL3 AArch64 Startup Code
+//
+// Basic Vectors, MMU, caches and GICv3 initialization
+//
+// Exits in EL1 AArch64
+//
+// Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_mmu.h"
+#include "v8_system.h"
+
+
+    .section StartUp, "ax"
+    .balign 4
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+
+    .global InvalidateUDCaches
+    .global ZeroBlock
+
+    .global SetPrivateIntSecurityBlock
+    .global SetSPISecurityAll
+    .global SetPrivateIntPriority
+
+    .global GetGICR
+    .global WakeupGICR
+    .global SyncAREinGICD
+    .global EnableGICD
+    .global EnablePrivateInt
+    .global GetPrivateIntPending
+    .global ClearPrivateIntPending
+
+    .global __main
+    //.global MainApp
+
+    .global Image$$EXEC$$RO$$Base
+    .global Image$$TTB0_L1$$ZI$$Base
+    .global Image$$TTB0_L2_RAM$$ZI$$Base
+    .global Image$$TTB0_L2_PERIPH$$ZI$$Base
+    .global Image$$TOP_OF_RAM$$ZI$$Base
+    .global Image$$GICD$$ZI$$Base
+    .global Image$$ARM_LIB_STACK$$ZI$$Limit
+    .global Image$$EL3_STACKS$$ZI$$Limit
+    .global Image$$CS3_PERIPHERALS$$ZI$$Base
+    // use separate stack and heap, as anticipated by scatter.scat
+    .global __use_two_region_memory
+
+
+// ------------------------------------------------------------
+
+    .global start64
+    .type start64, "function"
+start64:
+
+    //
+    // program the VBARs
+    //
+    ldr x1, =el1_vectors
+    msr VBAR_EL1, x1
+
+    ldr x1, =el2_vectors
+    msr VBAR_EL2, x1
+
+    ldr x1, =el3_vectors
+    msr VBAR_EL3, x1
+
+
+    // GIC-500 comes out of reset in GICv2 compatibility mode - first set
+    // system register enables for all relevant exception levels, and
+    // select GICv3 operating mode
+    //
+    msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL3, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
+
+    //
+    // set lower exception levels as non-secure, with no access
+    // back to EL2 or EL3, and are AArch64 capable
+    //
+    mov x3, #(SCR_EL3_RW  | \
+              SCR_EL3_SMD | \
+              SCR_EL3_NS)      // Set NS bit, to access Non-secure registers
+    msr SCR_EL3, x3
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL2, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
+
+
+    //
+    // no traps or VM modifications from the Hypervisor, EL1 is AArch64
+    //
+    mov x2, #HCR_EL2_RW
+    msr HCR_EL2, x2
+
+    //
+    // VMID is still significant, even when virtualisation is not
+    // being used, so ensure VTTBR_EL2 is properly initialised
+    //
+    msr VTTBR_EL2, xzr
+
+    //
+    // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
+    //  VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
+    // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
+    // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
+    // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
+    //
+    mrs x0, MPIDR_EL1
+    msr VMPIDR_EL2, x0
+    mrs x0, MIDR_EL1
+    msr VPIDR_EL2, x0
+
+    // extract the core number from MPIDR_EL1 and store it in
+    // x19 (defined by the AAPCS as callee-saved), so we can re-use
+    // the number later
+    //
+    bl GetCPUID
+    mov x19, x0
+
+    //
+    // neither EL3 nor EL2 trap floating point or accesses to CPACR
+    //
+    msr CPTR_EL3, xzr
+    msr CPTR_EL2, xzr
+
+    //
+    // SCTLR_ELx may come out of reset with UNKNOWN values so we will
+    // set the fields to 0 except, possibly, the endianess field(s).
+    // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
+    // is not strictly needed, since we're never in EL2 or EL0
+    //
+#ifdef __ARM_BIG_ENDIAN
+    mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
+#else
+    mov x0, #0
+#endif
+    msr SCTLR_EL3, x0
+    msr SCTLR_EL2, x0
+    msr SCTLR_EL1, x0
+
+#ifdef CORTEXA
+    //
+    // Configure ACTLR_EL[23]
+    // ----------------------
+    //
+    // These bits are IMPLEMENTATION DEFINED, so are different for
+    // different processors
+    //
+    // For Cortex-A57, the controls we set are:
+    //
+    //  Enable lower level access to CPUACTLR_EL1
+    //  Enable lower level access to CPUECTLR_EL1
+    //  Enable lower level access to L2CTLR_EL1
+    //  Enable lower level access to L2ECTLR_EL1
+    //  Enable lower level access to L2ACTLR_EL1
+    //
+    mov x0, #((1 << 0) | \
+              (1 << 1) | \
+              (1 << 4) | \
+              (1 << 5) | \
+              (1 << 6))
+
+    msr ACTLR_EL3, x0
+    msr ACTLR_EL2, x0
+
+    //
+    // configure CPUECTLR_EL1
+    //
+    // These bits are IMP DEF, so need to different for different
+    // processors
+    //
+    // SMPEN - bit 6 - Enables the processor to receive cache
+    //                 and TLB maintenance operations
+    //
+    // Note: For Cortex-A57/53 SMPEN should be set before enabling
+    //       the caches and MMU, or performing any cache and TLB
+    //       maintenance operations.
+    //
+    //       This register has a defined reset value, so we use a
+    //       read-modify-write sequence to set SMPEN
+    //
+    mrs x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
+    orr x0, x0, #(1 << 6)  // Set the SMPEN bit
+    msr S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
+
+    isb
+#endif
+
+    //
+    // That's the last of the control settings for now
+    //
+    // Note: no ISB after all these changes, as registers won't be
+    // accessed until after an exception return, which is itself a
+    // context synchronisation event
+    //
+
+    //
+    // Setup some EL3 stack space, ready for calling some subroutines, below.
+    //
+    // Stack space allocation is CPU-specific, so use CPU
+    // number already held in x19
+    //
+    // 2^12 bytes per CPU for the EL3 stacks
+    //
+    ldr x0, =Image$$EL3_STACKS$$ZI$$Limit
+    sub x0, x0, x19, lsl #12
+    mov sp, x0
+
+    //
+    // we need to configure the GIC while still in secure mode, specifically
+    // all PPIs and SPIs have to be programmed as Group1 interrupts
+    //
+
+    //
+    // Before the GIC can be reliably programmed, we need to
+    // enable Affinity Routing, as this affects where the configuration
+    // registers are (with Affinity Routing enabled, some registers are
+    // in the Redistributor, whereas those same registers are in the
+    // Distributor with Affinity Routing disabled (i.e. when in GICv2
+    // compatibility mode).
+    //
+    mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
+    mov x1, x19
+    bl  SyncAREinGICD
+
+    //
+    // The Redistributor comes out of reset assuming the processor is
+    // asleep - correct that assumption
+    //
+    bl  GetAffinity
+    bl  GetGICR
+    mov w20, w0     // Keep a copy for later
+    bl  WakeupGICR
+
+    //
+    // Now we're ready to set security and other initialisations
+    //
+    // This is a per-CPU configuration for these interrupts
+    //
+    // for the first cluster, CPU number is the redistributor index
+    //
+    mov w0, w20
+    mov w1, #1    // gicigroupr_G1NS
+    bl  SetPrivateIntSecurityBlock
+
+    //
+    // While we're in the Secure World, set the priority mask low enough
+    // for it to be writable in the Non-Secure World
+    //
+    //mov x0, #16 << 3    // 5 bits of priority in the Secure world
+    mov x0, #0xFF  // for Non-Secure interrupts
+    msr ICC_PMR_EL1, x0
+
+    //
+    // there's more GIC setup to do, but only for the primary CPU
+    //
+    cbnz x19, drop_to_el1
+
+    //
+    // There's more to do to the GIC - call the utility routine to set
+    // all SPIs to Group1
+    //
+    mov w0, #1    // gicigroupr_G1NS
+    bl  SetSPISecurityAll
+
+    //
+    // Set up EL1 entry point and "dummy" exception return information,
+    // then perform exception return to enter EL1
+    //
+    .global drop_to_el1
+drop_to_el1:
+    adr x1, el1_entry_aarch64
+    msr ELR_EL3, x1
+    mov x1, #(AARCH64_SPSR_EL1h | \
+              AARCH64_SPSR_F  | \
+              AARCH64_SPSR_I  | \
+              AARCH64_SPSR_A)
+    msr SPSR_EL3, x1
+    eret
+
+
+
+// ------------------------------------------------------------
+// EL1 - Common start-up code
+// ------------------------------------------------------------
+
+    .global el1_entry_aarch64
+    .type el1_entry_aarch64, "function"
+el1_entry_aarch64:
+
+    //
+    // Now we're in EL1, setup the application stack
+    // the scatter file allocates 2^14 bytes per app stack
+    //
+    ldr x0, =Image$$HANDLER_STACK$$ZI$$Limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+    MSR     SPSel, #0
+    ISB
+    ldr x0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+
+    //
+    // Enable floating point
+    //
+    mov x0, #CPACR_EL1_FPEN
+    msr CPACR_EL1, x0
+
+    //
+    // Invalidate caches and TLBs for all stage 1
+    // translations used at EL1
+    //
+    // Cortex-A processors automatically invalidate their caches on reset
+    // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
+    // It is therefore not necessary for software to invalidate the caches 
+    // on startup, however, this is done here in case of a warm reset.
+    bl  InvalidateUDCaches
+    tlbi VMALLE1
+
+
+    //
+    // Set TTBR0 Base address
+    //
+    // The CPUs share one set of translation tables that are
+    // generated by CPU0 at run-time
+    //
+    // TTBR1_EL1 is not used in this example
+    //
+    ldr x1, =Image$$TTB0_L1$$ZI$$Base
+    msr TTBR0_EL1, x1
+
+
+    //
+    // Set up memory attributes
+    //
+    // These equate to:
+    //
+    // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
+    // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
+    // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
+    //
+    mov  x1, #0xff44
+    movk x1, #4, LSL #16    // equiv to: movk x1, #0x0000000000040000
+    msr MAIR_EL1, x1
+
+
+    //
+    // Set up TCR_EL1
+    //
+    // We're using only TTBR0 (EPD1 = 1), and the page table entries:
+    //  - are using an 8-bit ASID from TTBR0
+    //  - have a 4K granularity (TG0 = 0b00)
+    //  - are outer-shareable (SH0 = 0b10)
+    //  - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
+    //  - map
+    //      + 32 bits of VA space (T0SZ = 0x20)
+    //      + into a 32-bit PA space (IPS = 0b000)
+    //
+    //     36   32   28   24   20   16   12    8    4    0
+    //  -----+----+----+----+----+----+----+----+----+----+
+    //       |    |    |OOII|    |    |    |OOII|    |    |
+    //    TT |    |    |RRRR|E T |   T|    |RRRR|E T |   T|
+    //    BB | I I|TTSS|GGGG|P 1 |   1|TTSS|GGGG|P 0 |   0|
+    //    IIA| P P|GGHH|NNNN|DAS |   S|GGHH|NNNN|D S |   S|
+    //    10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
+    //
+    //    000 0000 0000 0000 1000 0000 0010 0101 0010 0000
+    //
+    //                    0x    8    0    2    5    2    0
+    //
+    // Note: the ISB is needed to ensure the changes to system
+    //       context are before the write of SCTLR_EL1.M to enable
+    //       the MMU. It is likely on a "real" implementation that
+    //       this setup would work without an ISB, due to the
+    //       amount of code that gets executed before enabling the
+    //       MMU, but that would not be architecturally correct.
+    //
+    ldr x1, =0x0000000000802520
+    msr TCR_EL1, x1
+    isb
+
+    //
+    // x19 already contains the CPU number, so branch to secondary
+    // code if we're not on CPU0
+    //
+    cbnz x19, el1_secondary
+
+    //
+    // Fall through to primary code
+    //
+
+
+//
+// ------------------------------------------------------------
+//
+// EL1 - primary CPU init code
+//
+// This code is run on CPU0, while the other CPUs are in the
+// holding pen
+//
+
+    .global el1_primary
+    .type el1_primary, "function"
+el1_primary:
+
+    //
+    // Turn on the banked GIC distributor enable,
+    // ready for individual CPU enables later
+    //
+    mov w0, #(1 << 1)  // gicdctlr_EnableGrp1A
+    bl  EnableGICD
+
+    //
+    // Generate TTBR0 L1
+    //
+    // at 4KB granularity, 32-bit VA space, table lookup starts at
+    // L1, with 1GB regions
+    //
+    // we are going to create entries pointing to L2 tables for a
+    // couple of these 1GB regions, the first of which is the
+    // RAM on the VE board model - get the table addresses and
+    // start by emptying out the L1 page tables (4 entries at L1
+    // for a 4K granularity)
+    //
+    // x21 = address of L1 tables
+    //
+    ldr x21, =Image$$TTB0_L1$$ZI$$Base
+    mov x0, x21
+    mov x1, #(4 << 3)
+    bl  ZeroBlock
+
+    //
+    // time to start mapping the RAM regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // x22 = address of L2 tables, needs to be remembered in case
+    //       we want to re-use the tables for mapping peripherals
+    //
+    ldr x22, =Image$$TTB0_L2_RAM$$ZI$$Base
+    mov x1, #(512 << 3)
+    mov x0, x22
+    bl  ZeroBlock
+
+    //
+    // Get the start address of RAM (the EXEC region) into x4
+    // and calculate the offset into the L1 table (1GB per region,
+    // max 4GB)
+    //
+    // x23 = L1 table offset, saved for later comparison against
+    //       peripheral offset
+    //
+    ldr x4, =Image$$EXEC$$RO$$Base
+    ubfx x23, x4, #30, #2
+
+    orr x1, x22, #TT_S1_ATTR_PAGE
+    str x1, [x21, x23, lsl #3]
+
+    //
+    // we've already used the RAM start address in x4 - we now need
+    // to get this in terms of an offset into the L2 page tables,
+    // where each entry covers 2MB
+    //
+    ubfx x2, x4, #21, #9
+
+    //
+    // TOP_OF_RAM in the scatter file marks the end of the
+    // Execute region in RAM: convert the end of this region to an
+    // offset too, being careful to round up, then calculate the
+    // number of entries to write
+    //
+    ldr x5, =Image$$TOP_OF_RAM$$ZI$$Base
+    sub  x3, x5, #1
+    ubfx x3, x3, #21, #9
+    add  x3, x3, #1
+    sub  x3, x3, x2
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as Shared, Normal WBWA (MAIR[1]) with a flat
+    // VA->PA translation
+    //
+    bic x4, x4, #((1 << 21) - 1)
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (1 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_SH_INNER | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // factor the offset into the page table address and then write
+    // the entries
+    //
+    add x0, x22, x2, lsl #3
+
+loop1:
+    subs x3, x3, #1
+    str x1, [x0], #8
+    add x1, x1, #0x200, LSL #12    // equiv to add x1, x1, #(1 << 21)  // 2MB per entry
+    bne loop1
+
+
+    //
+    // now mapping the Peripheral regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // The assumption here is that all peripherals live within
+    // a common 1GB region (i.e. that there's a single set of
+    // L2 pages for all the peripherals). We only use a UART
+    // and the GIC in this example, so the assumption is sound
+    //
+    // x24 = address of L2 peripheral tables
+    //
+    ldr x24, =Image$$TTB0_L2_PERIPH$$ZI$$Base
+
+    //
+    // get the GICD address into x4 and calculate
+    // the offset into the L1 table
+    //
+    // x25 = L1 table offset
+    //
+    ldr x4, =Image$$GICD$$ZI$$Base
+    ubfx x25, x4, #30, #2
+
+    //
+    // here's the tricky bit: it's possible that the peripherals are
+    // in the same 1GB region as the RAM, in which case we don't need
+    // to prime a separate set of L2 page tables, nor add them to the
+    // L1 tables
+    //
+    // if we're going to re-use the TTB0_L2_RAM tables, get their
+    // address into x24, which is used later on to write the PTEs
+    //
+    cmp x25, x23
+    csel x24, x22, x24, EQ
+    b.eq nol2setup
+
+    //
+    // Peripherals are in a separate 1GB region, and so have their own
+    // set of L2 tables - clean out the tables and add them to the L1
+    // table
+    //
+    mov x0, x24
+    mov x1, #512 << 3
+    bl  ZeroBlock
+
+    orr x1, x24, #TT_S1_ATTR_PAGE
+    str x1, [x21, x25, lsl #3]
+
+    //
+    // there's only going to be a single 2MB region for GICD (in
+    // x4) - get this in terms of an offset into the L2 page tables
+    //
+    // with larger systems, it is possible that the GIC redistributor
+    // registers require extra 2MB pages, in which case extra code
+    // would be required here
+    //
+nol2setup:
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry for this, so no loop as we have for RAM, above
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // we have CS3_PERIPHERALS that include the UART controller
+    //
+    // Again, the code is making assumptions - this time that the CS3_PERIPHERALS
+    // region uses the same 1GB portion of the address space as the GICD,
+    // and thus shares the same set of L2 page tables
+    //
+    // Get CS3_PERIPHERALS address into x4 and calculate the offset into the
+    // L2 tables
+    //
+    ldr x4, =Image$$CS3_PERIPHERALS$$ZI$$Base
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry again - write it
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // issue a barrier to ensure all table entry writes are complete
+    //
+    dsb ish
+
+    //
+    // Enable the MMU.  Caches will be enabled later, after scatterloading.
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // Branch to C library init code
+    //
+    b  __main
+
+
+// ------------------------------------------------------------
+
+// AArch64 Arm C library startup add-in:
+
+// The Arm Architecture Reference Manual for Armv8-A states:
+//
+//     Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
+//     Correspondingly, the sequence for ensuring that modifications to instructions are available
+//     for execution must include invalidation of the modified locations from the instruction cache,
+//     even if the instructions are held in Normal Non-cacheable memory.
+//     This includes cases where the instruction cache is disabled.
+//
+// To invalidate the AArch64 instruction cache after scatter-loading and before initialization of the stack and heap,
+// it is necessary for the user to:
+//
+// * Implement instruction cache invalidation code in _platform_pre_stackheap_init.
+// * Ensure all code on the path from the program entry up to and including _platform_pre_stackheap_init is located in a root region.
+//
+// In this example, this function is only called once, by the primary core
+
+    .global _platform_pre_stackheap_init
+    .type _platform_pre_stackheap_init, "function"
+    .cfi_startproc
+_platform_pre_stackheap_init:
+    dsb ish     // ensure all previous stores have completed before invalidating
+    ic  ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
+    dsb ish     // ensure completion on inner shareable domain   (which includes secondary cores)
+    isb
+
+    // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    msr SCTLR_EL1, x1
+    isb
+
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+// EL1 - secondary CPU init code
+//
+// This code is run on CPUs 1, 2, 3 etc....
+// ------------------------------------------------------------
+
+    .global el1_secondary
+    .type el1_secondary, "function"
+el1_secondary:
+
+    //
+    // the primary CPU is going to use SGI 15 as a wakeup event
+    // to let us know when it is OK to proceed, so prepare for
+    // receiving that interrupt
+    //
+    // NS interrupt priorities run from 0 to 15, with 15 being
+    // too low a priority to ever raise an interrupt, so let's
+    // use 14
+    //
+    mov w0, w20
+    mov w1, #15
+    mov w2, #14 << 4    // we're in NS world, so 4 bits of priority,
+                        // 8-bit field, - 4 = 4-bit shift
+    bl SetPrivateIntPriority
+
+    mov w0, w20
+    mov w1, #15
+    bl  EnablePrivateInt
+
+    //
+    // set priority mask as low as possible; although,being in the
+    // NS World, we can't set bit[7] of the priority, we still
+    // write all 8-bits of priority to an ICC register
+    //
+    mov x0, #31 << 3
+    msr ICC_PMR_EL1, x0
+
+    //
+    // set global enable and wait for our interrupt to arrive
+    //
+    mov x0, #1
+    msr ICC_IGRPEN1_EL1, x0
+    isb
+
+loop_wfi:
+    dsb SY      // Clear all pending data accesses
+    wfi         // Go to sleep
+
+    //
+    // something woke us from our wait, was it the required interrupt?
+    //
+    mov w0, w20
+    mov w1, #15
+    bl  GetPrivateIntPending
+    cbz w0, loop_wfi
+
+    //
+    // it was - there's no need to actually take the interrupt,
+    // so just clear it
+    //
+    mov w0, w20
+    mov w1, #15
+    bl  ClearPrivateIntPending
+
+    //
+    // Enable the MMU and caches
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // Branch to thread start
+    //
+    //B  MainApp
+    b  __main
+
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/timer_interrupts.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/timer_interrupts.c
new file mode 100644
index 00000000..8f522217
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/timer_interrupts.c
@@ -0,0 +1,152 @@
+/* Bare-metal example for Armv8-A FVP Base model */
+
+/* Timer and interrupts */
+
+/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */
+/* Use, modification and redistribution of this file is subject to your possession of a     */
+/* valid End User License Agreement for the Arm Product of which these examples are part of */
+/* and your compliance with all applicable terms and conditions of such licence agreement.  */
+
+#include <stdio.h>
+
+#include "GICv3.h"
+#include "GICv3_gicc.h"
+#include "sp804_timer.h"
+
+void   _tx_timer_interrupt(void);
+
+// LED Base address
+#define LED_BASE (volatile unsigned int *)0x1C010008
+
+
+void nudge_leds(void) // Move LEDs along
+{
+    static int state = 1;
+    static int value = 1;
+
+    if (state)
+    {
+        int max = (1 << 7);
+        value <<= 1;
+        if (value == max)
+            state = 0;
+    }
+    else
+    {
+        value >>= 1;
+        if (value == 1)
+            state = 1;
+    }
+
+    *LED_BASE = value;  // Update LEDs hardware
+}
+
+
+// Initialize Timer 0 and Interrupt Controller
+void init_timer(void)
+{
+    // Enable interrupts
+    __asm("MSR DAIFClr, #0xF");
+    setICC_IGRPEN1_EL1(igrpEnable);
+
+    // Configure the SP804 timer to generate an interrupt
+    setTimerBaseAddress(0x1C110000);
+    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
+    startTimer();
+
+    // The SP804 timer generates SPI INTID 34.  Enable
+    // this ID, and route it to core 0.0.0.0 (this one!)
+    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
+    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
+    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
+    EnableSPI(34);                                   // Enable INTID 34
+}
+
+
+// --------------------------------------------------------
+
+void irqHandler(void)
+{
+  unsigned int ID;
+
+  ID = getICC_IAR1(); // readIntAck();
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+      //printf("irqHandler() - Reserved INTID %d\n\n", ID);
+      return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("irqHandler() - External timer interrupt\n\n");
+      nudge_leds();
+      clearTimerIrq();
+
+      /* Call ThreadX timer interrupt processing.  */
+      _tx_timer_interrupt();
+
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("irqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
+
+// --------------------------------------------------------
+
+// Not actually used in this example, but provided for completeness
+
+void fiqHandler(void)
+{
+  unsigned int ID;
+  unsigned int aliased = 0;
+
+  ID = getICC_IAR0(); // readIntAck();
+  //printf("fiqHandler() - Read %d from IAR0\n", ID);
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+    //printf("fiqHandler() - Reserved INTID %d\n\n", ID);
+    ID = getICC_IAR1(); // readAliasedIntAck();
+    //printf("fiqHandler() - Read %d from AIAR\n", ID);
+    aliased = 1;
+
+    // If still spurious then simply return
+    if ((1020 <= ID) && (ID <= 1023))
+        return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("fiqHandler() - External timer interrupt\n\n");
+      clearTimerIrq();
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  // NOTE: If the ID was read from the Aliased IAR, then
+  // the aliased EOI register must be used
+  if (aliased == 0)
+    setICC_EOIR0(ID); // writeEOI(ID);
+  else
+    setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S
new file mode 100644
index 00000000..8f9581a4
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S
@@ -0,0 +1,100 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_initialize_low_level                          Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for any low-level processor            */
+/*    initialization, including setting up interrupt vectors, setting     */
+/*    up a periodic timer interrupt source, saving the system stack       */
+/*    pointer for use in ISR processing later, and finding the first      */
+/*    available RAM memory address for tx_application_define.             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_initialize_low_level(VOID)
+// {
+    .global  _tx_initialize_low_level
+    .type    _tx_initialize_low_level, @function
+_tx_initialize_low_level:
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+
+    /* Save the system stack pointer.  */
+    // _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
+
+    LDR     x0, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    MOV     x1, sp                              // Pickup SP
+    BIC     x1, x1, #0xF                        // Get 16-bit alignment
+    STR     x1, [x0]                            // Store system stack
+
+    /* Save the first available memory address.  */
+    /* _tx_initialize_unused_memory =  (VOID_PTR) Image$$ZI$$Limit;  */
+
+    LDR     x0, =_tx_initialize_unused_memory   // Pickup address of unused memory ptr
+    LDR     x1, =zi_limit                       // Pickup unused memory address
+    LDR     x1, [x1]                            //
+    STR     x1, [x0]                            // Store unused memory address
+
+    /* Done, return to caller.  */
+
+    RET                                         // Return to caller
+// }
+
+
+zi_limit:
+    .quad (Image$$TOP_OF_RAM$$Base)
+
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S
new file mode 100644
index 00000000..f8db3bfe
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S
@@ -0,0 +1,179 @@
+// ------------------------------------------------------------
+// Armv8-A AArch64 - Common helper functions
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global EnableCachesEL1
+    .global DisableCachesEL1
+    .global InvalidateUDCaches
+    .global GetMIDR
+    .global GetMPIDR
+    .global GetAffinity
+    .global GetCPUID
+
+// ------------------------------------------------------------
+
+//
+// void EnableCachesEL1(void)
+//
+//    enable Instruction and Data caches
+//
+    .type EnableCachesEL1, "function"
+    .cfi_startproc
+EnableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    orr x0, x0, #SCTLR_ELx_I
+    orr x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+    .type DisableCachesEL1, "function"
+    .cfi_startproc
+DisableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    bic x0, x0, #SCTLR_ELx_I
+    bic x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// void InvalidateUDCaches(void)
+//
+//    Invalidate data and unified caches
+//
+    .type InvalidateUDCaches, "function"
+    .cfi_startproc
+InvalidateUDCaches:
+    // From the Armv8-A Architecture Reference Manual
+
+    dmb  ish                   // ensure all prior inner-shareable accesses have been observed
+
+    mrs  x0, CLIDR_EL1
+    and  w3, w0, #0x07000000   // get 2 x level of coherence
+    lsr  w3, w3, #23
+    cbz  w3, finished
+    mov  w10, #0               // w10 = 2 x cache level
+    mov  w8, #1                // w8 = constant 0b1
+loop_level:
+    add  w2, w10, w10, lsr #1  // calculate 3 x cache level
+    lsr  w1, w0, w2            // extract 3-bit cache type for this level
+    and  w1, w1, #0x7
+    cmp  w1, #2
+    b.lt next_level            // no data or unified cache at this level
+    msr  CSSELR_EL1, x10       // select this cache level
+    isb                        // synchronize change of csselr
+    mrs  x1, CCSIDR_EL1        // read ccsidr
+    and  w2, w1, #7            // w2 = log2(linelen)-4
+    add  w2, w2, #4            // w2 = log2(linelen)
+    ubfx w4, w1, #3, #10       // w4 = max way number, right aligned
+    clz  w5, w4                // w5 = 32-log2(ways), bit position of way in dc operand
+    lsl  w9, w4, w5            // w9 = max way number, aligned to position in dc operand
+    lsl  w16, w8, w5           // w16 = amount to decrement way number per iteration
+loop_way:
+    ubfx w7, w1, #13, #15      // w7 = max set number, right aligned
+    lsl  w7, w7, w2            // w7 = max set number, aligned to position in dc operand
+    lsl  w17, w8, w2           // w17 = amount to decrement set number per iteration
+loop_set:
+    orr  w11, w10, w9          // w11 = combine way number and cache number ...
+    orr  w11, w11, w7          // ... and set number for dc operand
+    dc   isw, x11              // do data cache invalidate by set and way
+    subs w7, w7, w17           // decrement set number
+    b.ge loop_set
+    subs x9, x9, x16           // decrement way number
+    b.ge loop_way
+next_level:
+    add  w10, w10, #2          // increment 2 x cache level
+    cmp  w3, w10
+    b.gt loop_level
+    dsb  sy                    // ensure completion of previous cache maintenance operation
+    isb
+finished:
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// ID Register functions
+//
+
+    .type GetMIDR, "function"
+    .cfi_startproc
+GetMIDR:
+
+    mrs x0, MIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetMPIDR, "function"
+    .cfi_startproc
+GetMPIDR:
+
+    mrs x0, MPIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetAffinity, "function"
+    .cfi_startproc
+GetAffinity:
+
+    mrs x0, MPIDR_EL1
+    ubfx x1, x0, #32, #8
+    bfi  w0, w1, #24, #8
+    ret
+    .cfi_endproc
+
+
+    .type GetCPUID, "function"
+    .cfi_startproc
+GetCPUID:
+
+    mrs x0, MIDR_EL1
+    ubfx    x0, x0, #4, #12 // extract PartNum
+    cmp x0, #0xD0D          // Cortex-A77
+    b.eq DynamIQ
+    cmp x0, #0xD0B          // Cortex-A76
+    b.eq DynamIQ
+    cmp x0, #0xD0A          // Cortex-A75
+    b.eq DynamIQ
+    cmp x0, #0xD05          // Cortex-A55
+    b.eq DynamIQ
+    b Others
+DynamIQ:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+
+Others:
+    mrs x0, MPIDR_EL1
+    ubfx    x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
+    ubfx    x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    add     x0, x1, x2, LSL #2
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h
new file mode 100644
index 00000000..b09079a4
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h
@@ -0,0 +1,103 @@
+/*
+ *
+ * Armv8-A AArch64 common helper functions
+ *
+ * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+
+#ifndef V8_AARCH64_H
+#define V8_AARCH64_H
+
+/*
+ * Parameters for data barriers
+ */
+#define OSHLD   1
+#define OSHST   2
+#define OSH     3
+#define NSHLD   5
+#define NSHST   6
+#define NSH     7
+#define ISHLD   9
+#define ISHST  10
+#define ISH    11
+#define LD     13
+#define ST     14
+#define SY     15
+
+/**********************************************************************/
+
+/*
+ * function prototypes
+ */
+
+/*
+ * void InvalidateUDCaches(void)
+ *   invalidates all Unified and Data Caches
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   <nothing>
+ *
+ * Side Effects
+ *   guarantees that all levels of cache will be invalidated before
+ *   returning to caller
+ */
+void InvalidateUDCaches(void);
+
+/*
+ * unsigned long long EnableCachesEL1(void)
+ *   enables I- and D- caches at EL1
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   New value of SCTLR_EL1
+ *
+ * Side Effects
+ *   context will be synchronised before returning to caller
+ */
+unsigned long long EnableCachesEL1(void);
+
+/*
+ * unsigned long long GetMIDR(void)
+ *   returns the contents of MIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MIDR_EL0
+ */
+unsigned long long GetMIDR(void);
+
+/*
+ * unsigned long long GetMPIDR(void)
+ *   returns the contents of MPIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MPIDR_EL0
+ */
+unsigned long long GetMPIDR(void);
+
+/*
+ * unsigned int GetCPUID(void)
+ *   returns the Aff0 field of MPIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MPIDR_EL0[7:0]
+ */
+unsigned int GetCPUID(void);
+
+#endif
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h
new file mode 100644
index 00000000..ee8834fa
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h
@@ -0,0 +1,128 @@
+//
+// Defines for v8 Memory Model
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_MMU_H
+#define V8_MMU_H
+
+//
+// Translation Control Register fields
+//
+// RGN field encodings
+//
+#define TCR_RGN_NC   0b00
+#define TCR_RGN_WBWA 0b01
+#define TCR_RGN_WT   0b10
+#define TCR_RGN_WBRA 0b11
+
+//
+// Shareability encodings
+//
+#define TCR_SHARE_NONE  0b00
+#define TCR_SHARE_OUTER 0b10
+#define TCR_SHARE_INNER 0b11
+
+//
+// Granule size encodings
+//
+#define TCR_GRANULE_4K  0b00
+#define TCR_GRANULE_64K 0b01
+#define TCR_GRANULE_16K 0b10
+
+//
+// Physical Address sizes
+//
+#define TCR_SIZE_4G   0b000
+#define TCR_SIZE_64G  0b001
+#define TCR_SIZE_1T   0b010
+#define TCR_SIZE_4T   0b011
+#define TCR_SIZE_16T  0b100
+#define TCR_SIZE_256T 0b101
+
+//
+// Translation Control Register fields
+//
+#define TCR_EL1_T0SZ_SHIFT   0
+#define TCR_EL1_EPD0  (1 << 7)
+#define TCR_EL1_IRGN0_SHIFT  8
+#define TCR_EL1_ORGN0_SHIFT 10
+#define TCR_EL1_SH0_SHIFT   12
+#define TCR_EL1_TG0_SHIFT   14
+
+#define TCR_EL1_T1SZ_SHIFT  16
+#define TCR_EL1_A1   (1 << 22)
+#define TCR_EL1_EPD1 (1 << 23)
+#define TCR_EL1_IRGN1_SHIFT 24
+#define TCR_EL1_ORGN1_SHIFT 26
+#define TCR_EL1_SH1_SHIFT   28
+#define TCR_EL1_TG1_SHIFT   30
+#define TCR_EL1_IPS_SHIFT   32
+#define TCR_EL1_AS   (1 << 36)
+#define TCR_EL1_TBI0 (1 << 37)
+#define TCR_EL1_TBI1 (1 << 38)
+
+//
+// Stage 1 Translation Table descriptor fields
+//
+#define TT_S1_ATTR_FAULT (0b00 << 0)
+#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
+#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
+#define TT_S1_ATTR_PAGE  (0b11 << 0) // Level 3
+
+#define TT_S1_ATTR_MATTR_LSB 2
+
+#define TT_S1_ATTR_NS (1 << 5)
+
+#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
+#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
+#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
+#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
+
+#define TT_S1_ATTR_SH_NONE   (0b00 << 8)
+#define TT_S1_ATTR_SH_OUTER  (0b10 << 8)
+#define TT_S1_ATTR_SH_INNER  (0b11 << 8)
+
+#define TT_S1_ATTR_AF (1 << 10)
+#define TT_S1_ATTR_nG (1 << 11)
+
+// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48]
+// and bits[47:16] are bits[47:16] of the output address for a page of memory
+
+#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0
+
+#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0
+
+#define TT_S1_ATTR_CONTIG (1 << 52)
+#define TT_S1_ATTR_PXN    (1 << 53)
+#define TT_S1_ATTR_UXN    (1 << 54)
+
+// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits 
+// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED
+
+#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
+#define TT_S1_MAIR_DEV_nGnRE  0b00000100
+#define TT_S1_MAIR_DEV_nGRE   0b00001000
+#define TT_S1_MAIR_DEV_GRE    0b00001100
+
+//
+// Inner and Outer Normal memory attributes use the same bit patterns
+// Outer attributes just need to be shifted up
+//
+#define TT_S1_MAIR_OUTER_SHIFT 4
+
+#define TT_S1_MAIR_WT_TRANS_RA  0b0010
+
+#define TT_S1_MAIR_WB_TRANS_RA  0b0110
+#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
+
+#define TT_S1_MAIR_WT_RA  0b1010
+
+#define TT_S1_MAIR_WB_RA  0b1110
+#define TT_S1_MAIR_WB_RWA 0b1111
+
+#endif // V8_MMU_H
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h
new file mode 100644
index 00000000..ff96deff
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h
@@ -0,0 +1,115 @@
+//
+// Defines for v8 System Registers
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_SYSTEM_H
+#define V8_SYSTEM_H
+
+//
+// AArch64 SPSR
+//
+#define AARCH64_SPSR_EL3h 0b1101
+#define AARCH64_SPSR_EL3t 0b1100
+#define AARCH64_SPSR_EL2h 0b1001
+#define AARCH64_SPSR_EL2t 0b1000
+#define AARCH64_SPSR_EL1h 0b0101
+#define AARCH64_SPSR_EL1t 0b0100
+#define AARCH64_SPSR_EL0t 0b0000
+#define AARCH64_SPSR_RW (1 << 4)
+#define AARCH64_SPSR_F  (1 << 6)
+#define AARCH64_SPSR_I  (1 << 7)
+#define AARCH64_SPSR_A  (1 << 8)
+#define AARCH64_SPSR_D  (1 << 9)
+#define AARCH64_SPSR_IL (1 << 20)
+#define AARCH64_SPSR_SS (1 << 21)
+#define AARCH64_SPSR_V  (1 << 28)
+#define AARCH64_SPSR_C  (1 << 29)
+#define AARCH64_SPSR_Z  (1 << 30)
+#define AARCH64_SPSR_N  (1 << 31)
+
+//
+// Multiprocessor Affinity Register
+//
+#define MPIDR_EL1_AFF3_LSB 32
+#define MPIDR_EL1_U  (1 << 30)
+#define MPIDR_EL1_MT (1 << 24)
+#define MPIDR_EL1_AFF2_LSB 16
+#define MPIDR_EL1_AFF1_LSB  8
+#define MPIDR_EL1_AFF0_LSB  0
+#define MPIDR_EL1_AFF_WIDTH 8
+
+//
+// Data Cache Zero ID Register
+//
+#define DCZID_EL0_BS_LSB   0
+#define DCZID_EL0_BS_WIDTH 4
+#define DCZID_EL0_DZP_LSB  5
+#define DCZID_EL0_DZP (1 << 5)
+
+//
+// System Control Register
+//
+#define SCTLR_EL1_UCI     (1 << 26)
+#define SCTLR_ELx_EE      (1 << 25)
+#define SCTLR_EL1_E0E     (1 << 24)
+#define SCTLR_ELx_WXN     (1 << 19)
+#define SCTLR_EL1_nTWE    (1 << 18)
+#define SCTLR_EL1_nTWI    (1 << 16)
+#define SCTLR_EL1_UCT     (1 << 15)
+#define SCTLR_EL1_DZE     (1 << 14)
+#define SCTLR_ELx_I       (1 << 12)
+#define SCTLR_EL1_UMA     (1 << 9)
+#define SCTLR_EL1_SED     (1 << 8)
+#define SCTLR_EL1_ITD     (1 << 7)
+#define SCTLR_EL1_THEE    (1 << 6)
+#define SCTLR_EL1_CP15BEN (1 << 5)
+#define SCTLR_EL1_SA0     (1 << 4)
+#define SCTLR_ELx_SA      (1 << 3)
+#define SCTLR_ELx_C       (1 << 2)
+#define SCTLR_ELx_A       (1 << 1)
+#define SCTLR_ELx_M       (1 << 0)
+
+//
+// Architectural Feature Access Control Register
+//
+#define CPACR_EL1_TTA     (1 << 28)
+#define CPACR_EL1_FPEN    (3 << 20)
+
+//
+// Architectural Feature Trap Register
+//
+#define CPTR_ELx_TCPAC (1 << 31)
+#define CPTR_ELx_TTA   (1 << 20)
+#define CPTR_ELx_TFP   (1 << 10)
+
+//
+// Secure Configuration Register
+//
+#define SCR_EL3_TWE  (1 << 13)
+#define SCR_EL3_TWI  (1 << 12)
+#define SCR_EL3_ST   (1 << 11)
+#define SCR_EL3_RW   (1 << 10)
+#define SCR_EL3_SIF  (1 << 9)
+#define SCR_EL3_HCE  (1 << 8)
+#define SCR_EL3_SMD  (1 << 7)
+#define SCR_EL3_EA   (1 << 3)
+#define SCR_EL3_FIQ  (1 << 2)
+#define SCR_EL3_IRQ  (1 << 1)
+#define SCR_EL3_NS   (1 << 0)
+
+//
+// Hypervisor Configuration Register
+//
+#define HCR_EL2_ID   (1 << 33)
+#define HCR_EL2_CD   (1 << 32)
+#define HCR_EL2_RW   (1 << 31)
+#define HCR_EL2_TRVM (1 << 30)
+#define HCR_EL2_HVC  (1 << 29)
+#define HCR_EL2_TDZ  (1 << 28)
+
+#endif // V8_SYSTEM_H
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S
new file mode 100644
index 00000000..f0fcef26
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S
@@ -0,0 +1,69 @@
+//
+// Simple utility routines for baremetal v8 code
+//
+// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//
+// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
+//
+// Zero fill a block of memory
+//   Fill memory pages or similar structures with zeros.
+//   The byte count must be a multiple of the block fill size (16 bytes)
+//
+//  Inputs:
+//    blockPtr - base address of block to fill
+//    nBytes - block size, in bytes
+//
+//  Returns:
+//    pointer to just filled block, NULL if nBytes is
+//  incompatible with block fill size
+//
+    .global ZeroBlock
+    .type ZeroBlock, "function"
+    .cfi_startproc
+ZeroBlock:
+
+    //
+    // we fill data by steam, 16 bytes at a time: check that
+    // blocksize is a multiple of that
+    //
+    ubfx x2, x1, #0, #4
+    cbnz x2, incompatible
+
+    //
+    // we already have one register full of zeros, get another
+    //
+    mov x3, x2
+
+    //
+    // OK, set temporary pointer and away we go
+    //
+    add x0, x0, x1
+
+loop0:
+    subs x1, x1, #16
+    stp  x2, x3, [x0, #-16]!
+    b.ne loop0
+
+    //
+    // that's all - x0 will be back to its start value
+    //
+    ret
+
+    //
+    // parameters are incompatible with block size - return
+    // an indication that this is so
+    //
+incompatible:
+    mov x0,#0
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S
new file mode 100644
index 00000000..9e60e001
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S
@@ -0,0 +1,252 @@
+// ------------------------------------------------------------
+// Armv8-A Vector tables
+//
+// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+    .global c0sync1
+    .global irqHandler
+    .global fiqHandler
+    .global irqFirstLevelHandler
+    .global fiqFirstLevelHandler
+
+    .section  EL1VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el1_vectors:
+c0sync1: B c0sync1
+
+    .balign 0x80
+c0irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr1: B c0serr1
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync1: B cxsync1
+
+    .balign 0x80
+cxirq1: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr1: B cxserr1
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync1: B l64sync1
+
+    .balign 0x80
+l64irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr1: B l64serr1
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync1: B l32sync1
+
+    .balign 0x80
+l32irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr1: B l32serr1
+
+//----------------------------------------------------------------
+
+    .section  EL2VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el2_vectors:
+c0sync2: B c0sync2
+
+    .balign 0x80
+c0irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr2: B c0serr2
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync2: B cxsync2
+
+    .balign 0x80
+cxirq2: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr2: B cxserr2
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync2: B l64sync2
+
+    .balign 0x80
+l64irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr2: B l64serr2
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync2: B l32sync2
+
+    .balign 0x80
+l32irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr2: B l32serr2
+
+//----------------------------------------------------------------
+
+    .section  EL3VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el3_vectors:
+c0sync3: B c0sync3
+
+    .balign 0x80
+c0irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr3: B c0serr3
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync3: B cxsync3
+
+    .balign 0x80
+cxirq3: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr3: B cxserr3
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync3: B l64sync3
+
+    .balign 0x80
+l64irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr3: B l64serr3
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync3: B l32sync3
+
+    .balign 0x80
+l32irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr3: B l32serr3
+
+
+    .section InterruptHandlers, "ax"
+    .balign 4
+
+    .type irqFirstLevelHandler, "function"
+irqFirstLevelHandler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+  BL       irqHandler
+  B        _tx_thread_context_restore
+
+    .type fiqFirstLevelHandler, "function"
+fiqFirstLevelHandler:
+  STP      x29, x30, [sp, #-16]!
+  STP      x18, x19, [sp, #-16]!
+  STP      x16, x17, [sp, #-16]!
+  STP      x14, x15, [sp, #-16]!
+  STP      x12, x13, [sp, #-16]!
+  STP      x10, x11, [sp, #-16]!
+  STP      x8, x9, [sp, #-16]!
+  STP      x6, x7, [sp, #-16]!
+  STP      x4, x5, [sp, #-16]!
+  STP      x2, x3, [sp, #-16]!
+  STP      x0, x1, [sp, #-16]!
+
+  BL       fiqHandler
+
+  LDP      x0, x1, [sp], #16
+  LDP      x2, x3, [sp], #16
+  LDP      x4, x5, [sp], #16
+  LDP      x6, x7, [sp], #16
+  LDP      x8, x9, [sp], #16
+  LDP      x10, x11, [sp], #16
+  LDP      x12, x13, [sp], #16
+  LDP      x14, x15, [sp], #16
+  LDP      x16, x17, [sp], #16
+  LDP      x18, x19, [sp], #16
+  LDP      x29, x30, [sp], #16
+  ERET
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject
new file mode 100644
index 00000000..e75d0d0e
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject
@@ -0,0 +1,220 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6">
+                            							
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+                            							
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+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371.1548806269" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1721512389" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.toolchain.v6.builder"/>
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+                                								
+                                <option id="com.arm.tool.c.linker.option.imagemap.928314316" name="Generate image map (--map)" superClass="com.arm.tool.c.linker.option.imagemap" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.eleminate.572315181" name="Eliminate unused sections (--remove)" superClass="com.arm.tool.c.linker.option.eleminate" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.option.flags.1527266578" name="Other flags" superClass="com.arm.tool.c.linker.option.flags" useByScannerDiscovery="true" valueType="stringList">
+                                    									
+                                    <listOptionValue builtIn="false" value="--symbols"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="--first &quot;txm_module_preamble.o(Init)&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.c.linker.option.redirectoutput.768531550" name="Redirect diagnostics output to file (--list)" superClass="com.arm.tool.c.linker.option.redirectoutput" useByScannerDiscovery="false" value="sample_threadx_module.map" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.linker.v6.option.useMicroLib.755943199" name="Use microlib" superClass="com.arm.tool.linker.v6.option.useMicroLib" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.1298703983" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/txm/Debug/txm.a}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.c.linker.option.callgraph.580370920" name="Generate call graph (--callgraph)" superClass="com.arm.tool.c.linker.option.callgraph" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.verbose.37337082" name="Verbose output (--verbose)" superClass="com.arm.tool.c.linker.option.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.totals.832607305" name="List total code and data sizes of output image (--info=totals)" superClass="com.arm.tool.c.linker.option.totals" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.elim.994414938" name="List unused sections that are eliminated (--info=unused)" superClass="com.arm.tool.c.linker.option.elim" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.compress.597638838" name="Print RW compression information (--info=compression)" superClass="com.arm.tool.c.linker.option.compress" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.inlineinfo.1002296295" name="List functions inlined by linker (--info=inline)" superClass="com.arm.tool.c.linker.option.inlineinfo" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.stack.663754292" name="List stack usage of global symbols (--info=stack)" superClass="com.arm.tool.c.linker.option.stack" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.graphfile.1079396865" name="Callgraph file (--callgraph_file)" superClass="com.arm.tool.c.linker.option.graphfile" useByScannerDiscovery="false" value="callgraph.html" valueType="string"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.project b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.project
new file mode 100644
index 00000000..17f6aba3
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx_module</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.arm.debug.ds.nature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c
new file mode 100644
index 00000000..3a3f8159
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c
@@ -0,0 +1,467 @@
+/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes 
+   examples of eight threads of different priorities, using a message queue, semaphore, mutex, 
+   event flags group, byte pool, and block pool.  */
+
+/* Specify that this is a module!  */
+
+#define TXM_MODULE
+
+
+/* Include the ThreadX module definitions.  */
+
+#include "txm_module.h"
+
+
+/* Define constants.  */
+
+#define DEMO_BYTE_POOL_SIZE     (1024 * 48)
+#define DEMO_STACK_SIZE         (1024 * 4)
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the pool space in the bss section of the module. ULONG is used to 
+   get the word alignment.  */
+
+ULONG                   demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)];
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               *thread_0;
+TX_THREAD               *thread_1;
+TX_THREAD               *thread_2;
+TX_THREAD               *thread_3;
+TX_THREAD               *thread_4;
+TX_THREAD               *thread_5;
+TX_THREAD               *thread_6;
+TX_THREAD               *thread_7;
+TX_QUEUE                *queue_0;
+TX_SEMAPHORE            *semaphore_0;
+TX_MUTEX                *mutex_0;
+TX_EVENT_FLAGS_GROUP    *event_flags_0;
+TX_BYTE_POOL            *byte_pool_0;
+TX_BLOCK_POOL           *block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter = 0;
+ULONG           thread_1_counter = 0;
+ULONG           thread_1_messages_sent = 0;
+ULONG           thread_2_counter = 0;
+ULONG           thread_2_messages_received = 0;
+ULONG           thread_3_counter = 0;
+ULONG           thread_4_counter = 0;
+ULONG           thread_5_counter = 0;
+ULONG           thread_6_counter = 0;
+ULONG           thread_7_counter = 0;
+ULONG           semaphore_0_puts = 0;
+ULONG           event_0_sets = 0;
+ULONG           queue_0_sends = 0;
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+void  semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
+{
+
+    if (semaphore_ptr == semaphore_0)
+        semaphore_0_puts++;
+}
+
+
+void  event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
+{
+
+    if (event_flag_group_ptr == event_flags_0)
+        event_0_sets++;
+}
+
+
+void  queue_0_notify(TX_QUEUE *queue_ptr)
+{
+
+    if (queue_ptr == queue_0)
+        queue_0_sends++;
+}
+
+
+/* Define the module start function.  */
+
+void    demo_module_start(ULONG id)
+{
+
+UINT    status;
+CHAR    *pointer;
+
+
+    /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within
+       their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting 
+       the control block(s).  */
+    status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
+    while (status != TX_SUCCESS);
+                               
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
+    while (status != TX_SUCCESS);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create the main thread.  */
+    status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 1.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 2.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 3.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 4.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 5.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 6.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 7.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the message queue.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    status = tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+    while (status != TX_SUCCESS);
+
+    status = tx_queue_send_notify(queue_0, queue_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    status = tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
+    while (status != TX_SUCCESS);
+
+    status = tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    status = tx_event_flags_create(event_flags_0, "module event flags 0");
+    while (status != TX_SUCCESS);
+
+    status = tx_event_flags_set_notify(event_flags_0, event_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    status = tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the memory for a small block pool.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    status = tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+    while (status != TX_SUCCESS);
+
+    /* Allocate a block and release the block memory.  */
+    status = tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Release the block back to the pool.  */
+    status = tx_block_release(pointer);
+    while (status != TX_SUCCESS);
+}
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+    
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+       
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S
new file mode 100644
index 00000000..f05656c3
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S
@@ -0,0 +1,63 @@
+    .text
+    .align 4
+    .section Init
+    
+    // External references
+    .global  _txm_module_thread_shell_entry
+    .global  _txm_module_callback_request_thread_entry
+    .global  demo_module_start
+    .global  Image$$ER_RO$$Length
+    .global  Image$$ER_RW$$Length
+    .global  Image$$ER_ZI$$Length
+
+    .global __txm_module_preamble
+__txm_module_preamble:
+    .dc.l   0x4D4F4455                                          // Module ID
+    .dc.l   0x6                                                 // Module Major Version
+    .dc.l   0x1                                                 // Module Minor Version
+    .dc.l   32                                                  // Module Preamble Size in 32-bit words
+    .dc.l   0x12345678                                          // Module ID (application defined)
+    .dc.l   0x01000000                                          // Module Properties where:
+                                                                //   Bits 31-24: Compiler ID
+                                                                //           0 -> IAR
+                                                                //           1 -> ARM
+                                                                //           2 -> GNU
+                                                                //   Bit 0:  0 -> Privileged mode execution
+                                                                //           1 -> User mode execution
+                                                                //   Bit 1:  0 -> No MPU protection
+                                                                //           1 -> MPU protection (must have user mode selected)
+                                                                //   Bit 2:  0 -> Disable shared/external memory access
+                                                                //           1 -> Enable shared/external memory access
+    .dc.l   _txm_module_thread_shell_entry                      // Module Shell Entry Point
+    .dc.l   demo_module_start                                   // Module Start Thread Entry Point
+    .dc.l   0                                                   // Module Stop Thread Entry Point
+    .dc.l   1                                                   // Module Start/Stop Thread Priority
+    .dc.l   4096                                                // Module Start/Stop Thread Stack Size
+    .dc.l   _txm_module_callback_request_thread_entry           // Module Callback Thread Entry
+    .dc.l   1                                                   // Module Callback Thread Priority
+    .dc.l   4096                                                // Module Callback Thread Stack Size
+    .dc.l   Image$$ER_RO$$Length                                // Module Code Size
+    .dc.l   Image$$ER_ZI$$Length                                // Module Data Size
+    .dc.l   0                                                   // Reserved 0
+    .dc.l   0                                                   // Reserved 1
+    .dc.l   0                                                   // Reserved 2
+    .dc.l   0                                                   // Reserved 3
+    .dc.l   0                                                   // Reserved 4
+    .dc.l   0                                                   // Reserved 5
+    .dc.l   0                                                   // Reserved 6
+    .dc.l   0                                                   // Reserved 7
+    .dc.l   0                                                   // Reserved 8
+    .dc.l   0                                                   // Reserved 9
+    .dc.l   0                                                   // Reserved 10
+    .dc.l   0                                                   // Reserved 11
+    .dc.l   0                                                   // Reserved 12
+    .dc.l   0                                                   // Reserved 13
+    .dc.l   0                                                   // Reserved 14
+    .dc.l   0                                                   // Reserved 15
+
+.image__er_ro__length:
+    .quad Image$$ER_RO$$Length
+.image__er_rw__length:
+    .quad Image$$ER_RW$$Length
+.image__er_zi__length:
+    .quad Image$$ER_ZI$$Length
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject
new file mode 100644
index 00000000..77c12df2
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject
@@ -0,0 +1,238 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6">
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.debug.level.2012923809" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371.1548806269" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx_module_manager}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1721512389" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.cpu.1798518755" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.defmac.663509616" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/sample_threadx_module_manager/inc_common_module_manager}&quot;"/>
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+                                </option>
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+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.904753152" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
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+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1069377025" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
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+                            </tool>
+                            							
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+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.target.1007894450" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="aarch64-arm-none-eabi" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.cpu.1820500228" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
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+                                <option id="com.arm.tool.assembler.v6.base.option.fpu.969773893" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.inst.1333768272" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.auto" valueType="enumerated"/>
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+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.incpath.1361570371" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath"/>
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+                                <option id="com.arm.tool.assembler.v6.base.option.force.preproc.1310042074" name="Preprocess input files (-x assembler-with-cpp)" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
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+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.linker.option.entry.1032206829" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="start64" valueType="string"/>
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+                                <option id="com.arm.tool.c.linker.option.scatter.1463218579" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="../sample_threadx.scat" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.libs.402211535" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="..\..\tx\Debug\tx.a"/>
+                                    								
+                                </option>
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+                                <option id="com.arm.tool.c.linker.option.verbose.1037588003" name="Verbose output (--verbose)" superClass="com.arm.tool.c.linker.option.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+                                <option id="com.arm.tool.c.linker.option.imagemap.288784399" name="Generate image map (--map)" superClass="com.arm.tool.c.linker.option.imagemap" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+                                <option id="com.arm.tool.c.linker.option.totals.202338982" name="List total code and data sizes of output image (--info=totals)" superClass="com.arm.tool.c.linker.option.totals" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+                                <option id="com.arm.tool.c.linker.option.elim.906699010" name="List unused sections that are eliminated (--info=unused)" superClass="com.arm.tool.c.linker.option.elim" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.compress.146553876" name="Print RW compression information (--info=compression)" superClass="com.arm.tool.c.linker.option.compress" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+                                <option id="com.arm.tool.c.linker.option.stack.1124843323" name="List stack usage of global symbols (--info=stack)" superClass="com.arm.tool.c.linker.option.stack" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.inlineinfo.1507799506" name="List functions inlined by linker (--info=inline)" superClass="com.arm.tool.c.linker.option.inlineinfo" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.redirectoutput.1150221552" name="Redirect diagnostics output to file (--list)" superClass="com.arm.tool.c.linker.option.redirectoutput" useByScannerDiscovery="false" value="sample_threadx_module_manager.map" valueType="string"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520.574595573" name="/" resourcePath="src_common_module_manager">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.1223583858" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6" unusedChildren="">
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+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986.1006506546" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986"/>
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+                            <option id="com.arm.toolchain.v6.base.options.debug.level.2012923809.1155748230" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level.2012923809"/>
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+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1927525577" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258">
+                                								
+                                <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1304794003" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/>
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+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.1573521907" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072">
+                                								
+                                <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1807654698" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1808081220" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179">
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.579682311" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.641966454" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.616745103" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx_module_manager.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.project b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.project
new file mode 100644
index 00000000..310289aa
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.project
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx_module_manager</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_common_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
+		</link>
+		<link>
+			<name>src_common_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h
new file mode 100644
index 00000000..23bc7fd8
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h
@@ -0,0 +1,561 @@
+/*
+ * GICv3.h - data types and function prototypes for GICv3 utility routines
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_h
+#define GICV3_h
+
+#include <stdint.h>
+
+/*
+ * extra flags for GICD enable
+ */
+typedef enum
+{
+    gicdctlr_EnableGrp0 = (1 << 0),
+    gicdctlr_EnableGrp1NS = (1 << 1),
+    gicdctlr_EnableGrp1A = (1 << 1),
+    gicdctlr_EnableGrp1S = (1 << 2),
+    gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
+    gicdctlr_ARE_S = (1 << 4),	/* Enable Secure state affinity routing */
+    gicdctlr_ARE_NS = (1 << 5),	/* Enable Non-Secure state affinity routing */
+    gicdctlr_DS = (1 << 6),	/* Disable Security support */
+    gicdctlr_E1NWF = (1 << 7)	/* Enable "1-of-N" wakeup model */
+} GICDCTLRFlags_t;
+
+/*
+ * modes for SPI routing
+ */
+typedef enum
+{
+    gicdirouter_ModeSpecific = 0,
+    gicdirouter_ModeAny = (1 << 31)
+} GICDIROUTERBits_t;
+
+typedef enum
+{
+    gicdicfgr_Level = 0,
+    gicdicfgr_Edge = (1 << 1)
+} GICDICFGRBits_t;
+
+typedef enum
+{
+    gicigroupr_G0S = 0,
+    gicigroupr_G1NS = (1 << 0),
+    gicigroupr_G1S = (1 << 2)
+} GICIGROUPRBits_t;
+
+typedef enum
+{
+    gicrwaker_ProcessorSleep = (1 << 1),
+    gicrwaker_ChildrenAsleep = (1 << 2)
+} GICRWAKERBits_t;
+
+/**********************************************************************/
+
+/*
+ * Utility macros & functions
+ */
+#define RANGE_LIMIT(x)		((sizeof(x) / sizeof((x)[0])) - 1)
+
+static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
+					 uint32_t aff1, uint32_t aff0)
+{
+    /*
+     * only need to cast aff3 to get type promotion for all affinities
+     */
+    return ((((uint64_t)aff3 & 0xff) << 32) |
+	    ((aff2 & 0xff) << 16) |
+	    ((aff1 & 0xff) << 8) | aff0);
+}
+
+/**********************************************************************/
+
+/*
+ * GIC Distributor Function Prototypes
+ */
+
+/*
+ * ConfigGICD - configure GIC Distributor prior to enabling it
+ *
+ * Inputs:
+ *
+ *  control - control flags
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void ConfigGICD(GICDCTLRFlags_t flags);
+
+/*
+ * EnableGICD - top-level enable for GIC Distributor
+ *
+ * Inputs:
+ *
+ *  flags - new control flags to set
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void EnableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * DisableGICD - top-level disable for GIC Distributor
+ *
+ * Inputs
+ *
+ *  flags - control flags to clear
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void DisableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * SyncAREinGICD - synchronise GICD Address Routing Enable bits
+ *
+ * Inputs
+ *
+ *  flags - absolute flag bits to set in GIC Distributor
+ *
+ *  dosync - flag whether to wait for ARE bits to match passed
+ *      flag field (dosync = true), or whether to set absolute
+ *      flag bits (dosync = false)
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ * This function is used to resolve a race in an MP system whereby secondary
+ * CPUs cannot reliably program all Redistributor registers until the
+ * primary CPU has enabled Address Routing. The primary CPU will call this
+ * function with dosync = false, while the secondaries will call it with
+ * dosync = true.
+ */
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
+
+/*
+ * EnableSPI - enable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnableSPI(uint32_t id);
+
+/*
+ * DisableSPI - disable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisableSPI(uint32_t id);
+
+/*
+ * SetSPIPriority - configure the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetSPIPriority(uint32_t id, uint32_t priority);
+
+/*
+ * GetSPIPriority - determine the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  interrupt priority in the range 0 - 0xff
+ */
+uint32_t GetSPIPriority(uint32_t id);
+
+/*
+ * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  affinity - prepacked "dotted quad" affinity routing. NOTE: use the
+ *      gicv3PackAffinity() helper routine to generate this input
+ *
+ *  mode - select routing mode (specific affinity, or any recipient)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
+
+/*
+ * GetSPIRoute - read ARE-enabled interrupt routing information
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  routing configuration
+ */
+uint64_t GetSPIRoute(uint32_t id);
+
+/*
+ * SetSPITarget - configure the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ *  target - 8-bit target bitmap
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPITarget(uint32_t id, uint32_t target);
+
+/*
+ * GetSPITarget - read the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *  8-bit target bitmap
+ */
+uint32_t GetSPITarget(uint32_t id);
+
+/*
+ * ConfigureSPI - setup an interrupt as edge- or level-triggered
+ *
+ * Inputs
+ *
+ *   id - interrupt identifier
+ *
+ *   config - desired configuration
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
+
+/*
+ * SetSPIPending - mark an interrupt as pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetSPIPending(uint32_t id);
+
+/*
+ * ClearSPIPending - mark an interrupt as not pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearSPIPending(uint32_t id);
+
+/*
+ * GetSPIPending - query whether an interrupt is pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetSPIPending(uint32_t id);
+
+/*
+ * SetSPISecurity - mark a shared peripheral interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityBlock - mark a block of 32 shared peripheral
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  block - which block to mark (e.g. 1 = Ints 32-63)
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityAll - mark all shared peripheral interrupts
+ *     as security <group>
+ *
+ * Inputs:
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityAll(GICIGROUPRBits_t group);
+
+/**********************************************************************/
+
+/*
+ * GIC Re-Distributor Function Prototypes
+ *
+ * The model for calling Redistributor functions is that, rather than
+ * identifying the target redistributor with every function call, the
+ * SelectRedistributor() function is used to identify which redistributor
+ * is to be used for all functions until a different redistributor is
+ * explicitly selected
+ */
+
+/*
+ * WakeupGICR - wake up a Redistributor
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to wakeup
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void WakeupGICR(uint32_t gicr);
+
+/*
+ * EnablePrivateInt - enable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * DisablePrivateInt - disable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
+
+/*
+ * GetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *   Int priority
+ */
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
+
+#endif /* ndef GICV3_h */
+
+/* EOF GICv3.h */
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h
new file mode 100644
index 00000000..8e6f0acc
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h
@@ -0,0 +1,249 @@
+/*
+ * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_gicc_h
+#define GICV3_gicc_h
+
+/**********************************************************************/
+
+typedef enum
+{
+    sreSRE = (1 << 0),
+    sreDFB = (1 << 1),
+    sreDIB = (1 << 2),
+    sreEnable = (1 << 3)
+} ICC_SREBits_t;
+
+static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL2(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL2\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL3\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    igrpEnable = (1 << 0),
+    igrpEnableGrp1NS = (1 << 0),
+    igrpEnableGrp1S = (1 << 2)
+} ICC_IGRPBits_t;
+
+static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    ctlrCBPR = (1 << 0),
+    ctlrCBPR_EL1S = (1 << 0),
+    ctlrEOImode = (1 << 1),
+    ctlrCBPR_EL1NS = (1 << 1),
+    ctlrEOImode_EL3 = (1 << 2),
+    ctlrEOImode_EL1S = (1 << 3),
+    ctlrEOImode_EL1NS = (1 << 4),
+    ctlrRM = (1 << 5),
+    ctlrPMHE = (1 << 6)
+} ICC_CTLRBits_t;
+
+static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
+{
+    asm("msr  ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_CTLR_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
+{
+    asm("msr  ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_CTLR_EL3\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+static inline uint64_t getICC_IAR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_IAR0_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_IAR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_IAR1_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_EOIR0(uint32_t interrupt)
+{
+    asm("msr  ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_EOIR1(uint32_t interrupt)
+{
+    asm("msr  ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_DIR(uint32_t interrupt)
+{
+    asm("msr  ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_PMR(uint32_t priority)
+{
+    asm("msr  ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority));
+}
+
+static inline void setICC_BPR0(uint32_t binarypoint)
+{
+    asm("msr  ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline void setICC_BPR1(uint32_t binarypoint)
+{
+    asm("msr  ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline uint64_t getICC_BPR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_BPR0_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_BPR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_BPR1_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_RPR(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_RPR_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    sgirIRMTarget = 0,
+    sgirIRMAll = (1ull << 40)
+} ICC_SGIRBits_t;
+
+static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+#endif /* ndef GICV3_gicc_h */
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c
new file mode 100644
index 00000000..3bfb4a93
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c
@@ -0,0 +1,339 @@
+/*
+ * GICv3_gicd.c - generic driver code for GICv3 distributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include <stdint.h>
+
+#include "GICv3.h"
+
+typedef struct
+{
+        volatile uint32_t GICD_CTLR;              // +0x0000
+  const volatile uint32_t GICD_TYPER;             // +0x0004
+  const volatile uint32_t GICD_IIDR;              // +0x0008
+
+  const volatile uint32_t padding0;               // +0x000c
+
+        volatile uint32_t GICD_STATUSR;           // +0x0010
+
+  const volatile uint32_t padding1[3];            // +0x0014
+
+        volatile uint32_t IMP_DEF[8];             // +0x0020
+
+        volatile uint32_t GICD_SETSPI_NSR;        // +0x0040
+  const volatile uint32_t padding2;               // +0x0044
+        volatile uint32_t GICD_CLRSPI_NSR;        // +0x0048
+  const volatile uint32_t padding3;               // +0x004c
+        volatile uint32_t GICD_SETSPI_SR;         // +0x0050
+  const volatile uint32_t padding4;               // +0x0054
+        volatile uint32_t GICD_CLRSPI_SR;         // +0x0058
+
+  const volatile uint32_t padding5[3];            // +0x005c
+
+        volatile uint32_t GICD_SEIR;              // +0x0068
+
+  const volatile uint32_t padding6[5];            // +0x006c
+
+        volatile uint32_t GICD_IGROUPR[32];       // +0x0080
+
+        volatile uint32_t GICD_ISENABLER[32];     // +0x0100
+        volatile uint32_t GICD_ICENABLER[32];     // +0x0180
+        volatile uint32_t GICD_ISPENDR[32];       // +0x0200
+        volatile uint32_t GICD_ICPENDR[32];       // +0x0280
+        volatile uint32_t GICD_ISACTIVER[32];     // +0x0300
+        volatile uint32_t GICD_ICACTIVER[32];     // +0x0380
+
+        volatile uint8_t  GICD_IPRIORITYR[1024];  // +0x0400
+        volatile uint8_t  GICD_ITARGETSR[1024];   // +0x0800
+        volatile uint32_t GICD_ICFGR[64];         // +0x0c00
+        volatile uint32_t GICD_IGRPMODR[32];      // +0x0d00
+  const volatile uint32_t padding7[32];           // +0x0d80
+        volatile uint32_t GICD_NSACR[64];         // +0x0e00
+
+        volatile uint32_t GICD_SGIR;              // +0x0f00
+
+  const volatile uint32_t padding8[3];            // +0x0f04
+
+        volatile uint32_t GICD_CPENDSGIR[4];      // +0x0f10
+        volatile uint32_t GICD_SPENDSGIR[4];      // +0x0f20
+
+  const volatile uint32_t padding9[52];           // +0x0f30
+  const volatile uint32_t padding10[5120];        // +0x1000
+
+        volatile uint64_t GICD_IROUTER[1024];     // +0x6000
+} GICv3_distributor;
+
+/*
+ * use the scatter file to place GICD
+ */
+static GICv3_distributor __attribute__((section(".bss.distributor"))) gicd;
+
+void ConfigGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR = flags;
+}
+
+void EnableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR |= flags;
+}
+
+void DisableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR &= ~flags;
+}
+
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
+{
+    if (dosync)
+    {
+	const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
+	const uint32_t tval = flags & tmask;
+
+	while ((gicd.GICD_CTLR & tmask) != tval)
+	    continue;
+    }
+    else
+	gicd.GICD_CTLR = flags;
+}
+
+void EnableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ISENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void DisableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ICENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void SetSPIPriority(uint32_t id, uint32_t priority)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    gicd.GICD_IPRIORITYR[bank] = priority;
+}
+
+uint32_t GetSPIPriority(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
+}
+
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
+}
+
+uint64_t GetSPIRoute(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    return gicd.GICD_IROUTER[bank];
+}
+
+void SetSPITarget(uint32_t id, uint32_t target)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    gicd.GICD_ITARGETSR[bank] = target;
+}
+
+uint32_t GetSPITarget(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    /*
+     * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
+     * target bitmap per register
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
+}
+
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
+{
+    uint32_t bank, tmp;
+
+    /*
+     * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
+     * configuration per register
+     */
+    bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
+    config &= 3;
+
+    id = (id & 0xf) << 1;
+
+    tmp = gicd.GICD_ICFGR[bank];
+    tmp &= ~(3 << id);
+    tmp |= config << id;
+    gicd.GICD_ICFGR[bank] = tmp;
+}
+
+void SetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ISPENDR[bank] = 1 << id;
+}
+
+void ClearSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ICPENDR[bank] = 1 << id;
+}
+
+uint32_t GetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    return (gicd.GICD_ICPENDR[bank] >> id) & 1;
+}
+
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
+{
+    uint32_t bank, groupmod;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicd.GICD_IGROUPR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGROUPR[bank] &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicd.GICD_IGRPMODR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
+}
+
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
+{
+    uint32_t groupmod;
+    const uint32_t nbits = (sizeof group * 8) - 1;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
+
+    /*
+     * get each bit of group config duplicated over all 32-bits in a word
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicd.GICD_IGROUPR[block] = group;
+    gicd.GICD_IGRPMODR[block] = groupmod;
+}
+
+void SetSPISecurityAll(GICIGROUPRBits_t group)
+{
+    uint32_t block;
+
+    /*
+     * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
+     * want to iterate over all blocks excluding 0 (which are the
+     * SGI/PPI interrupts, and not relevant here)
+     */
+    for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
+	SetSPISecurityBlock(block, group);
+}
+
+/* EOF GICv3_gicd.c */
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c
new file mode 100644
index 00000000..7b437b18
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c
@@ -0,0 +1,308 @@
+/*
+ * GICv3_gicr.c - generic driver code for GICv3 redistributor
+ *
+ * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include "GICv3.h"
+
+/*
+ * physical LPI Redistributor register map
+ */
+typedef struct
+{
+        volatile uint32_t GICR_CTLR;             // +0x0000 - RW - Redistributor Control Register
+  const volatile uint32_t GICR_IIDR;             // +0x0004 - RO - Implementer Identification Register
+  const volatile uint32_t GICR_TYPER[2];         // +0x0008 - RO - Redistributor Type Register
+        volatile uint32_t GICR_STATUSR;          // +0x0010 - RW - Error Reporting Status Register, optional
+        volatile uint32_t GICR_WAKER;            // +0x0014 - RW - Redistributor Wake Register
+  const volatile uint32_t padding1[2];           // +0x0018 - RESERVED
+#ifndef USE_GIC600
+        volatile uint32_t IMPDEF1[8];            // +0x0020 - ?? - IMPLEMENTATION DEFINED
+#else
+        volatile uint32_t GICR_FCTLR;            // +0x0020 - RW - Function Control Register
+        volatile uint32_t GICR_PWRR;             // +0x0024 - RW - Power Management Control Register
+        volatile uint32_t GICR_CLASS;            // +0x0028 - RW - Class Register
+  const volatile uint32_t padding2[5];           // +0x002C - RESERVED
+#endif
+        volatile uint64_t GICR_SETLPIR;          // +0x0040 - WO - Set LPI Pending Register
+        volatile uint64_t GICR_CLRLPIR;          // +0x0048 - WO - Clear LPI Pending Register
+  const volatile uint32_t padding3[8];           // +0x0050 - RESERVED
+        volatile uint64_t GICR_PROPBASER;        // +0x0070 - RW - Redistributor Properties Base Address Register
+        volatile uint64_t GICR_PENDBASER;        // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
+  const volatile uint32_t padding4[8];           // +0x0080 - RESERVED
+        volatile uint64_t GICR_INVLPIR;          // +0x00A0 - WO - Redistributor Invalidate LPI Register
+  const volatile uint32_t padding5[2];           // +0x00A8 - RESERVED
+        volatile uint64_t GICR_INVALLR;          // +0x00B0 - WO - Redistributor Invalidate All Register
+  const volatile uint32_t padding6[2];           // +0x00B8 - RESERVED
+        volatile uint64_t GICR_SYNCR;            // +0x00C0 - RO - Redistributor Synchronize Register
+  const volatile uint32_t padding7[2];           // +0x00C8 - RESERVED
+  const volatile uint32_t padding8[12];          // +0x00D0 - RESERVED
+        volatile uint64_t IMPDEF2;               // +0x0100 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding9[2];           // +0x0108 - RESERVED
+        volatile uint64_t IMPDEF3;               // +0x0110 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding10[2];          // +0x0118 - RESERVED
+} GICv3_redistributor_RD;
+
+/*
+ * SGI and PPI Redistributor register map
+ */
+typedef struct
+{
+  const volatile uint32_t padding1[32];          // +0x0000 - RESERVED
+        volatile uint32_t GICR_IGROUPR0;         // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
+  const volatile uint32_t padding2[31];          // +0x0084 - RESERVED
+        volatile uint32_t GICR_ISENABLER;        // +0x0100 - RW - Interrupt Set-Enable Registers
+  const volatile uint32_t padding3[31];          // +0x0104 - RESERVED
+        volatile uint32_t GICR_ICENABLER;        // +0x0180 - RW - Interrupt Clear-Enable Registers
+  const volatile uint32_t padding4[31];          // +0x0184 - RESERVED
+        volatile uint32_t GICR_ISPENDR;          // +0x0200 - RW - Interrupt Set-Pending Registers
+  const volatile uint32_t padding5[31];          // +0x0204 - RESERVED
+        volatile uint32_t GICR_ICPENDR;          // +0x0280 - RW - Interrupt Clear-Pending Registers
+  const volatile uint32_t padding6[31];          // +0x0284 - RESERVED
+        volatile uint32_t GICR_ISACTIVER;        // +0x0300 - RW - Interrupt Set-Active Register
+  const volatile uint32_t padding7[31];          // +0x0304 - RESERVED
+        volatile uint32_t GICR_ICACTIVER;        // +0x0380 - RW - Interrupt Clear-Active Register
+  const volatile uint32_t padding8[31];          // +0x0184 - RESERVED
+        volatile uint8_t  GICR_IPRIORITYR[32];   // +0x0400 - RW - Interrupt Priority Registers
+  const volatile uint32_t padding9[504];         // +0x0420 - RESERVED
+        volatile uint32_t GICR_ICnoFGR[2];       // +0x0C00 - RW - Interrupt Configuration Registers
+  const volatile uint32_t padding10[62];         // +0x0C08 - RESERVED
+        volatile uint32_t GICR_IGRPMODR0;        // +0x0D00 - RW - ????
+  const volatile uint32_t padding11[63];         // +0x0D04 - RESERVED
+        volatile uint32_t GICR_NSACR;            // +0x0E00 - RW - Non-Secure Access Control Register
+} GICv3_redistributor_SGI;
+
+/*
+ * We have a multiplicity of GIC Redistributors; on the GIC-AEM and
+ * GIC-500 they are arranged as one 128KB region per redistributor: one
+ * 64KB page of GICR LPI registers, and one 64KB page of GICR Private
+ * Int registers
+ */
+typedef struct
+{
+    union
+    {
+        GICv3_redistributor_RD RD_base;
+        uint8_t padding[64 * 1024];
+    } RDblock;
+
+    union
+    {
+        GICv3_redistributor_SGI SGI_base;
+        uint8_t padding[64 * 1024];
+    } SGIblock;
+} GICv3_GICR;
+
+/*
+ * use the scatter file to place GIC Redistributor base address
+ *
+ * although this code doesn't know how many Redistributor banks
+ * a particular system will have, we declare gicrbase as an array
+ * to avoid unwanted compiler optimisations when calculating the
+ * base of a particular Redistributor bank
+ */
+static const GICv3_GICR gicrbase[2] __attribute__((section (".bss.redistributor")));
+
+/**********************************************************************/
+
+/*
+ * utility functions to calculate base of a particular
+ * Redistributor bank
+ */
+
+static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
+{
+    GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
+
+    return &((arraybase + gicr)->RDblock.RD_base);
+}
+
+static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
+{
+    GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
+
+    return &(arraybase[gicr].SGIblock.SGI_base);
+}
+
+/**********************************************************************/
+
+// This function walks a block of RDs to find one with the matching affinity
+uint32_t GetGICR(uint32_t affinity)
+{
+  GICv3_redistributor_RD* gicr;
+  uint32_t index = 0;
+
+  do
+  {
+    gicr = getgicrRD(index);
+    if (gicr->GICR_TYPER[1] == affinity)
+       return index;
+
+    index++;
+  }
+  while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block
+
+  return 0xFFFFFFFF; // return -1 to signal not RD found
+}
+
+void WakeupGICR(uint32_t gicr)
+{
+    GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
+#ifdef USE_GIC600
+    //Power up Re-distributor for GIC-600
+    gicrRD->GICR_PWRR = 0x2;
+#endif
+
+    /*
+     * step 1 - ensure GICR_WAKER.ProcessorSleep is off
+     */
+    gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
+
+    /*
+     * step 2 - wait for children asleep to be cleared
+     */
+    while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
+        continue;
+
+    /*
+     * OK, GICR is go
+     */
+    return;
+}
+
+void EnablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISENABLER = 1 << id;
+}
+
+void DisablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICENABLER = 1 << id;
+}
+
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    gicrSGI->GICR_IPRIORITYR[id] = priority;
+}
+
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
+}
+
+void SetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISPENDR = 1 << id;
+}
+
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ICPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICPENDR = 1 << id;
+}
+
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
+}
+
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    uint32_t groupmod;
+
+    /*
+     * GICR_IGROUPR0 is one 32-bit register
+     */
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+        gicrSGI->GICR_IGROUPR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+        gicrSGI->GICR_IGRPMODR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
+}
+
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    const uint32_t nbits = (sizeof group * 8) - 1;
+    uint32_t groupmod;
+
+    /*
+     * get each bit of group config duplicated over all 32 bits
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicrSGI->GICR_IGROUPR0 = group;
+    gicrSGI->GICR_IGRPMODR0 = groupmod;
+}
+
+/* EOF GICv3_gicr.c */
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S
new file mode 100644
index 00000000..e7f95aa7
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S
@@ -0,0 +1,133 @@
+//
+// Armv8-A AArch64 - Basic Mutex Example
+// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global _mutex_initialize
+    .global _mutex_acquire
+    .global _mutex_release
+
+//
+// These routines implement the mutex management functions required for running
+// the Arm C library in a multi-threaded environment.
+//
+// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
+//
+// **********************************************************************
+//
+
+    .type _mutex_initialize, "function"
+    .cfi_startproc
+_mutex_initialize:
+
+    //
+    // mark the mutex as unlocked
+    //
+    mov     w1, #0
+    str     w1, [x0]
+
+    //
+    // we are running multi-threaded, so set a non-zero return
+    // value (function prototype says use 1)
+    //
+    mov     w0, #1
+    ret
+    .cfi_endproc
+
+#if !defined(USE_LSE_ATOMIC)
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+
+    //
+    // send ourselves an event, so we don't stick on the wfe at the
+    // top of the loop
+    //
+    sevl
+
+    //
+    // wait until the mutex is available
+    //
+loop:
+    wfe
+    ldaxr   w1, [x0]
+    cbnz    w1, loop
+
+    //
+    // mutex is (at least, it was) available - try to claim it
+    //
+    mov     w1, #1
+    stxr    w2, w1, [x0]
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+
+    mov     w1, #0
+    stlr    w1, [x0]
+    ret
+    .cfi_endproc
+
+#else  // LSE version
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+    // This uses a "ticket lock".  The lock is stored as a 32-bit value: 
+    // - the upper 16-bits record the thread's ticket number ("take a ticket")
+    // - the lower 16-bits record the ticket being served    ("now serving")
+
+    // atomically load then increment the thread's ticket number ("take a ticket")
+    mov w3, #(1 << 16)
+    ldadda w3, w1, [x0]
+
+    // is the ticket now being served?
+    eor w2, w1, w1, ror #16
+    cbz w2, loop_exit
+
+    // no, so wait for the ticket to be served
+
+    // send a local event to avoid missing an unlock before the exclusive load
+    sevl
+
+loop:
+    wfe
+    ldaxrh  w3, [x0]
+    eor w2, w3, w1, lsr #16
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+loop_exit:
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+    mov     w1, #1
+    staddlh w1, [x0]
+    ret
+    .cfi_endproc
+#endif
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h
new file mode 100644
index 00000000..ec1a1d28
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h
@@ -0,0 +1,66 @@
+/*
+ * Armv8-A AArch64 - Basic Mutex Example
+ *
+ * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef MP_MUTEX_H
+#define MP_MUTEX_H
+
+/*
+ * The Arm C library calls-out to these functions to manage multithreading.
+ * They can also be called by user application code.
+ *
+ * Mutex type is specified by the Arm C library
+ *
+ * Declare function prototypes for libc mutex routines
+ */
+typedef signed int *mutex;
+
+/*
+ * int _mutex_initialize(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  0 - application is non-threaded
+ *  1 - application is threaded
+ *  The C library uses the return result to indicate whether it is being used in a multithreaded environment.
+ */
+int _mutex_initialize(mutex *m);
+
+/*
+ * void _mutex_acquire(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  <nothing>
+ *
+ * Side Effects
+ *  Routine does not return until the mutex has been claimed. A load-acquire
+ *  is used to guarantee that the mutex claim is properly ordered with
+ *  respect to any accesses to the resource protected by the mutex
+ */
+void _mutex_acquire(mutex *m);
+
+/*
+ * void _mutex_release(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  <nothing>
+ *
+ * Side Effects
+ *  A store-release is used to guarantee that the mutex release is properly
+ *  ordered with respect any accesses to the resource protected by the mutex
+ */
+void _mutex_release(mutex *m);
+
+#endif
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h
new file mode 100644
index 00000000..52c9a0fe
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h
@@ -0,0 +1,66 @@
+//
+// Private Peripheral Map for the v8 Architecture Envelope Model
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef PPM_AEM_H
+#define PPM_AEM_H
+
+//
+// Distributor layout
+//
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+//
+// CPU Interface layout
+//
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+
+#endif // PPM_AEM_H
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat
new file mode 100644
index 00000000..deb16ebe
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat
@@ -0,0 +1,107 @@
+;********************************************************
+; Scatter file for Armv8-A Startup code on FVP Base model
+; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+; Use, modification and redistribution of this file is subject to your possession of a
+; valid End User License Agreement for the Arm Product of which these examples are part of 
+; and your compliance with all applicable terms and conditions of such licence agreement.
+;********************************************************
+
+LOAD 0x80000000
+{
+    EXEC +0
+    {
+        startup.o (StartUp, +FIRST)
+        * (+RO, +RW, +ZI)
+    }
+
+    ;
+    ; App stacks for all CPUs
+    ; All stacks and heap are aligned to a cache-line boundary
+    ;
+    ARM_LIB_STACK    +0 ALIGN 64 EMPTY 8 * 0x4000 {}
+
+    ;
+    ; Separate heap - import symbol __use_two_region_memory
+    ; in source code for this to work correctly
+    ;
+    ARM_LIB_HEAP     +0 ALIGN 64 EMPTY 0xA0000 {}
+    
+    ;
+    ; Handler stacks for all CPUs
+    ; All stacks and heap are aligned to a cache-line boundary
+    ;
+    HANDLER_STACK    +0 ALIGN 64 EMPTY 4 * 0x4000 {}
+
+    ;
+    ; Stacks for EL3
+    ;
+    EL3_STACKS       +0 ALIGN 64 EMPTY 8 * 0x1000 {}
+    ;
+    ; Strictly speaking, the L1 tables do not need to
+    ; be so strongly aligned, but no matter
+    ;
+    TTB0_L1          +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    ;
+    ; Various sets of L2 tables
+    ;
+    ; Alignment is 4KB, since the code uses a 4K page
+    ; granularity - larger granularities would require
+    ; correspondingly stricter alignment
+    ;
+    TTB0_L2_RAM      +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    TTB0_L2_PRIVATE  +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    TTB0_L2_PERIPH   +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    MODULE_ABSOLUTE  0x80180000 EMPTY 0x60000 {}
+
+    SHARED_MEMORY    0x801F0000 EMPTY 0x8000 {}
+
+    ;
+    ; The startup code uses the end of this region to calculate
+    ; the top of memory - do not place any RAM regions after it
+    ;
+    TOP_OF_RAM  +0 EMPTY 4 {}
+
+    ;
+    ; CS3 Peripherals is a 64MB region from 0x1c000000
+    ; that includes the following:
+    ; System Registers             at 0x1C010000
+    ; UART0 (PL011)                at 0x1C090000
+    ; Color LCD Controller (PL111) at 0x1C1F0000
+    ; plus a number of others.
+    ; CS3_PERIPHERALS is used by the startup code for page-table generation
+    ; This region is not truly empty, but we have no
+    ; predefined objects that live within it
+    ;
+    CS3_PERIPHERALS  0x1c000000 EMPTY 0x90000 {}
+
+    ;
+    ; Place the UART peripheral registers data structure
+    ; This is only really needed if USE_SERIAL_PORT is defined, but
+    ; the linker will remove unused sections if not needed
+;    PL011  0x1c090000 UNINIT 0x1000
+;    {
+;        uart.o (+ZI)
+;    }
+    ; Note that some other CS3_PERIPHERALS follow this
+
+    ;
+    ; GICv3 distributor
+    ;
+    GICD  0x2f000000 UNINIT 0x8000
+    {
+        GICv3_gicd.o (.bss.distributor)
+    }
+
+    ;
+    ; GICv3 redistributors
+    ; 128KB for each redistributor in the system
+    ;
+    GICR  0x2f100000 UNINIT 0x80000
+    {
+        GICv3_gicr.o (.bss.redistributor)
+    }
+}
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
new file mode 100644
index 00000000..c7296646
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
@@ -0,0 +1,149 @@
+/* Small demonstration of the ThreadX module manager.  */
+
+#include "tx_api.h"
+#include "txm_module.h"
+#include <stddef.h>
+
+
+/* Define the ThreadX module manager thread and stack...  */
+
+TX_THREAD               module_manager;
+#define MODULE_MANAGER_STACK_SIZE (1024 * 4)
+ALIGN_TYPE              module_manager_stack[MODULE_MANAGER_STACK_SIZE / sizeof(ALIGN_TYPE)];
+
+
+/* Define the module instance object  */
+
+TXM_MODULE_INSTANCE     my_module;
+
+
+/* The module code should be loaded here.  */
+
+#define MODULE_CODE (0x80180000)
+
+
+/* Define the object pool area.  */
+
+UCHAR                   object_memory[1024 * 16];
+
+
+/* Define the module data pool area.  */
+
+#define MODULE_DATA_SIZE (1024 * 32)
+ALIGN_TYPE MODULE_DATA [MODULE_DATA_SIZE / sizeof(ALIGN_TYPE)];
+
+
+/* Define the count of memory faults.  */
+
+ULONG                   memory_faults = 0;
+
+
+/* Define thread prototypes.  */
+
+void    module_manager_entry(ULONG thread_input);
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+UCHAR   event_buffer[65536];
+
+#endif
+
+
+/* Define main entry point.  */
+
+int main(void)
+{
+
+    /* Initialize timer for ThreadX.  */
+    extern void init_timer(void);    /* in timer_interrupts.c  */
+    init_timer();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+
+    /* The functions doesn't really return*/
+    return 0;
+}
+
+ULONG simple_thread_counter = 0;
+TX_THREAD simple_thread;
+#define SIMPLE_THREAD_STACK_SIZE (1024 * 4)
+ALIGN_TYPE simple_thread_stack[SIMPLE_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)];
+void simple_thread_entry(ULONG thread_input)
+{
+    while(1)
+    {
+        simple_thread_counter++;
+        tx_thread_sleep(2);
+    }
+}
+
+/* Define what the initial system looks like.  */
+
+void tx_application_define(void *first_unused_memory)
+{
+    tx_thread_create(
+            &module_manager,
+            "Module Manager Thread",
+            module_manager_entry, 0,
+            module_manager_stack, MODULE_MANAGER_STACK_SIZE,
+            1, 1,
+            TX_NO_TIME_SLICE,
+            TX_AUTO_START);
+
+    tx_thread_create(
+            &simple_thread,
+            "Simple Thread",
+            simple_thread_entry, 0,
+            simple_thread_stack, SIMPLE_THREAD_STACK_SIZE,
+            1, 1,
+            TX_NO_TIME_SLICE,
+            TX_AUTO_START);
+}
+
+
+/* Define the test threads.  */
+
+void module_manager_entry(ULONG thread_input)
+{
+
+    /* Initialize the module manager.   */
+    txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE);
+
+    txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
+
+    /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download.  */
+    txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
+    
+    /* Start the module.  */
+    txm_module_manager_start(&my_module);
+
+    /* Sleep for a while....  */
+    {
+        int i;
+        for (i = 0; i < 10; i++)
+        {
+            tx_thread_sleep(10);
+        }
+    }
+    
+    /* Stop the module.  */
+    txm_module_manager_stop(&my_module);
+    
+    /* Unload the module.  */
+    txm_module_manager_unload(&my_module);
+
+    /* Load the module again.  */
+    txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
+
+    /* Start the module again.  */
+    txm_module_manager_start(&my_module);
+    
+    /* Now just spin...  */
+    while(1)
+    {
+    
+        tx_thread_sleep(10);
+    }
+}
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
new file mode 100644
index 00000000..a70c574d
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+    <listAttribute key="1685211613816507265.viewid=2">
+        <listEntry value="thread_info"/>
+        <listEntry value="thread_ptr"/>
+        <listEntry value="shell_function"/>
+        <listEntry value="thread_entry_info"/>
+        <listEntry value="module_instance"/>
+        <listEntry value="module_preamble"/>
+        <listEntry value="return_value"/>
+        <listEntry value="status"/>
+        <listEntry value="_entry_param_thread_ptr"/>
+        <listEntry value="data_allocation_size"/>
+        <listEntry value="_txm_module_manager_byte_pool"/>
+        <listEntry value="pool_ptr"/>
+        <listEntry value="&amp;_txm_module_manager_byte_pool"/>
+        <listEntry value="(void*)(_txm_module_manager_byte_pool.tx_byte_pool_start)"/>
+        <listEntry value="(void*)(_txm_module_manager_byte_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size)"/>
+        <listEntry value="_tx_timer_thread"/>
+        <listEntry value="byte_pool_ptr"/>
+        <listEntry value="object_ptr"/>
+        <listEntry value="module_instance -&gt; txm_module_instance_data_start"/>
+        <listEntry value="module_instance -&gt; txm_module_instance_data_end"/>
+        <listEntry value="code_alignment"/>
+    </listAttribute>
+    <mapAttribute key="1685211613816507265.viewid=2.ExpressionsData">
+        <mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,1;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
+        <mapEntry key="1" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
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+    <stringAttribute key="dtsl_config" value="DtslScript"/>
+    <stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
+    <stringAttribute key="dtsl_options_file" value="default"/>
+    <stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
+    <stringAttribute key="launch_configuration_version" value="2020.0"/>
+    <booleanAttribute key="linuxOS" value="false"/>
+    <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
+    <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
+    <booleanAttribute key="runAfterConnect" value="false"/>
+    <mapAttribute key="scripts_view_script_links">
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+        <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
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+    </listAttribute>
+    <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
+    <stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
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diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c
new file mode 100644
index 00000000..4dc009b2
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c
@@ -0,0 +1,122 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "sp804_timer.h"
+
+#define TIMER_SP804_CTRL_TIMEREN     (1 << 7)
+#define TIMER_SP804_CTRL_TIMERMODE   (1 << 6)        // Bit 6:
+#define TIMER_SP804_CTRL_INTENABLE   (1 << 5)
+#define TIMER_SP804_CTRL_TIMERSIZE   (1 << 1)        // Bit 1: 0=16-bit, 1=32-bit
+#define TIMER_SP804_CTRL_ONESHOT     (1 << 0)        // Bit 0: 0=wrapping, 1=one-shot
+
+#define TIMER_SP804_CTRL_PRESCALE_1  (0 << 2)        // clk/1
+#define TIMER_SP804_CTRL_PRESCALE_4  (1 << 2)        // clk/4
+#define TIMER_SP804_CTRL_PRESCALE_8  (2 << 2)        // clk/8
+
+struct sp804_timer
+{
+        volatile uint32_t Time1Load;     // +0x00
+  const volatile uint32_t Time1Value;    // +0x04 - RO
+        volatile uint32_t Timer1Control; // +0x08
+        volatile uint32_t Timer1IntClr;  // +0x0C - WO
+  const volatile uint32_t Timer1RIS;     // +0x10 - RO
+  const volatile uint32_t Timer1MIS;     // +0x14 - RO
+        volatile uint32_t Timer1BGLoad;  // +0x18
+
+        volatile uint32_t Time2Load;     // +0x20
+        volatile uint32_t Time2Value;    // +0x24
+        volatile uint8_t  Timer2Control; // +0x28
+        volatile uint32_t Timer2IntClr;  // +0x2C - WO
+  const volatile uint32_t Timer2RIS;     // +0x30 - RO
+  const volatile uint32_t Timer2MIS;     // +0x34 - RO
+        volatile uint32_t Timer2BGLoad;  // +0x38
+
+  // Not including ID registers
+
+};
+
+// Instance of the dual timer, will be placed using the scatter file
+struct sp804_timer* dual_timer;
+
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address)
+{
+  dual_timer = (struct sp804_timer*)address;
+  return;
+}
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
+{
+  uint32_t tmp = 0;
+
+  dual_timer->Time1Load = load_value;
+
+  // Fixed setting: 32-bit, no prescaling
+  tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
+
+  // Settings from parameters: interrupt generation & reload
+  tmp = tmp | interrupt | auto_reload;
+
+  // Write control register
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Starts the timer
+void startTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp | TIMER_SP804_CTRL_TIMEREN;      // Set TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Stops the timer
+void stopTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN;     // Clear TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void)
+{
+  return dual_timer->Time1Value;
+}
+
+
+void clearTimerIrq(void)
+{
+  // A write to this register, of any value, clears the interrupt
+  dual_timer->Timer1IntClr = 1;
+}
+
+
+// ------------------------------------------------------------
+// End of sp804_timer.c
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h
new file mode 100644
index 00000000..777062cc
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h
@@ -0,0 +1,53 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+// Header Filer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#ifndef _SP804_TIMER_
+#define _SP804_TIMER_
+
+#include <stdint.h>
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address);
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+
+#define SP804_AUTORELOAD   (0)
+#define SP804_SINGLESHOT   (1)
+#define SP804_GENERATE_IRQ (1 << 5)
+#define SP804_NO_IRQ       (0)
+
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
+
+
+// Starts the timer
+void startTimer(void);
+
+
+// Stops the timer
+void stopTimer(void);
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void);
+
+
+// Clears the timer interrupt
+void clearTimerIrq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of sp804_timer.h
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S
new file mode 100644
index 00000000..de100e56
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S
@@ -0,0 +1,779 @@
+// ------------------------------------------------------------
+// Armv8-A MPCore EL3 AArch64 Startup Code
+//
+// Basic Vectors, MMU, caches and GICv3 initialization
+//
+// Exits in EL1 AArch64
+//
+// Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_mmu.h"
+#include "v8_system.h"
+
+
+    .section StartUp, "ax"
+    .balign 4
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+
+    .global InvalidateUDCaches
+    .global ZeroBlock
+
+    .global SetPrivateIntSecurityBlock
+    .global SetSPISecurityAll
+    .global SetPrivateIntPriority
+
+    .global GetGICR
+    .global WakeupGICR
+    .global SyncAREinGICD
+    .global EnableGICD
+    .global EnablePrivateInt
+    .global GetPrivateIntPending
+    .global ClearPrivateIntPending
+
+    .global __main
+    //.global MainApp
+
+    .global Image$$EXEC$$RO$$Base
+    .global Image$$TTB0_L1$$ZI$$Base
+    .global Image$$TTB0_L2_RAM$$ZI$$Base
+    .global Image$$TTB0_L2_PERIPH$$ZI$$Base
+    .global Image$$TOP_OF_RAM$$ZI$$Base
+    .global Image$$GICD$$ZI$$Base
+    .global Image$$ARM_LIB_STACK$$ZI$$Limit
+    .global Image$$EL3_STACKS$$ZI$$Limit
+    .global Image$$CS3_PERIPHERALS$$ZI$$Base
+    // use separate stack and heap, as anticipated by scatter.scat
+    .global __use_two_region_memory
+
+
+// ------------------------------------------------------------
+
+    .global start64
+    .type start64, "function"
+start64:
+
+    //
+    // program the VBARs
+    //
+    ldr x1, =el1_vectors
+    msr VBAR_EL1, x1
+
+    ldr x1, =el2_vectors
+    msr VBAR_EL2, x1
+
+    ldr x1, =el3_vectors
+    msr VBAR_EL3, x1
+
+
+    // GIC-500 comes out of reset in GICv2 compatibility mode - first set
+    // system register enables for all relevant exception levels, and
+    // select GICv3 operating mode
+    //
+    msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL3, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
+
+    //
+    // set lower exception levels as non-secure, with no access
+    // back to EL2 or EL3, and are AArch64 capable
+    //
+    mov x3, #(SCR_EL3_RW  | \
+              SCR_EL3_SMD | \
+              SCR_EL3_NS)      // Set NS bit, to access Non-secure registers
+    msr SCR_EL3, x3
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL2, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
+
+
+    //
+    // no traps or VM modifications from the Hypervisor, EL1 is AArch64
+    //
+    mov x2, #HCR_EL2_RW
+    msr HCR_EL2, x2
+
+    //
+    // VMID is still significant, even when virtualisation is not
+    // being used, so ensure VTTBR_EL2 is properly initialised
+    //
+    msr VTTBR_EL2, xzr
+
+    //
+    // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
+    //  VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
+    // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
+    // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
+    // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
+    //
+    mrs x0, MPIDR_EL1
+    msr VMPIDR_EL2, x0
+    mrs x0, MIDR_EL1
+    msr VPIDR_EL2, x0
+
+    // extract the core number from MPIDR_EL1 and store it in
+    // x19 (defined by the AAPCS as callee-saved), so we can re-use
+    // the number later
+    //
+    bl GetCPUID
+    mov x19, x0
+
+    //
+    // neither EL3 nor EL2 trap floating point or accesses to CPACR
+    //
+    msr CPTR_EL3, xzr
+    msr CPTR_EL2, xzr
+
+    //
+    // SCTLR_ELx may come out of reset with UNKNOWN values so we will
+    // set the fields to 0 except, possibly, the endianess field(s).
+    // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
+    // is not strictly needed, since we're never in EL2 or EL0
+    //
+#ifdef __ARM_BIG_ENDIAN
+    mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
+#else
+    mov x0, #0
+#endif
+    msr SCTLR_EL3, x0
+    msr SCTLR_EL2, x0
+    msr SCTLR_EL1, x0
+
+#ifdef CORTEXA
+    //
+    // Configure ACTLR_EL[23]
+    // ----------------------
+    //
+    // These bits are IMPLEMENTATION DEFINED, so are different for
+    // different processors
+    //
+    // For Cortex-A57, the controls we set are:
+    //
+    //  Enable lower level access to CPUACTLR_EL1
+    //  Enable lower level access to CPUECTLR_EL1
+    //  Enable lower level access to L2CTLR_EL1
+    //  Enable lower level access to L2ECTLR_EL1
+    //  Enable lower level access to L2ACTLR_EL1
+    //
+    mov x0, #((1 << 0) | \
+              (1 << 1) | \
+              (1 << 4) | \
+              (1 << 5) | \
+              (1 << 6))
+
+    msr ACTLR_EL3, x0
+    msr ACTLR_EL2, x0
+
+    //
+    // configure CPUECTLR_EL1
+    //
+    // These bits are IMP DEF, so need to different for different
+    // processors
+    //
+    // SMPEN - bit 6 - Enables the processor to receive cache
+    //                 and TLB maintenance operations
+    //
+    // Note: For Cortex-A57/53 SMPEN should be set before enabling
+    //       the caches and MMU, or performing any cache and TLB
+    //       maintenance operations.
+    //
+    //       This register has a defined reset value, so we use a
+    //       read-modify-write sequence to set SMPEN
+    //
+    mrs x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
+    orr x0, x0, #(1 << 6)  // Set the SMPEN bit
+    msr S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
+
+    isb
+#endif
+
+    //
+    // That's the last of the control settings for now
+    //
+    // Note: no ISB after all these changes, as registers won't be
+    // accessed until after an exception return, which is itself a
+    // context synchronisation event
+    //
+
+    //
+    // Setup some EL3 stack space, ready for calling some subroutines, below.
+    //
+    // Stack space allocation is CPU-specific, so use CPU
+    // number already held in x19
+    //
+    // 2^12 bytes per CPU for the EL3 stacks
+    //
+    ldr x0, =Image$$EL3_STACKS$$ZI$$Limit
+    sub x0, x0, x19, lsl #12
+    mov sp, x0
+
+    //
+    // we need to configure the GIC while still in secure mode, specifically
+    // all PPIs and SPIs have to be programmed as Group1 interrupts
+    //
+
+    //
+    // Before the GIC can be reliably programmed, we need to
+    // enable Affinity Routing, as this affects where the configuration
+    // registers are (with Affinity Routing enabled, some registers are
+    // in the Redistributor, whereas those same registers are in the
+    // Distributor with Affinity Routing disabled (i.e. when in GICv2
+    // compatibility mode).
+    //
+    mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
+    mov x1, x19
+    bl  SyncAREinGICD
+
+    //
+    // The Redistributor comes out of reset assuming the processor is
+    // asleep - correct that assumption
+    //
+    bl  GetAffinity
+    bl  GetGICR
+    mov w20, w0     // Keep a copy for later
+    bl  WakeupGICR
+
+    //
+    // Now we're ready to set security and other initialisations
+    //
+    // This is a per-CPU configuration for these interrupts
+    //
+    // for the first cluster, CPU number is the redistributor index
+    //
+    mov w0, w20
+    mov w1, #1    // gicigroupr_G1NS
+    bl  SetPrivateIntSecurityBlock
+
+    //
+    // While we're in the Secure World, set the priority mask low enough
+    // for it to be writable in the Non-Secure World
+    //
+    //mov x0, #16 << 3    // 5 bits of priority in the Secure world
+    mov x0, #0xFF  // for Non-Secure interrupts
+    msr ICC_PMR_EL1, x0
+
+    //
+    // there's more GIC setup to do, but only for the primary CPU
+    //
+    cbnz x19, drop_to_el1
+
+    //
+    // There's more to do to the GIC - call the utility routine to set
+    // all SPIs to Group1
+    //
+    mov w0, #1    // gicigroupr_G1NS
+    bl  SetSPISecurityAll
+
+    //
+    // Set up EL1 entry point and "dummy" exception return information,
+    // then perform exception return to enter EL1
+    //
+    .global drop_to_el1
+drop_to_el1:
+    adr x1, el1_entry_aarch64
+    msr ELR_EL3, x1
+    mov x1, #(AARCH64_SPSR_EL1h | \
+              AARCH64_SPSR_F  | \
+              AARCH64_SPSR_I  | \
+              AARCH64_SPSR_A)
+    msr SPSR_EL3, x1
+    eret
+
+
+
+// ------------------------------------------------------------
+// EL1 - Common start-up code
+// ------------------------------------------------------------
+
+    .global el1_entry_aarch64
+    .type el1_entry_aarch64, "function"
+el1_entry_aarch64:
+
+    //
+    // Now we're in EL1, setup the application stack
+    // the scatter file allocates 2^14 bytes per app stack
+    //
+    ldr x0, =Image$$HANDLER_STACK$$ZI$$Limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+    MSR     SPSel, #0
+    ISB
+    ldr x0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+
+    //
+    // Enable floating point
+    //
+    mov x0, #CPACR_EL1_FPEN
+    msr CPACR_EL1, x0
+
+    //
+    // Invalidate caches and TLBs for all stage 1
+    // translations used at EL1
+    //
+    // Cortex-A processors automatically invalidate their caches on reset
+    // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
+    // It is therefore not necessary for software to invalidate the caches 
+    // on startup, however, this is done here in case of a warm reset.
+    bl  InvalidateUDCaches
+    tlbi VMALLE1
+
+
+    //
+    // Set TTBR0 Base address
+    //
+    // The CPUs share one set of translation tables that are
+    // generated by CPU0 at run-time
+    //
+    // TTBR1_EL1 is not used in this example
+    //
+    ldr x1, =Image$$TTB0_L1$$ZI$$Base
+    msr TTBR0_EL1, x1
+
+
+    //
+    // Set up memory attributes
+    //
+    // These equate to:
+    //
+    // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
+    // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
+    // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
+    //
+    mov  x1, #0xff44
+    movk x1, #4, LSL #16    // equiv to: movk x1, #0x0000000000040000
+    msr MAIR_EL1, x1
+
+
+    //
+    // Set up TCR_EL1
+    //
+    // We're using only TTBR0 (EPD1 = 1), and the page table entries:
+    //  - are using an 8-bit ASID from TTBR0
+    //  - have a 4K granularity (TG0 = 0b00)
+    //  - are outer-shareable (SH0 = 0b10)
+    //  - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
+    //  - map
+    //      + 32 bits of VA space (T0SZ = 0x20)
+    //      + into a 32-bit PA space (IPS = 0b000)
+    //
+    //     36   32   28   24   20   16   12    8    4    0
+    //  -----+----+----+----+----+----+----+----+----+----+
+    //       |    |    |OOII|    |    |    |OOII|    |    |
+    //    TT |    |    |RRRR|E T |   T|    |RRRR|E T |   T|
+    //    BB | I I|TTSS|GGGG|P 1 |   1|TTSS|GGGG|P 0 |   0|
+    //    IIA| P P|GGHH|NNNN|DAS |   S|GGHH|NNNN|D S |   S|
+    //    10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
+    //
+    //    000 0000 0000 0000 1000 0000 0010 0101 0010 0000
+    //
+    //                    0x    8    0    2    5    2    0
+    //
+    // Note: the ISB is needed to ensure the changes to system
+    //       context are before the write of SCTLR_EL1.M to enable
+    //       the MMU. It is likely on a "real" implementation that
+    //       this setup would work without an ISB, due to the
+    //       amount of code that gets executed before enabling the
+    //       MMU, but that would not be architecturally correct.
+    //
+    ldr x1, =0x0000000000802520
+    msr TCR_EL1, x1
+    isb
+
+    //
+    // x19 already contains the CPU number, so branch to secondary
+    // code if we're not on CPU0
+    //
+    cbnz x19, el1_secondary
+
+    //
+    // Fall through to primary code
+    //
+
+
+//
+// ------------------------------------------------------------
+//
+// EL1 - primary CPU init code
+//
+// This code is run on CPU0, while the other CPUs are in the
+// holding pen
+//
+
+    .global el1_primary
+    .type el1_primary, "function"
+el1_primary:
+
+    //
+    // Turn on the banked GIC distributor enable,
+    // ready for individual CPU enables later
+    //
+    mov w0, #(1 << 1)  // gicdctlr_EnableGrp1A
+    bl  EnableGICD
+
+    //
+    // Generate TTBR0 L1
+    //
+    // at 4KB granularity, 32-bit VA space, table lookup starts at
+    // L1, with 1GB regions
+    //
+    // we are going to create entries pointing to L2 tables for a
+    // couple of these 1GB regions, the first of which is the
+    // RAM on the VE board model - get the table addresses and
+    // start by emptying out the L1 page tables (4 entries at L1
+    // for a 4K granularity)
+    //
+    // x21 = address of L1 tables
+    //
+    ldr x21, =Image$$TTB0_L1$$ZI$$Base
+    mov x0, x21
+    mov x1, #(4 << 3)
+    bl  ZeroBlock
+
+    //
+    // time to start mapping the RAM regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // x22 = address of L2 tables, needs to be remembered in case
+    //       we want to re-use the tables for mapping peripherals
+    //
+    ldr x22, =Image$$TTB0_L2_RAM$$ZI$$Base
+    mov x1, #(512 << 3)
+    mov x0, x22
+    bl  ZeroBlock
+
+    //
+    // Get the start address of RAM (the EXEC region) into x4
+    // and calculate the offset into the L1 table (1GB per region,
+    // max 4GB)
+    //
+    // x23 = L1 table offset, saved for later comparison against
+    //       peripheral offset
+    //
+    ldr x4, =Image$$EXEC$$RO$$Base
+    ubfx x23, x4, #30, #2
+
+    orr x1, x22, #TT_S1_ATTR_PAGE
+    str x1, [x21, x23, lsl #3]
+
+    //
+    // we've already used the RAM start address in x4 - we now need
+    // to get this in terms of an offset into the L2 page tables,
+    // where each entry covers 2MB
+    //
+    ubfx x2, x4, #21, #9
+
+    //
+    // TOP_OF_RAM in the scatter file marks the end of the
+    // Execute region in RAM: convert the end of this region to an
+    // offset too, being careful to round up, then calculate the
+    // number of entries to write
+    //
+    ldr x5, =Image$$TOP_OF_RAM$$ZI$$Base
+    sub  x3, x5, #1
+    ubfx x3, x3, #21, #9
+    add  x3, x3, #1
+    sub  x3, x3, x2
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as Shared, Normal WBWA (MAIR[1]) with a flat
+    // VA->PA translation
+    //
+    bic x4, x4, #((1 << 21) - 1)
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (1 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_SH_INNER | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // factor the offset into the page table address and then write
+    // the entries
+    //
+    add x0, x22, x2, lsl #3
+
+loop1:
+    subs x3, x3, #1
+    str x1, [x0], #8
+    add x1, x1, #0x200, LSL #12    // equiv to add x1, x1, #(1 << 21)  // 2MB per entry
+    bne loop1
+
+
+    //
+    // now mapping the Peripheral regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // The assumption here is that all peripherals live within
+    // a common 1GB region (i.e. that there's a single set of
+    // L2 pages for all the peripherals). We only use a UART
+    // and the GIC in this example, so the assumption is sound
+    //
+    // x24 = address of L2 peripheral tables
+    //
+    ldr x24, =Image$$TTB0_L2_PERIPH$$ZI$$Base
+
+    //
+    // get the GICD address into x4 and calculate
+    // the offset into the L1 table
+    //
+    // x25 = L1 table offset
+    //
+    ldr x4, =Image$$GICD$$ZI$$Base
+    ubfx x25, x4, #30, #2
+
+    //
+    // here's the tricky bit: it's possible that the peripherals are
+    // in the same 1GB region as the RAM, in which case we don't need
+    // to prime a separate set of L2 page tables, nor add them to the
+    // L1 tables
+    //
+    // if we're going to re-use the TTB0_L2_RAM tables, get their
+    // address into x24, which is used later on to write the PTEs
+    //
+    cmp x25, x23
+    csel x24, x22, x24, EQ
+    b.eq nol2setup
+
+    //
+    // Peripherals are in a separate 1GB region, and so have their own
+    // set of L2 tables - clean out the tables and add them to the L1
+    // table
+    //
+    mov x0, x24
+    mov x1, #512 << 3
+    bl  ZeroBlock
+
+    orr x1, x24, #TT_S1_ATTR_PAGE
+    str x1, [x21, x25, lsl #3]
+
+    //
+    // there's only going to be a single 2MB region for GICD (in
+    // x4) - get this in terms of an offset into the L2 page tables
+    //
+    // with larger systems, it is possible that the GIC redistributor
+    // registers require extra 2MB pages, in which case extra code
+    // would be required here
+    //
+nol2setup:
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry for this, so no loop as we have for RAM, above
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // we have CS3_PERIPHERALS that include the UART controller
+    //
+    // Again, the code is making assumptions - this time that the CS3_PERIPHERALS
+    // region uses the same 1GB portion of the address space as the GICD,
+    // and thus shares the same set of L2 page tables
+    //
+    // Get CS3_PERIPHERALS address into x4 and calculate the offset into the
+    // L2 tables
+    //
+    ldr x4, =Image$$CS3_PERIPHERALS$$ZI$$Base
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry again - write it
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // issue a barrier to ensure all table entry writes are complete
+    //
+    dsb ish
+
+    //
+    // Enable the MMU.  Caches will be enabled later, after scatterloading.
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // Branch to C library init code
+    //
+    b  __main
+
+
+// ------------------------------------------------------------
+
+// AArch64 Arm C library startup add-in:
+
+// The Arm Architecture Reference Manual for Armv8-A states:
+//
+//     Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
+//     Correspondingly, the sequence for ensuring that modifications to instructions are available
+//     for execution must include invalidation of the modified locations from the instruction cache,
+//     even if the instructions are held in Normal Non-cacheable memory.
+//     This includes cases where the instruction cache is disabled.
+//
+// To invalidate the AArch64 instruction cache after scatter-loading and before initialization of the stack and heap,
+// it is necessary for the user to:
+//
+// * Implement instruction cache invalidation code in _platform_pre_stackheap_init.
+// * Ensure all code on the path from the program entry up to and including _platform_pre_stackheap_init is located in a root region.
+//
+// In this example, this function is only called once, by the primary core
+
+    .global _platform_pre_stackheap_init
+    .type _platform_pre_stackheap_init, "function"
+    .cfi_startproc
+_platform_pre_stackheap_init:
+    dsb ish     // ensure all previous stores have completed before invalidating
+    ic  ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
+    dsb ish     // ensure completion on inner shareable domain   (which includes secondary cores)
+    isb
+
+    // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    msr SCTLR_EL1, x1
+    isb
+
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+// EL1 - secondary CPU init code
+//
+// This code is run on CPUs 1, 2, 3 etc....
+// ------------------------------------------------------------
+
+    .global el1_secondary
+    .type el1_secondary, "function"
+el1_secondary:
+
+    //
+    // the primary CPU is going to use SGI 15 as a wakeup event
+    // to let us know when it is OK to proceed, so prepare for
+    // receiving that interrupt
+    //
+    // NS interrupt priorities run from 0 to 15, with 15 being
+    // too low a priority to ever raise an interrupt, so let's
+    // use 14
+    //
+    mov w0, w20
+    mov w1, #15
+    mov w2, #14 << 4    // we're in NS world, so 4 bits of priority,
+                        // 8-bit field, - 4 = 4-bit shift
+    bl SetPrivateIntPriority
+
+    mov w0, w20
+    mov w1, #15
+    bl  EnablePrivateInt
+
+    //
+    // set priority mask as low as possible; although,being in the
+    // NS World, we can't set bit[7] of the priority, we still
+    // write all 8-bits of priority to an ICC register
+    //
+    mov x0, #31 << 3
+    msr ICC_PMR_EL1, x0
+
+    //
+    // set global enable and wait for our interrupt to arrive
+    //
+    mov x0, #1
+    msr ICC_IGRPEN1_EL1, x0
+    isb
+
+loop_wfi:
+    dsb SY      // Clear all pending data accesses
+    wfi         // Go to sleep
+
+    //
+    // something woke us from our wait, was it the required interrupt?
+    //
+    mov w0, w20
+    mov w1, #15
+    bl  GetPrivateIntPending
+    cbz w0, loop_wfi
+
+    //
+    // it was - there's no need to actually take the interrupt,
+    // so just clear it
+    //
+    mov w0, w20
+    mov w1, #15
+    bl  ClearPrivateIntPending
+
+    //
+    // Enable the MMU and caches
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // Branch to thread start
+    //
+    //B  MainApp
+    b  __main
+
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/timer_interrupts.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/timer_interrupts.c
new file mode 100644
index 00000000..8f522217
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/timer_interrupts.c
@@ -0,0 +1,152 @@
+/* Bare-metal example for Armv8-A FVP Base model */
+
+/* Timer and interrupts */
+
+/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */
+/* Use, modification and redistribution of this file is subject to your possession of a     */
+/* valid End User License Agreement for the Arm Product of which these examples are part of */
+/* and your compliance with all applicable terms and conditions of such licence agreement.  */
+
+#include <stdio.h>
+
+#include "GICv3.h"
+#include "GICv3_gicc.h"
+#include "sp804_timer.h"
+
+void   _tx_timer_interrupt(void);
+
+// LED Base address
+#define LED_BASE (volatile unsigned int *)0x1C010008
+
+
+void nudge_leds(void) // Move LEDs along
+{
+    static int state = 1;
+    static int value = 1;
+
+    if (state)
+    {
+        int max = (1 << 7);
+        value <<= 1;
+        if (value == max)
+            state = 0;
+    }
+    else
+    {
+        value >>= 1;
+        if (value == 1)
+            state = 1;
+    }
+
+    *LED_BASE = value;  // Update LEDs hardware
+}
+
+
+// Initialize Timer 0 and Interrupt Controller
+void init_timer(void)
+{
+    // Enable interrupts
+    __asm("MSR DAIFClr, #0xF");
+    setICC_IGRPEN1_EL1(igrpEnable);
+
+    // Configure the SP804 timer to generate an interrupt
+    setTimerBaseAddress(0x1C110000);
+    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
+    startTimer();
+
+    // The SP804 timer generates SPI INTID 34.  Enable
+    // this ID, and route it to core 0.0.0.0 (this one!)
+    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
+    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
+    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
+    EnableSPI(34);                                   // Enable INTID 34
+}
+
+
+// --------------------------------------------------------
+
+void irqHandler(void)
+{
+  unsigned int ID;
+
+  ID = getICC_IAR1(); // readIntAck();
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+      //printf("irqHandler() - Reserved INTID %d\n\n", ID);
+      return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("irqHandler() - External timer interrupt\n\n");
+      nudge_leds();
+      clearTimerIrq();
+
+      /* Call ThreadX timer interrupt processing.  */
+      _tx_timer_interrupt();
+
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("irqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
+
+// --------------------------------------------------------
+
+// Not actually used in this example, but provided for completeness
+
+void fiqHandler(void)
+{
+  unsigned int ID;
+  unsigned int aliased = 0;
+
+  ID = getICC_IAR0(); // readIntAck();
+  //printf("fiqHandler() - Read %d from IAR0\n", ID);
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+    //printf("fiqHandler() - Reserved INTID %d\n\n", ID);
+    ID = getICC_IAR1(); // readAliasedIntAck();
+    //printf("fiqHandler() - Read %d from AIAR\n", ID);
+    aliased = 1;
+
+    // If still spurious then simply return
+    if ((1020 <= ID) && (ID <= 1023))
+        return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("fiqHandler() - External timer interrupt\n\n");
+      clearTimerIrq();
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  // NOTE: If the ID was read from the Aliased IAR, then
+  // the aliased EOI register must be used
+  if (aliased == 0)
+    setICC_EOIR0(ID); // writeEOI(ID);
+  else
+    setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S
new file mode 100644
index 00000000..6e1935a5
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S
@@ -0,0 +1,99 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+	.text
+	.align 3
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_initialize_low_level                          Cortex-A35/AC6    */ 
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is responsible for any low-level processor            */ 
+/*    initialization, including setting up interrupt vectors, setting     */ 
+/*    up a periodic timer interrupt source, saving the system stack       */ 
+/*    pointer for use in ISR processing later, and finding the first      */ 
+/*    available RAM memory address for tx_application_define.             */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_initialize_low_level(VOID)
+{ */
+    .global  _tx_initialize_low_level
+    .type    _tx_initialize_low_level, @function
+_tx_initialize_low_level:
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+
+    /* Save the system stack pointer.  */
+    /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp);  */
+
+    LDR     x0, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    MOV     x1, sp                              // Pickup SP
+    BIC     x1, x1, #0xF                        // Get 16-bit alignment
+    STR     x1, [x0]                            // Store system stack
+
+    /* Save the first available memory address.  */
+    /* _tx_initialize_unused_memory =  (VOID_PTR) Image$$ZI$$Limit;  */
+
+    LDR     x0, =_tx_initialize_unused_memory   // Pickup address of unused memory ptr
+    LDR     x1, =zi_limit                       // Pickup unused memory address
+    LDR     x1, [x1]                            //
+    STR     x1, [x0]                            // Store unused memory address
+
+    /* Done, return to caller.  */
+
+    RET                                         // Return to caller
+/* } */
+
+
+zi_limit:
+    .quad (Image$$TOP_OF_RAM$$Base)
+
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S
new file mode 100644
index 00000000..f8db3bfe
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S
@@ -0,0 +1,179 @@
+// ------------------------------------------------------------
+// Armv8-A AArch64 - Common helper functions
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global EnableCachesEL1
+    .global DisableCachesEL1
+    .global InvalidateUDCaches
+    .global GetMIDR
+    .global GetMPIDR
+    .global GetAffinity
+    .global GetCPUID
+
+// ------------------------------------------------------------
+
+//
+// void EnableCachesEL1(void)
+//
+//    enable Instruction and Data caches
+//
+    .type EnableCachesEL1, "function"
+    .cfi_startproc
+EnableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    orr x0, x0, #SCTLR_ELx_I
+    orr x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+    .type DisableCachesEL1, "function"
+    .cfi_startproc
+DisableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    bic x0, x0, #SCTLR_ELx_I
+    bic x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// void InvalidateUDCaches(void)
+//
+//    Invalidate data and unified caches
+//
+    .type InvalidateUDCaches, "function"
+    .cfi_startproc
+InvalidateUDCaches:
+    // From the Armv8-A Architecture Reference Manual
+
+    dmb  ish                   // ensure all prior inner-shareable accesses have been observed
+
+    mrs  x0, CLIDR_EL1
+    and  w3, w0, #0x07000000   // get 2 x level of coherence
+    lsr  w3, w3, #23
+    cbz  w3, finished
+    mov  w10, #0               // w10 = 2 x cache level
+    mov  w8, #1                // w8 = constant 0b1
+loop_level:
+    add  w2, w10, w10, lsr #1  // calculate 3 x cache level
+    lsr  w1, w0, w2            // extract 3-bit cache type for this level
+    and  w1, w1, #0x7
+    cmp  w1, #2
+    b.lt next_level            // no data or unified cache at this level
+    msr  CSSELR_EL1, x10       // select this cache level
+    isb                        // synchronize change of csselr
+    mrs  x1, CCSIDR_EL1        // read ccsidr
+    and  w2, w1, #7            // w2 = log2(linelen)-4
+    add  w2, w2, #4            // w2 = log2(linelen)
+    ubfx w4, w1, #3, #10       // w4 = max way number, right aligned
+    clz  w5, w4                // w5 = 32-log2(ways), bit position of way in dc operand
+    lsl  w9, w4, w5            // w9 = max way number, aligned to position in dc operand
+    lsl  w16, w8, w5           // w16 = amount to decrement way number per iteration
+loop_way:
+    ubfx w7, w1, #13, #15      // w7 = max set number, right aligned
+    lsl  w7, w7, w2            // w7 = max set number, aligned to position in dc operand
+    lsl  w17, w8, w2           // w17 = amount to decrement set number per iteration
+loop_set:
+    orr  w11, w10, w9          // w11 = combine way number and cache number ...
+    orr  w11, w11, w7          // ... and set number for dc operand
+    dc   isw, x11              // do data cache invalidate by set and way
+    subs w7, w7, w17           // decrement set number
+    b.ge loop_set
+    subs x9, x9, x16           // decrement way number
+    b.ge loop_way
+next_level:
+    add  w10, w10, #2          // increment 2 x cache level
+    cmp  w3, w10
+    b.gt loop_level
+    dsb  sy                    // ensure completion of previous cache maintenance operation
+    isb
+finished:
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// ID Register functions
+//
+
+    .type GetMIDR, "function"
+    .cfi_startproc
+GetMIDR:
+
+    mrs x0, MIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetMPIDR, "function"
+    .cfi_startproc
+GetMPIDR:
+
+    mrs x0, MPIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetAffinity, "function"
+    .cfi_startproc
+GetAffinity:
+
+    mrs x0, MPIDR_EL1
+    ubfx x1, x0, #32, #8
+    bfi  w0, w1, #24, #8
+    ret
+    .cfi_endproc
+
+
+    .type GetCPUID, "function"
+    .cfi_startproc
+GetCPUID:
+
+    mrs x0, MIDR_EL1
+    ubfx    x0, x0, #4, #12 // extract PartNum
+    cmp x0, #0xD0D          // Cortex-A77
+    b.eq DynamIQ
+    cmp x0, #0xD0B          // Cortex-A76
+    b.eq DynamIQ
+    cmp x0, #0xD0A          // Cortex-A75
+    b.eq DynamIQ
+    cmp x0, #0xD05          // Cortex-A55
+    b.eq DynamIQ
+    b Others
+DynamIQ:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+
+Others:
+    mrs x0, MPIDR_EL1
+    ubfx    x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
+    ubfx    x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    add     x0, x1, x2, LSL #2
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h
new file mode 100644
index 00000000..b09079a4
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h
@@ -0,0 +1,103 @@
+/*
+ *
+ * Armv8-A AArch64 common helper functions
+ *
+ * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+
+#ifndef V8_AARCH64_H
+#define V8_AARCH64_H
+
+/*
+ * Parameters for data barriers
+ */
+#define OSHLD   1
+#define OSHST   2
+#define OSH     3
+#define NSHLD   5
+#define NSHST   6
+#define NSH     7
+#define ISHLD   9
+#define ISHST  10
+#define ISH    11
+#define LD     13
+#define ST     14
+#define SY     15
+
+/**********************************************************************/
+
+/*
+ * function prototypes
+ */
+
+/*
+ * void InvalidateUDCaches(void)
+ *   invalidates all Unified and Data Caches
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   <nothing>
+ *
+ * Side Effects
+ *   guarantees that all levels of cache will be invalidated before
+ *   returning to caller
+ */
+void InvalidateUDCaches(void);
+
+/*
+ * unsigned long long EnableCachesEL1(void)
+ *   enables I- and D- caches at EL1
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   New value of SCTLR_EL1
+ *
+ * Side Effects
+ *   context will be synchronised before returning to caller
+ */
+unsigned long long EnableCachesEL1(void);
+
+/*
+ * unsigned long long GetMIDR(void)
+ *   returns the contents of MIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MIDR_EL0
+ */
+unsigned long long GetMIDR(void);
+
+/*
+ * unsigned long long GetMPIDR(void)
+ *   returns the contents of MPIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MPIDR_EL0
+ */
+unsigned long long GetMPIDR(void);
+
+/*
+ * unsigned int GetCPUID(void)
+ *   returns the Aff0 field of MPIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MPIDR_EL0[7:0]
+ */
+unsigned int GetCPUID(void);
+
+#endif
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h
new file mode 100644
index 00000000..ee8834fa
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h
@@ -0,0 +1,128 @@
+//
+// Defines for v8 Memory Model
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_MMU_H
+#define V8_MMU_H
+
+//
+// Translation Control Register fields
+//
+// RGN field encodings
+//
+#define TCR_RGN_NC   0b00
+#define TCR_RGN_WBWA 0b01
+#define TCR_RGN_WT   0b10
+#define TCR_RGN_WBRA 0b11
+
+//
+// Shareability encodings
+//
+#define TCR_SHARE_NONE  0b00
+#define TCR_SHARE_OUTER 0b10
+#define TCR_SHARE_INNER 0b11
+
+//
+// Granule size encodings
+//
+#define TCR_GRANULE_4K  0b00
+#define TCR_GRANULE_64K 0b01
+#define TCR_GRANULE_16K 0b10
+
+//
+// Physical Address sizes
+//
+#define TCR_SIZE_4G   0b000
+#define TCR_SIZE_64G  0b001
+#define TCR_SIZE_1T   0b010
+#define TCR_SIZE_4T   0b011
+#define TCR_SIZE_16T  0b100
+#define TCR_SIZE_256T 0b101
+
+//
+// Translation Control Register fields
+//
+#define TCR_EL1_T0SZ_SHIFT   0
+#define TCR_EL1_EPD0  (1 << 7)
+#define TCR_EL1_IRGN0_SHIFT  8
+#define TCR_EL1_ORGN0_SHIFT 10
+#define TCR_EL1_SH0_SHIFT   12
+#define TCR_EL1_TG0_SHIFT   14
+
+#define TCR_EL1_T1SZ_SHIFT  16
+#define TCR_EL1_A1   (1 << 22)
+#define TCR_EL1_EPD1 (1 << 23)
+#define TCR_EL1_IRGN1_SHIFT 24
+#define TCR_EL1_ORGN1_SHIFT 26
+#define TCR_EL1_SH1_SHIFT   28
+#define TCR_EL1_TG1_SHIFT   30
+#define TCR_EL1_IPS_SHIFT   32
+#define TCR_EL1_AS   (1 << 36)
+#define TCR_EL1_TBI0 (1 << 37)
+#define TCR_EL1_TBI1 (1 << 38)
+
+//
+// Stage 1 Translation Table descriptor fields
+//
+#define TT_S1_ATTR_FAULT (0b00 << 0)
+#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
+#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
+#define TT_S1_ATTR_PAGE  (0b11 << 0) // Level 3
+
+#define TT_S1_ATTR_MATTR_LSB 2
+
+#define TT_S1_ATTR_NS (1 << 5)
+
+#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
+#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
+#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
+#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
+
+#define TT_S1_ATTR_SH_NONE   (0b00 << 8)
+#define TT_S1_ATTR_SH_OUTER  (0b10 << 8)
+#define TT_S1_ATTR_SH_INNER  (0b11 << 8)
+
+#define TT_S1_ATTR_AF (1 << 10)
+#define TT_S1_ATTR_nG (1 << 11)
+
+// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48]
+// and bits[47:16] are bits[47:16] of the output address for a page of memory
+
+#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0
+
+#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0
+
+#define TT_S1_ATTR_CONTIG (1 << 52)
+#define TT_S1_ATTR_PXN    (1 << 53)
+#define TT_S1_ATTR_UXN    (1 << 54)
+
+// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits 
+// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED
+
+#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
+#define TT_S1_MAIR_DEV_nGnRE  0b00000100
+#define TT_S1_MAIR_DEV_nGRE   0b00001000
+#define TT_S1_MAIR_DEV_GRE    0b00001100
+
+//
+// Inner and Outer Normal memory attributes use the same bit patterns
+// Outer attributes just need to be shifted up
+//
+#define TT_S1_MAIR_OUTER_SHIFT 4
+
+#define TT_S1_MAIR_WT_TRANS_RA  0b0010
+
+#define TT_S1_MAIR_WB_TRANS_RA  0b0110
+#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
+
+#define TT_S1_MAIR_WT_RA  0b1010
+
+#define TT_S1_MAIR_WB_RA  0b1110
+#define TT_S1_MAIR_WB_RWA 0b1111
+
+#endif // V8_MMU_H
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h
new file mode 100644
index 00000000..ff96deff
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h
@@ -0,0 +1,115 @@
+//
+// Defines for v8 System Registers
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_SYSTEM_H
+#define V8_SYSTEM_H
+
+//
+// AArch64 SPSR
+//
+#define AARCH64_SPSR_EL3h 0b1101
+#define AARCH64_SPSR_EL3t 0b1100
+#define AARCH64_SPSR_EL2h 0b1001
+#define AARCH64_SPSR_EL2t 0b1000
+#define AARCH64_SPSR_EL1h 0b0101
+#define AARCH64_SPSR_EL1t 0b0100
+#define AARCH64_SPSR_EL0t 0b0000
+#define AARCH64_SPSR_RW (1 << 4)
+#define AARCH64_SPSR_F  (1 << 6)
+#define AARCH64_SPSR_I  (1 << 7)
+#define AARCH64_SPSR_A  (1 << 8)
+#define AARCH64_SPSR_D  (1 << 9)
+#define AARCH64_SPSR_IL (1 << 20)
+#define AARCH64_SPSR_SS (1 << 21)
+#define AARCH64_SPSR_V  (1 << 28)
+#define AARCH64_SPSR_C  (1 << 29)
+#define AARCH64_SPSR_Z  (1 << 30)
+#define AARCH64_SPSR_N  (1 << 31)
+
+//
+// Multiprocessor Affinity Register
+//
+#define MPIDR_EL1_AFF3_LSB 32
+#define MPIDR_EL1_U  (1 << 30)
+#define MPIDR_EL1_MT (1 << 24)
+#define MPIDR_EL1_AFF2_LSB 16
+#define MPIDR_EL1_AFF1_LSB  8
+#define MPIDR_EL1_AFF0_LSB  0
+#define MPIDR_EL1_AFF_WIDTH 8
+
+//
+// Data Cache Zero ID Register
+//
+#define DCZID_EL0_BS_LSB   0
+#define DCZID_EL0_BS_WIDTH 4
+#define DCZID_EL0_DZP_LSB  5
+#define DCZID_EL0_DZP (1 << 5)
+
+//
+// System Control Register
+//
+#define SCTLR_EL1_UCI     (1 << 26)
+#define SCTLR_ELx_EE      (1 << 25)
+#define SCTLR_EL1_E0E     (1 << 24)
+#define SCTLR_ELx_WXN     (1 << 19)
+#define SCTLR_EL1_nTWE    (1 << 18)
+#define SCTLR_EL1_nTWI    (1 << 16)
+#define SCTLR_EL1_UCT     (1 << 15)
+#define SCTLR_EL1_DZE     (1 << 14)
+#define SCTLR_ELx_I       (1 << 12)
+#define SCTLR_EL1_UMA     (1 << 9)
+#define SCTLR_EL1_SED     (1 << 8)
+#define SCTLR_EL1_ITD     (1 << 7)
+#define SCTLR_EL1_THEE    (1 << 6)
+#define SCTLR_EL1_CP15BEN (1 << 5)
+#define SCTLR_EL1_SA0     (1 << 4)
+#define SCTLR_ELx_SA      (1 << 3)
+#define SCTLR_ELx_C       (1 << 2)
+#define SCTLR_ELx_A       (1 << 1)
+#define SCTLR_ELx_M       (1 << 0)
+
+//
+// Architectural Feature Access Control Register
+//
+#define CPACR_EL1_TTA     (1 << 28)
+#define CPACR_EL1_FPEN    (3 << 20)
+
+//
+// Architectural Feature Trap Register
+//
+#define CPTR_ELx_TCPAC (1 << 31)
+#define CPTR_ELx_TTA   (1 << 20)
+#define CPTR_ELx_TFP   (1 << 10)
+
+//
+// Secure Configuration Register
+//
+#define SCR_EL3_TWE  (1 << 13)
+#define SCR_EL3_TWI  (1 << 12)
+#define SCR_EL3_ST   (1 << 11)
+#define SCR_EL3_RW   (1 << 10)
+#define SCR_EL3_SIF  (1 << 9)
+#define SCR_EL3_HCE  (1 << 8)
+#define SCR_EL3_SMD  (1 << 7)
+#define SCR_EL3_EA   (1 << 3)
+#define SCR_EL3_FIQ  (1 << 2)
+#define SCR_EL3_IRQ  (1 << 1)
+#define SCR_EL3_NS   (1 << 0)
+
+//
+// Hypervisor Configuration Register
+//
+#define HCR_EL2_ID   (1 << 33)
+#define HCR_EL2_CD   (1 << 32)
+#define HCR_EL2_RW   (1 << 31)
+#define HCR_EL2_TRVM (1 << 30)
+#define HCR_EL2_HVC  (1 << 29)
+#define HCR_EL2_TDZ  (1 << 28)
+
+#endif // V8_SYSTEM_H
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S
new file mode 100644
index 00000000..f0fcef26
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S
@@ -0,0 +1,69 @@
+//
+// Simple utility routines for baremetal v8 code
+//
+// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//
+// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
+//
+// Zero fill a block of memory
+//   Fill memory pages or similar structures with zeros.
+//   The byte count must be a multiple of the block fill size (16 bytes)
+//
+//  Inputs:
+//    blockPtr - base address of block to fill
+//    nBytes - block size, in bytes
+//
+//  Returns:
+//    pointer to just filled block, NULL if nBytes is
+//  incompatible with block fill size
+//
+    .global ZeroBlock
+    .type ZeroBlock, "function"
+    .cfi_startproc
+ZeroBlock:
+
+    //
+    // we fill data by steam, 16 bytes at a time: check that
+    // blocksize is a multiple of that
+    //
+    ubfx x2, x1, #0, #4
+    cbnz x2, incompatible
+
+    //
+    // we already have one register full of zeros, get another
+    //
+    mov x3, x2
+
+    //
+    // OK, set temporary pointer and away we go
+    //
+    add x0, x0, x1
+
+loop0:
+    subs x1, x1, #16
+    stp  x2, x3, [x0, #-16]!
+    b.ne loop0
+
+    //
+    // that's all - x0 will be back to its start value
+    //
+    ret
+
+    //
+    // parameters are incompatible with block size - return
+    // an indication that this is so
+    //
+incompatible:
+    mov x0,#0
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S
new file mode 100644
index 00000000..9e60e001
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S
@@ -0,0 +1,252 @@
+// ------------------------------------------------------------
+// Armv8-A Vector tables
+//
+// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+    .global c0sync1
+    .global irqHandler
+    .global fiqHandler
+    .global irqFirstLevelHandler
+    .global fiqFirstLevelHandler
+
+    .section  EL1VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el1_vectors:
+c0sync1: B c0sync1
+
+    .balign 0x80
+c0irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr1: B c0serr1
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync1: B cxsync1
+
+    .balign 0x80
+cxirq1: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr1: B cxserr1
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync1: B l64sync1
+
+    .balign 0x80
+l64irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr1: B l64serr1
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync1: B l32sync1
+
+    .balign 0x80
+l32irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr1: B l32serr1
+
+//----------------------------------------------------------------
+
+    .section  EL2VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el2_vectors:
+c0sync2: B c0sync2
+
+    .balign 0x80
+c0irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr2: B c0serr2
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync2: B cxsync2
+
+    .balign 0x80
+cxirq2: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr2: B cxserr2
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync2: B l64sync2
+
+    .balign 0x80
+l64irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr2: B l64serr2
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync2: B l32sync2
+
+    .balign 0x80
+l32irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr2: B l32serr2
+
+//----------------------------------------------------------------
+
+    .section  EL3VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el3_vectors:
+c0sync3: B c0sync3
+
+    .balign 0x80
+c0irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr3: B c0serr3
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync3: B cxsync3
+
+    .balign 0x80
+cxirq3: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr3: B cxserr3
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync3: B l64sync3
+
+    .balign 0x80
+l64irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr3: B l64serr3
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync3: B l32sync3
+
+    .balign 0x80
+l32irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr3: B l32serr3
+
+
+    .section InterruptHandlers, "ax"
+    .balign 4
+
+    .type irqFirstLevelHandler, "function"
+irqFirstLevelHandler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+  BL       irqHandler
+  B        _tx_thread_context_restore
+
+    .type fiqFirstLevelHandler, "function"
+fiqFirstLevelHandler:
+  STP      x29, x30, [sp, #-16]!
+  STP      x18, x19, [sp, #-16]!
+  STP      x16, x17, [sp, #-16]!
+  STP      x14, x15, [sp, #-16]!
+  STP      x12, x13, [sp, #-16]!
+  STP      x10, x11, [sp, #-16]!
+  STP      x8, x9, [sp, #-16]!
+  STP      x6, x7, [sp, #-16]!
+  STP      x4, x5, [sp, #-16]!
+  STP      x2, x3, [sp, #-16]!
+  STP      x0, x1, [sp, #-16]!
+
+  BL       fiqHandler
+
+  LDP      x0, x1, [sp], #16
+  LDP      x2, x3, [sp], #16
+  LDP      x4, x5, [sp], #16
+  LDP      x6, x7, [sp], #16
+  LDP      x8, x9, [sp], #16
+  LDP      x10, x11, [sp], #16
+  LDP      x12, x13, [sp], #16
+  LDP      x14, x15, [sp], #16
+  LDP      x16, x17, [sp], #16
+  LDP      x18, x19, [sp], #16
+  LDP      x29, x30, [sp], #16
+  ERET
diff --git a/ports_module/cortex_a35/ac6/example_build/tx/.cproject b/ports_module/cortex_a35/ac6/example_build/tx/.cproject
new file mode 100644
index 00000000..51f626a6
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/tx/.cproject
@@ -0,0 +1,172 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings>
+                    					
+                    <externalSetting>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
+                        					
+                    </externalSetting>
+                    				
+                </externalSettings>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.174366982" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6">
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.319260876" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.debug.level.287044124" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.174366982.1434986226" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.2017005160" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1905027615" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.cpu.317101671" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.preproc.enableToolSpecificSettings.1714523388" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.v6.base.options.preproc.enableToolSpecificSettings" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.defmac.1928960091" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.866578922" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_port}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.448503435" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                								
+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.409900163" superClass="com.arm.tool.c.compiler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.87976211" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.542056309" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.567657544" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.cpu.230057138" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.options.preproc.enableToolSpecificSettings.2042679359" name="Enable tool specific settings" superClass="com.arm.tool.assembler.v6.base.options.preproc.enableToolSpecificSettings" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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+                                <option id="com.arm.tool.assembler.v6.base.options.debug.level.481373844" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.defmac.323399329" name="Define macro (-D)" superClass="com.arm.tool.assembler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
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+                                    <listOptionValue builtIn="false" value="EL1"/>
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+                                <option id="com.arm.tool.assembler.v6.base.option.force.preproc.501787008" name="Preprocess input files (-x assembler-with-cpp)" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+                                <inputType id="com.arm.tool.assembler.v6.base.input.424570744" superClass="com.arm.tool.assembler.v6.base.input"/>
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+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.302832878" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1893346540" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="src_generic/tx_misra.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="tx.com.arm.eclipse.build.project.v6.lib.1209080418" name="Static Library"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/ac6/example_build/tx/.project b/ports_module/cortex_a35/ac6/example_build/tx/.project
new file mode 100644
index 00000000..8f71f94d
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/tx/.project
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>tx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_modules</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
+		</link>
+		<link>
+			<name>src_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/src</locationURI>
+		</link>
+		<link>
+			<name>src_port</name>
+			<type>2</type>
+			<locationURI>PARENT-2-PROJECT_LOC/module_manager/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35/ac6/example_build/txm/.cproject b/ports_module/cortex_a35/ac6/example_build/txm/.cproject
new file mode 100644
index 00000000..dddf4382
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/txm/.cproject
@@ -0,0 +1,172 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings>
+                    					
+                    <externalSetting>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/>
+                        					
+                    </externalSetting>
+                    				
+                </externalSettings>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6">
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.688166309" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.floatabi.197203083" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.floatabi.auto" valueType="enumerated"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.inst.552700328" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.inst.auto" valueType="enumerated"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.debug.level.1623863720" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766.195306460" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1164059605" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.100103692" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.target.775437314" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="aarch64-arm-none-eabi" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.cpu.957518664" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.fpu.1476959906" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.floatabi.2113301488" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.auto" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.inst.36110020" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.auto" valueType="enumerated"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498990421" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic_module_manager}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.536480260" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.c.compiler.v6.base.option.flags.292072134" name="Other flags" superClass="com.arm.tool.c.compiler.v6.base.option.flags" useByScannerDiscovery="true" valueType="stringList"/>
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+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.1961882835" superClass="com.arm.tool.c.compiler.v6.base.input"/>
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+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.262825882" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1390685682" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.596919840" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.target.1155866423" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="aarch64-arm-none-eabi" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.cpu.1741335442" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.fpu.169397194" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.floatabi.1378563076" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.auto" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.inst.213408634" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.auto" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.options.debug.level.383141003" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.flags.1542396439" name="Other flags" superClass="com.arm.tool.assembler.v6.base.option.flags" useByScannerDiscovery="true" valueType="stringList"/>
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.1847017761" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1124663047" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1439633481" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/txm"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/ac6/example_build/txm/.project b/ports_module/cortex_a35/ac6/example_build/txm/.project
new file mode 100644
index 00000000..8b510516
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/example_build/txm/.project
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>txm</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_generic_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_generic_modules</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
+		</link>
+		<link>
+			<name>src_generic_module_lib</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_lib/src</locationURI>
+		</link>
+		<link>
+			<name>src_port_module_lib</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/module_lib/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35/ac6/inc/tx_port.h b/ports_module/cortex_a35/ac6/inc/tx_port.h
new file mode 100644
index 00000000..7072796c
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/inc/tx_port.h
@@ -0,0 +1,396 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include <stdlib.h>
+#include <string.h>
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef int                                     LONG;
+typedef unsigned int                            ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Override the alignment type to use 64-bit alignment and storage for pointers.  */
+
+#define ALIGN_TYPE_DEFINED
+typedef unsigned long long                      ALIGN_TYPE;
+
+
+/* Override the free block marker for byte pools to be a 64-bit constant.   */
+
+#define TX_BYTE_BLOCK_FREE                      ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE)
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              4096        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex ARMv8 port.  */ 
+
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ & FIQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#else
+#ifndef TX_TRACE_TIME_SOURCE
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0
+#define TX_THREAD_EXTENSION_1
+#define TX_THREAD_EXTENSION_2               ULONG   tx_thread_fp_enable;
+#define TX_THREAD_EXTENSION_3               VOID    *tx_thread_extension_ptr;               \
+                                            VOID    *tx_thread_module_instance_ptr;         \
+                                            VOID    *tx_thread_module_entry_info_ptr;       \
+                                            ULONG   tx_thread_module_current_user_mode;     \
+                                            ULONG   tx_thread_module_user_mode;             \
+                                            ULONG   tx_thread_module_saved_lr;              \
+                                            VOID    *tx_thread_module_kernel_stack_start;   \
+                                            VOID    *tx_thread_module_kernel_stack_end;     \
+                                            ULONG   tx_thread_module_kernel_stack_size;     \
+                                            VOID    *tx_thread_module_stack_ptr;            \
+                                            VOID    *tx_thread_module_stack_start;          \
+                                            VOID    *tx_thread_module_stack_end;            \
+                                            ULONG   tx_thread_module_stack_size;            \
+                                            VOID    *tx_thread_module_reserved;
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       b =  (UINT) __builtin_ctz((unsigned int) m);
+
+#endif
+
+
+/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout
+   can figure out what thread timeout to process.  */
+   
+#define TX_TIMER_INTERNAL_EXTENSION             VOID    *tx_timer_internal_thread_timeout_ptr;
+
+
+/* Define the thread timeout setup logic in _tx_thread_create.  */
+
+#define TX_THREAD_CREATE_TIMEOUT_SETUP(t)    (t) -> tx_thread_timer.tx_timer_internal_timeout_function =    &(_tx_thread_timeout);            \
+                                             (t) -> tx_thread_timer.tx_timer_internal_timeout_param =       0;                                \
+                                             (t) -> tx_thread_timer.tx_timer_internal_thread_timeout_ptr =  (VOID *) (t);
+
+
+/* Define the thread timeout pointer setup in _tx_thread_timeout.  */
+
+#define TX_THREAD_TIMEOUT_POINTER_SETUP(t)   (t) =  (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr;
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifndef TX_DISABLE_INLINE
+
+/* Define macros, with in-line assembly for performance.  */
+
+__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void)
+{
+
+unsigned long long  daif_value;
+
+    __asm__ volatile (" MRS  %0, DAIF ": "=r" (daif_value) );
+    __asm__ volatile (" MSR  DAIFSet, 0x3" : : : "memory" );
+    return((unsigned int) daif_value);
+}
+
+__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int daif_value)
+{
+
+unsigned long long temp;
+
+    temp =  (unsigned long long) daif_value;
+    __asm__ volatile (" MSR  DAIF,%0": : "r" (temp): "memory" );
+}
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+#define TX_DISABLE                              interrupt_save =  __disable_interrupts();
+#define TX_RESTORE                              __restore_interrupts(interrupt_save);
+
+#else
+
+unsigned int   _tx_thread_interrupt_disable(void);
+unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+#endif
+
+
+/* Define FP extension for the Cortex-A35.  Each is assumed to be called in the context of the executing
+   thread.  */
+
+#ifndef TX_SOURCE_CODE
+#define tx_thread_fp_enable                     _tx_thread_fp_enable
+#define tx_thread_fp_disable                    _tx_thread_fp_disable
+#endif
+
+VOID    tx_thread_fp_enable(VOID);
+VOID    tx_thread_fp_disable(VOID);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Modules Cortex-A35/AC6 Version 6.1.3 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
diff --git a/ports_module/cortex_a35/ac6/inc/txm_module_port.h b/ports_module/cortex_a35/ac6/inc/txm_module_port.h
new file mode 100644
index 00000000..adbef2de
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/inc/txm_module_port.h
@@ -0,0 +1,284 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
+/*                                                                        */
+/*    txm_module_port.h                                 Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file defines the basic module constants, interface structures, */
+/*    and function prototypes.                                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TXM_MODULE_PORT_H
+#define TXM_MODULE_PORT_H
+
+/* Determine if the optional Modules user define file should be used.  */
+
+#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in txm_module_user.h. The defines in this file may
+   alternately be defined on the command line.  */
+
+#include "txm_module_user.h"
+#endif
+
+/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
+  following extensions to the ThreadX thread control block (this code should replace
+  the corresponding macro define in tx_port.h):
+
+#define TX_THREAD_EXTENSION_2               VOID    *tx_thread_module_instance_ptr;         \
+                                            VOID    *tx_thread_module_entry_info_ptr;       \
+                                            ULONG   tx_thread_module_current_user_mode;     \
+                                            ULONG   tx_thread_module_user_mode;             \
+                                            ULONG   tx_thread_module_saved_lr;              \
+                                            VOID    *tx_thread_module_kernel_stack_start;   \
+                                            VOID    *tx_thread_module_kernel_stack_end;     \
+                                            ULONG   tx_thread_module_kernel_stack_size;     \
+                                            VOID    *tx_thread_module_stack_ptr;            \
+                                            VOID    *tx_thread_module_stack_start;          \
+                                            VOID    *tx_thread_module_stack_end;            \
+                                            ULONG   tx_thread_module_stack_size;            \
+                                            VOID    *tx_thread_module_reserved;
+
+The following extensions must also be defined in tx_port.h:
+
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+*/
+
+/* Define the kernel stack size for a module thread.  */
+#ifndef TXM_MODULE_KERNEL_STACK_SIZE
+#define TXM_MODULE_KERNEL_STACK_SIZE            768
+#endif
+
+/* Define constants specific to the tools the module can be built with for this particular modules port.  */
+
+#define TXM_MODULE_IAR_COMPILER                 0x00000000
+#define TXM_MODULE_RVDS_COMPILER                0x01000000
+#define TXM_MODULE_GNU_COMPILER                 0x02000000
+#define TXM_MODULE_COMPILER_MASK                0xFF000000
+#define TXM_MODULE_OPTIONS_MASK                 0x000000FF
+
+
+/* Define the properties for this particular module port.  */
+
+#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
+
+#ifdef  TXM_MODULE_MEMORY_PROTECTION_ENABLED
+#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
+#else
+#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
+#endif
+
+#define TXM_MODULE_USER_MODE                        0x00000001
+#define TXM_MODULE_MEMORY_PROTECTION                0x00000002
+#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS    0x00000004
+
+
+/* Define the supported options for this module.   */
+
+#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS    (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
+#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS     0
+
+
+/* Define offset adjustments according to the compiler used to build the module.  */
+
+#define TXM_MODULE_IAR_SHELL_ADJUST             24
+#define TXM_MODULE_IAR_START_ADJUST             28
+#define TXM_MODULE_IAR_STOP_ADJUST              32
+#define TXM_MODULE_IAR_CALLBACK_ADJUST          44
+
+#define TXM_MODULE_RVDS_SHELL_ADJUST            0
+#define TXM_MODULE_RVDS_START_ADJUST            0
+#define TXM_MODULE_RVDS_STOP_ADJUST             0
+#define TXM_MODULE_RVDS_CALLBACK_ADJUST         0
+
+#define TXM_MODULE_GNU_SHELL_ADJUST             24
+#define TXM_MODULE_GNU_START_ADJUST             28
+#define TXM_MODULE_GNU_STOP_ADJUST              32
+#define TXM_MODULE_GNU_CALLBACK_ADJUST          44
+
+
+/* Define other module port-specific constants.  */
+
+/* Define INLINE_DECLARE to inline for ARM compiler.  */
+
+#define INLINE_DECLARE inline
+
+
+/* Define the port-extensions to the module manager instance structure.  */
+
+#define TXM_MODULE_MANAGER_PORT_EXTENSION
+
+
+/* Define the memory fault information structure that is populated when a memory fault occurs.  */
+
+typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
+{
+    TX_THREAD           *txm_module_manager_memory_fault_info_thread_ptr;
+    VOID                *txm_module_manager_memory_fault_info_code_location;
+    ULONG               txm_module_manager_memory_fault_info_shcsr;
+    ULONG               txm_module_manager_memory_fault_info_cfsr;
+    ULONG               txm_module_manager_memory_fault_info_mmfar;
+    ULONG               txm_module_manager_memory_fault_info_bfar;
+    ULONG               txm_module_manager_memory_fault_info_control;
+    ULONG               txm_module_manager_memory_fault_info_sp;
+    ULONG               txm_module_manager_memory_fault_info_r0;
+    ULONG               txm_module_manager_memory_fault_info_r1;
+    ULONG               txm_module_manager_memory_fault_info_r2;
+    ULONG               txm_module_manager_memory_fault_info_r3;
+    ULONG               txm_module_manager_memory_fault_info_r4;
+    ULONG               txm_module_manager_memory_fault_info_r5;
+    ULONG               txm_module_manager_memory_fault_info_r6;
+    ULONG               txm_module_manager_memory_fault_info_r7;
+    ULONG               txm_module_manager_memory_fault_info_r8;
+    ULONG               txm_module_manager_memory_fault_info_r9;
+    ULONG               txm_module_manager_memory_fault_info_r10;
+    ULONG               txm_module_manager_memory_fault_info_r11;
+    ULONG               txm_module_manager_memory_fault_info_r12;
+    ULONG               txm_module_manager_memory_fault_info_lr;
+    ULONG               txm_module_manager_memory_fault_info_xpsr;
+} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
+
+
+#define TXM_MODULE_MANAGER_FAULT_INFO                                               \
+    TXM_MODULE_MANAGER_MEMORY_FAULT_INFO    _txm_module_manager_memory_fault_info;
+
+/* Define the macro to check the code alignment.  */
+
+#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment)    \
+    {                                                                               \
+        ALIGN_TYPE   temp;                                                          \
+        temp =  (ALIGN_TYPE) module_location;                                       \
+        temp =  temp & (code_alignment - 1);                                        \
+        if (temp)                                                                   \
+        {                                                                           \
+            _tx_mutex_put(&_txm_module_manager_mutex);                              \
+            return(TXM_MODULE_ALIGNMENT_ERROR);                                     \
+        }                                                                           \
+    }
+
+
+/* Define the macro to adjust the alignment and size for code/data areas.  */
+
+#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) \
+    {                                                                                                              \
+        code_size = (code_size % 32) ? ((code_size + 32) & ~32) : (code_size);                                     \
+        code_alignment = 32;                                                                                       \
+        data_size = (data_size % 32) ? ((data_size + 32) & ~32) : (data_size);                                     \
+        data_alignment = 32;                                                                                       \
+    }
+
+
+/* Define the macro to adjust the symbols in the module preamble.  */
+
+#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
+    if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER)         \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_IAR_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_IAR_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_IAR_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_IAR_CALLBACK_ADJUST;                 \
+    }                                                                               \
+    else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER)   \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_RVDS_SHELL_ADJUST;                   \
+        start_function_adjust =     TXM_MODULE_RVDS_START_ADJUST;                   \
+        stop_function_adjust =      TXM_MODULE_RVDS_STOP_ADJUST;                    \
+        callback_function_adjust =  TXM_MODULE_RVDS_CALLBACK_ADJUST;                \
+    }                                                                               \
+    else                                                                            \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_GNU_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_GNU_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_GNU_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_GNU_CALLBACK_ADJUST;                 \
+    }
+
+
+/* Define the macro to populate the thread control block with module port-specific information.
+   Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
+*/
+
+#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance)                                                                    \
+    thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher =   _txm_module_manager_kernel_dispatch;
+
+
+/* Define the macro to populate the module control block with module port-specific information.
+*/
+#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance)
+
+
+/* Define the macro to perform port-specific functions when unloading the module.  */
+/* Nothing needs to be done for this port.  */
+#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
+
+
+/* Define the macros to perform port-specific checks when passing pointers to the kernel.  */
+
+/* Define macro to make sure object is inside the module's data.  */
+#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) (TX_SUCCESS)
+
+/* Define some internal prototypes to this module port.  */
+
+#ifndef TX_SOURCE_CODE
+#define txm_module_manager_memory_fault_notify              _txm_module_manager_memory_fault_notify
+#endif
+
+
+#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES                                                                                                                      \
+VOID  _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment);   \
+ULONG _txm_module_manager_region_size_get(ULONG block_size);                                                                                                          \
+UINT  _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);                                                 \
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2);
+
+#define TXM_MODULE_MANAGER_VERSION_ID   \
+CHAR                            _txm_module_manager_version_id[] =  \
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Module Cortex-A35/AC6 Version 6.1.3 *";
+
+#endif
diff --git a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S
new file mode 100644
index 00000000..86c3aa4b
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S
@@ -0,0 +1,63 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TXM_MODULE_HEAP_SIZE 512
+
+    .text
+
+// module entry point
+    .align 3
+    .global _txm_module_initialize
+_txm_module_initialize:
+    sub     sp, sp, 16
+    str     x30, [sp]
+    B       __main
+
+// main function called by the C library
+    .align 3
+    .global main
+main:
+    // Do nothing
+    RET
+
+// custom exit, return to the initialization caller
+    .align 3
+    .global exit
+exit:
+    ldr     x30, [sp]
+    add     sp, sp, 16
+    RET
+
+// returns heap start address in  R0
+// returns heap end address in    R2
+// does not touch SP, it is already set up before the module runs
+    .align 3
+    .global __user_setup_stackheap
+__user_setup_stackheap:
+    LDR     x0, =_txm_heap                      // load heap offset
+    MOV     x2, TXM_MODULE_HEAP_SIZE            // load heap size
+    ADD     x2, x2, x0                          // calculate heap end address
+    RET
+
+    .align 8
+_txm_heap:
+    .zero   TXM_MODULE_HEAP_SIZE
diff --git a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c
new file mode 100644
index 00000000..3132be35
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c
@@ -0,0 +1,180 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#ifndef TXM_MODULE
+#define TXM_MODULE
+#endif
+
+#ifndef TX_SOURCE_CODE
+#define TX_SOURCE_CODE
+#endif
+
+
+/* Include necessary system files.  */
+
+#include "txm_module.h"
+#include "tx_thread.h"
+
+/* Define the global module entry pointer from the start thread of the module.  */
+
+TXM_MODULE_THREAD_ENTRY_INFO    *_txm_module_entry_info;
+
+
+/* Define the dispatch function pointer used in the module implementation.  */
+
+ALIGN_TYPE                      (*_txm_module_kernel_call_dispatcher)(ULONG type, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param3);
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_thread_shell_entry                   Cortex-A35/AC6     */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function calls the specified entry function of the thread.  It */
+/*    also provides a place for the thread's entry function to return.    */
+/*    If the thread returns, this function places the thread in a         */
+/*    "COMPLETED" state.                                                  */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                        Pointer to current thread         */
+/*    thread_info                       Pointer to thread entry info      */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_initialize            cstartup initialization           */
+/*    thread_entry                      Thread's entry function           */
+/*    tx_thread_resume                  Resume the module callback thread */
+/*    _txm_module_thread_system_suspend Module thread suspension routine  */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Initial thread stack frame                                          */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
+{
+
+TX_INTERRUPT_SAVE_AREA
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+VOID            (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type);
+#endif
+
+
+    /* Perform any additional activities for tool or user purpose.  */
+    TX_THREAD_STARTED_EXTENSION(thread_ptr)
+
+    /* Determine if this is the start thread.  If so, we must prepare the module for
+       execution.  If not, simply skip the C startup code.  */
+    if (thread_info -> txm_module_thread_entry_info_start_thread)
+    {
+        /* Initialize the C library */
+        extern void _txm_module_initialize(void);
+        _txm_module_initialize();
+
+        /* Save the entry info pointer, for later use.  */
+        _txm_module_entry_info =  thread_info;
+
+        /* Save the kernel function dispatch address. This is used to make all resident calls from
+           the module.  */
+        _txm_module_kernel_call_dispatcher =  thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
+
+        /* Ensure that we have a valid pointer.  */
+        while (!_txm_module_kernel_call_dispatcher)
+        {
+            /* Loop here, if an error is present getting the dispatch function pointer!
+               An error here typically indicates the resident portion of _tx_thread_schedule
+               is not supporting the trap to obtain the function pointer.   */
+        }
+        
+        /* Resume the module's callback thread, already created in the manager.  */
+        _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
+    }
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Disable interrupts.  */
+    TX_DISABLE
+
+    /* Pickup the entry/exit application callback routine.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Restore interrupts.  */
+    TX_RESTORE
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has been entered!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
+    }
+#endif
+
+    /* Call current thread's entry function.  */
+    (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
+
+    /* Suspend thread with a "completed" state.  */
+
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Pickup the entry/exit application callback routine again.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has exited!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
+    }
+#endif
+
+    /* Call actual thread suspension routine.  */
+    _txm_module_thread_system_suspend(thread_ptr);
+
+#ifdef TX_SAFETY_CRITICAL
+
+    /* If we ever get here, raise safety critical exception.  */
+    TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
+#endif
+}
+
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..9e552c94
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S
@@ -0,0 +1,287 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_restore                        Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function restores the interrupt context if it is processing a  */
+/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+/*    if no thread was running, the function returns to the scheduler.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling routine     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                  Interrupt Service Routines    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_restore(VOID)
+// {
+    .global _tx_thread_context_restore
+    .type   _tx_thread_context_restore, @function
+_tx_thread_context_restore:
+
+    /* Lockout interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR exit function to indicate an ISR is complete.  */
+
+    BL      _tx_execution_isr_exit              // Call the ISR exit function
+#endif
+
+    /* Determine if interrupts are nested.  */
+    // if (--_tx_thread_system_state)
+    // {
+
+    LDR     x3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     w2, [x3, #0]                        // Pickup system state
+    SUB     w2, w2, #1                          // Decrement the counter
+    STR     w2, [x3, #0]                        // Store the counter 
+    CMP     w2, #0                              // Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      // If so, not a nested restore
+
+    /* Interrupts are nested.  */
+
+    /* Just recover the saved registers and return to the point of 
+       interrupt.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+    // }
+__tx_thread_not_nested_restore:
+
+    /* Determine if a thread was interrupted and no preemption is required.  */
+    // else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+    //           || (_tx_thread_preempt_disable))
+    // {
+
+    LDR     x1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     x0, [x1, #0]                        // Pickup actual current thread pointer
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     // Yes, idle system was interrupted
+
+    LDR     x3, =_tx_thread_preempt_disable     // Pickup preempt disable address
+    LDR     w2, [x3, #0]                        // Pickup actual preempt disable flag
+    CMP     w2, #0                              // Is it set?
+    BNE     __tx_thread_no_preempt_restore      // Yes, don't preempt this thread
+    LDR     x3, =_tx_thread_execute_ptr         // Pickup address of execute thread ptr
+    LDR     x2, [x3, #0]                        // Pickup actual execute thread pointer
+    CMP     x0, x2                              // Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore         // No, preemption needs to happen
+
+
+__tx_thread_no_preempt_restore:
+
+    /* Restore interrupted thread or ISR.  */
+
+    /* Pickup the saved stack pointer.  */
+    // sp =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+
+    LDR     x4, [x0, #8]                        // Switch to thread stack pointer
+    MOV     sp, x4                              //
+
+   /* Recover the saved context and return to the point of interrupt.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+    // }
+    // else
+    // {
+__tx_thread_preempt_restore:
+
+    LDR     x4, [x0, #8]                        // Switch to thread stack pointer
+    MOV     sp, x4                              //
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+    STP     x20, x21, [sp, #-16]!               // Save x20, x21
+    STP     x22, x23, [sp, #-16]!               // Save x22, x23
+    STP     x24, x25, [sp, #-16]!               // Save x24, x25
+    STP     x26, x27, [sp, #-16]!               // Save x26, x27
+    STP     x28, x29, [sp, #-16]!               // Save x28, x29
+#ifdef ENABLE_ARM_FP
+    LDR     w3, [x0, #248]                      // Pickup FP enable flag
+    CMP     w3, #0                              // Is FP enabled?
+    BEQ     _skip_fp_save                       // No, skip FP save
+    STP     q0,  q1,  [sp, #-32]!               // Save q0, q1
+    STP     q2,  q3,  [sp, #-32]!               // Save q2, q3
+    STP     q4,  q5,  [sp, #-32]!               // Save q4, q5
+    STP     q6,  q7,  [sp, #-32]!               // Save q6, q7
+    STP     q8,  q9,  [sp, #-32]!               // Save q8, q9
+    STP     q10, q11, [sp, #-32]!               // Save q10, q11
+    STP     q12, q13, [sp, #-32]!               // Save q12, q13
+    STP     q14, q15, [sp, #-32]!               // Save q14, q15
+    STP     q16, q17, [sp, #-32]!               // Save q16, q17
+    STP     q18, q19, [sp, #-32]!               // Save q18, q19
+    STP     q20, q21, [sp, #-32]!               // Save q20, q21
+    STP     q22, q23, [sp, #-32]!               // Save q22, q23
+    STP     q24, q25, [sp, #-32]!               // Save q24, q25
+    STP     q26, q27, [sp, #-32]!               // Save q26, q27
+    STP     q28, q29, [sp, #-32]!               // Save q28, q29
+    STP     q30, q31, [sp, #-32]!               // Save q30, q31
+    MRS     x2, FPSR                            // Pickup FPSR
+    MRS     x3, FPCR                            // Pickup FPCR
+    STP     x2, x3, [sp, #-16]!                 // Save FPSR, FPCR
+_skip_fp_save:
+#endif
+    STP     x4, x5, [sp, #-16]!                 // Save x4 (SPSR_EL3), x5 (ELR_E3)
+
+    MOV     x3, sp                              // Move sp into x3
+    STR     x3, [x0, #8]                        // Save stack pointer in thread control
+                                                //   block
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, #0]                        // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+
+    /* Save the remaining time-slice and disable it.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    LDR     x3, =_tx_timer_time_slice           // Pickup time-slice variable address
+    LDR     w2, [x3, #0]                        // Pickup time-slice
+    CMP     w2, #0                              // Is it active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save it
+
+        /* _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+        _tx_timer_time_slice =  0;  */
+
+    STR     w2, [x0, #36]                       // Save thread's time-slice
+    MOV     w2, #0                              // Clear value
+    STR     w2, [x3, #0]                        // Disable global time-slice flag
+
+    // }
+__tx_thread_dont_save_ts:
+
+
+    /* Clear the current task pointer.  */
+    // _tx_thread_current_ptr =  TX_NULL;
+
+    MOV     x0, #0                              // NULL value
+    STR     x0, [x1, #0]                        // Clear current thread pointer
+
+    /* Return to the scheduler.  */
+    // _tx_thread_schedule();
+
+    // }
+
+__tx_thread_idle_system_restore:
+
+    /* Just return back to the scheduler!  */
+
+    LDR    x1, =_tx_thread_schedule             // Build address for _tx_thread_schedule
+#ifdef EL1
+    MSR    ELR_EL1, x1                          // Setup point of interrupt
+//    MOV    x1, #0x4                             // Setup EL1 return
+//    MSR    spsr_el1, x1                         // Move into SPSR
+#else
+#ifdef EL2
+    MSR    ELR_EL2, x1                          // Setup point of interrupt
+//    MOV    x1, #0x8                             // Setup EL2 return
+//    MSR    spsr_el2, x1                         // Move into SPSR
+#else
+    MSR    ELR_EL3, x1                          // Setup point of interrupt
+//    MOV    x1, #0xC                             // Setup EL3 return
+//    MSR    spsr_el3, x1                         // Move into SPSR
+#endif
+#endif
+    ERET                                        // Return to scheduler
+// }
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S
new file mode 100644
index 00000000..c0185b7b
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S
@@ -0,0 +1,217 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_save                           Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves the context of an executing thread in the       */
+/*    beginning of interrupt processing.  The function also ensures that  */
+/*    the system stack is used upon return to the calling ISR.            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_save(VOID)
+// {
+    .global _tx_thread_context_save
+    .type   _tx_thread_context_save, @function
+_tx_thread_context_save:
+
+    /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked
+       out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, 
+       and all other registers are intact.  */
+
+    /* Check for a nested interrupt condition.  */
+    // if (_tx_thread_system_state++)
+    // {
+
+    STP     x0, x1, [sp, #-16]!                 // Save x0, x1
+    STP     x2, x3, [sp, #-16]!                 // Save x2, x3
+    LDR     x3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     w2, [x3, #0]                        // Pickup system state
+    CMP     w2, #0                              // Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         // Yes, not a nested context save
+
+    /* Nested interrupt condition.  */
+
+    ADD     w2, w2, #1                          // Increment the nested interrupt counter
+    STR     w2, [x3, #0]                        // Store it back in the variable
+
+   /* Save the rest of the scratch registers on the stack and return to the
+      calling ISR.  */
+
+    STP     x4, x5, [sp, #-16]!                 // Save x4, x5
+    STP     x6, x7, [sp, #-16]!                 // Save x6, x7
+    STP     x8, x9, [sp, #-16]!                 // Save x8, x9
+    STP     x10, x11, [sp, #-16]!               // Save x10, x11
+    STP     x12, x13, [sp, #-16]!               // Save x12, x13
+    STP     x14, x15, [sp, #-16]!               // Save x14, x15
+    STP     x16, x17, [sp, #-16]!               // Save x16, x17
+    STP     x18, x19, [sp, #-16]!               // Save x18, x19
+#ifdef EL1
+    MRS     x0, SPSR_EL1                        // Pickup SPSR
+    MRS     x1, ELR_EL1                         // Pickup ELR (point of interrupt)
+#else
+#ifdef EL2
+    MRS     x0, SPSR_EL2                        // Pickup SPSR
+    MRS     x1, ELR_EL2                         // Pickup ELR (point of interrupt)
+#else
+    MRS     x0, SPSR_EL3                        // Pickup SPSR
+    MRS     x1, ELR_EL3                         // Pickup ELR (point of interrupt)
+#endif
+#endif
+    STP     x0, x1, [sp, #-16]!                 // Save SPSR, ELR
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    /* Return to the ISR.  */
+
+    RET                                         // Return to ISR
+
+__tx_thread_not_nested_save:
+    // }
+
+    /* Otherwise, not nested, check to see if a thread was running.  */
+    // else if (_tx_thread_current_ptr)
+    // {
+
+    ADD     w2, w2, #1                          // Increment the interrupt counter
+    STR     w2, [x3, #0]                        // Store it back in the variable
+    LDR     x1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     x0, [x1, #0]                        // Pickup current thread pointer
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_save        // If so, interrupt occurred in 
+                                                //   scheduling loop - nothing needs saving!
+
+    /* Save minimal context of interrupted thread.  */
+
+    STP     x4, x5, [sp, #-16]!                 // Save x4, x5
+    STP     x6, x7, [sp, #-16]!                 // Save x6, x7
+    STP     x8, x9, [sp, #-16]!                 // Save x8, x9
+    STP     x10, x11, [sp, #-16]!               // Save x10, x11
+    STP     x12, x13, [sp, #-16]!               // Save x12, x13
+    STP     x14, x15, [sp, #-16]!               // Save x14, x15
+    STP     x16, x17, [sp, #-16]!               // Save x16, x17
+    STP     x18, x19, [sp, #-16]!               // Save x18, x19
+#ifdef EL1
+    MRS     x4, SPSR_EL1                        // Pickup SPSR
+    MRS     x5, ELR_EL1                         // Pickup ELR (point of interrupt)
+#else
+#ifdef EL2
+    MRS     x4, SPSR_EL2                        // Pickup SPSR
+    MRS     x5, ELR_EL2                         // Pickup ELR (point of interrupt)
+#else
+    MRS     x4, SPSR_EL3                        // Pickup SPSR
+    MRS     x5, ELR_EL3                         // Pickup ELR (point of interrupt)
+#endif
+#endif
+    STP     x4, x5, [sp, #-16]!                 // Save SPSR, ELR
+
+    /* Save the current stack pointer in the thread's control block.  */
+    // _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+
+    MOV     x4, sp                              //
+    STR     x4, [x0, #8]                        // Save thread stack pointer
+
+    /* Switch to the system stack.  */
+    // sp =  _tx_thread_system_stack_ptr
+
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, #0]                        // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    RET                                         // Return to caller
+
+    // }
+    // else
+    // {
+
+__tx_thread_idle_system_save:
+
+    /* Interrupt occurred in the scheduling loop.  */
+
+    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+       processing.  */
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    ADD     sp, sp, #48                         // Recover saved registers
+    RET                                         // Continue IRQ processing  
+
+    // }
+// } 
+
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c
new file mode 100644
index 00000000..8a82c0af
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c
@@ -0,0 +1,94 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fp_disable                             Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function disables the FP for the currently executing thread.   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_fp_disable(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+ULONG       system_state;
+
+
+    /* Pickup the current thread pointer.  */
+    TX_THREAD_GET_CURRENT(thread_ptr);
+
+    /* Get the system state.  */
+    system_state =  TX_THREAD_GET_SYSTEM_STATE();
+
+    /* Make sure it is not NULL. */
+    if (thread_ptr != TX_NULL)
+    {
+        
+        /* Thread is running... make sure the call is from the thread context.  */
+        if (system_state == 0)
+        {
+        
+            /* Yes, now set the FP enable flag to false in the TX_THREAD structure.  */
+            thread_ptr -> tx_thread_fp_enable =  TX_FALSE;
+        }
+    }
+}
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c
new file mode 100644
index 00000000..c39078b0
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c
@@ -0,0 +1,94 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fp_enable                              Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function enabled the FP for the currently executing thread.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_fp_enable(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+ULONG       system_state;
+
+
+    /* Pickup the current thread pointer.  */
+    TX_THREAD_GET_CURRENT(thread_ptr);
+
+    /* Get the system state.  */
+    system_state =  TX_THREAD_GET_SYSTEM_STATE();
+
+    /* Make sure it is not NULL. */
+    if (thread_ptr != TX_NULL)
+    {
+        
+        /* Thread is running... make sure the call is from the thread context.  */
+        if (system_state == 0)
+        {
+        
+            /* Yes, now setup the FP enable flag in the TX_THREAD structure.  */
+            thread_ptr -> tx_thread_fp_enable =  TX_TRUE;
+        }
+    }
+}
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..c4ab0722
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S
@@ -0,0 +1,80 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_control                      Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for changing the interrupt lockout     */
+/*    posture of the system.                                              */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    new_posture                           New interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_control(UINT new_posture)
+// {
+    .global  _tx_thread_interrupt_control
+    .type    _tx_thread_interrupt_control, @function
+_tx_thread_interrupt_control:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     x1, DAIF                            // Pickup current interrupt posture
+
+    /* Apply the new interrupt posture.  */
+
+    MSR     DAIF, x0                            // Set new interrupt posture
+    MOV     x0, x1                              // Setup return value
+    RET                                         // Return to caller
+// }
+
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S
new file mode 100644
index 00000000..d4b3fb77
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S
@@ -0,0 +1,78 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_disable                      Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for disabling interrupts               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_disable(void)
+// {
+    .global _tx_thread_interrupt_disable
+    .type   _tx_thread_interrupt_disable, @function
+_tx_thread_interrupt_disable:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     x0, DAIF                            // Pickup current interrupt lockout posture
+
+    /* Mask interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    RET                                         // Return to caller
+// }
+
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S
new file mode 100644
index 00000000..feed8bd0
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S
@@ -0,0 +1,75 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_restore                      Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for restoring interrupts to the state  */
+/*    returned by a previous _tx_thread_interrupt_disable call.           */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_restore(UINT old_posture)
+// {
+    .global _tx_thread_interrupt_restore
+    .type   _tx_thread_interrupt_restore, @function
+_tx_thread_interrupt_restore:
+
+    /* Restore the old interrupt posture.  */
+
+    MSR     DAIF, x0                            // Setup the old posture
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S
new file mode 100644
index 00000000..954e4cd4
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S
@@ -0,0 +1,225 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_schedule                               Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function waits for a thread control block pointer to appear in */
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+/*    in the variable, the corresponding thread is resumed.               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+/*    _tx_thread_system_return             Return to system from thread   */
+/*    _tx_thread_context_restore           Restore thread's context       */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_schedule(VOID)
+// {
+    .global _tx_thread_schedule
+    .type   _tx_thread_schedule, @function
+_tx_thread_schedule:
+
+    /* Enable interrupts.  */
+
+    MSR     DAIFClr, 0x3                        // Enable interrupts
+
+    // Wait for a thread to execute.  */
+    // do
+    // {
+    
+    LDR     x1, =_tx_thread_execute_ptr         // Address of thread execute ptr
+
+#ifdef TX_ENABLE_WFI
+__tx_thread_schedule_loop:
+    LDR     x0, [x1, #0]                        // Pickup next thread to execute
+    CMP     x0, #0                              // Is it NULL?
+    BNE     _tx_thread_schedule_thread          // 
+    WFI                                         // 
+    B       __tx_thread_schedule_loop           // Keep looking for a thread
+_tx_thread_schedule_thread:
+#else
+__tx_thread_schedule_loop:
+    LDR     x0, [x1, #0]                        // Pickup next thread to execute
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_schedule_loop           // If so, keep looking for a thread
+#endif
+
+    // }
+    // while(_tx_thread_execute_ptr == TX_NULL);
+    
+    /* Yes! We have a thread to execute.  Lockout interrupts and
+       transfer control to it.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    /* Setup the current thread pointer.  */
+    // _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+
+    LDR     x1, =_tx_thread_current_ptr         // Pickup address of current thread 
+    STR     x0, [x1, #0]                        // Setup current thread pointer
+
+    /* Increment the run count for this thread.  */
+    // _tx_thread_current_ptr -> tx_thread_run_count++;
+
+    LDR     w2, [x0, #4]                        // Pickup run counter
+    LDR     w3, [x0, #36]                       // Pickup time-slice for this thread
+    ADD     w2, w2, #1                          // Increment thread run-counter
+    STR     w2, [x0, #4]                        // Store the new run counter
+
+    /* Setup time-slice, if present.  */
+    // _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+
+    LDR     x2, =_tx_timer_time_slice           // Pickup address of time slice 
+                                                //   variable
+    LDR     x4, [x0, #8]                        // Switch stack pointers
+    MOV     sp, x4                              //
+    STR     w3, [x2, #0]                        // Setup time-slice
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread entry function to indicate the thread is executing.  */
+
+    MOV     x19, x0                             // Save x0
+    BL      _tx_execution_thread_enter          // Call the thread execution enter function
+    MOV     x0, x19                             // Restore x0
+#endif
+
+    /* Switch to the thread's stack.  */
+    // sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+
+    /* Determine if an interrupt frame or a synchronous task suspension frame
+       is present.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+    CMP     x5, #0                              // Check for synchronous context switch (ELR_EL1 = NULL)
+    BEQ     _tx_solicited_return
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+#ifdef ENABLE_ARM_FP
+    LDR     w1, [x0, #248]                      // Pickup FP enable flag
+    CMP     w1, #0                              // Is FP enabled?
+    BEQ     _skip_interrupt_fp_restore          // No, skip FP restore
+    LDP     x0, x1,   [sp], #16                 // Pickup FPSR, FPCR
+    MSR     FPSR, x0                            // Recover FPSR
+    MSR     FPCR, x1                            // Recover FPCR
+    LDP     q30, q31, [sp], #32                 // Recover q30, q31
+    LDP     q28, q29, [sp], #32                 // Recover q28, q29
+    LDP     q26, q27, [sp], #32                 // Recover q26, q27
+    LDP     q24, q25, [sp], #32                 // Recover q24, q25
+    LDP     q22, q23, [sp], #32                 // Recover q22, q23
+    LDP     q20, q21, [sp], #32                 // Recover q20, q21
+    LDP     q18, q19, [sp], #32                 // Recover q18, q19
+    LDP     q16, q17, [sp], #32                 // Recover q16, q17
+    LDP     q14, q15, [sp], #32                 // Recover q14, q15
+    LDP     q12, q13, [sp], #32                 // Recover q12, q13
+    LDP     q10, q11, [sp], #32                 // Recover q10, q11
+    LDP     q8,  q9,  [sp], #32                 // Recover q8, q9
+    LDP     q6,  q7,  [sp], #32                 // Recover q6, q7
+    LDP     q4,  q5,  [sp], #32                 // Recover q4, q5
+    LDP     q2,  q3,  [sp], #32                 // Recover q2, q3
+    LDP     q0,  q1,  [sp], #32                 // Recover q0, q1
+_skip_interrupt_fp_restore:
+#endif
+    LDP     x28, x29, [sp], #16                 // Recover x28
+    LDP     x26, x27, [sp], #16                 // Recover x26, x27
+    LDP     x24, x25, [sp], #16                 // Recover x24, x25
+    LDP     x22, x23, [sp], #16                 // Recover x22, x23
+    LDP     x20, x21, [sp], #16                 // Recover x20, x21
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+_tx_solicited_return:
+
+#ifdef ENABLE_ARM_FP
+    LDR     w1, [x0, #248]                      // Pickup FP enable flag
+    CMP     w1, #0                              // Is FP enabled?
+    BEQ     _skip_solicited_fp_restore          // No, skip FP restore
+    LDP     x0, x1,   [sp], #16                 // Pickup FPSR, FPCR
+    MSR     FPSR, x0                            // Recover FPSR
+    MSR     FPCR, x1                            // Recover FPCR
+    LDP     q14, q15, [sp], #32                 // Recover q14, q15
+    LDP     q12, q13, [sp], #32                 // Recover q12, q13
+    LDP     q10, q11, [sp], #32                 // Recover q10, q11
+    LDP     q8,  q9,  [sp], #32                 // Recover q8, q9
+_skip_solicited_fp_restore:
+#endif
+    LDP     x27, x28, [sp], #16                 // Recover x27, x28
+    LDP     x25, x26, [sp], #16                 // Recover x25, x26
+    LDP     x23, x24, [sp], #16                 // Recover x23, x24
+    LDP     x21, x22, [sp], #16                 // Recover x21, x22
+    LDP     x19, x20, [sp], #16                 // Recover x19, x20
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    MSR     DAIF, x4                            // Recover DAIF
+    RET                                         // Return to caller
+// }
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..54fe1170
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S
@@ -0,0 +1,157 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_stack_build                            Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread control blk */
+/*    function_ptr                          Pointer to entry function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+// {
+    .global _tx_thread_stack_build
+    .type   _tx_thread_stack_build, @function
+_tx_thread_stack_build:
+
+
+    /* Build an interrupt frame.  On Cortex-A35 it should look like this:
+
+       Stack Top:      SSPR        Initial SSPR
+                       ELR         Point of interrupt
+                       x28         Initial value for x28
+                       not used    Not used
+                       x26         Initial value for x26
+                       x27         Initial value for x27
+                       x24         Initial value for x24
+                       x25         Initial value for x25
+                       x22         Initial value for x22
+                       x23         Initial value for x23
+                       x20         Initial value for x20
+                       x21         Initial value for x21
+                       x18         Initial value for x18
+                       x19         Initial value for x19
+                       x16         Initial value for x16
+                       x17         Initial value for x17
+                       x14         Initial value for x14
+                       x15         Initial value for x15
+                       x12         Initial value for x12
+                       x13         Initial value for x13
+                       x10         Initial value for x10
+                       x11         Initial value for x11
+                       x8          Initial value for x8
+                       x9          Initial value for x9
+                       x6          Initial value for x6
+                       x7          Initial value for x7
+                       x4          Initial value for x4
+                       x5          Initial value for x5
+                       x2          Initial value for x2
+                       x3          Initial value for x3
+                       x0          Initial value for x0
+                       x1          Initial value for x1
+                       x29         Initial value for x29 (frame pointer)
+                       x30         Initial value for x30 (link register)
+                       0           For stack backtracing
+
+       Stack Bottom: (higher memory address)
+    */
+
+    LDR     x4, [x0, #24]                       // Pickup end of stack area
+    BIC     x4, x4, #0xF                        // Ensure 16-byte alignment
+
+    /* Actually build the stack frame.  */
+
+    MOV     x2, #0                              // Build clear value
+    MOV     x3, #0                              //
+
+    STP     x2, x3, [x4, #-16]!                 // Set backtrace to 0
+    STP     x2, x3, [x4, #-16]!                 // Set initial x29, x30
+    STP     x2, x3, [x4, #-16]!                 // Set initial x0, x1
+    STP     x2, x3, [x4, #-16]!                 // Set initial x2, x3
+    STP     x2, x3, [x4, #-16]!                 // Set initial x4, x5
+    STP     x2, x3, [x4, #-16]!                 // Set initial x6, x7
+    STP     x2, x3, [x4, #-16]!                 // Set initial x8, x9
+    STP     x2, x3, [x4, #-16]!                 // Set initial x10, x11
+    STP     x2, x3, [x4, #-16]!                 // Set initial x12, x13
+    STP     x2, x3, [x4, #-16]!                 // Set initial x14, x15
+    STP     x2, x3, [x4, #-16]!                 // Set initial x16, x17
+    STP     x2, x3, [x4, #-16]!                 // Set initial x18, x19
+    STP     x2, x3, [x4, #-16]!                 // Set initial x20, x21
+    STP     x2, x3, [x4, #-16]!                 // Set initial x22, x23
+    STP     x2, x3, [x4, #-16]!                 // Set initial x24, x25
+    STP     x2, x3, [x4, #-16]!                 // Set initial x26, x27
+    STP     x2, x3, [x4, #-16]!                 // Set initial x28
+#ifdef EL1
+    MOV     x2, #0x4                            // Build initial SPSR  (EL1)
+#else
+#ifdef EL2
+    MOV     x2, #0x8                            // Build initial SPSR  (EL2)
+#else
+    MOV     x2, #0xC                            // Build initial SPSR  (EL3)
+#endif
+#endif
+    MOV     x3, x1                              // Build initial ELR
+    STP     x2, x3, [x4, #-16]!                 // Set initial SPSR & ELR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  x2;  */
+
+    STR     x4, [x0, #8]                        // Save stack pointer in thread's
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S
new file mode 100644
index 00000000..ff633812
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S
@@ -0,0 +1,151 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_system_return                          Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is target processor specific.  It is used to transfer */
+/*    control from a thread back to the ThreadX system.  Only a           */
+/*    minimal context is saved since the compiler assumes temp registers  */
+/*    are going to get slicked by a function call anyway.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling loop        */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_system_return(VOID)
+// {
+    .global _tx_thread_system_return
+    .type   _tx_thread_system_return, @function
+_tx_thread_system_return:
+
+    /* Save minimal context on the stack.  */
+
+    MRS     x0, DAIF                            // Pickup DAIF
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    STP     x29, x30, [sp, #-16]!               // Save x29 (frame pointer), x30 (link register)
+    STP     x19, x20, [sp, #-16]!               // Save x19, x20
+    STP     x21, x22, [sp, #-16]!               // Save x21, x22
+    STP     x23, x24, [sp, #-16]!               // Save x23, x24
+    STP     x25, x26, [sp, #-16]!               // Save x25, x26
+    STP     x27, x28, [sp, #-16]!               // Save x27, x28
+    LDR     x5, =_tx_thread_current_ptr         // Pickup address of current ptr
+    LDR     x6, [x5, #0]                        // Pickup current thread pointer
+
+#ifdef ENABLE_ARM_FP
+    LDR     w7, [x6, #248]                      // Pickup FP enable flag
+    CMP     w7, #0                              // Is FP enabled?
+    BEQ     _skip_fp_save                       // No, skip FP save
+    STP     q8,  q9,  [sp, #-32]!               // Save q8, q9
+    STP     q10, q11, [sp, #-32]!               // Save q10, q11
+    STP     q12, q13, [sp, #-32]!               // Save q12, q13
+    STP     q14, q15, [sp, #-32]!               // Save q14, q15
+    MRS     x2, FPSR                            // Pickup FPSR
+    MRS     x3, FPCR                            // Pickup FPCR
+    STP     x2, x3, [sp, #-16]!                 // Save FPSR, FPCR
+_skip_fp_save:
+#endif
+
+    MOV     x1, #0                              // Clear x1
+    STP     x0, x1, [sp, #-16]!                 // Save DAIF and clear value for ELR_EK1
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread exit function to indicate the thread is no longer executing.  */
+
+    MOV     x19, x5                             // Save x5
+    MOV     x20, x6                             // Save x6
+    BL      _tx_execution_thread_exit           // Call the thread exit function
+    MOV     x5, x19                             // Restore x5
+    MOV     x6, x20                             // Restore x6
+#endif
+
+    LDR     x2, =_tx_timer_time_slice           // Pickup address of time slice
+    LDR     w1, [x2, #0]                        // Pickup current time slice
+
+    /* Save current stack and switch to system stack.  */
+    // _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+    // sp = _tx_thread_system_stack_ptr;
+
+    MOV     x4, sp                              //
+    STR     x4, [x6, #8]                        // Save thread stack pointer
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, #0]                        // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+    /* Determine if the time-slice is active.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    MOV     x4, #0                              // Build clear value
+    CMP     w1, #0                              // Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save the time-slice
+
+       /* Save the current remaining time-slice.  */
+       // _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+       // _tx_timer_time_slice =  0;
+
+    STR     w4, [x2, #0]                        // Clear time-slice
+    STR     w1, [x6, #36]                       // Store current time-slice
+
+    // }
+__tx_thread_dont_save_ts:
+
+    /* Clear the current thread pointer.  */
+    // _tx_thread_current_ptr =  TX_NULL;
+
+    STR     x4, [x5, #0]                        // Clear current thread pointer
+
+    B       _tx_thread_schedule                 // Jump to scheduler!
+
+// }
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..7127755d
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S
@@ -0,0 +1,228 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_timer_interrupt                               Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function processes the hardware timer interrupt.  This         */
+/*    processing includes incrementing the system clock and checking for  */
+/*    time slice and/or timer expiration.  If either is found, the        */
+/*    interrupt context save/restore functions are called along with the  */
+/*    expiration functions.                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_timer_expiration_process          Timer expiration processing   */
+/*    _tx_thread_time_slice                 Time slice interrupted thread */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    interrupt vector                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_timer_interrupt(VOID)
+// {
+    .global _tx_timer_interrupt
+    .type   _tx_timer_interrupt, @function
+_tx_timer_interrupt:
+
+    /* Upon entry to this routine, it is assumed that context save has already
+       been called, and therefore the compiler scratch registers are available
+       for use.  */
+
+    /* Increment the system clock.  */
+    // _tx_timer_system_clock++;
+
+    LDR     x1, =_tx_timer_system_clock         // Pickup address of system clock
+    LDR     w0, [x1, #0]                        // Pickup system clock
+    ADD     w0, w0, #1                          // Increment system clock
+    STR     w0, [x1, #0]                        // Store new system clock
+
+    /* Test for time-slice expiration.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    LDR     x3, =_tx_timer_time_slice           // Pickup address of time-slice 
+    LDR     w2, [x3, #0]                        // Pickup time-slice
+    CMP     w2, #0                              // Is it non-active?
+    BEQ     __tx_timer_no_time_slice            // Yes, skip time-slice processing
+
+       /* Decrement the time_slice.  */
+       // _tx_timer_time_slice--;
+
+    SUB     w2, w2, #1                          // Decrement the time-slice
+    STR     w2, [x3, #0]                        // Store new time-slice value
+
+       /* Check for expiration.  */
+       // if (__tx_timer_time_slice == 0)
+
+    CMP     w2, #0                              // Has it expired?
+    BNE     __tx_timer_no_time_slice            // No, skip expiration processing
+
+       /* Set the time-slice expired flag.  */
+       // _tx_timer_expired_time_slice =  TX_TRUE;
+
+    LDR     x3, =_tx_timer_expired_time_slice   // Pickup address of expired flag
+    MOV     w0, #1                              // Build expired value
+    STR     w0, [x3, #0]                        // Set time-slice expiration flag
+
+    /* } */
+
+__tx_timer_no_time_slice:
+
+    /* Test for timer expiration.  */
+    // if (*_tx_timer_current_ptr)
+    // {
+
+    LDR     x1, =_tx_timer_current_ptr          // Pickup current timer pointer addr
+    LDR     x0, [x1, #0]                        // Pickup current timer
+    LDR     x2, [x0, #0]                        // Pickup timer list entry
+    CMP     x2, #0                              // Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 // No, just increment the timer
+
+        /* Set expiration flag.  */
+        // _tx_timer_expired =  TX_TRUE;
+
+    LDR     x3, =_tx_timer_expired              // Pickup expiration flag address
+    MOV     w2, #1                              // Build expired value
+    STR     w2, [x3, #0]                        // Set expired flag
+    B       __tx_timer_done                     // Finished timer processing
+
+    // }
+    // else
+    // {
+__tx_timer_no_timer:
+
+        /* No timer expired, increment the timer pointer.  */
+        // _tx_timer_current_ptr++;
+
+    ADD     x0, x0, #8                          // Move to next timer
+
+        /* Check for wrap-around.  */
+        // if (_tx_timer_current_ptr == _tx_timer_list_end)
+
+    LDR     x3, =_tx_timer_list_end             // Pickup addr of timer list end
+    LDR     x2, [x3, #0]                        // Pickup list end
+    CMP     x0, x2                              // Are we at list end?
+    BNE     __tx_timer_skip_wrap                // No, skip wrap-around logic
+
+            /* Wrap to beginning of list.  */
+            // _tx_timer_current_ptr =  _tx_timer_list_start;
+
+    LDR     x3, =_tx_timer_list_start           // Pickup addr of timer list start
+    LDR     x0, [x3, #0]                        // Set current pointer to list start
+
+__tx_timer_skip_wrap:
+
+    STR     x0, [x1, #0]                        // Store new current timer pointer
+    // }
+
+__tx_timer_done:
+
+
+    /* See if anything has expired.  */
+    // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+    // {
+
+    LDR     x3, =_tx_timer_expired_time_slice   // Pickup addr of expired flag
+    LDR     w2, [x3, #0]                        // Pickup time-slice expired flag
+    CMP     w2, #0                              // Did a time-slice expire?
+    BNE     __tx_something_expired              // If non-zero, time-slice expired
+    LDR     x1, =_tx_timer_expired              // Pickup addr of other expired flag
+    LDR     w0, [x1, #0]                        // Pickup timer expired flag
+    CMP     w0, #0                              // Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          // No, nothing expired
+
+__tx_something_expired:
+
+
+    STP     x29, x30, [sp, #-16]!               // Save x29 (frame pointer), x30 (link register)
+
+    /* Did a timer expire?  */
+    // if (_tx_timer_expired)
+    // {
+
+    LDR     x1, =_tx_timer_expired              // Pickup addr of expired flag
+    LDR     w0, [x1, #0]                        // Pickup timer expired flag
+    CMP     w0, #0                              // Check for timer expiration
+    BEQ     __tx_timer_dont_activate            // If not set, skip timer activation
+
+        /* Process timer expiration.  */
+        // _tx_timer_expiration_process();
+
+    BL      _tx_timer_expiration_process        // Call the timer expiration handling routine
+
+    /* }  */
+__tx_timer_dont_activate:
+
+    /* Did time slice expire?  */
+    // if (_tx_timer_expired_time_slice)
+    // {
+
+    LDR     x3, =_tx_timer_expired_time_slice   // Pickup addr of time-slice expired 
+    LDR     w2, [x3, #0]                        // Pickup the actual flag
+    CMP     w2, #0                              // See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        // No, skip time-slice processing
+
+        /* Time slice interrupted thread.  */
+        // _tx_thread_time_slice();
+
+    BL      _tx_thread_time_slice               // Call time-slice processing
+
+    // }
+
+__tx_timer_not_ts_expiration:
+
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    // }
+
+__tx_timer_nothing_expired:
+
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c
new file mode 100644
index 00000000..39dccb14
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c
@@ -0,0 +1,85 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "txm_module.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_port_dispatch                 Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function dispatches the module's kernel request based upon the */
+/*    ID and parameters specified in the request.                         */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Module pointer                    */
+/*    kernel_request                    Module's kernel request           */
+/*    param_0                           First parameter                   */
+/*    param_1                           Second parameter                  */
+/*    param_2                           Third parameter                   */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    Port-specific ThreadX API Calls                                     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _txm_module_manager_kernel_dispatch                                 */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)
+{
+
+ALIGN_TYPE return_value = TX_NOT_AVAILABLE;
+
+    switch(kernel_request)
+    {
+        default:
+        {
+            /* Unhandled kernel request, return an error!  */
+            break;
+        }
+    }
+    
+    return(return_value);
+}
diff --git a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S
new file mode 100644
index 00000000..74d712e1
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S
@@ -0,0 +1,163 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_thread_stack_build            Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread             */
+/*    function_ptr                          Pointer to entry function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
+// {
+    .global  _txm_module_manager_thread_stack_build
+    .type    _txm_module_manager_thread_stack_build, @function
+_txm_module_manager_thread_stack_build:
+
+
+    /* Build an interrupt frame.  On Cortex-A35 it should look like this:
+
+       Stack Top:      SSPR        Initial SSPR
+                       ELR         Point of interrupt
+                       x28         Initial value for x28
+                       not used    Not used
+                       x26         Initial value for x26
+                       x27         Initial value for x27
+                       x24         Initial value for x24
+                       x25         Initial value for x25
+                       x22         Initial value for x22
+                       x23         Initial value for x23
+                       x20         Initial value for x20
+                       x21         Initial value for x21
+                       x18         Initial value for x18
+                       x19         Initial value for x19
+                       x16         Initial value for x16
+                       x17         Initial value for x17
+                       x14         Initial value for x14
+                       x15         Initial value for x15
+                       x12         Initial value for x12
+                       x13         Initial value for x13
+                       x10         Initial value for x10
+                       x11         Initial value for x11
+                       x8          Initial value for x8
+                       x9          Initial value for x9
+                       x6          Initial value for x6
+                       x7          Initial value for x7
+                       x4          Initial value for x4
+                       x5          Initial value for x5
+                       x2          Initial value for x2
+                       x3          Initial value for x3
+                       x0          Initial value for x0
+                       x1          Initial value for x1
+                       x29         Initial value for x29 (frame pointer)
+                       x30         Initial value for x30 (link register)
+                       0           For stack backtracing
+
+       Stack Bottom: (higher memory address)
+    */
+
+    LDR     x4, [x0, #24]                       // Pickup end of stack area
+    BIC     x4, x4, #0xF                        // Ensure 16-byte alignment
+
+    LDR     x5, [x0, #8]                        // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
+                                                //   It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
+                                                //   function with the actual, initial stack pointer.
+
+    /* Actually build the stack frame.  */
+
+    MOV     x2, #0                              // Build clear value
+    MOV     x3, #0                              //
+
+    STP     x2, x3, [x4, #-16]!                 // Set backtrace to 0
+    STP     x2, x3, [x4, #-16]!                 // Set initial x29, x30
+    STP     x0, x5, [x4, #-16]!                 // Set initial x0, x1
+                                                //   x0->x0 is the thread control block pointer
+                                                //   x5->x1 is the thread entry info pointer
+    STP     x2, x3, [x4, #-16]!                 // Set initial x2, x3
+    STP     x2, x3, [x4, #-16]!                 // Set initial x4, x5
+    STP     x2, x3, [x4, #-16]!                 // Set initial x6, x7
+    STP     x2, x3, [x4, #-16]!                 // Set initial x8, x9
+    STP     x2, x3, [x4, #-16]!                 // Set initial x10, x11
+    STP     x2, x3, [x4, #-16]!                 // Set initial x12, x13
+    STP     x2, x3, [x4, #-16]!                 // Set initial x14, x15
+    STP     x2, x3, [x4, #-16]!                 // Set initial x16, x17
+    STP     x2, x3, [x4, #-16]!                 // Set initial x18, x19
+    STP     x2, x3, [x4, #-16]!                 // Set initial x20, x21
+    STP     x2, x3, [x4, #-16]!                 // Set initial x22, x23
+    STP     x2, x3, [x4, #-16]!                 // Set initial x24, x25
+    STP     x2, x3, [x4, #-16]!                 // Set initial x26, x27
+    STP     x2, x3, [x4, #-16]!                 // Set initial x28
+#ifdef EL1
+    MOV     x2, #0x4                            // Build initial SPSR  (EL1)
+#else
+#ifdef EL2
+    MOV     x2, #0x8                            // Build initial SPSR  (EL2)
+#else
+    MOV     x2, #0xC                            // Build initial SPSR  (EL3)
+#endif
+#endif
+    MOV     x3, x1                              // Build initial ELR
+    STP     x2, x3, [x4, #-16]!                 // Set initial SPSR & ELR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  x2;  */
+
+    STR     x4, [x0, #8]                        // Save stack pointer in thread's
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35/ac6/readme_threadx.txt b/ports_module/cortex_a35/ac6/readme_threadx.txt
new file mode 100644
index 00000000..e8c6ce96
--- /dev/null
+++ b/ports_module/cortex_a35/ac6/readme_threadx.txt
@@ -0,0 +1,266 @@
+                     Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 
+
+                           Using the ARM Compiler 6 & DS
+
+1. Import the ThreadX Modules Projects
+
+In order to build the ThreadX library and the ThreadX demonstration, first import 
+the 'tx', 'txm', 'sample_threadx', 'sample_threadx_module' and
+'sample_thread_module_manager' projects (located in the "example_build" directory) 
+into your DS workspace.
+
+
+2.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy; simply select the Eclipse project file 
+"tx" and then select the build button. You should now observe the compilation 
+and assembly of the ThreadX library. This project build produces the ThreadX 
+library file tx.a. To bild the ThreadX Module library select the project "txm"
+and select the build button to produce the file txm.a.
+
+
+3.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the DS debugger on the
+Base_A35x1 Bare Metal simulator.
+
+Building the basic ThreadX demonstration is easy; simply select the sample_threadx project, and
+select the build button. Next, in the sample_threadx project, right-click on the
+sample_threadx.launch file and select 'Debug As -> sample_threadx'.  The debugger is
+setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load
+the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute
+the ThreadX demonstration.
+
+The ThreadX Modules demonstration is composed of a module and a module manager.
+First build the ThreadX sample module project sample_thread_module by selecting it and
+clicking the build button. Next built the ThreadX Module Manager sample by selecting
+sample_threadx_module_manager and clicking the build button.
+
+To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, 
+right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'.  
+The debugger is setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load
+the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute
+the ThreadX demonstration.
+
+
+4.  System Initialization
+
+The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label 
+"start64". This is defined within the AC6 compiler's startup code. In addition, 
+this is where all static and global pre-set C variable initialization processing 
+takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for determining the 
+first available RAM address for use by the application, which is supplied as the 
+sole input parameter to your application definition function, tx_application_define.
+
+
+5.  Register Usage and Stack Frames
+
+The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers 
+for each function. All other registers used by a C function must be preserved 
+by the function. ThreadX takes advantage of this in situations where a context 
+switch happens as a result of making a ThreadX service call (which is itself a 
+C function). In such cases, the saved context of a thread is only the 
+non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+FP not enabled and TX_THREAD.tx_thread_fp_enable == 0:
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x000                  SPSR                        DAIF
+     0x008                  ELR                         0
+     0x010                  x28                         x27
+     0x018                  reserved                    x28
+     0x020                  x26                         x25
+     0x028                  x27                         x26
+     0x030                  x24                         x23
+     0x038                  x25                         x24
+     0x040                  x22                         x21
+     0x048                  x23                         x22
+     0x050                  x20                         x19
+     0x058                  x21                         x20
+     0x060                  x18                         x29
+     0x068                  x19                         x30
+     0x070                  x16
+     0x078                  x17
+     0x080                  x14
+     0x088                  x15
+     0x090                  x12
+     0x098                  x13
+     0x0A0                  x10
+     0x0A8                  x11
+     0x0B0                  x8
+     0x0B8                  x9
+     0x0C0                  x6
+     0x0C8                  x7
+     0x0D0                  x4
+     0x0D8                  x5
+     0x0E0                  x2
+     0x0E8                  x3
+     0x0F0                  x0
+     0x0F8                  x1
+     0x100                  x29
+     0x108                  x30 
+
+
+FP enabled and TX_THREAD.tx_thread_fp_enable == 1:
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x000                  SPSR                        DAIF
+     0x008                  ELR                         0
+     0x010                  FPSR                        FPSR
+     0x018                  FPCR                        FPCR
+     0x020                  q30                         q14
+     0x030                  q31                         q15
+     0x040                  q28                         q12
+     0x050                  q29                         q13
+     0x060                  q26                         q10
+     0x070                  q27                         q11
+     0x080                  q24                         q8
+     0x090                  q25                         q9
+     0x0A0                  q22                         x27
+     0x0A8                                              x28
+     0x0B0                  q23                         x25
+     0x0B8                                              x26
+     0x0C0                  q20                         x23
+     0x0C8                                              x24
+     0x0D0                  q21                         x21
+     0x0D8                                              x22
+     0x0E0                  q18                         x19
+     0x0E8                                              x20
+     0x0F0                  q19                         x29
+     0x0F8                                              x30
+     0x100                  q16
+     0x110                  q17
+     0x120                  q14
+     0x130                  q15
+     0x140                  q12
+     0x150                  q13
+     0x160                  q10
+     0x170                  q11
+     0x180                  q8
+     0x190                  q9
+     0x1A0                  q6
+     0x1B0                  q7
+     0x1C0                  q4
+     0x1D0                  q5
+     0x1E0                  q2
+     0x1F0                  q3
+     0x200                  q0
+     0x210                  q1
+     0x220                  x28
+     0x228                  reserved
+     0x230                  x26
+     0x238                  x27
+     0x240                  x24
+     0x248                  x25
+     0x250                  x22
+     0x258                  x23
+     0x260                  x20
+     0x268                  x21
+     0x270                  x18
+     0x278                  x19
+     0x280                  x16
+     0x288                  x17
+     0x290                  x14
+     0x298                  x15
+     0x2A0                  x12
+     0x2A8                  x13
+     0x2B0                  x10
+     0x2B8                  x11
+     0x2C0                  x8
+     0x2C8                  x9
+     0x2D0                  x6
+     0x2D8                  x7
+     0x2E0                  x4
+     0x2E8                  x5
+     0x2F0                  x2
+     0x2F8                  x3
+     0x300                  x0
+     0x308                  x1
+     0x310                  x29
+     0x318                  x30
+
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler optimizations. 
+This makes it easy to debug because you can trace or set breakpoints inside of 
+ThreadX itself. Of course, this costs some performance. To make it run faster, 
+you can change the project settings to the desired compiler optimization level.
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-A35
+targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following
+format:
+
+        .global irq_handler
+irq_handler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+
+  /* Your ISR call goes here!  */
+  BL       application_isr_handler
+
+  B        _tx_thread_context_restore
+
+By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 
+and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined.
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, 
+timeouts, and application timers. Without such a timer interrupt source, these services 
+are not functional. However, all other ThreadX services are operational without a 
+periodic timer source.
+
+
+9. ARM FP Support
+
+By default, FP support is disabled for each thread. If saving the context of the FP registers
+is needed, the following API call must be made from the context of the application thread - before 
+the FP usage:
+
+void    tx_thread_fp_enable(void);
+
+After this API is called in the application, FP registers will be saved/restored for this thread if it
+is preempted via an interrupt. All other suspension of the this thread will not require the FP registers
+to be saved/restored.
+
+To disable FP register context saving, simply call the following API:
+
+void    tx_thread_fp_disable(void);
+
+
+10.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+12-31-2020  Initial ThreadX 6.1 version for Cortex-A35 using AC6 tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject
new file mode 100644
index 00000000..7eb75c64
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject
@@ -0,0 +1,252 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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+            </storageModule>
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+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.857388488" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.703057645" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.494258017" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.2016749997" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1332640632" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1069857726" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.1027551600" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/.project b/ports_module/cortex_a35/gnu/example_build/sample_threadx/.project
new file mode 100644
index 00000000..a1b15572
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/.project
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h
new file mode 100644
index 00000000..23bc7fd8
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h
@@ -0,0 +1,561 @@
+/*
+ * GICv3.h - data types and function prototypes for GICv3 utility routines
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_h
+#define GICV3_h
+
+#include <stdint.h>
+
+/*
+ * extra flags for GICD enable
+ */
+typedef enum
+{
+    gicdctlr_EnableGrp0 = (1 << 0),
+    gicdctlr_EnableGrp1NS = (1 << 1),
+    gicdctlr_EnableGrp1A = (1 << 1),
+    gicdctlr_EnableGrp1S = (1 << 2),
+    gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
+    gicdctlr_ARE_S = (1 << 4),	/* Enable Secure state affinity routing */
+    gicdctlr_ARE_NS = (1 << 5),	/* Enable Non-Secure state affinity routing */
+    gicdctlr_DS = (1 << 6),	/* Disable Security support */
+    gicdctlr_E1NWF = (1 << 7)	/* Enable "1-of-N" wakeup model */
+} GICDCTLRFlags_t;
+
+/*
+ * modes for SPI routing
+ */
+typedef enum
+{
+    gicdirouter_ModeSpecific = 0,
+    gicdirouter_ModeAny = (1 << 31)
+} GICDIROUTERBits_t;
+
+typedef enum
+{
+    gicdicfgr_Level = 0,
+    gicdicfgr_Edge = (1 << 1)
+} GICDICFGRBits_t;
+
+typedef enum
+{
+    gicigroupr_G0S = 0,
+    gicigroupr_G1NS = (1 << 0),
+    gicigroupr_G1S = (1 << 2)
+} GICIGROUPRBits_t;
+
+typedef enum
+{
+    gicrwaker_ProcessorSleep = (1 << 1),
+    gicrwaker_ChildrenAsleep = (1 << 2)
+} GICRWAKERBits_t;
+
+/**********************************************************************/
+
+/*
+ * Utility macros & functions
+ */
+#define RANGE_LIMIT(x)		((sizeof(x) / sizeof((x)[0])) - 1)
+
+static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
+					 uint32_t aff1, uint32_t aff0)
+{
+    /*
+     * only need to cast aff3 to get type promotion for all affinities
+     */
+    return ((((uint64_t)aff3 & 0xff) << 32) |
+	    ((aff2 & 0xff) << 16) |
+	    ((aff1 & 0xff) << 8) | aff0);
+}
+
+/**********************************************************************/
+
+/*
+ * GIC Distributor Function Prototypes
+ */
+
+/*
+ * ConfigGICD - configure GIC Distributor prior to enabling it
+ *
+ * Inputs:
+ *
+ *  control - control flags
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void ConfigGICD(GICDCTLRFlags_t flags);
+
+/*
+ * EnableGICD - top-level enable for GIC Distributor
+ *
+ * Inputs:
+ *
+ *  flags - new control flags to set
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void EnableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * DisableGICD - top-level disable for GIC Distributor
+ *
+ * Inputs
+ *
+ *  flags - control flags to clear
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void DisableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * SyncAREinGICD - synchronise GICD Address Routing Enable bits
+ *
+ * Inputs
+ *
+ *  flags - absolute flag bits to set in GIC Distributor
+ *
+ *  dosync - flag whether to wait for ARE bits to match passed
+ *      flag field (dosync = true), or whether to set absolute
+ *      flag bits (dosync = false)
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ * This function is used to resolve a race in an MP system whereby secondary
+ * CPUs cannot reliably program all Redistributor registers until the
+ * primary CPU has enabled Address Routing. The primary CPU will call this
+ * function with dosync = false, while the secondaries will call it with
+ * dosync = true.
+ */
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
+
+/*
+ * EnableSPI - enable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnableSPI(uint32_t id);
+
+/*
+ * DisableSPI - disable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisableSPI(uint32_t id);
+
+/*
+ * SetSPIPriority - configure the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetSPIPriority(uint32_t id, uint32_t priority);
+
+/*
+ * GetSPIPriority - determine the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  interrupt priority in the range 0 - 0xff
+ */
+uint32_t GetSPIPriority(uint32_t id);
+
+/*
+ * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  affinity - prepacked "dotted quad" affinity routing. NOTE: use the
+ *      gicv3PackAffinity() helper routine to generate this input
+ *
+ *  mode - select routing mode (specific affinity, or any recipient)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
+
+/*
+ * GetSPIRoute - read ARE-enabled interrupt routing information
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  routing configuration
+ */
+uint64_t GetSPIRoute(uint32_t id);
+
+/*
+ * SetSPITarget - configure the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ *  target - 8-bit target bitmap
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPITarget(uint32_t id, uint32_t target);
+
+/*
+ * GetSPITarget - read the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *  8-bit target bitmap
+ */
+uint32_t GetSPITarget(uint32_t id);
+
+/*
+ * ConfigureSPI - setup an interrupt as edge- or level-triggered
+ *
+ * Inputs
+ *
+ *   id - interrupt identifier
+ *
+ *   config - desired configuration
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
+
+/*
+ * SetSPIPending - mark an interrupt as pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetSPIPending(uint32_t id);
+
+/*
+ * ClearSPIPending - mark an interrupt as not pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearSPIPending(uint32_t id);
+
+/*
+ * GetSPIPending - query whether an interrupt is pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetSPIPending(uint32_t id);
+
+/*
+ * SetSPISecurity - mark a shared peripheral interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityBlock - mark a block of 32 shared peripheral
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  block - which block to mark (e.g. 1 = Ints 32-63)
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityAll - mark all shared peripheral interrupts
+ *     as security <group>
+ *
+ * Inputs:
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityAll(GICIGROUPRBits_t group);
+
+/**********************************************************************/
+
+/*
+ * GIC Re-Distributor Function Prototypes
+ *
+ * The model for calling Redistributor functions is that, rather than
+ * identifying the target redistributor with every function call, the
+ * SelectRedistributor() function is used to identify which redistributor
+ * is to be used for all functions until a different redistributor is
+ * explicitly selected
+ */
+
+/*
+ * WakeupGICR - wake up a Redistributor
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to wakeup
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void WakeupGICR(uint32_t gicr);
+
+/*
+ * EnablePrivateInt - enable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * DisablePrivateInt - disable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
+
+/*
+ * GetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *   Int priority
+ */
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
+
+#endif /* ndef GICV3_h */
+
+/* EOF GICv3.h */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h
new file mode 100644
index 00000000..0928d14c
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h
@@ -0,0 +1,113 @@
+//
+// Aliases for GICv3 registers
+//
+// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef GICV3_ALIASES_H
+#define GICV3_ALIASES_H
+
+#ifndef __clang__
+
+/*
+ * Mapping of MSR and MRS to physical and virtual CPU interface registers
+ *
+ * Arm Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3.0 and version 4.0
+ * Table 8-5
+ */
+#define ICC_AP0R0_EL1       S3_0_C12_C8_4
+#define ICC_AP0R1_EL1       S3_0_C12_C8_5
+#define ICC_AP0R2_EL1       S3_0_C12_C8_6
+#define ICC_AP0R3_EL1       S3_0_C12_C8_7
+
+#define ICC_AP1R0_EL1       S3_0_C12_C9_0
+#define ICC_AP1R1_EL1       S3_0_C12_C9_1
+#define ICC_AP1R2_EL1       S3_0_C12_C9_2
+#define ICC_AP1R3_EL1       S3_0_C12_C9_3
+
+#define ICC_ASGI1R_EL1      S3_0_C12_C11_6
+
+#define ICC_BPR0_EL1        S3_0_C12_C8_3
+#define ICC_BPR1_EL1        S3_0_C12_C12_3
+
+#define ICC_CTLR_EL1        S3_0_C12_C12_4
+#define ICC_CTLR_EL3        S3_6_C12_C12_4
+
+#define ICC_DIR_EL1         S3_0_C12_C11_1
+
+#define ICC_EOIR0_EL1       S3_0_C12_C8_1
+#define ICC_EOIR1_EL1       S3_0_C12_C12_1
+
+#define ICC_HPPIR0_EL1      S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1      S3_0_C12_C12_2
+
+#define ICC_IAR0_EL1        S3_0_C12_C8_0
+#define ICC_IAR1_EL1        S3_0_C12_C12_0
+
+#define ICC_IGRPEN0_EL1     S3_0_C12_C12_6
+#define ICC_IGRPEN1_EL1     S3_0_C12_C12_7
+#define ICC_IGRPEN1_EL3     S3_6_C12_C12_7
+
+#define ICC_PMR_EL1         S3_0_C4_C6_0
+#define ICC_RPR_EL1         S3_0_C12_C11_3
+
+#define ICC_SGI0R_EL1       S3_0_C12_C11_7
+#define ICC_SGI1R_EL1       S3_0_C12_C11_5
+
+#define ICC_SRE_EL1         S3_0_C12_C12_5
+#define ICC_SRE_EL2         S3_4_C12_C9_5
+#define ICC_SRE_EL3         S3_6_C12_C12_5
+
+/*
+ * Mapping of MSR and MRS to virtual interface control registers
+ *
+ * Arm Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3.0 and version 4.0
+ * Table 8-6
+ */
+#define ICH_AP0R0_EL2       S3_4_C12_C8_0
+#define ICH_AP0R1_EL2       S3_4_C12_C8_1
+#define ICH_AP0R2_EL2       S3_4_C12_C8_2
+#define ICH_AP0R3_EL2       S3_4_C12_C8_3
+
+#define ICH_AP1R0_EL2       S3_4_C12_C9_0
+#define ICH_AP1R1_EL2       S3_4_C12_C9_1
+#define ICH_AP1R2_EL2       S3_4_C12_C9_2
+#define ICH_AP1R3_EL2       S3_4_C12_C9_3
+
+#define ICH_HCR_EL2         S3_4_C12_C11_0
+
+#define ICH_VTR_EL2         S3_4_C12_C11_1
+
+#define ICH_MISR_EL2        S3_4_C12_C11_2
+
+#define ICH_EISR_EL2        S3_4_C12_C11_3
+
+#define ICH_ELRSR_EL2       S3_4_C12_C11_5
+
+#define ICH_VMCR_EL2        S3_4_C12_C11_7
+
+#define ICH_LR0_EL2         S3_4_C12_C12_0
+#define ICH_LR1_EL2         S3_4_C12_C12_1
+#define ICH_LR2_EL2         S3_4_C12_C12_2
+#define ICH_LR3_EL2         S3_4_C12_C12_3
+#define ICH_LR4_EL2         S3_4_C12_C12_4
+#define ICH_LR5_EL2         S3_4_C12_C12_5
+#define ICH_LR6_EL2         S3_4_C12_C12_6
+#define ICH_LR7_EL2         S3_4_C12_C12_7
+#define ICH_LR8_EL2         S3_4_C12_C13_0
+#define ICH_LR9_EL2         S3_4_C12_C13_1
+#define ICH_LR10_EL2        S3_4_C12_C13_2
+#define ICH_LR11_EL2        S3_4_C12_C13_3
+#define ICH_LR12_EL2        S3_4_C12_C13_4
+#define ICH_LR13_EL2        S3_4_C12_C13_5
+#define ICH_LR14_EL2        S3_4_C12_C13_6
+#define ICH_LR15_EL2        S3_4_C12_C13_7
+
+#endif /* not __clang__ */
+
+#endif /* GICV3_ALIASES */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h
new file mode 100644
index 00000000..2b8a2d3e
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h
@@ -0,0 +1,254 @@
+/*
+ * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_gicc_h
+#define GICV3_gicc_h
+
+#include "GICv3_aliases.h"
+
+#define stringify_no_expansion(x) #x
+#define stringify(x) stringify_no_expansion(x)
+
+/**********************************************************************/
+
+typedef enum
+{
+    sreSRE = (1 << 0),
+    sreDFB = (1 << 1),
+    sreDIB = (1 << 2),
+    sreEnable = (1 << 3)
+} ICC_SREBits_t;
+
+static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL2(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    igrpEnable = (1 << 0),
+    igrpEnableGrp1NS = (1 << 0),
+    igrpEnableGrp1S = (1 << 2)
+} ICC_IGRPBits_t;
+
+static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    ctlrCBPR = (1 << 0),
+    ctlrCBPR_EL1S = (1 << 0),
+    ctlrEOImode = (1 << 1),
+    ctlrCBPR_EL1NS = (1 << 1),
+    ctlrEOImode_EL3 = (1 << 2),
+    ctlrEOImode_EL1S = (1 << 3),
+    ctlrEOImode_EL1NS = (1 << 4),
+    ctlrRM = (1 << 5),
+    ctlrPMHE = (1 << 6)
+} ICC_CTLRBits_t;
+
+static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
+{
+    asm("msr  "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
+{
+    asm("msr  "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+static inline uint64_t getICC_IAR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_IAR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_EOIR0(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_EOIR1(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_DIR(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_PMR(uint32_t priority)
+{
+    asm("msr  "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority));
+}
+
+static inline void setICC_BPR0(uint32_t binarypoint)
+{
+    asm("msr  "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline void setICC_BPR1(uint32_t binarypoint)
+{
+    asm("msr  "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline uint64_t getICC_BPR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_BPR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_RPR(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    sgirIRMTarget = 0,
+    sgirIRMAll = (1ull << 40)
+} ICC_SGIRBits_t;
+
+static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+#endif /* ndef GICV3_gicc_h */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c
new file mode 100644
index 00000000..2cf9e843
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c
@@ -0,0 +1,339 @@
+/*
+ * GICv3_gicd.c - generic driver code for GICv3 distributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include <stdint.h>
+
+#include "GICv3.h"
+
+typedef struct
+{
+        volatile uint32_t GICD_CTLR;              // +0x0000
+  const volatile uint32_t GICD_TYPER;             // +0x0004
+  const volatile uint32_t GICD_IIDR;              // +0x0008
+
+  const volatile uint32_t padding0;               // +0x000c
+
+        volatile uint32_t GICD_STATUSR;           // +0x0010
+
+  const volatile uint32_t padding1[3];            // +0x0014
+
+        volatile uint32_t IMP_DEF[8];             // +0x0020
+
+        volatile uint32_t GICD_SETSPI_NSR;        // +0x0040
+  const volatile uint32_t padding2;               // +0x0044
+        volatile uint32_t GICD_CLRSPI_NSR;        // +0x0048
+  const volatile uint32_t padding3;               // +0x004c
+        volatile uint32_t GICD_SETSPI_SR;         // +0x0050
+  const volatile uint32_t padding4;               // +0x0054
+        volatile uint32_t GICD_CLRSPI_SR;         // +0x0058
+
+  const volatile uint32_t padding5[3];            // +0x005c
+
+        volatile uint32_t GICD_SEIR;              // +0x0068
+
+  const volatile uint32_t padding6[5];            // +0x006c
+
+        volatile uint32_t GICD_IGROUPR[32];       // +0x0080
+
+        volatile uint32_t GICD_ISENABLER[32];     // +0x0100
+        volatile uint32_t GICD_ICENABLER[32];     // +0x0180
+        volatile uint32_t GICD_ISPENDR[32];       // +0x0200
+        volatile uint32_t GICD_ICPENDR[32];       // +0x0280
+        volatile uint32_t GICD_ISACTIVER[32];     // +0x0300
+        volatile uint32_t GICD_ICACTIVER[32];     // +0x0380
+
+        volatile uint8_t  GICD_IPRIORITYR[1024];  // +0x0400
+        volatile uint8_t  GICD_ITARGETSR[1024];   // +0x0800
+        volatile uint32_t GICD_ICFGR[64];         // +0x0c00
+        volatile uint32_t GICD_IGRPMODR[32];      // +0x0d00
+  const volatile uint32_t padding7[32];           // +0x0d80
+        volatile uint32_t GICD_NSACR[64];         // +0x0e00
+
+        volatile uint32_t GICD_SGIR;              // +0x0f00
+
+  const volatile uint32_t padding8[3];            // +0x0f04
+
+        volatile uint32_t GICD_CPENDSGIR[4];      // +0x0f10
+        volatile uint32_t GICD_SPENDSGIR[4];      // +0x0f20
+
+  const volatile uint32_t padding9[52];           // +0x0f30
+  const volatile uint32_t padding10[5120];        // +0x1000
+
+        volatile uint64_t GICD_IROUTER[1024];     // +0x6000
+} GICv3_distributor;
+
+/*
+ * use the scatter file to place GICD
+ */
+GICv3_distributor __attribute__((section(".gicd"))) gicd;
+
+void ConfigGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR = flags;
+}
+
+void EnableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR |= flags;
+}
+
+void DisableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR &= ~flags;
+}
+
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
+{
+    if (dosync)
+    {
+	const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
+	const uint32_t tval = flags & tmask;
+
+	while ((gicd.GICD_CTLR & tmask) != tval)
+	    continue;
+    }
+    else
+	gicd.GICD_CTLR = flags;
+}
+
+void EnableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ISENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void DisableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ICENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void SetSPIPriority(uint32_t id, uint32_t priority)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    gicd.GICD_IPRIORITYR[bank] = priority;
+}
+
+uint32_t GetSPIPriority(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
+}
+
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
+}
+
+uint64_t GetSPIRoute(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    return gicd.GICD_IROUTER[bank];
+}
+
+void SetSPITarget(uint32_t id, uint32_t target)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    gicd.GICD_ITARGETSR[bank] = target;
+}
+
+uint32_t GetSPITarget(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    /*
+     * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
+     * target bitmap per register
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
+}
+
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
+{
+    uint32_t bank, tmp;
+
+    /*
+     * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
+     * configuration per register
+     */
+    bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
+    config &= 3;
+
+    id = (id & 0xf) << 1;
+
+    tmp = gicd.GICD_ICFGR[bank];
+    tmp &= ~(3 << id);
+    tmp |= config << id;
+    gicd.GICD_ICFGR[bank] = tmp;
+}
+
+void SetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ISPENDR[bank] = 1 << id;
+}
+
+void ClearSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ICPENDR[bank] = 1 << id;
+}
+
+uint32_t GetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    return (gicd.GICD_ICPENDR[bank] >> id) & 1;
+}
+
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
+{
+    uint32_t bank, groupmod;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicd.GICD_IGROUPR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGROUPR[bank] &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicd.GICD_IGRPMODR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
+}
+
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
+{
+    uint32_t groupmod;
+    const uint32_t nbits = (sizeof group * 8) - 1;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
+
+    /*
+     * get each bit of group config duplicated over all 32-bits in a word
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicd.GICD_IGROUPR[block] = group;
+    gicd.GICD_IGRPMODR[block] = groupmod;
+}
+
+void SetSPISecurityAll(GICIGROUPRBits_t group)
+{
+    uint32_t block;
+
+    /*
+     * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
+     * want to iterate over all blocks excluding 0 (which are the
+     * SGI/PPI interrupts, and not relevant here)
+     */
+    for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
+	SetSPISecurityBlock(block, group);
+}
+
+/* EOF GICv3_gicd.c */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c
new file mode 100644
index 00000000..b0d22c40
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c
@@ -0,0 +1,308 @@
+/*
+ * GICv3_gicr.c - generic driver code for GICv3 redistributor
+ *
+ * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include "GICv3.h"
+
+/*
+ * physical LPI Redistributor register map
+ */
+typedef struct
+{
+        volatile uint32_t GICR_CTLR;             // +0x0000 - RW - Redistributor Control Register
+  const volatile uint32_t GICR_IIDR;             // +0x0004 - RO - Implementer Identification Register
+  const volatile uint32_t GICR_TYPER[2];         // +0x0008 - RO - Redistributor Type Register
+        volatile uint32_t GICR_STATUSR;          // +0x0010 - RW - Error Reporting Status Register, optional
+        volatile uint32_t GICR_WAKER;            // +0x0014 - RW - Redistributor Wake Register
+  const volatile uint32_t padding1[2];           // +0x0018 - RESERVED
+#ifndef USE_GIC600
+        volatile uint32_t IMPDEF1[8];            // +0x0020 - ?? - IMPLEMENTATION DEFINED
+#else
+        volatile uint32_t GICR_FCTLR;            // +0x0020 - RW - Function Control Register
+        volatile uint32_t GICR_PWRR;             // +0x0024 - RW - Power Management Control Register
+        volatile uint32_t GICR_CLASS;            // +0x0028 - RW - Class Register
+  const volatile uint32_t padding2[5];           // +0x002C - RESERVED
+#endif
+        volatile uint64_t GICR_SETLPIR;          // +0x0040 - WO - Set LPI Pending Register
+        volatile uint64_t GICR_CLRLPIR;          // +0x0048 - WO - Clear LPI Pending Register
+  const volatile uint32_t padding3[8];           // +0x0050 - RESERVED
+        volatile uint64_t GICR_PROPBASER;        // +0x0070 - RW - Redistributor Properties Base Address Register
+        volatile uint64_t GICR_PENDBASER;        // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
+  const volatile uint32_t padding4[8];           // +0x0080 - RESERVED
+        volatile uint64_t GICR_INVLPIR;          // +0x00A0 - WO - Redistributor Invalidate LPI Register
+  const volatile uint32_t padding5[2];           // +0x00A8 - RESERVED
+        volatile uint64_t GICR_INVALLR;          // +0x00B0 - WO - Redistributor Invalidate All Register
+  const volatile uint32_t padding6[2];           // +0x00B8 - RESERVED
+        volatile uint64_t GICR_SYNCR;            // +0x00C0 - RO - Redistributor Synchronize Register
+  const volatile uint32_t padding7[2];           // +0x00C8 - RESERVED
+  const volatile uint32_t padding8[12];          // +0x00D0 - RESERVED
+        volatile uint64_t IMPDEF2;               // +0x0100 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding9[2];           // +0x0108 - RESERVED
+        volatile uint64_t IMPDEF3;               // +0x0110 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding10[2];          // +0x0118 - RESERVED
+} GICv3_redistributor_RD;
+
+/*
+ * SGI and PPI Redistributor register map
+ */
+typedef struct
+{
+  const volatile uint32_t padding1[32];          // +0x0000 - RESERVED
+        volatile uint32_t GICR_IGROUPR0;         // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
+  const volatile uint32_t padding2[31];          // +0x0084 - RESERVED
+        volatile uint32_t GICR_ISENABLER;        // +0x0100 - RW - Interrupt Set-Enable Registers
+  const volatile uint32_t padding3[31];          // +0x0104 - RESERVED
+        volatile uint32_t GICR_ICENABLER;        // +0x0180 - RW - Interrupt Clear-Enable Registers
+  const volatile uint32_t padding4[31];          // +0x0184 - RESERVED
+        volatile uint32_t GICR_ISPENDR;          // +0x0200 - RW - Interrupt Set-Pending Registers
+  const volatile uint32_t padding5[31];          // +0x0204 - RESERVED
+        volatile uint32_t GICR_ICPENDR;          // +0x0280 - RW - Interrupt Clear-Pending Registers
+  const volatile uint32_t padding6[31];          // +0x0284 - RESERVED
+        volatile uint32_t GICR_ISACTIVER;        // +0x0300 - RW - Interrupt Set-Active Register
+  const volatile uint32_t padding7[31];          // +0x0304 - RESERVED
+        volatile uint32_t GICR_ICACTIVER;        // +0x0380 - RW - Interrupt Clear-Active Register
+  const volatile uint32_t padding8[31];          // +0x0184 - RESERVED
+        volatile uint8_t  GICR_IPRIORITYR[32];   // +0x0400 - RW - Interrupt Priority Registers
+  const volatile uint32_t padding9[504];         // +0x0420 - RESERVED
+        volatile uint32_t GICR_ICnoFGR[2];       // +0x0C00 - RW - Interrupt Configuration Registers
+  const volatile uint32_t padding10[62];         // +0x0C08 - RESERVED
+        volatile uint32_t GICR_IGRPMODR0;        // +0x0D00 - RW - ????
+  const volatile uint32_t padding11[63];         // +0x0D04 - RESERVED
+        volatile uint32_t GICR_NSACR;            // +0x0E00 - RW - Non-Secure Access Control Register
+} GICv3_redistributor_SGI;
+
+/*
+ * We have a multiplicity of GIC Redistributors; on the GIC-AEM and
+ * GIC-500 they are arranged as one 128KB region per redistributor: one
+ * 64KB page of GICR LPI registers, and one 64KB page of GICR Private
+ * Int registers
+ */
+typedef struct
+{
+    union
+    {
+        GICv3_redistributor_RD RD_base;
+        uint8_t padding[64 * 1024];
+    } RDblock;
+
+    union
+    {
+        GICv3_redistributor_SGI SGI_base;
+        uint8_t padding[64 * 1024];
+    } SGIblock;
+} GICv3_GICR;
+
+/*
+ * use the scatter file to place GIC Redistributor base address
+ *
+ * although this code doesn't know how many Redistributor banks
+ * a particular system will have, we declare gicrbase as an array
+ * to avoid unwanted compiler optimisations when calculating the
+ * base of a particular Redistributor bank
+ */
+static const GICv3_GICR gicrbase[2] __attribute__((section (".gicr")));
+
+/**********************************************************************/
+
+/*
+ * utility functions to calculate base of a particular
+ * Redistributor bank
+ */
+
+static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
+{
+    GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
+
+    return &((arraybase + gicr)->RDblock.RD_base);
+}
+
+static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
+{
+    GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
+
+    return &(arraybase[gicr].SGIblock.SGI_base);
+}
+
+/**********************************************************************/
+
+// This function walks a block of RDs to find one with the matching affinity
+uint32_t GetGICR(uint32_t affinity)
+{
+  GICv3_redistributor_RD* gicr;
+  uint32_t index = 0;
+
+  do
+  {
+    gicr = getgicrRD(index);
+    if (gicr->GICR_TYPER[1] == affinity)
+       return index;
+
+    index++;
+  }
+  while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block
+
+  return 0xFFFFFFFF; // return -1 to signal not RD found
+}
+
+void WakeupGICR(uint32_t gicr)
+{
+    GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
+#ifdef USE_GIC600
+    //Power up Re-distributor for GIC-600
+    gicrRD->GICR_PWRR = 0x2;
+#endif
+
+    /*
+     * step 1 - ensure GICR_WAKER.ProcessorSleep is off
+     */
+    gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
+
+    /*
+     * step 2 - wait for children asleep to be cleared
+     */
+    while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
+        continue;
+
+    /*
+     * OK, GICR is go
+     */
+    return;
+}
+
+void EnablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISENABLER = 1 << id;
+}
+
+void DisablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICENABLER = 1 << id;
+}
+
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    gicrSGI->GICR_IPRIORITYR[id] = priority;
+}
+
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
+}
+
+void SetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISPENDR = 1 << id;
+}
+
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ICPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICPENDR = 1 << id;
+}
+
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
+}
+
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    uint32_t groupmod;
+
+    /*
+     * GICR_IGROUPR0 is one 32-bit register
+     */
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+        gicrSGI->GICR_IGROUPR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+        gicrSGI->GICR_IGRPMODR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
+}
+
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    const uint32_t nbits = (sizeof group * 8) - 1;
+    uint32_t groupmod;
+
+    /*
+     * get each bit of group config duplicated over all 32 bits
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicrSGI->GICR_IGROUPR0 = group;
+    gicrSGI->GICR_IGRPMODR0 = groupmod;
+}
+
+/* EOF GICv3_gicr.c */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S
new file mode 100644
index 00000000..e7f95aa7
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S
@@ -0,0 +1,133 @@
+//
+// Armv8-A AArch64 - Basic Mutex Example
+// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global _mutex_initialize
+    .global _mutex_acquire
+    .global _mutex_release
+
+//
+// These routines implement the mutex management functions required for running
+// the Arm C library in a multi-threaded environment.
+//
+// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
+//
+// **********************************************************************
+//
+
+    .type _mutex_initialize, "function"
+    .cfi_startproc
+_mutex_initialize:
+
+    //
+    // mark the mutex as unlocked
+    //
+    mov     w1, #0
+    str     w1, [x0]
+
+    //
+    // we are running multi-threaded, so set a non-zero return
+    // value (function prototype says use 1)
+    //
+    mov     w0, #1
+    ret
+    .cfi_endproc
+
+#if !defined(USE_LSE_ATOMIC)
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+
+    //
+    // send ourselves an event, so we don't stick on the wfe at the
+    // top of the loop
+    //
+    sevl
+
+    //
+    // wait until the mutex is available
+    //
+loop:
+    wfe
+    ldaxr   w1, [x0]
+    cbnz    w1, loop
+
+    //
+    // mutex is (at least, it was) available - try to claim it
+    //
+    mov     w1, #1
+    stxr    w2, w1, [x0]
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+
+    mov     w1, #0
+    stlr    w1, [x0]
+    ret
+    .cfi_endproc
+
+#else  // LSE version
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+    // This uses a "ticket lock".  The lock is stored as a 32-bit value: 
+    // - the upper 16-bits record the thread's ticket number ("take a ticket")
+    // - the lower 16-bits record the ticket being served    ("now serving")
+
+    // atomically load then increment the thread's ticket number ("take a ticket")
+    mov w3, #(1 << 16)
+    ldadda w3, w1, [x0]
+
+    // is the ticket now being served?
+    eor w2, w1, w1, ror #16
+    cbz w2, loop_exit
+
+    // no, so wait for the ticket to be served
+
+    // send a local event to avoid missing an unlock before the exclusive load
+    sevl
+
+loop:
+    wfe
+    ldaxrh  w3, [x0]
+    eor w2, w3, w1, lsr #16
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+loop_exit:
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+    mov     w1, #1
+    staddlh w1, [x0]
+    ret
+    .cfi_endproc
+#endif
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h
new file mode 100644
index 00000000..ec1a1d28
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h
@@ -0,0 +1,66 @@
+/*
+ * Armv8-A AArch64 - Basic Mutex Example
+ *
+ * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef MP_MUTEX_H
+#define MP_MUTEX_H
+
+/*
+ * The Arm C library calls-out to these functions to manage multithreading.
+ * They can also be called by user application code.
+ *
+ * Mutex type is specified by the Arm C library
+ *
+ * Declare function prototypes for libc mutex routines
+ */
+typedef signed int *mutex;
+
+/*
+ * int _mutex_initialize(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  0 - application is non-threaded
+ *  1 - application is threaded
+ *  The C library uses the return result to indicate whether it is being used in a multithreaded environment.
+ */
+int _mutex_initialize(mutex *m);
+
+/*
+ * void _mutex_acquire(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  <nothing>
+ *
+ * Side Effects
+ *  Routine does not return until the mutex has been claimed. A load-acquire
+ *  is used to guarantee that the mutex claim is properly ordered with
+ *  respect to any accesses to the resource protected by the mutex
+ */
+void _mutex_acquire(mutex *m);
+
+/*
+ * void _mutex_release(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  <nothing>
+ *
+ * Side Effects
+ *  A store-release is used to guarantee that the mutex release is properly
+ *  ordered with respect any accesses to the resource protected by the mutex
+ */
+void _mutex_release(mutex *m);
+
+#endif
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h
new file mode 100644
index 00000000..52c9a0fe
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h
@@ -0,0 +1,66 @@
+//
+// Private Peripheral Map for the v8 Architecture Envelope Model
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef PPM_AEM_H
+#define PPM_AEM_H
+
+//
+// Distributor layout
+//
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+//
+// CPU Interface layout
+//
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+
+#endif // PPM_AEM_H
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c
new file mode 100644
index 00000000..8898ff39
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c
@@ -0,0 +1,377 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+#include <stddef.h>
+
+#define DEMO_STACK_SIZE         2048
+#define DEMO_BYTE_POOL_SIZE     64000
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+UCHAR					memory_pool[DEMO_BYTE_POOL_SIZE];
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+void init_timer();
+
+/* Define main entry point.  */
+
+int main()
+{
+
+	/* Initialize timer for ThreadX.  */
+	init_timer();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+UCHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.launch b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.launch
new file mode 100644
index 00000000..5f96a35c
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.launch
@@ -0,0 +1,333 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+    <listAttribute key="7759977680573821445.viewid=2"/>
+    <mapAttribute key="7759977680573821445.viewid=2.ExpressionsData"/>
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+    <stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+    <stringAttribute key="ANDROID_APPLICATION" value=""/>
+    <stringAttribute key="ANDROID_APP_DIR" value=""/>
+    <stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+    <mapAttribute key="AverageDurationTracker">
+        <mapEntry key="*Fetching Data Model" value="242421"/>
+        <mapEntry key="*list global low level symbols" value="550637"/>
+        <mapEntry key="*loading memory from target" value="820184"/>
+        <mapEntry key="*loading values from target" value="3615698"/>
+        <mapEntry key="*trace" value="23145986"/>
+        <mapEntry key="*updating expressions" value="3262163"/>
+        <mapEntry key="*updating registers" value="44165495"/>
+        <mapEntry key="*updating variables" value="3437258"/>
+        <mapEntry key="Add Watchpoint" value="24597988"/>
+        <mapEntry key="AddEventObserver" value="1699715"/>
+        <mapEntry key="Evaluate" value="739734"/>
+        <mapEntry key="GlobalsLoaderCommand" value="154351059"/>
+        <mapEntry key="Retrieving globals list" value="179166850"/>
+        <mapEntry key="areCachesAvailable" value="446589"/>
+        <mapEntry key="backtrace" value="5112231"/>
+        <mapEntry key="break" value="5437771"/>
+        <mapEntry key="checking tracepoints" value="219920"/>
+        <mapEntry key="compute execution mode" value="210984"/>
+        <mapEntry key="continue" value="41080237"/>
+        <mapEntry key="core" value="6422300"/>
+        <mapEntry key="directory" value="1721303"/>
+        <mapEntry key="disable" value="1478680"/>
+        <mapEntry key="disassemble" value="29905864"/>
+        <mapEntry key="enable" value="1860234"/>
+        <mapEntry key="evaluate" value="2783965"/>
+        <mapEntry key="evaluate address" value="1157313"/>
+        <mapEntry key="get byte order" value="472733"/>
+        <mapEntry key="get capabilities" value="184017"/>
+        <mapEntry key="get cwd" value="220300"/>
+        <mapEntry key="get execution addresss" value="349574"/>
+        <mapEntry key="get source lines" value="264784"/>
+        <mapEntry key="get substitute paths" value="194068"/>
+        <mapEntry key="get value" value="402104"/>
+        <mapEntry key="getValidEncodings" value="454134"/>
+        <mapEntry key="initialize command help" value="32833321"/>
+        <mapEntry key="interrupt" value="4763438"/>
+        <mapEntry key="list breakpoint options" value="117078"/>
+        <mapEntry key="list breakpoints" value="387235"/>
+        <mapEntry key="list instruction sets" value="240494"/>
+        <mapEntry key="list signals" value="513624"/>
+        <mapEntry key="list source files" value="864344"/>
+        <mapEntry key="list watchpoint options" value="429611"/>
+        <mapEntry key="list watchpoints" value="304000"/>
+        <mapEntry key="loadfile" value="64967535"/>
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+        <mapEntry key="nexti" value="29780513"/>
+        <mapEntry key="remove" value="4067339"/>
+        <mapEntry key="run script" value="20282886"/>
+        <mapEntry key="set CWD" value="1301575"/>
+        <mapEntry key="set breakpoint properties" value="2759508"/>
+        <mapEntry key="set debug-from" value="554750"/>
+        <mapEntry key="set substitute-path" value="5401889"/>
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+        <mapEntry key="step" value="30959584"/>
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+        <mapEntry key="synchronizing trace ranges" value="25059"/>
+        <mapEntry key="toggleBreakpoint" value="14304795"/>
+        <mapEntry key="waitForTargetToStop" value="260589037"/>
+        <mapEntry key="write expression" value="5812240"/>
+    </mapAttribute>
+    <listAttribute key="DEBUG_TAB."/>
+    <stringAttribute key="DEBUG_TAB..RESOURCES.0.TYPE" value="SOURCE_DIR"/>
+    <stringAttribute key="DEBUG_TAB..RESOURCES.0.VALUE" value="${workspace_loc:/tx}"/>
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+    <intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+    <intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
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+    <listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
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+    <stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+    <stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value="${workspace_loc:/sample_threadx/Debug/sample_threadx.axf}"/>
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+        <listEntry value="formatter"/>
+        <listEntry value="Hexadecimal"/>
+    </listAttribute>
+    <listAttribute key="TREE_NODE_PROPERTIES:debugger.view.NewRegisterView">
+        <listEntry value="NODE CACHE VERSION 1"/>
+        <listEntry value="REGISTER_SET:$AARCH64"/>
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+        <listEntry value="expanded"/>
+        <listEntry value="true"/>
+        <listEntry value="REGISTER_GROUP:$AARCH64::$Core"/>
+        <listEntry value="1"/>
+        <listEntry value="expanded"/>
+        <listEntry value="true"/>
+    </listAttribute>
+    <booleanAttribute key="VFS_ENABLED" value="true"/>
+    <stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+    <stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+    <stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot; hardwareBreakpoint=&quot;yes&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL3:0x0000000080003268&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\gnu\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL3:0x0000000080003268&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\gnu\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;1&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL3:0x00000000800032B0&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\gnu\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;2&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL1N:0x0000000080003268&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\gnu\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;3&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL1N:0x00000000800032B0&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\gnu\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;195&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
+    <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
+        <listEntry value="&lt;Next Instruction&gt;"/>
+        <listEntry value=""/>
+        <listEntry value="0x0000000080009140"/>
+        <listEntry value="0x000000008000E660"/>
+        <listEntry value="EL1N:0x000000008000E660"/>
+    </listAttribute>
+    <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
+        <listEntry value="100"/>
+        <listEntry value=""/>
+        <listEntry value="100"/>
+        <listEntry value="100"/>
+        <listEntry value="100"/>
+    </listAttribute>
+    <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.addresses">
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+        <listEntry value="0x80180000"/>
+        <listEntry value="0x00000000801A80D4"/>
+        <listEntry value="0x801FFF00"/>
+        <listEntry value="0x801F0000"/>
+        <listEntry value="0x80150000"/>
+        <listEntry value="0x80100000"/>
+        <listEntry value="0x80200000"/>
+        <listEntry value="0x8001Df00"/>
+        <listEntry value="0x8001Df50"/>
+        <listEntry value="&lt;Next Instruction&gt;"/>
+        <listEntry value="&amp;(thread_0_counter)"/>
+    </listAttribute>
+    <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.ranges">
+        <listEntry value=""/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="1024"/>
+        <listEntry value="sizeof(thread_0_counter)"/>
+    </listAttribute>
+    <listAttribute key="com.arm.debugger.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
+        <listEntry value="_tx_thread_schedule"/>
+        <listEntry value="&lt;Next Instruction&gt;"/>
+    </listAttribute>
+    <listAttribute key="com.arm.debugger.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
+        <listEntry value="100"/>
+        <listEntry value="100"/>
+    </listAttribute>
+    <stringAttribute key="config_db_activity_name" value="Debug Cortex-A35"/>
+    <stringAttribute key="config_db_connection_keys" value="dtsl_config dtsl_tracecapture_option dtsl_config_script model_params config_file setup TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+    <stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+    <stringAttribute key="config_db_platform_name" value="Arm FVP (Installed with Arm DS) - Base_A35x1"/>
+    <stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+    <stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+    <stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/base_a35x1"/>
+    <stringAttribute key="config_file" value="CDB://cadi_config.xml"/>
+    <booleanAttribute key="connectOnly" value="false"/>
+    <listAttribute key="debugger.view.DisassemblyView:current">
+        <listEntry value="&lt;Next Instruction&gt;"/>
+        <listEntry value="100"/>
+    </listAttribute>
+    <listAttribute key="debugger.view.DisassemblyView:current:133102083840333696.viewid=2">
+        <listEntry value="&lt;Next Instruction&gt;"/>
+        <listEntry value="100"/>
+    </listAttribute>
+    <listAttribute key="debugger.view.DisassemblyView:current:3239034212381883008.viewid=2">
+        <listEntry value="_tx_thread_schedule"/>
+        <listEntry value="100"/>
+    </listAttribute>
+    <listAttribute key="debugger.view.DisassemblyView:current:4564877728016551851.viewid=3">
+        <listEntry value=""/>
+        <listEntry value=""/>
+    </listAttribute>
+    <listAttribute key="debugger.view.ExpressionsView">
+        <listEntry value="thread_0_counter"/>
+        <listEntry value="thread_1_counter"/>
+        <listEntry value="thread_1_messages_sent"/>
+        <listEntry value="thread_2_counter"/>
+        <listEntry value="thread_2_messages_received"/>
+        <listEntry value="thread_3_counter"/>
+        <listEntry value="thread_4_counter"/>
+        <listEntry value="thread_5_counter"/>
+        <listEntry value="thread_6_counter"/>
+        <listEntry value="thread_7_counter"/>
+    </listAttribute>
+    <listAttribute key="debugger.view.ExpressionsView.ExpressionTypes">
+        <listEntry value=""/>
+        <listEntry value=""/>
+        <listEntry value=""/>
+        <listEntry value=""/>
+        <listEntry value=""/>
+        <listEntry value=""/>
+        <listEntry value=""/>
+        <listEntry value=""/>
+    </listAttribute>
+    <mapAttribute key="debugger.view.ExpressionsView.ExpressionsData">
+        <mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="1" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="2" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="3" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="4" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="5" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="6" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="7" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="8" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="9" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+    </mapAttribute>
+    <stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;274&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;159&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;75&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;244&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.MemoryView" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;page&gt;&#10;&#9;&lt;memoryView/&gt;&#10;&lt;/page&gt;&#10;"/>
+    <listAttribute key="debugger.view.MemoryView:current">
+        <listEntry value=""/>
+        <listEntry value=""/>
+    </listAttribute>
+    <stringAttribute key="debugger.view.NewRegisterView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;64&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;false&#9;420&#9;-1&#9;true&#9;3&#9;false&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;false&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;false&#9;48&#9;-1&#9;true&#9;6&#9;false&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;false&#9;69&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.NewRegisterView:_selectedRegisterSet" value="All registers"/>
+    <mapAttribute key="debugger.view.NewRegisterView_registerSets"/>
+    <stringAttribute key="debugger.view.StackView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;49&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;45&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;41&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;62&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
+    <listAttribute key="debugger.view.TraceView:TRACE_EXPORT_FILTERS"/>
+    <stringAttribute key="debugger.view.VariableTreeView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;197&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;137&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <listAttribute key="debugger.view.VariableTreeView:USER_ADDED_FILE_STATICS"/>
+    <listAttribute key="debugger.view.VariableTreeView:USER_ADDED_GLOBALS"/>
+    <listAttribute key="debugger.view.VariableTreeView:USER_ADDED_UNRESOLVED"/>
+    <booleanAttribute key="debugger.view.expression.DrawAsHex" value="false"/>
+    <booleanAttribute key="debugger.view.register.DrawAsHex" value="false"/>
+    <booleanAttribute key="debugger.view.variable.DrawAsHex" value="false"/>
+    <stringAttribute key="dtsl_config" value="DtslScript"/>
+    <stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
+    <stringAttribute key="dtsl_options_file" value="default"/>
+    <stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
+    <stringAttribute key="launch_configuration_version" value="2020.0"/>
+    <booleanAttribute key="linuxOS" value="false"/>
+    <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
+    <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
+    <booleanAttribute key="runAfterConnect" value="false"/>
+    <mapAttribute key="scripts_view_script_links">
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
+    </mapAttribute>
+    <listAttribute key="setup">
+        <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
+        <listEntry value="&quot;FVP_Base_Cortex-A35x1&quot;"/>
+    </listAttribute>
+    <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
+    <stringAttribute key="substitutePath" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;tuplelist&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:\temp1702\tx\&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\temp1702\tx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&lt;/tuplelist&gt;&#10;"/>
+    <stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
+</launchConfiguration>
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld
new file mode 100644
index 00000000..eec8f12b
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld
@@ -0,0 +1,245 @@
+/* Linker script to place sections and symbol values.
+ * It references following symbols, which must be defined in code:
+ *   start64 : Entry point
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __cs3_peripherals
+ *   __code_start
+ *   __exidx_start
+ *   __exidx_end
+ *   __data_start
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   __stack
+ *   __el3_stack
+ *   __ttb0_l1
+ *   __ttb0_l2_ram
+ *   __ttb0_l2_private
+ *   __ttb0_l2_periph
+ *   __top_of_ram
+ */
+
+ENTRY(start64)
+
+SECTIONS
+{
+    /*
+     * CS3 Peripherals is a 64MB region from 0x1c000000
+     * that includes the following:
+     * System Registers             at 0x1C010000
+     * UART0 (PL011)                at 0x1C090000
+     * Color LCD Controller (PL111) at 0x1C1F0000
+     * plus a number of others.
+     * CS3_PERIPHERALS is used by the startup code for page-table generation
+     * This region is not truly empty, but we have no
+     * predefined objects that live within it
+     */
+    __cs3_peripherals  = 0x1c000000;
+
+    /*
+     * GICv3 distributor
+     */
+    .gicd 0x2f000000 (NOLOAD):
+    {
+        *(.gicd)
+    }
+
+    /*
+     * GICv3 redistributors
+     * 128KB for each redistributor in the system
+     */
+    .gicr 0x2f100000 (NOLOAD):
+    {
+        *(.gicr)
+    }
+
+    .vectors 0x80000000:
+    {
+        __code_start = .;
+        KEEP(*(StartUp))
+        KEEP(*(EL1VECTORS EL2VECTORS EL3VECTORS))
+    }
+
+    .init :
+    {
+        KEEP (*(SORT_NONE(.init)))
+    }
+
+    .text :
+    {
+        *(.text*)
+    }
+
+    .fini :
+    {
+        KEEP (*(SORT_NONE(.fini)))
+    }
+
+    .rodata :
+    {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+    }
+
+    .eh_frame :
+    {
+        KEEP (*(.eh_frame))
+    }
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    }
+
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    }
+
+    .preinit_array :
+    {
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+    }
+
+    .init_array :
+    {
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array ))
+        PROVIDE_HIDDEN (__init_array_end = .);
+    }
+
+    .fini_array :
+    {
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP (*(SORT(.fini_array.*)))
+        KEEP (*(.fini_array ))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+    }
+
+    .ctors :
+    {
+        /* gcc uses crtbegin.o to find the start of
+           the constructors, so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtbegin.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtbegin.o
+           is in.  */
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*crtbegin?.o(.ctors))
+        /* We don't want to include the .ctor section from
+           the crtend.o file until after the sorted ctors.
+           The .ctor section from the crtend file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+    }
+
+    .dtors :
+    {
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*crtbegin?.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+    }
+
+    .jcr :
+    {
+        KEEP (*(.jcr))
+    }
+
+    .data :
+    {
+        __data_start = . ;
+        *(.data .data.* .gnu.linkonce.d.*)
+        SORT(CONSTRUCTORS)
+    }
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    }
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(64);
+        __end__ = .;
+        PROVIDE(end = .);
+        . = . + 0x1000;
+    }
+
+    .stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 8 * 0x4000;
+        __handler_stack = .;
+    }
+
+    .stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 8 * 0x4000;
+        __stack = .;
+    }
+
+    .el3_stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 8 * 0x1000;
+        __el3_stack = .;
+    }
+
+    .ttb0_l1 (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l1 = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_ram (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_ram = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_private (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_private = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_periph (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_periph = .;
+        . = . + 0x1000;
+    }
+
+    /*
+     * The startup code uses the end of this region to calculate
+     * the top of memory - don't place any RAM regions after it
+     */
+    __top_of_ram = .;
+}
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c
new file mode 100644
index 00000000..4dc009b2
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c
@@ -0,0 +1,122 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "sp804_timer.h"
+
+#define TIMER_SP804_CTRL_TIMEREN     (1 << 7)
+#define TIMER_SP804_CTRL_TIMERMODE   (1 << 6)        // Bit 6:
+#define TIMER_SP804_CTRL_INTENABLE   (1 << 5)
+#define TIMER_SP804_CTRL_TIMERSIZE   (1 << 1)        // Bit 1: 0=16-bit, 1=32-bit
+#define TIMER_SP804_CTRL_ONESHOT     (1 << 0)        // Bit 0: 0=wrapping, 1=one-shot
+
+#define TIMER_SP804_CTRL_PRESCALE_1  (0 << 2)        // clk/1
+#define TIMER_SP804_CTRL_PRESCALE_4  (1 << 2)        // clk/4
+#define TIMER_SP804_CTRL_PRESCALE_8  (2 << 2)        // clk/8
+
+struct sp804_timer
+{
+        volatile uint32_t Time1Load;     // +0x00
+  const volatile uint32_t Time1Value;    // +0x04 - RO
+        volatile uint32_t Timer1Control; // +0x08
+        volatile uint32_t Timer1IntClr;  // +0x0C - WO
+  const volatile uint32_t Timer1RIS;     // +0x10 - RO
+  const volatile uint32_t Timer1MIS;     // +0x14 - RO
+        volatile uint32_t Timer1BGLoad;  // +0x18
+
+        volatile uint32_t Time2Load;     // +0x20
+        volatile uint32_t Time2Value;    // +0x24
+        volatile uint8_t  Timer2Control; // +0x28
+        volatile uint32_t Timer2IntClr;  // +0x2C - WO
+  const volatile uint32_t Timer2RIS;     // +0x30 - RO
+  const volatile uint32_t Timer2MIS;     // +0x34 - RO
+        volatile uint32_t Timer2BGLoad;  // +0x38
+
+  // Not including ID registers
+
+};
+
+// Instance of the dual timer, will be placed using the scatter file
+struct sp804_timer* dual_timer;
+
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address)
+{
+  dual_timer = (struct sp804_timer*)address;
+  return;
+}
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
+{
+  uint32_t tmp = 0;
+
+  dual_timer->Time1Load = load_value;
+
+  // Fixed setting: 32-bit, no prescaling
+  tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
+
+  // Settings from parameters: interrupt generation & reload
+  tmp = tmp | interrupt | auto_reload;
+
+  // Write control register
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Starts the timer
+void startTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp | TIMER_SP804_CTRL_TIMEREN;      // Set TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Stops the timer
+void stopTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN;     // Clear TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void)
+{
+  return dual_timer->Time1Value;
+}
+
+
+void clearTimerIrq(void)
+{
+  // A write to this register, of any value, clears the interrupt
+  dual_timer->Timer1IntClr = 1;
+}
+
+
+// ------------------------------------------------------------
+// End of sp804_timer.c
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h
new file mode 100644
index 00000000..777062cc
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h
@@ -0,0 +1,53 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+// Header Filer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#ifndef _SP804_TIMER_
+#define _SP804_TIMER_
+
+#include <stdint.h>
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address);
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+
+#define SP804_AUTORELOAD   (0)
+#define SP804_SINGLESHOT   (1)
+#define SP804_GENERATE_IRQ (1 << 5)
+#define SP804_NO_IRQ       (0)
+
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
+
+
+// Starts the timer
+void startTimer(void);
+
+
+// Stops the timer
+void stopTimer(void);
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void);
+
+
+// Clears the timer interrupt
+void clearTimerIrq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of sp804_timer.h
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S
new file mode 100644
index 00000000..67dd8a6a
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S
@@ -0,0 +1,787 @@
+// ------------------------------------------------------------
+// Armv8-A MPCore EL3 AArch64 Startup Code
+//
+// Basic Vectors, MMU, caches and GICv3 initialization
+//
+// Exits in EL1 AArch64
+//
+// Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_mmu.h"
+#include "v8_system.h"
+#include "GICv3_aliases.h"
+
+    .section StartUp, "ax"
+    .balign 4
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+
+    .global InvalidateUDCaches
+    .global ZeroBlock
+
+    .global SetPrivateIntSecurityBlock
+    .global SetSPISecurityAll
+    .global SetPrivateIntPriority
+
+    .global GetGICR
+    .global WakeupGICR
+    .global SyncAREinGICD
+    .global EnableGICD
+    .global EnablePrivateInt
+    .global GetPrivateIntPending
+    .global ClearPrivateIntPending
+
+    .global _start
+    .global MainApp
+
+    .global __code_start
+    .global __ttb0_l1
+    .global __ttb0_l2_ram
+    .global __ttb0_l2_periph
+    .global __top_of_ram
+    .global gicd
+    .global __stack
+    .global __el3_stack
+    .global __cs3_peripherals
+
+
+
+
+// ------------------------------------------------------------
+
+    .global start64
+    .type start64, "function"
+start64:
+
+    //
+    // program the VBARs
+    //
+    ldr x1, =el1_vectors
+    msr VBAR_EL1, x1
+
+    ldr x1, =el2_vectors
+    msr VBAR_EL2, x1
+
+    ldr x1, =el3_vectors
+    msr VBAR_EL3, x1
+
+
+    // GIC-500 comes out of reset in GICv2 compatibility mode - first set
+    // system register enables for all relevant exception levels, and
+    // select GICv3 operating mode
+    //
+    msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL3, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
+
+    //
+    // set lower exception levels as non-secure, with no access
+    // back to EL2 or EL3, and are AArch64 capable
+    //
+    mov x3, #(SCR_EL3_RW  | \
+              SCR_EL3_SMD | \
+              SCR_EL3_NS)      // Set NS bit, to access Non-secure registers
+    msr SCR_EL3, x3
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL2, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
+
+
+    //
+    // no traps or VM modifications from the Hypervisor, EL1 is AArch64
+    //
+    mov x2, #HCR_EL2_RW
+    msr HCR_EL2, x2
+
+    //
+    // VMID is still significant, even when virtualisation is not
+    // being used, so ensure VTTBR_EL2 is properly initialised
+    //
+    msr VTTBR_EL2, xzr
+
+    //
+    // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
+    //  VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
+    // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
+    // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
+    // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
+    //
+    mrs x0, MPIDR_EL1
+    msr VMPIDR_EL2, x0
+    mrs x0, MIDR_EL1
+    msr VPIDR_EL2, x0
+
+    // extract the core number from MPIDR_EL1 and store it in
+    // x19 (defined by the AAPCS as callee-saved), so we can re-use
+    // the number later
+    //
+    bl GetCPUID
+    mov x19, x0
+
+    //
+    // neither EL3 nor EL2 trap floating point or accesses to CPACR
+    //
+    msr CPTR_EL3, xzr
+    msr CPTR_EL2, xzr
+
+    //
+    // SCTLR_ELx may come out of reset with UNKNOWN values so we will
+    // set the fields to 0 except, possibly, the endianess field(s).
+    // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
+    // is not strictly needed, since we're never in EL2 or EL0
+    //
+#ifdef __ARM_BIG_ENDIAN
+    mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
+#else
+    mov x0, #0
+#endif
+    msr SCTLR_EL3, x0
+    msr SCTLR_EL2, x0
+    msr SCTLR_EL1, x0
+
+#ifdef CORTEXA
+    //
+    // Configure ACTLR_EL[23]
+    // ----------------------
+    //
+    // These bits are IMPLEMENTATION DEFINED, so are different for
+    // different processors
+    //
+    // For Cortex-A57, the controls we set are:
+    //
+    //  Enable lower level access to CPUACTLR_EL1
+    //  Enable lower level access to CPUECTLR_EL1
+    //  Enable lower level access to L2CTLR_EL1
+    //  Enable lower level access to L2ECTLR_EL1
+    //  Enable lower level access to L2ACTLR_EL1
+    //
+    mov x0, #((1 << 0) | \
+              (1 << 1) | \
+              (1 << 4) | \
+              (1 << 5) | \
+              (1 << 6))
+
+    msr ACTLR_EL3, x0
+    msr ACTLR_EL2, x0
+
+    //
+    // configure CPUECTLR_EL1
+    //
+    // These bits are IMP DEF, so need to different for different
+    // processors
+    //
+    // SMPEN - bit 6 - Enables the processor to receive cache
+    //                 and TLB maintenance operations
+    //
+    // Note: For Cortex-A57/53 SMPEN should be set before enabling
+    //       the caches and MMU, or performing any cache and TLB
+    //       maintenance operations.
+    //
+    //       This register has a defined reset value, so we use a
+    //       read-modify-write sequence to set SMPEN
+    //
+    mrs x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
+    orr x0, x0, #(1 << 6)  // Set the SMPEN bit
+    msr S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
+
+    isb
+#endif
+
+    //
+    // That's the last of the control settings for now
+    //
+    // Note: no ISB after all these changes, as registers won't be
+    // accessed until after an exception return, which is itself a
+    // context synchronisation event
+    //
+
+    //
+    // Setup some EL3 stack space, ready for calling some subroutines, below.
+    //
+    // Stack space allocation is CPU-specific, so use CPU
+    // number already held in x19
+    //
+    // 2^12 bytes per CPU for the EL3 stacks
+    //
+    ldr x0, =__el3_stack
+    sub x0, x0, x19, lsl #12
+    mov sp, x0
+
+    //
+    // we need to configure the GIC while still in secure mode, specifically
+    // all PPIs and SPIs have to be programmed as Group1 interrupts
+    //
+
+    //
+    // Before the GIC can be reliably programmed, we need to
+    // enable Affinity Routing, as this affects where the configuration
+    // registers are (with Affinity Routing enabled, some registers are
+    // in the Redistributor, whereas those same registers are in the
+    // Distributor with Affinity Routing disabled (i.e. when in GICv2
+    // compatibility mode).
+    //
+    mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
+    mov x1, x19
+    bl  SyncAREinGICD
+
+    //
+    // The Redistributor comes out of reset assuming the processor is
+    // asleep - correct that assumption
+    //
+    bl  GetAffinity
+    bl  GetGICR
+    mov w20, w0     // Keep a copy for later
+    bl  WakeupGICR
+
+    //
+    // Now we're ready to set security and other initialisations
+    //
+    // This is a per-CPU configuration for these interrupts
+    //
+    // for the first cluster, CPU number is the redistributor index
+    //
+    mov w0, w20
+    mov w1, #1    // gicigroupr_G1NS
+    bl  SetPrivateIntSecurityBlock
+
+    //
+    // While we're in the Secure World, set the priority mask low enough
+    // for it to be writable in the Non-Secure World
+    //
+    //mov x0, #16 << 3    // 5 bits of priority in the Secure world
+    mov x0, #0xFF  // for Non-Secure interrupts
+    msr ICC_PMR_EL1, x0
+
+    //
+    // there's more GIC setup to do, but only for the primary CPU
+    //
+    cbnz x19, drop_to_el1
+
+    //
+    // There's more to do to the GIC - call the utility routine to set
+    // all SPIs to Group1
+    //
+    mov w0, #1    // gicigroupr_G1NS
+    bl  SetSPISecurityAll
+
+    //
+    // Set up EL1 entry point and "dummy" exception return information,
+    // then perform exception return to enter EL1
+    //
+    .global drop_to_el1
+drop_to_el1:
+    adr x1, el1_entry_aarch64
+    msr ELR_EL3, x1
+    mov x1, #(AARCH64_SPSR_EL1h | \
+              AARCH64_SPSR_F  | \
+              AARCH64_SPSR_I  | \
+              AARCH64_SPSR_A)
+    msr SPSR_EL3, x1
+    eret
+
+
+
+// ------------------------------------------------------------
+// EL1 - Common start-up code
+// ------------------------------------------------------------
+
+    .global el1_entry_aarch64
+    .type el1_entry_aarch64, "function"
+el1_entry_aarch64:
+
+    //
+    // Now we're in EL1, setup the application stack
+    // the scatter file allocates 2^14 bytes per app stack
+    //
+    ldr x0, =__handler_stack
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+    MSR     SPSel, #0
+    ISB
+    ldr x0, =__stack
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+
+    //
+    // Enable floating point
+    //
+    mov x0, #CPACR_EL1_FPEN
+    msr CPACR_EL1, x0
+
+    //
+    // Invalidate caches and TLBs for all stage 1
+    // translations used at EL1
+    //
+    // Cortex-A processors automatically invalidate their caches on reset
+    // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
+    // It is therefore not necessary for software to invalidate the caches 
+    // on startup, however, this is done here in case of a warm reset.
+    bl  InvalidateUDCaches
+    tlbi VMALLE1
+
+
+    //
+    // Set TTBR0 Base address
+    //
+    // The CPUs share one set of translation tables that are
+    // generated by CPU0 at run-time
+    //
+    // TTBR1_EL1 is not used in this example
+    //
+    ldr x1, =__ttb0_l1
+    msr TTBR0_EL1, x1
+
+
+    //
+    // Set up memory attributes
+    //
+    // These equate to:
+    //
+    // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
+    // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
+    // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
+    //
+    mov  x1, #0xff44
+    movk x1, #4, LSL #16    // equiv to: movk x1, #0x0000000000040000
+    msr MAIR_EL1, x1
+
+
+    //
+    // Set up TCR_EL1
+    //
+    // We're using only TTBR0 (EPD1 = 1), and the page table entries:
+    //  - are using an 8-bit ASID from TTBR0
+    //  - have a 4K granularity (TG0 = 0b00)
+    //  - are outer-shareable (SH0 = 0b10)
+    //  - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
+    //  - map
+    //      + 32 bits of VA space (T0SZ = 0x20)
+    //      + into a 32-bit PA space (IPS = 0b000)
+    //
+    //     36   32   28   24   20   16   12    8    4    0
+    //  -----+----+----+----+----+----+----+----+----+----+
+    //       |    |    |OOII|    |    |    |OOII|    |    |
+    //    TT |    |    |RRRR|E T |   T|    |RRRR|E T |   T|
+    //    BB | I I|TTSS|GGGG|P 1 |   1|TTSS|GGGG|P 0 |   0|
+    //    IIA| P P|GGHH|NNNN|DAS |   S|GGHH|NNNN|D S |   S|
+    //    10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
+    //
+    //    000 0000 0000 0000 1000 0000 0010 0101 0010 0000
+    //
+    //                    0x    8    0    2    5    2    0
+    //
+    // Note: the ISB is needed to ensure the changes to system
+    //       context are before the write of SCTLR_EL1.M to enable
+    //       the MMU. It is likely on a "real" implementation that
+    //       this setup would work without an ISB, due to the
+    //       amount of code that gets executed before enabling the
+    //       MMU, but that would not be architecturally correct.
+    //
+    ldr x1, =0x0000000000802520
+    msr TCR_EL1, x1
+    isb
+
+    //
+    // x19 already contains the CPU number, so branch to secondary
+    // code if we're not on CPU0
+    //
+    cbnz x19, el1_secondary
+
+    //
+    // Fall through to primary code
+    //
+
+
+//
+// ------------------------------------------------------------
+//
+// EL1 - primary CPU init code
+//
+// This code is run on CPU0, while the other CPUs are in the
+// holding pen
+//
+
+    .global el1_primary
+    .type el1_primary, "function"
+el1_primary:
+
+    //
+    // Turn on the banked GIC distributor enable,
+    // ready for individual CPU enables later
+    //
+    mov w0, #(1 << 1)  // gicdctlr_EnableGrp1A
+    bl  EnableGICD
+
+    //
+    // Generate TTBR0 L1
+    //
+    // at 4KB granularity, 32-bit VA space, table lookup starts at
+    // L1, with 1GB regions
+    //
+    // we are going to create entries pointing to L2 tables for a
+    // couple of these 1GB regions, the first of which is the
+    // RAM on the VE board model - get the table addresses and
+    // start by emptying out the L1 page tables (4 entries at L1
+    // for a 4K granularity)
+    //
+    // x21 = address of L1 tables
+    //
+    ldr x21, =__ttb0_l1
+    mov x0, x21
+    mov x1, #(4 << 3)
+    bl  ZeroBlock
+
+    //
+    // time to start mapping the RAM regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // x22 = address of L2 tables, needs to be remembered in case
+    //       we want to re-use the tables for mapping peripherals
+    //
+    ldr x22, =__ttb0_l2_ram
+    mov x1, #(512 << 3)
+    mov x0, x22
+    bl  ZeroBlock
+
+    //
+    // Get the start address of RAM (the EXEC region) into x4
+    // and calculate the offset into the L1 table (1GB per region,
+    // max 4GB)
+    //
+    // x23 = L1 table offset, saved for later comparison against
+    //       peripheral offset
+    //
+    ldr x4, =__code_start
+    ubfx x23, x4, #30, #2
+
+    orr x1, x22, #TT_S1_ATTR_PAGE
+    str x1, [x21, x23, lsl #3]
+
+    //
+    // we've already used the RAM start address in x4 - we now need
+    // to get this in terms of an offset into the L2 page tables,
+    // where each entry covers 2MB
+    //
+    ubfx x2, x4, #21, #9
+
+    //
+    // TOP_OF_RAM in the scatter file marks the end of the
+    // Execute region in RAM: convert the end of this region to an
+    // offset too, being careful to round up, then calculate the
+    // number of entries to write
+    //
+    ldr x5, =__top_of_ram
+    sub  x3, x5, #1
+    ubfx x3, x3, #21, #9
+    add  x3, x3, #1
+    sub  x3, x3, x2
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as Shared, Normal WBWA (MAIR[1]) with a flat
+    // VA->PA translation
+    //
+    bic x4, x4, #((1 << 21) - 1)
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (1 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_SH_INNER | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // factor the offset into the page table address and then write
+    // the entries
+    //
+    add x0, x22, x2, lsl #3
+
+loop1:
+    subs x3, x3, #1
+    str x1, [x0], #8
+    add x1, x1, #0x200, LSL #12    // equiv to add x1, x1, #(1 << 21)  // 2MB per entry
+    bne loop1
+
+
+    //
+    // now mapping the Peripheral regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // The assumption here is that all peripherals live within
+    // a common 1GB region (i.e. that there's a single set of
+    // L2 pages for all the peripherals). We only use a UART
+    // and the GIC in this example, so the assumption is sound
+    //
+    // x24 = address of L2 peripheral tables
+    //
+    ldr x24, =__ttb0_l2_periph
+
+    //
+    // get the GICD address into x4 and calculate
+    // the offset into the L1 table
+    //
+    // x25 = L1 table offset
+    //
+    ldr x4, =gicd
+    ubfx x25, x4, #30, #2
+
+    //
+    // here's the tricky bit: it's possible that the peripherals are
+    // in the same 1GB region as the RAM, in which case we don't need
+    // to prime a separate set of L2 page tables, nor add them to the
+    // L1 tables
+    //
+    // if we're going to re-use the TTB0_L2_RAM tables, get their
+    // address into x24, which is used later on to write the PTEs
+    //
+    cmp x25, x23
+    csel x24, x22, x24, EQ
+    b.eq nol2setup
+
+    //
+    // Peripherals are in a separate 1GB region, and so have their own
+    // set of L2 tables - clean out the tables and add them to the L1
+    // table
+    //
+    mov x0, x24
+    mov x1, #512 << 3
+    bl  ZeroBlock
+
+    orr x1, x24, #TT_S1_ATTR_PAGE
+    str x1, [x21, x25, lsl #3]
+
+    //
+    // there's only going to be a single 2MB region for GICD (in
+    // x4) - get this in terms of an offset into the L2 page tables
+    //
+    // with larger systems, it is possible that the GIC redistributor
+    // registers require extra 2MB pages, in which case extra code
+    // would be required here
+    //
+nol2setup:
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry for this, so no loop as we have for RAM, above
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // we have CS3_PERIPHERALS that include the UART controller
+    //
+    // Again, the code is making assumptions - this time that the CS3_PERIPHERALS
+    // region uses the same 1GB portion of the address space as the GICD,
+    // and thus shares the same set of L2 page tables
+    //
+    // Get CS3_PERIPHERALS address into x4 and calculate the offset into the
+    // L2 tables
+    //
+    ldr x4, =__cs3_peripherals
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry again - write it
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // issue a barrier to ensure all table entry writes are complete
+    //
+    dsb ish
+
+    //
+    // Enable the MMU.  Caches will be enabled later, after scatterloading.
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // The Arm Architecture Reference Manual for Armv8-A states:
+    //
+    //     Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
+    //     Correspondingly, the sequence for ensuring that modifications to instructions are available
+    //     for execution must include invalidation of the modified locations from the instruction cache,
+    //     even if the instructions are held in Normal Non-cacheable memory.
+    //     This includes cases where the instruction cache is disabled.
+    //
+
+    dsb ish     // ensure all previous stores have completed before invalidating
+    ic  ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
+    dsb ish     // ensure completion on inner shareable domain   (which includes secondary cores)
+    isb
+
+    // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    msr SCTLR_EL1, x1
+    isb
+
+    // Zero the bss
+    ldr x0, =__bss_start__ // Start of block
+    mov x1, #0             // Fill value
+    ldr x2, =__bss_end__   // End of block
+    sub x2, x2, x0         // Length of block
+    bl  memset
+
+    // Set up the standard file handles
+    bl  initialise_monitor_handles
+
+    // Set up _fini and fini_array to be called at exit
+    ldr x0, =__libc_fini_array
+    bl  atexit
+
+    // Call preinit_array, _init and init_array
+    bl  __libc_init_array
+
+    // Set argc = 1, argv[0] = "" and then call main
+    .pushsection .data
+    .align 3
+argv:
+    .dword arg0
+    .dword 0
+arg0:
+    .byte 0
+    .popsection
+
+    mov x0, #1
+    ldr x1, =argv
+    bl main
+
+    b exit // Will not return
+
+// ------------------------------------------------------------
+// EL1 - secondary CPU init code
+//
+// This code is run on CPUs 1, 2, 3 etc....
+// ------------------------------------------------------------
+
+    .global el1_secondary
+    .type el1_secondary, "function"
+el1_secondary:
+
+    //
+    // the primary CPU is going to use SGI 15 as a wakeup event
+    // to let us know when it is OK to proceed, so prepare for
+    // receiving that interrupt
+    //
+    // NS interrupt priorities run from 0 to 15, with 15 being
+    // too low a priority to ever raise an interrupt, so let's
+    // use 14
+    //
+    mov w0, w20
+    mov w1, #15
+    mov w2, #14 << 4    // we're in NS world, so 4 bits of priority,
+                        // 8-bit field, - 4 = 4-bit shift
+    bl SetPrivateIntPriority
+
+    mov w0, w20
+    mov w1, #15
+    bl  EnablePrivateInt
+
+    //
+    // set priority mask as low as possible; although,being in the
+    // NS World, we can't set bit[7] of the priority, we still
+    // write all 8-bits of priority to an ICC register
+    //
+    mov x0, #31 << 3
+    msr ICC_PMR_EL1, x0
+
+    //
+    // set global enable and wait for our interrupt to arrive
+    //
+    mov x0, #1
+    msr ICC_IGRPEN1_EL1, x0
+    isb
+
+loop_wfi:
+    dsb SY      // Clear all pending data accesses
+    wfi         // Go to sleep
+
+    //
+    // something woke us from our wait, was it the required interrupt?
+    //
+    mov w0, w20
+    mov w1, #15
+    bl  GetPrivateIntPending
+    cbz w0, loop_wfi
+
+    //
+    // it was - there's no need to actually take the interrupt,
+    // so just clear it
+    //
+    mov w0, w20
+    mov w1, #15
+    bl  ClearPrivateIntPending
+
+    //
+    // Enable the MMU and caches
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // Branch to thread start
+    //
+    //B  MainApp
+
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/timer_interrupts.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/timer_interrupts.c
new file mode 100644
index 00000000..8f522217
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/timer_interrupts.c
@@ -0,0 +1,152 @@
+/* Bare-metal example for Armv8-A FVP Base model */
+
+/* Timer and interrupts */
+
+/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */
+/* Use, modification and redistribution of this file is subject to your possession of a     */
+/* valid End User License Agreement for the Arm Product of which these examples are part of */
+/* and your compliance with all applicable terms and conditions of such licence agreement.  */
+
+#include <stdio.h>
+
+#include "GICv3.h"
+#include "GICv3_gicc.h"
+#include "sp804_timer.h"
+
+void   _tx_timer_interrupt(void);
+
+// LED Base address
+#define LED_BASE (volatile unsigned int *)0x1C010008
+
+
+void nudge_leds(void) // Move LEDs along
+{
+    static int state = 1;
+    static int value = 1;
+
+    if (state)
+    {
+        int max = (1 << 7);
+        value <<= 1;
+        if (value == max)
+            state = 0;
+    }
+    else
+    {
+        value >>= 1;
+        if (value == 1)
+            state = 1;
+    }
+
+    *LED_BASE = value;  // Update LEDs hardware
+}
+
+
+// Initialize Timer 0 and Interrupt Controller
+void init_timer(void)
+{
+    // Enable interrupts
+    __asm("MSR DAIFClr, #0xF");
+    setICC_IGRPEN1_EL1(igrpEnable);
+
+    // Configure the SP804 timer to generate an interrupt
+    setTimerBaseAddress(0x1C110000);
+    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
+    startTimer();
+
+    // The SP804 timer generates SPI INTID 34.  Enable
+    // this ID, and route it to core 0.0.0.0 (this one!)
+    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
+    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
+    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
+    EnableSPI(34);                                   // Enable INTID 34
+}
+
+
+// --------------------------------------------------------
+
+void irqHandler(void)
+{
+  unsigned int ID;
+
+  ID = getICC_IAR1(); // readIntAck();
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+      //printf("irqHandler() - Reserved INTID %d\n\n", ID);
+      return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("irqHandler() - External timer interrupt\n\n");
+      nudge_leds();
+      clearTimerIrq();
+
+      /* Call ThreadX timer interrupt processing.  */
+      _tx_timer_interrupt();
+
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("irqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
+
+// --------------------------------------------------------
+
+// Not actually used in this example, but provided for completeness
+
+void fiqHandler(void)
+{
+  unsigned int ID;
+  unsigned int aliased = 0;
+
+  ID = getICC_IAR0(); // readIntAck();
+  //printf("fiqHandler() - Read %d from IAR0\n", ID);
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+    //printf("fiqHandler() - Reserved INTID %d\n\n", ID);
+    ID = getICC_IAR1(); // readAliasedIntAck();
+    //printf("fiqHandler() - Read %d from AIAR\n", ID);
+    aliased = 1;
+
+    // If still spurious then simply return
+    if ((1020 <= ID) && (ID <= 1023))
+        return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("fiqHandler() - External timer interrupt\n\n");
+      clearTimerIrq();
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  // NOTE: If the ID was read from the Aliased IAR, then
+  // the aliased EOI register must be used
+  if (aliased == 0)
+    setICC_EOIR0(ID); // writeEOI(ID);
+  else
+    setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S
new file mode 100644
index 00000000..f467b8a7
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S
@@ -0,0 +1,95 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+	.text
+	.align 3
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_initialize_low_level                          Cortex-A35/GNU    */ 
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is responsible for any low-level processor            */ 
+/*    initialization, including setting up interrupt vectors, setting     */ 
+/*    up a periodic timer interrupt source, saving the system stack       */ 
+/*    pointer for use in ISR processing later, and finding the first      */ 
+/*    available RAM memory address for tx_application_define.             */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_initialize_low_level(VOID)
+{ */
+    .global  _tx_initialize_low_level
+    .type    _tx_initialize_low_level, @function
+_tx_initialize_low_level:
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+
+    /* Save the system stack pointer.  */
+    /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp);  */
+
+    LDR     x0, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    MOV     x1, sp                              // Pickup SP
+    BIC     x1, x1, #0xF                        // Get 16-bit alignment
+    STR     x1, [x0]                            // Store system stack
+
+    /* Save the first available memory address.  */
+    /* _tx_initialize_unused_memory =  (VOID_PTR) Image$$ZI$$Limit;  */
+
+    LDR     x0, =_tx_initialize_unused_memory   // Pickup address of unused memory ptr
+    LDR     x1, =__top_of_ram                   // Pickup unused memory address
+    LDR     x1, [x1]                            //
+    STR     x1, [x0]                            // Store unused memory address
+
+    /* Done, return to caller.  */
+
+    RET                                         // Return to caller
+/* } */
+
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S
new file mode 100644
index 00000000..f8db3bfe
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S
@@ -0,0 +1,179 @@
+// ------------------------------------------------------------
+// Armv8-A AArch64 - Common helper functions
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global EnableCachesEL1
+    .global DisableCachesEL1
+    .global InvalidateUDCaches
+    .global GetMIDR
+    .global GetMPIDR
+    .global GetAffinity
+    .global GetCPUID
+
+// ------------------------------------------------------------
+
+//
+// void EnableCachesEL1(void)
+//
+//    enable Instruction and Data caches
+//
+    .type EnableCachesEL1, "function"
+    .cfi_startproc
+EnableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    orr x0, x0, #SCTLR_ELx_I
+    orr x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+    .type DisableCachesEL1, "function"
+    .cfi_startproc
+DisableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    bic x0, x0, #SCTLR_ELx_I
+    bic x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// void InvalidateUDCaches(void)
+//
+//    Invalidate data and unified caches
+//
+    .type InvalidateUDCaches, "function"
+    .cfi_startproc
+InvalidateUDCaches:
+    // From the Armv8-A Architecture Reference Manual
+
+    dmb  ish                   // ensure all prior inner-shareable accesses have been observed
+
+    mrs  x0, CLIDR_EL1
+    and  w3, w0, #0x07000000   // get 2 x level of coherence
+    lsr  w3, w3, #23
+    cbz  w3, finished
+    mov  w10, #0               // w10 = 2 x cache level
+    mov  w8, #1                // w8 = constant 0b1
+loop_level:
+    add  w2, w10, w10, lsr #1  // calculate 3 x cache level
+    lsr  w1, w0, w2            // extract 3-bit cache type for this level
+    and  w1, w1, #0x7
+    cmp  w1, #2
+    b.lt next_level            // no data or unified cache at this level
+    msr  CSSELR_EL1, x10       // select this cache level
+    isb                        // synchronize change of csselr
+    mrs  x1, CCSIDR_EL1        // read ccsidr
+    and  w2, w1, #7            // w2 = log2(linelen)-4
+    add  w2, w2, #4            // w2 = log2(linelen)
+    ubfx w4, w1, #3, #10       // w4 = max way number, right aligned
+    clz  w5, w4                // w5 = 32-log2(ways), bit position of way in dc operand
+    lsl  w9, w4, w5            // w9 = max way number, aligned to position in dc operand
+    lsl  w16, w8, w5           // w16 = amount to decrement way number per iteration
+loop_way:
+    ubfx w7, w1, #13, #15      // w7 = max set number, right aligned
+    lsl  w7, w7, w2            // w7 = max set number, aligned to position in dc operand
+    lsl  w17, w8, w2           // w17 = amount to decrement set number per iteration
+loop_set:
+    orr  w11, w10, w9          // w11 = combine way number and cache number ...
+    orr  w11, w11, w7          // ... and set number for dc operand
+    dc   isw, x11              // do data cache invalidate by set and way
+    subs w7, w7, w17           // decrement set number
+    b.ge loop_set
+    subs x9, x9, x16           // decrement way number
+    b.ge loop_way
+next_level:
+    add  w10, w10, #2          // increment 2 x cache level
+    cmp  w3, w10
+    b.gt loop_level
+    dsb  sy                    // ensure completion of previous cache maintenance operation
+    isb
+finished:
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// ID Register functions
+//
+
+    .type GetMIDR, "function"
+    .cfi_startproc
+GetMIDR:
+
+    mrs x0, MIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetMPIDR, "function"
+    .cfi_startproc
+GetMPIDR:
+
+    mrs x0, MPIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetAffinity, "function"
+    .cfi_startproc
+GetAffinity:
+
+    mrs x0, MPIDR_EL1
+    ubfx x1, x0, #32, #8
+    bfi  w0, w1, #24, #8
+    ret
+    .cfi_endproc
+
+
+    .type GetCPUID, "function"
+    .cfi_startproc
+GetCPUID:
+
+    mrs x0, MIDR_EL1
+    ubfx    x0, x0, #4, #12 // extract PartNum
+    cmp x0, #0xD0D          // Cortex-A77
+    b.eq DynamIQ
+    cmp x0, #0xD0B          // Cortex-A76
+    b.eq DynamIQ
+    cmp x0, #0xD0A          // Cortex-A75
+    b.eq DynamIQ
+    cmp x0, #0xD05          // Cortex-A55
+    b.eq DynamIQ
+    b Others
+DynamIQ:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+
+Others:
+    mrs x0, MPIDR_EL1
+    ubfx    x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
+    ubfx    x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    add     x0, x1, x2, LSL #2
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h
new file mode 100644
index 00000000..b09079a4
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h
@@ -0,0 +1,103 @@
+/*
+ *
+ * Armv8-A AArch64 common helper functions
+ *
+ * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+
+#ifndef V8_AARCH64_H
+#define V8_AARCH64_H
+
+/*
+ * Parameters for data barriers
+ */
+#define OSHLD   1
+#define OSHST   2
+#define OSH     3
+#define NSHLD   5
+#define NSHST   6
+#define NSH     7
+#define ISHLD   9
+#define ISHST  10
+#define ISH    11
+#define LD     13
+#define ST     14
+#define SY     15
+
+/**********************************************************************/
+
+/*
+ * function prototypes
+ */
+
+/*
+ * void InvalidateUDCaches(void)
+ *   invalidates all Unified and Data Caches
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   <nothing>
+ *
+ * Side Effects
+ *   guarantees that all levels of cache will be invalidated before
+ *   returning to caller
+ */
+void InvalidateUDCaches(void);
+
+/*
+ * unsigned long long EnableCachesEL1(void)
+ *   enables I- and D- caches at EL1
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   New value of SCTLR_EL1
+ *
+ * Side Effects
+ *   context will be synchronised before returning to caller
+ */
+unsigned long long EnableCachesEL1(void);
+
+/*
+ * unsigned long long GetMIDR(void)
+ *   returns the contents of MIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MIDR_EL0
+ */
+unsigned long long GetMIDR(void);
+
+/*
+ * unsigned long long GetMPIDR(void)
+ *   returns the contents of MPIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MPIDR_EL0
+ */
+unsigned long long GetMPIDR(void);
+
+/*
+ * unsigned int GetCPUID(void)
+ *   returns the Aff0 field of MPIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MPIDR_EL0[7:0]
+ */
+unsigned int GetCPUID(void);
+
+#endif
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h
new file mode 100644
index 00000000..ee8834fa
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h
@@ -0,0 +1,128 @@
+//
+// Defines for v8 Memory Model
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_MMU_H
+#define V8_MMU_H
+
+//
+// Translation Control Register fields
+//
+// RGN field encodings
+//
+#define TCR_RGN_NC   0b00
+#define TCR_RGN_WBWA 0b01
+#define TCR_RGN_WT   0b10
+#define TCR_RGN_WBRA 0b11
+
+//
+// Shareability encodings
+//
+#define TCR_SHARE_NONE  0b00
+#define TCR_SHARE_OUTER 0b10
+#define TCR_SHARE_INNER 0b11
+
+//
+// Granule size encodings
+//
+#define TCR_GRANULE_4K  0b00
+#define TCR_GRANULE_64K 0b01
+#define TCR_GRANULE_16K 0b10
+
+//
+// Physical Address sizes
+//
+#define TCR_SIZE_4G   0b000
+#define TCR_SIZE_64G  0b001
+#define TCR_SIZE_1T   0b010
+#define TCR_SIZE_4T   0b011
+#define TCR_SIZE_16T  0b100
+#define TCR_SIZE_256T 0b101
+
+//
+// Translation Control Register fields
+//
+#define TCR_EL1_T0SZ_SHIFT   0
+#define TCR_EL1_EPD0  (1 << 7)
+#define TCR_EL1_IRGN0_SHIFT  8
+#define TCR_EL1_ORGN0_SHIFT 10
+#define TCR_EL1_SH0_SHIFT   12
+#define TCR_EL1_TG0_SHIFT   14
+
+#define TCR_EL1_T1SZ_SHIFT  16
+#define TCR_EL1_A1   (1 << 22)
+#define TCR_EL1_EPD1 (1 << 23)
+#define TCR_EL1_IRGN1_SHIFT 24
+#define TCR_EL1_ORGN1_SHIFT 26
+#define TCR_EL1_SH1_SHIFT   28
+#define TCR_EL1_TG1_SHIFT   30
+#define TCR_EL1_IPS_SHIFT   32
+#define TCR_EL1_AS   (1 << 36)
+#define TCR_EL1_TBI0 (1 << 37)
+#define TCR_EL1_TBI1 (1 << 38)
+
+//
+// Stage 1 Translation Table descriptor fields
+//
+#define TT_S1_ATTR_FAULT (0b00 << 0)
+#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
+#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
+#define TT_S1_ATTR_PAGE  (0b11 << 0) // Level 3
+
+#define TT_S1_ATTR_MATTR_LSB 2
+
+#define TT_S1_ATTR_NS (1 << 5)
+
+#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
+#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
+#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
+#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
+
+#define TT_S1_ATTR_SH_NONE   (0b00 << 8)
+#define TT_S1_ATTR_SH_OUTER  (0b10 << 8)
+#define TT_S1_ATTR_SH_INNER  (0b11 << 8)
+
+#define TT_S1_ATTR_AF (1 << 10)
+#define TT_S1_ATTR_nG (1 << 11)
+
+// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48]
+// and bits[47:16] are bits[47:16] of the output address for a page of memory
+
+#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0
+
+#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0
+
+#define TT_S1_ATTR_CONTIG (1 << 52)
+#define TT_S1_ATTR_PXN    (1 << 53)
+#define TT_S1_ATTR_UXN    (1 << 54)
+
+// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits 
+// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED
+
+#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
+#define TT_S1_MAIR_DEV_nGnRE  0b00000100
+#define TT_S1_MAIR_DEV_nGRE   0b00001000
+#define TT_S1_MAIR_DEV_GRE    0b00001100
+
+//
+// Inner and Outer Normal memory attributes use the same bit patterns
+// Outer attributes just need to be shifted up
+//
+#define TT_S1_MAIR_OUTER_SHIFT 4
+
+#define TT_S1_MAIR_WT_TRANS_RA  0b0010
+
+#define TT_S1_MAIR_WB_TRANS_RA  0b0110
+#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
+
+#define TT_S1_MAIR_WT_RA  0b1010
+
+#define TT_S1_MAIR_WB_RA  0b1110
+#define TT_S1_MAIR_WB_RWA 0b1111
+
+#endif // V8_MMU_H
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h
new file mode 100644
index 00000000..ff96deff
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h
@@ -0,0 +1,115 @@
+//
+// Defines for v8 System Registers
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_SYSTEM_H
+#define V8_SYSTEM_H
+
+//
+// AArch64 SPSR
+//
+#define AARCH64_SPSR_EL3h 0b1101
+#define AARCH64_SPSR_EL3t 0b1100
+#define AARCH64_SPSR_EL2h 0b1001
+#define AARCH64_SPSR_EL2t 0b1000
+#define AARCH64_SPSR_EL1h 0b0101
+#define AARCH64_SPSR_EL1t 0b0100
+#define AARCH64_SPSR_EL0t 0b0000
+#define AARCH64_SPSR_RW (1 << 4)
+#define AARCH64_SPSR_F  (1 << 6)
+#define AARCH64_SPSR_I  (1 << 7)
+#define AARCH64_SPSR_A  (1 << 8)
+#define AARCH64_SPSR_D  (1 << 9)
+#define AARCH64_SPSR_IL (1 << 20)
+#define AARCH64_SPSR_SS (1 << 21)
+#define AARCH64_SPSR_V  (1 << 28)
+#define AARCH64_SPSR_C  (1 << 29)
+#define AARCH64_SPSR_Z  (1 << 30)
+#define AARCH64_SPSR_N  (1 << 31)
+
+//
+// Multiprocessor Affinity Register
+//
+#define MPIDR_EL1_AFF3_LSB 32
+#define MPIDR_EL1_U  (1 << 30)
+#define MPIDR_EL1_MT (1 << 24)
+#define MPIDR_EL1_AFF2_LSB 16
+#define MPIDR_EL1_AFF1_LSB  8
+#define MPIDR_EL1_AFF0_LSB  0
+#define MPIDR_EL1_AFF_WIDTH 8
+
+//
+// Data Cache Zero ID Register
+//
+#define DCZID_EL0_BS_LSB   0
+#define DCZID_EL0_BS_WIDTH 4
+#define DCZID_EL0_DZP_LSB  5
+#define DCZID_EL0_DZP (1 << 5)
+
+//
+// System Control Register
+//
+#define SCTLR_EL1_UCI     (1 << 26)
+#define SCTLR_ELx_EE      (1 << 25)
+#define SCTLR_EL1_E0E     (1 << 24)
+#define SCTLR_ELx_WXN     (1 << 19)
+#define SCTLR_EL1_nTWE    (1 << 18)
+#define SCTLR_EL1_nTWI    (1 << 16)
+#define SCTLR_EL1_UCT     (1 << 15)
+#define SCTLR_EL1_DZE     (1 << 14)
+#define SCTLR_ELx_I       (1 << 12)
+#define SCTLR_EL1_UMA     (1 << 9)
+#define SCTLR_EL1_SED     (1 << 8)
+#define SCTLR_EL1_ITD     (1 << 7)
+#define SCTLR_EL1_THEE    (1 << 6)
+#define SCTLR_EL1_CP15BEN (1 << 5)
+#define SCTLR_EL1_SA0     (1 << 4)
+#define SCTLR_ELx_SA      (1 << 3)
+#define SCTLR_ELx_C       (1 << 2)
+#define SCTLR_ELx_A       (1 << 1)
+#define SCTLR_ELx_M       (1 << 0)
+
+//
+// Architectural Feature Access Control Register
+//
+#define CPACR_EL1_TTA     (1 << 28)
+#define CPACR_EL1_FPEN    (3 << 20)
+
+//
+// Architectural Feature Trap Register
+//
+#define CPTR_ELx_TCPAC (1 << 31)
+#define CPTR_ELx_TTA   (1 << 20)
+#define CPTR_ELx_TFP   (1 << 10)
+
+//
+// Secure Configuration Register
+//
+#define SCR_EL3_TWE  (1 << 13)
+#define SCR_EL3_TWI  (1 << 12)
+#define SCR_EL3_ST   (1 << 11)
+#define SCR_EL3_RW   (1 << 10)
+#define SCR_EL3_SIF  (1 << 9)
+#define SCR_EL3_HCE  (1 << 8)
+#define SCR_EL3_SMD  (1 << 7)
+#define SCR_EL3_EA   (1 << 3)
+#define SCR_EL3_FIQ  (1 << 2)
+#define SCR_EL3_IRQ  (1 << 1)
+#define SCR_EL3_NS   (1 << 0)
+
+//
+// Hypervisor Configuration Register
+//
+#define HCR_EL2_ID   (1 << 33)
+#define HCR_EL2_CD   (1 << 32)
+#define HCR_EL2_RW   (1 << 31)
+#define HCR_EL2_TRVM (1 << 30)
+#define HCR_EL2_HVC  (1 << 29)
+#define HCR_EL2_TDZ  (1 << 28)
+
+#endif // V8_SYSTEM_H
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S
new file mode 100644
index 00000000..f0fcef26
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S
@@ -0,0 +1,69 @@
+//
+// Simple utility routines for baremetal v8 code
+//
+// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//
+// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
+//
+// Zero fill a block of memory
+//   Fill memory pages or similar structures with zeros.
+//   The byte count must be a multiple of the block fill size (16 bytes)
+//
+//  Inputs:
+//    blockPtr - base address of block to fill
+//    nBytes - block size, in bytes
+//
+//  Returns:
+//    pointer to just filled block, NULL if nBytes is
+//  incompatible with block fill size
+//
+    .global ZeroBlock
+    .type ZeroBlock, "function"
+    .cfi_startproc
+ZeroBlock:
+
+    //
+    // we fill data by steam, 16 bytes at a time: check that
+    // blocksize is a multiple of that
+    //
+    ubfx x2, x1, #0, #4
+    cbnz x2, incompatible
+
+    //
+    // we already have one register full of zeros, get another
+    //
+    mov x3, x2
+
+    //
+    // OK, set temporary pointer and away we go
+    //
+    add x0, x0, x1
+
+loop0:
+    subs x1, x1, #16
+    stp  x2, x3, [x0, #-16]!
+    b.ne loop0
+
+    //
+    // that's all - x0 will be back to its start value
+    //
+    ret
+
+    //
+    // parameters are incompatible with block size - return
+    // an indication that this is so
+    //
+incompatible:
+    mov x0,#0
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S
new file mode 100644
index 00000000..9e60e001
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S
@@ -0,0 +1,252 @@
+// ------------------------------------------------------------
+// Armv8-A Vector tables
+//
+// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+    .global c0sync1
+    .global irqHandler
+    .global fiqHandler
+    .global irqFirstLevelHandler
+    .global fiqFirstLevelHandler
+
+    .section  EL1VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el1_vectors:
+c0sync1: B c0sync1
+
+    .balign 0x80
+c0irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr1: B c0serr1
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync1: B cxsync1
+
+    .balign 0x80
+cxirq1: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr1: B cxserr1
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync1: B l64sync1
+
+    .balign 0x80
+l64irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr1: B l64serr1
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync1: B l32sync1
+
+    .balign 0x80
+l32irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr1: B l32serr1
+
+//----------------------------------------------------------------
+
+    .section  EL2VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el2_vectors:
+c0sync2: B c0sync2
+
+    .balign 0x80
+c0irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr2: B c0serr2
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync2: B cxsync2
+
+    .balign 0x80
+cxirq2: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr2: B cxserr2
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync2: B l64sync2
+
+    .balign 0x80
+l64irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr2: B l64serr2
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync2: B l32sync2
+
+    .balign 0x80
+l32irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr2: B l32serr2
+
+//----------------------------------------------------------------
+
+    .section  EL3VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el3_vectors:
+c0sync3: B c0sync3
+
+    .balign 0x80
+c0irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr3: B c0serr3
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync3: B cxsync3
+
+    .balign 0x80
+cxirq3: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr3: B cxserr3
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync3: B l64sync3
+
+    .balign 0x80
+l64irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr3: B l64serr3
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync3: B l32sync3
+
+    .balign 0x80
+l32irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr3: B l32serr3
+
+
+    .section InterruptHandlers, "ax"
+    .balign 4
+
+    .type irqFirstLevelHandler, "function"
+irqFirstLevelHandler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+  BL       irqHandler
+  B        _tx_thread_context_restore
+
+    .type fiqFirstLevelHandler, "function"
+fiqFirstLevelHandler:
+  STP      x29, x30, [sp, #-16]!
+  STP      x18, x19, [sp, #-16]!
+  STP      x16, x17, [sp, #-16]!
+  STP      x14, x15, [sp, #-16]!
+  STP      x12, x13, [sp, #-16]!
+  STP      x10, x11, [sp, #-16]!
+  STP      x8, x9, [sp, #-16]!
+  STP      x6, x7, [sp, #-16]!
+  STP      x4, x5, [sp, #-16]!
+  STP      x2, x3, [sp, #-16]!
+  STP      x0, x1, [sp, #-16]!
+
+  BL       fiqHandler
+
+  LDP      x0, x1, [sp], #16
+  LDP      x2, x3, [sp], #16
+  LDP      x4, x5, [sp], #16
+  LDP      x6, x7, [sp], #16
+  LDP      x8, x9, [sp], #16
+  LDP      x10, x11, [sp], #16
+  LDP      x12, x13, [sp], #16
+  LDP      x14, x15, [sp], #16
+  LDP      x16, x17, [sp], #16
+  LDP      x18, x19, [sp], #16
+  LDP      x29, x30, [sp], #16
+  ERET
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject
new file mode 100644
index 00000000..296685a7
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject
@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1413182734" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1413182734.1169749362" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/sample_threadx_module}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.848667697" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.2024653550" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.1939971857" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1613679555" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.261941817" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.1053841009" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym.598981017" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1953125833" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.1741634605" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1189207744" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.62845631" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.208858280" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.267102905" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" valueType="boolean"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.1148824792" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym.983261594" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.1143700068" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.1591133511" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libs.1533546658" name="Libraries (-l)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="txm"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.1940339274" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="--specs=nosys.specs -nostartfiles -e _txm_module_thread_shell_entry" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.script.124204299" name="Linker script" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.script" useByScannerDiscovery="false" value="..\sample_threadx_module.ld" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch.1660266056" name="Library search path (-L)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch" useByScannerDiscovery="false" valueType="libPaths">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;..\..\txm\Debug&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.extras.896111217" name="Other options (-Xlinker [option])" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.extras" useByScannerDiscovery="false" valueType="stringList">
+                                    									
+                                    <listOptionValue builtIn="false" value="-Map=sample_threadx_module.map"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input.1527380188" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input">
+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.413208540" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.2066918847" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.project b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.project
new file mode 100644
index 00000000..17f6aba3
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx_module</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.arm.debug.ds.nature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s
new file mode 100644
index 00000000..7c454996
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s
@@ -0,0 +1,129 @@
+
+    .text
+    .align 4
+
+    .global _gcc_setup
+_gcc_setup:
+
+	sub 	sp, sp, 16		// Store other preserved registers here
+	str 	x30, [sp]
+
+    ldr     x3, =__FLASH_segment_start__
+    ldr     x4, =__RAM_segment_start__
+    mov     x5,x0
+
+// This is for modules linked to absolute addresses
+// On PIC modules x9 (or r9) will hold the data base address
+    ldr     x9, =__RAM_segment_start__
+
+    /* Copy GOT table. */
+  
+    ldr     x0, =__got_load_start__
+    sub     x0 ,x0, x3
+    add     x0, x0, x5
+    ldr     x1, =__new_got_start__
+    sub     x1, x1, x4
+    add     x1, x1, x9
+    ldr     x2, =__new_got_end__
+    sub     x2, x2, x4
+    add     x2, x2, x9
+
+new_got_setup:
+    cmp     x1, x2          // See if there are more GOT entries
+    beq     got_setup_done  // No, done with GOT setup
+    ldr     x6, [x0]        // Pickup current GOT entry
+    cmp     x6, #0          // Is it 0?
+    beq     address_built   // Yes, just skip the adjustment
+    cmp     x6, x4          // Is it in the code or data area?
+    blt     flash_area      // If less than, it is a code address
+    sub     x6, x6, x4      // Compute offset of data area
+    add     x6, x6, x9      // Build address based on the loaded data address
+    b       address_built   // Finished building address
+flash_area:
+    sub     x6, x6, x3      // Compute offset of code area
+    add     x6, x6, x5      // Build address based on the loaded code address
+address_built:
+    str     x6, [x1]        // Store in new GOT table
+    add     x0, x0, #4      // Move to next entry
+    add     x1, x1, #4      //
+    b       new_got_setup   // Continue at the top of the loop
+got_setup_done:
+
+
+    /* Copy initialised sections into RAM if required. */
+  
+    ldr     x0, =__data_load_start__
+    sub     x0, x0, x3
+    add     x0, x0, x5
+    ldr     x1, =__data_start__
+    sub     x1, x1, x4
+    add     x1, x1, x9
+    ldr     x2, =__data_end__
+    sub     x2, x2, x4
+    add     x2, x2, x9
+    bl      crt0_memory_copy
+  
+    /* Zero bss. */
+    
+    ldr     x0, =__bss_start__
+    sub     x0, x0, x4
+    add     x0, x0, x9
+    ldr     x1, =__bss_end__
+    sub     x1, x1, x4
+    add     x1, x1, x9
+    mov     x2, #0
+    bl      crt0_memory_set
+
+
+    /* Setup heap - not recommended for Threadx but here for compatibility reasons */
+
+    ldr     x0, =__heap_start__
+    sub     x0, x0, x4
+    add     x0, x0, x9
+    ldr     x1, =__heap_end__
+    sub     x1, x1, x4
+    add     x1, x1, x9
+    sub     x1, x1, x0
+    mov     x2, #0
+    str     x2, [x0]
+    add     x0, x0, #4
+    str     x1, [x0]
+    
+	ldr 	x30, [sp]		// Restore other preserved registers
+	add 	sp, sp, 16
+
+    ret	                    // Return to caller
+  
+
+  /* Startup helper functions. */
+
+    .align 4
+crt0_memory_copy:
+    cmp     x0, x1
+    beq     memory_copy_done
+    cmp     x2, x1
+    beq     memory_copy_done
+    sub     x2, x2, x1
+memory_copy_loop:
+    ldrb    w3, [x0]
+    add     x0, x0, #1
+    strb    w3, [x1]
+    add     x1, x1, #1
+    sub     x2, x2, #1
+    cmp     x2, #0
+    bne     memory_copy_loop
+memory_copy_done:
+    ret
+
+crt0_memory_set:
+    cmp     x0, x1
+    beq     memory_set_done
+    str     w2, [x0]
+    add     x0, x0, #1
+    b       crt0_memory_set
+memory_set_done:
+    ret
+
+    /* Setup attibutes of heap section so it doesn't take up room in the elf file */
+    .section .heap, "wa", %nobits
+  
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c
new file mode 100644
index 00000000..3a3f8159
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c
@@ -0,0 +1,467 @@
+/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes 
+   examples of eight threads of different priorities, using a message queue, semaphore, mutex, 
+   event flags group, byte pool, and block pool.  */
+
+/* Specify that this is a module!  */
+
+#define TXM_MODULE
+
+
+/* Include the ThreadX module definitions.  */
+
+#include "txm_module.h"
+
+
+/* Define constants.  */
+
+#define DEMO_BYTE_POOL_SIZE     (1024 * 48)
+#define DEMO_STACK_SIZE         (1024 * 4)
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the pool space in the bss section of the module. ULONG is used to 
+   get the word alignment.  */
+
+ULONG                   demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)];
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               *thread_0;
+TX_THREAD               *thread_1;
+TX_THREAD               *thread_2;
+TX_THREAD               *thread_3;
+TX_THREAD               *thread_4;
+TX_THREAD               *thread_5;
+TX_THREAD               *thread_6;
+TX_THREAD               *thread_7;
+TX_QUEUE                *queue_0;
+TX_SEMAPHORE            *semaphore_0;
+TX_MUTEX                *mutex_0;
+TX_EVENT_FLAGS_GROUP    *event_flags_0;
+TX_BYTE_POOL            *byte_pool_0;
+TX_BLOCK_POOL           *block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter = 0;
+ULONG           thread_1_counter = 0;
+ULONG           thread_1_messages_sent = 0;
+ULONG           thread_2_counter = 0;
+ULONG           thread_2_messages_received = 0;
+ULONG           thread_3_counter = 0;
+ULONG           thread_4_counter = 0;
+ULONG           thread_5_counter = 0;
+ULONG           thread_6_counter = 0;
+ULONG           thread_7_counter = 0;
+ULONG           semaphore_0_puts = 0;
+ULONG           event_0_sets = 0;
+ULONG           queue_0_sends = 0;
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+void  semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
+{
+
+    if (semaphore_ptr == semaphore_0)
+        semaphore_0_puts++;
+}
+
+
+void  event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
+{
+
+    if (event_flag_group_ptr == event_flags_0)
+        event_0_sets++;
+}
+
+
+void  queue_0_notify(TX_QUEUE *queue_ptr)
+{
+
+    if (queue_ptr == queue_0)
+        queue_0_sends++;
+}
+
+
+/* Define the module start function.  */
+
+void    demo_module_start(ULONG id)
+{
+
+UINT    status;
+CHAR    *pointer;
+
+
+    /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within
+       their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting 
+       the control block(s).  */
+    status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
+    while (status != TX_SUCCESS);
+                               
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
+    while (status != TX_SUCCESS);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create the main thread.  */
+    status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 1.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 2.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 3.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 4.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 5.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 6.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 7.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the message queue.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    status = tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+    while (status != TX_SUCCESS);
+
+    status = tx_queue_send_notify(queue_0, queue_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    status = tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
+    while (status != TX_SUCCESS);
+
+    status = tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    status = tx_event_flags_create(event_flags_0, "module event flags 0");
+    while (status != TX_SUCCESS);
+
+    status = tx_event_flags_set_notify(event_flags_0, event_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    status = tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the memory for a small block pool.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    status = tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+    while (status != TX_SUCCESS);
+
+    /* Allocate a block and release the block memory.  */
+    status = tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Release the block back to the pool.  */
+    status = tx_block_release(pointer);
+    while (status != TX_SUCCESS);
+}
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+    
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+       
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld
new file mode 100644
index 00000000..042b59bf
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld
@@ -0,0 +1,195 @@
+SECTIONS
+{
+  __FLASH_segment_start__ = 0x80180000;
+  __RAM_segment_start__   = 0x801A0000;
+
+  __HEAPSIZE__ = 1024;
+
+  __text_load_start__ =  ALIGN(__FLASH_segment_start__ , 4);
+  .text ALIGN(__text_load_start__ , 4) : AT(ALIGN(__text_load_start__, 4))
+  {
+    __preamble_start__ = .;
+    * (.txm_module_preamble)
+    __text_start__ = .;
+    *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table  )
+  }
+  __text_end__ = __text_start__ + SIZEOF(.text);
+
+  __dynsym_load_start__ =  ALIGN(__text_end__ , 4);
+  .dynsym ALIGN(__dynsym_load_start__ , 4) : AT(ALIGN(__dynsym_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.dynsym))
+    KEEP (*(.dynsym*))
+    . = ALIGN(4);
+  }
+  __dynsym_end__ = __dynsym_load_start__ + SIZEOF(.dynsym);
+
+  __dynstr_load_start__ =  ALIGN(__dynsym_end__ , 4);
+  .dynstr ALIGN(__dynstr_load_start__ , 4) : AT(ALIGN(__dynstr_load_start__, 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.dynstr))
+    KEEP (*(.dynstr*))
+    . = ALIGN(4);
+  }
+  __dynstr_end__ = __dynstr_load_start__ + SIZEOF(.dynstr);
+
+  __reldyn_load_start__ =  ALIGN(__dynstr_end__ , 4);
+  .rel.dyn ALIGN(__reldyn_load_start__ , 4) : AT(ALIGN(__reldyn_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.rel.dyn))
+    KEEP (*(.rel.dyn*))
+    . = ALIGN(4);
+  }
+  __reldyn_end__ = __reldyn_load_start__ + SIZEOF(.rel.dyn);
+
+  __relplt_load_start__ =  ALIGN(__reldyn_end__ , 4);
+  .rel.plt ALIGN(__relplt_load_start__ , 4) : AT(ALIGN(__relplt_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.rel.plt))
+    KEEP (*(.rel.plt*))
+    . = ALIGN(4);
+  }
+  __relplt_end__ = __relplt_load_start__ + SIZEOF(.rel.plt);
+
+  __plt_load_start__ =  ALIGN(__relplt_end__ , 4);
+  .plt ALIGN(__plt_load_start__ , 4) : AT(ALIGN(__plt_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.plt))
+    KEEP (*(.plt*))
+    . = ALIGN(4);
+  }
+  __plt_end__ = __plt_load_start__ + SIZEOF(.plt);
+
+  __interp_load_start__ =  ALIGN(__plt_end__ , 4);
+  .interp ALIGN(__interp_load_start__ , 4) : AT(ALIGN(__interp_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.interp))
+    KEEP (*(.interp*))
+    . = ALIGN(4);
+  }
+  __interp_end__ = __interp_load_start__ + SIZEOF(.interp);
+
+  __hash_load_start__ =  ALIGN(__interp_end__ , 4);
+  .hash ALIGN(__hash_load_start__ , 4) : AT(ALIGN(__hash_load_start__, 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.hash))
+    KEEP (*(.hash*))
+    . = ALIGN(4);
+  }
+  __hash_end__ = __hash_load_start__ + SIZEOF(.hash);
+
+  __dtors_load_start__ = ALIGN(__hash_end__ , 4);
+  .dtors ALIGN(__hash_end__ , 4) : AT(ALIGN(__hash_end__ , 4))
+  {
+    __dtors_start__ = .;
+    KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))
+  }
+  __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
+
+  __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
+  .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
+  {
+    __ctors_start__ = .;
+    KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))
+  }
+  __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
+
+  __got_load_start__ = ALIGN(__ctors_end__ , 4);
+  .got ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
+  {
+    . = ALIGN(4);
+    _sgot = .;
+    KEEP (*(.got))
+    KEEP (*(.got*))
+    . = ALIGN(4);
+    _egot = .;
+  } 
+  __got_end__ =  __got_load_start__ + SIZEOF(.got);
+
+  __rodata_load_start__ = ALIGN(__got_end__ , 4);
+  .rodata ALIGN(__got_end__ , 4) : AT(ALIGN(__got_end__ , 4))
+  {
+    __rodata_start__ = .;
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+  }
+  __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
+ 
+  __code_size__ =  __rodata_end__ - __FLASH_segment_start__;
+
+  __fast_load_start__ = ALIGN(__rodata_end__ , 4);
+
+  __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
+
+  __new_got_start__ = ALIGN(__RAM_segment_start__ , 4);
+
+  __new_got_end__ =  __new_got_start__ + SIZEOF(.got);
+
+  .fast ALIGN(__new_got_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
+  {
+    __fast_start__ = .;
+    *(.fast .fast.*)
+  }
+  __fast_end__ = __fast_start__ + SIZEOF(.fast);
+
+  .fast_run ALIGN(__fast_end__ , 4) (NOLOAD) :
+  {
+    __fast_run_start__ = .;
+    . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
+  }
+  __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
+
+  __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
+  .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
+  {
+    __data_start__ = .;
+    *(.data .data.* .gnu.linkonce.d.*)
+  }
+  __data_end__ = __data_start__ + SIZEOF(.data);
+
+  __data_load_end__ = __data_load_start__ + SIZEOF(.data);
+
+  __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data);
+
+  .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
+  {
+    __data_run_start__ = .;
+    . = MAX(__data_run_start__ + SIZEOF(.data), .);
+  }
+  __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
+
+  __bss_load_start__ = ALIGN(__data_run_end__ , 4);
+  .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
+  {
+    __bss_start__ = .;
+    *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+  }
+  __bss_end__ = __bss_start__ + SIZEOF(.bss);
+
+  __non_init_load_start__ = ALIGN(__bss_end__ , 4);
+  .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
+  {
+    __non_init_start__ = .;
+    *(.non_init .non_init.*)
+  }
+  __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
+
+  __heap_load_start__ = ALIGN(__non_init_end__ , 4);
+  .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
+  {
+    __heap_start__ = .;
+    *(.heap)
+    . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
+  }
+  __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+  __data_size__ =  __heap_end__ - __RAM_segment_start__;
+
+}
+
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S
new file mode 100644
index 00000000..cce29ef8
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S
@@ -0,0 +1,53 @@
+    .section .txm_module_preamble
+    .align 4
+    
+    // External references
+    .global  _txm_module_thread_shell_entry
+    .global  _txm_module_callback_request_thread_entry
+    .global  demo_module_start
+
+    .global __txm_module_preamble
+__txm_module_preamble:
+    .dc.l   0x4D4F4455                                          // Module ID
+    .dc.l   0x6                                                 // Module Major Version
+    .dc.l   0x1                                                 // Module Minor Version
+    .dc.l   32                                                  // Module Preamble Size in 32-bit words
+    .dc.l   0x12345678                                          // Module ID (application defined)
+    .dc.l   0x02000000                                          // Module Properties where:
+                                                                //   Bits 31-24: Compiler ID
+                                                                //           0 -> IAR
+                                                                //           1 -> ARM
+                                                                //           2 -> GNU
+                                                                //   Bit 0:  0 -> Privileged mode execution
+                                                                //           1 -> User mode execution
+                                                                //   Bit 1:  0 -> No MPU protection
+                                                                //           1 -> MPU protection (must have user mode selected)
+                                                                //   Bit 2:  0 -> Disable shared/external memory access
+                                                                //           1 -> Enable shared/external memory access
+    .dc.l   _txm_module_thread_shell_entry                      // Module Shell Entry Point
+    .dc.l   demo_module_start                                   // Module Start Thread Entry Point
+    .dc.l   0                                                   // Module Stop Thread Entry Point
+    .dc.l   1                                                   // Module Start/Stop Thread Priority
+    .dc.l   4096                                                // Module Start/Stop Thread Stack Size
+    .dc.l   _txm_module_callback_request_thread_entry           // Module Callback Thread Entry
+    .dc.l   1                                                   // Module Callback Thread Priority
+    .dc.l   4096                                                // Module Callback Thread Stack Size
+    .dc.l   __code_size__                                       // Module Code Size
+    .dc.l   __data_size__                                       // Module Data Size
+    .dc.l   0                                                   // Reserved 0
+    .dc.l   0                                                   // Reserved 1
+    .dc.l   0                                                   // Reserved 2
+    .dc.l   0                                                   // Reserved 3
+    .dc.l   0                                                   // Reserved 4
+    .dc.l   0                                                   // Reserved 5
+    .dc.l   0                                                   // Reserved 6
+    .dc.l   0                                                   // Reserved 7
+    .dc.l   0                                                   // Reserved 8
+    .dc.l   0                                                   // Reserved 9
+    .dc.l   0                                                   // Reserved 10
+    .dc.l   0                                                   // Reserved 11
+    .dc.l   0                                                   // Reserved 12
+    .dc.l   0                                                   // Reserved 13
+    .dc.l   0                                                   // Reserved 14
+    .dc.l   0                                                   // Reserved 15
+
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject
new file mode 100644
index 00000000..79e120b4
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject
@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.33749088" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.33749088.1343346543" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/sample_threadx_module_manager}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.910370896" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1331565505" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.831465095" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/sample_threadx_module_manager/inc_common_module_manager}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym.1613866201" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1769854265" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.268949876" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.1607040325" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.warnings.all.559759568" name="All warnings (-Wall)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.warnings.all" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.301538030" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.64294854" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1835980884" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.788212214" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                							
+                            </tool>
+                            							
+                            <tool command="aarch64-elf-gcc.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.1804365799" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.490655419" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" valueType="boolean"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.694327385" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym.1950316412" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.883450564" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.891273559" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libs.654731770" name="Libraries (-l)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="tx"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch.764636049" name="Library search path (-L)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch" useByScannerDiscovery="false" valueType="libPaths">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;..\..\tx\Debug&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.script.1545347593" name="Linker script" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.script" useByScannerDiscovery="false" value="..\sample_threadx_module_manager.ld" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.846498594" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="--specs=rdimon.specs" valueType="string"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input.1672586300" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input">
+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.2107716357" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.1675872554" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.release.base.262471578">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" name="Release" parent="com.arm.eclipse.build.config.v6.exe.release.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.release.base.262471578." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6.2039978271" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6">
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6.2039978271.1401365679" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx_module_manager}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.152908166" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2113724202" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.1064912621" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
+                                								
+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.274442412" superClass="com.arm.tool.c.compiler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.857388488" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.703057645" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.494258017" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.2016749997" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1332640632" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1069857726" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx_module_manager.com.arm.eclipse.build.project.v6.exe.1027551600" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        		
+        <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.exe.debug.base.515451048;com.arm.eclipse.build.config.v6.exe.debug.base.515451048.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1331565505;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.301538030">
+            			
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+            		
+        </scannerConfigBuildInfo>
+        	
+    </storageModule>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.project b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.project
new file mode 100644
index 00000000..310289aa
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.project
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx_module_manager</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_common_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
+		</link>
+		<link>
+			<name>src_common_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h
new file mode 100644
index 00000000..23bc7fd8
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h
@@ -0,0 +1,561 @@
+/*
+ * GICv3.h - data types and function prototypes for GICv3 utility routines
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_h
+#define GICV3_h
+
+#include <stdint.h>
+
+/*
+ * extra flags for GICD enable
+ */
+typedef enum
+{
+    gicdctlr_EnableGrp0 = (1 << 0),
+    gicdctlr_EnableGrp1NS = (1 << 1),
+    gicdctlr_EnableGrp1A = (1 << 1),
+    gicdctlr_EnableGrp1S = (1 << 2),
+    gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
+    gicdctlr_ARE_S = (1 << 4),	/* Enable Secure state affinity routing */
+    gicdctlr_ARE_NS = (1 << 5),	/* Enable Non-Secure state affinity routing */
+    gicdctlr_DS = (1 << 6),	/* Disable Security support */
+    gicdctlr_E1NWF = (1 << 7)	/* Enable "1-of-N" wakeup model */
+} GICDCTLRFlags_t;
+
+/*
+ * modes for SPI routing
+ */
+typedef enum
+{
+    gicdirouter_ModeSpecific = 0,
+    gicdirouter_ModeAny = (1 << 31)
+} GICDIROUTERBits_t;
+
+typedef enum
+{
+    gicdicfgr_Level = 0,
+    gicdicfgr_Edge = (1 << 1)
+} GICDICFGRBits_t;
+
+typedef enum
+{
+    gicigroupr_G0S = 0,
+    gicigroupr_G1NS = (1 << 0),
+    gicigroupr_G1S = (1 << 2)
+} GICIGROUPRBits_t;
+
+typedef enum
+{
+    gicrwaker_ProcessorSleep = (1 << 1),
+    gicrwaker_ChildrenAsleep = (1 << 2)
+} GICRWAKERBits_t;
+
+/**********************************************************************/
+
+/*
+ * Utility macros & functions
+ */
+#define RANGE_LIMIT(x)		((sizeof(x) / sizeof((x)[0])) - 1)
+
+static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
+					 uint32_t aff1, uint32_t aff0)
+{
+    /*
+     * only need to cast aff3 to get type promotion for all affinities
+     */
+    return ((((uint64_t)aff3 & 0xff) << 32) |
+	    ((aff2 & 0xff) << 16) |
+	    ((aff1 & 0xff) << 8) | aff0);
+}
+
+/**********************************************************************/
+
+/*
+ * GIC Distributor Function Prototypes
+ */
+
+/*
+ * ConfigGICD - configure GIC Distributor prior to enabling it
+ *
+ * Inputs:
+ *
+ *  control - control flags
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void ConfigGICD(GICDCTLRFlags_t flags);
+
+/*
+ * EnableGICD - top-level enable for GIC Distributor
+ *
+ * Inputs:
+ *
+ *  flags - new control flags to set
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void EnableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * DisableGICD - top-level disable for GIC Distributor
+ *
+ * Inputs
+ *
+ *  flags - control flags to clear
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void DisableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * SyncAREinGICD - synchronise GICD Address Routing Enable bits
+ *
+ * Inputs
+ *
+ *  flags - absolute flag bits to set in GIC Distributor
+ *
+ *  dosync - flag whether to wait for ARE bits to match passed
+ *      flag field (dosync = true), or whether to set absolute
+ *      flag bits (dosync = false)
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ * This function is used to resolve a race in an MP system whereby secondary
+ * CPUs cannot reliably program all Redistributor registers until the
+ * primary CPU has enabled Address Routing. The primary CPU will call this
+ * function with dosync = false, while the secondaries will call it with
+ * dosync = true.
+ */
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
+
+/*
+ * EnableSPI - enable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnableSPI(uint32_t id);
+
+/*
+ * DisableSPI - disable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisableSPI(uint32_t id);
+
+/*
+ * SetSPIPriority - configure the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetSPIPriority(uint32_t id, uint32_t priority);
+
+/*
+ * GetSPIPriority - determine the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  interrupt priority in the range 0 - 0xff
+ */
+uint32_t GetSPIPriority(uint32_t id);
+
+/*
+ * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  affinity - prepacked "dotted quad" affinity routing. NOTE: use the
+ *      gicv3PackAffinity() helper routine to generate this input
+ *
+ *  mode - select routing mode (specific affinity, or any recipient)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
+
+/*
+ * GetSPIRoute - read ARE-enabled interrupt routing information
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  routing configuration
+ */
+uint64_t GetSPIRoute(uint32_t id);
+
+/*
+ * SetSPITarget - configure the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ *  target - 8-bit target bitmap
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPITarget(uint32_t id, uint32_t target);
+
+/*
+ * GetSPITarget - read the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *  8-bit target bitmap
+ */
+uint32_t GetSPITarget(uint32_t id);
+
+/*
+ * ConfigureSPI - setup an interrupt as edge- or level-triggered
+ *
+ * Inputs
+ *
+ *   id - interrupt identifier
+ *
+ *   config - desired configuration
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
+
+/*
+ * SetSPIPending - mark an interrupt as pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetSPIPending(uint32_t id);
+
+/*
+ * ClearSPIPending - mark an interrupt as not pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearSPIPending(uint32_t id);
+
+/*
+ * GetSPIPending - query whether an interrupt is pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetSPIPending(uint32_t id);
+
+/*
+ * SetSPISecurity - mark a shared peripheral interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityBlock - mark a block of 32 shared peripheral
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  block - which block to mark (e.g. 1 = Ints 32-63)
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityAll - mark all shared peripheral interrupts
+ *     as security <group>
+ *
+ * Inputs:
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityAll(GICIGROUPRBits_t group);
+
+/**********************************************************************/
+
+/*
+ * GIC Re-Distributor Function Prototypes
+ *
+ * The model for calling Redistributor functions is that, rather than
+ * identifying the target redistributor with every function call, the
+ * SelectRedistributor() function is used to identify which redistributor
+ * is to be used for all functions until a different redistributor is
+ * explicitly selected
+ */
+
+/*
+ * WakeupGICR - wake up a Redistributor
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to wakeup
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void WakeupGICR(uint32_t gicr);
+
+/*
+ * EnablePrivateInt - enable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * DisablePrivateInt - disable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
+
+/*
+ * GetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *   Int priority
+ */
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
+
+#endif /* ndef GICV3_h */
+
+/* EOF GICv3.h */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h
new file mode 100644
index 00000000..0928d14c
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h
@@ -0,0 +1,113 @@
+//
+// Aliases for GICv3 registers
+//
+// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef GICV3_ALIASES_H
+#define GICV3_ALIASES_H
+
+#ifndef __clang__
+
+/*
+ * Mapping of MSR and MRS to physical and virtual CPU interface registers
+ *
+ * Arm Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3.0 and version 4.0
+ * Table 8-5
+ */
+#define ICC_AP0R0_EL1       S3_0_C12_C8_4
+#define ICC_AP0R1_EL1       S3_0_C12_C8_5
+#define ICC_AP0R2_EL1       S3_0_C12_C8_6
+#define ICC_AP0R3_EL1       S3_0_C12_C8_7
+
+#define ICC_AP1R0_EL1       S3_0_C12_C9_0
+#define ICC_AP1R1_EL1       S3_0_C12_C9_1
+#define ICC_AP1R2_EL1       S3_0_C12_C9_2
+#define ICC_AP1R3_EL1       S3_0_C12_C9_3
+
+#define ICC_ASGI1R_EL1      S3_0_C12_C11_6
+
+#define ICC_BPR0_EL1        S3_0_C12_C8_3
+#define ICC_BPR1_EL1        S3_0_C12_C12_3
+
+#define ICC_CTLR_EL1        S3_0_C12_C12_4
+#define ICC_CTLR_EL3        S3_6_C12_C12_4
+
+#define ICC_DIR_EL1         S3_0_C12_C11_1
+
+#define ICC_EOIR0_EL1       S3_0_C12_C8_1
+#define ICC_EOIR1_EL1       S3_0_C12_C12_1
+
+#define ICC_HPPIR0_EL1      S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1      S3_0_C12_C12_2
+
+#define ICC_IAR0_EL1        S3_0_C12_C8_0
+#define ICC_IAR1_EL1        S3_0_C12_C12_0
+
+#define ICC_IGRPEN0_EL1     S3_0_C12_C12_6
+#define ICC_IGRPEN1_EL1     S3_0_C12_C12_7
+#define ICC_IGRPEN1_EL3     S3_6_C12_C12_7
+
+#define ICC_PMR_EL1         S3_0_C4_C6_0
+#define ICC_RPR_EL1         S3_0_C12_C11_3
+
+#define ICC_SGI0R_EL1       S3_0_C12_C11_7
+#define ICC_SGI1R_EL1       S3_0_C12_C11_5
+
+#define ICC_SRE_EL1         S3_0_C12_C12_5
+#define ICC_SRE_EL2         S3_4_C12_C9_5
+#define ICC_SRE_EL3         S3_6_C12_C12_5
+
+/*
+ * Mapping of MSR and MRS to virtual interface control registers
+ *
+ * Arm Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3.0 and version 4.0
+ * Table 8-6
+ */
+#define ICH_AP0R0_EL2       S3_4_C12_C8_0
+#define ICH_AP0R1_EL2       S3_4_C12_C8_1
+#define ICH_AP0R2_EL2       S3_4_C12_C8_2
+#define ICH_AP0R3_EL2       S3_4_C12_C8_3
+
+#define ICH_AP1R0_EL2       S3_4_C12_C9_0
+#define ICH_AP1R1_EL2       S3_4_C12_C9_1
+#define ICH_AP1R2_EL2       S3_4_C12_C9_2
+#define ICH_AP1R3_EL2       S3_4_C12_C9_3
+
+#define ICH_HCR_EL2         S3_4_C12_C11_0
+
+#define ICH_VTR_EL2         S3_4_C12_C11_1
+
+#define ICH_MISR_EL2        S3_4_C12_C11_2
+
+#define ICH_EISR_EL2        S3_4_C12_C11_3
+
+#define ICH_ELRSR_EL2       S3_4_C12_C11_5
+
+#define ICH_VMCR_EL2        S3_4_C12_C11_7
+
+#define ICH_LR0_EL2         S3_4_C12_C12_0
+#define ICH_LR1_EL2         S3_4_C12_C12_1
+#define ICH_LR2_EL2         S3_4_C12_C12_2
+#define ICH_LR3_EL2         S3_4_C12_C12_3
+#define ICH_LR4_EL2         S3_4_C12_C12_4
+#define ICH_LR5_EL2         S3_4_C12_C12_5
+#define ICH_LR6_EL2         S3_4_C12_C12_6
+#define ICH_LR7_EL2         S3_4_C12_C12_7
+#define ICH_LR8_EL2         S3_4_C12_C13_0
+#define ICH_LR9_EL2         S3_4_C12_C13_1
+#define ICH_LR10_EL2        S3_4_C12_C13_2
+#define ICH_LR11_EL2        S3_4_C12_C13_3
+#define ICH_LR12_EL2        S3_4_C12_C13_4
+#define ICH_LR13_EL2        S3_4_C12_C13_5
+#define ICH_LR14_EL2        S3_4_C12_C13_6
+#define ICH_LR15_EL2        S3_4_C12_C13_7
+
+#endif /* not __clang__ */
+
+#endif /* GICV3_ALIASES */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h
new file mode 100644
index 00000000..2b8a2d3e
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h
@@ -0,0 +1,254 @@
+/*
+ * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_gicc_h
+#define GICV3_gicc_h
+
+#include "GICv3_aliases.h"
+
+#define stringify_no_expansion(x) #x
+#define stringify(x) stringify_no_expansion(x)
+
+/**********************************************************************/
+
+typedef enum
+{
+    sreSRE = (1 << 0),
+    sreDFB = (1 << 1),
+    sreDIB = (1 << 2),
+    sreEnable = (1 << 3)
+} ICC_SREBits_t;
+
+static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL2(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    igrpEnable = (1 << 0),
+    igrpEnableGrp1NS = (1 << 0),
+    igrpEnableGrp1S = (1 << 2)
+} ICC_IGRPBits_t;
+
+static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    ctlrCBPR = (1 << 0),
+    ctlrCBPR_EL1S = (1 << 0),
+    ctlrEOImode = (1 << 1),
+    ctlrCBPR_EL1NS = (1 << 1),
+    ctlrEOImode_EL3 = (1 << 2),
+    ctlrEOImode_EL1S = (1 << 3),
+    ctlrEOImode_EL1NS = (1 << 4),
+    ctlrRM = (1 << 5),
+    ctlrPMHE = (1 << 6)
+} ICC_CTLRBits_t;
+
+static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
+{
+    asm("msr  "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
+{
+    asm("msr  "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+static inline uint64_t getICC_IAR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_IAR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_EOIR0(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_EOIR1(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_DIR(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_PMR(uint32_t priority)
+{
+    asm("msr  "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority));
+}
+
+static inline void setICC_BPR0(uint32_t binarypoint)
+{
+    asm("msr  "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline void setICC_BPR1(uint32_t binarypoint)
+{
+    asm("msr  "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline uint64_t getICC_BPR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_BPR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_RPR(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    sgirIRMTarget = 0,
+    sgirIRMAll = (1ull << 40)
+} ICC_SGIRBits_t;
+
+static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+#endif /* ndef GICV3_gicc_h */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c
new file mode 100644
index 00000000..2cf9e843
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c
@@ -0,0 +1,339 @@
+/*
+ * GICv3_gicd.c - generic driver code for GICv3 distributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include <stdint.h>
+
+#include "GICv3.h"
+
+typedef struct
+{
+        volatile uint32_t GICD_CTLR;              // +0x0000
+  const volatile uint32_t GICD_TYPER;             // +0x0004
+  const volatile uint32_t GICD_IIDR;              // +0x0008
+
+  const volatile uint32_t padding0;               // +0x000c
+
+        volatile uint32_t GICD_STATUSR;           // +0x0010
+
+  const volatile uint32_t padding1[3];            // +0x0014
+
+        volatile uint32_t IMP_DEF[8];             // +0x0020
+
+        volatile uint32_t GICD_SETSPI_NSR;        // +0x0040
+  const volatile uint32_t padding2;               // +0x0044
+        volatile uint32_t GICD_CLRSPI_NSR;        // +0x0048
+  const volatile uint32_t padding3;               // +0x004c
+        volatile uint32_t GICD_SETSPI_SR;         // +0x0050
+  const volatile uint32_t padding4;               // +0x0054
+        volatile uint32_t GICD_CLRSPI_SR;         // +0x0058
+
+  const volatile uint32_t padding5[3];            // +0x005c
+
+        volatile uint32_t GICD_SEIR;              // +0x0068
+
+  const volatile uint32_t padding6[5];            // +0x006c
+
+        volatile uint32_t GICD_IGROUPR[32];       // +0x0080
+
+        volatile uint32_t GICD_ISENABLER[32];     // +0x0100
+        volatile uint32_t GICD_ICENABLER[32];     // +0x0180
+        volatile uint32_t GICD_ISPENDR[32];       // +0x0200
+        volatile uint32_t GICD_ICPENDR[32];       // +0x0280
+        volatile uint32_t GICD_ISACTIVER[32];     // +0x0300
+        volatile uint32_t GICD_ICACTIVER[32];     // +0x0380
+
+        volatile uint8_t  GICD_IPRIORITYR[1024];  // +0x0400
+        volatile uint8_t  GICD_ITARGETSR[1024];   // +0x0800
+        volatile uint32_t GICD_ICFGR[64];         // +0x0c00
+        volatile uint32_t GICD_IGRPMODR[32];      // +0x0d00
+  const volatile uint32_t padding7[32];           // +0x0d80
+        volatile uint32_t GICD_NSACR[64];         // +0x0e00
+
+        volatile uint32_t GICD_SGIR;              // +0x0f00
+
+  const volatile uint32_t padding8[3];            // +0x0f04
+
+        volatile uint32_t GICD_CPENDSGIR[4];      // +0x0f10
+        volatile uint32_t GICD_SPENDSGIR[4];      // +0x0f20
+
+  const volatile uint32_t padding9[52];           // +0x0f30
+  const volatile uint32_t padding10[5120];        // +0x1000
+
+        volatile uint64_t GICD_IROUTER[1024];     // +0x6000
+} GICv3_distributor;
+
+/*
+ * use the scatter file to place GICD
+ */
+GICv3_distributor __attribute__((section(".gicd"))) gicd;
+
+void ConfigGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR = flags;
+}
+
+void EnableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR |= flags;
+}
+
+void DisableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR &= ~flags;
+}
+
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
+{
+    if (dosync)
+    {
+	const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
+	const uint32_t tval = flags & tmask;
+
+	while ((gicd.GICD_CTLR & tmask) != tval)
+	    continue;
+    }
+    else
+	gicd.GICD_CTLR = flags;
+}
+
+void EnableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ISENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void DisableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ICENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void SetSPIPriority(uint32_t id, uint32_t priority)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    gicd.GICD_IPRIORITYR[bank] = priority;
+}
+
+uint32_t GetSPIPriority(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
+}
+
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
+}
+
+uint64_t GetSPIRoute(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    return gicd.GICD_IROUTER[bank];
+}
+
+void SetSPITarget(uint32_t id, uint32_t target)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    gicd.GICD_ITARGETSR[bank] = target;
+}
+
+uint32_t GetSPITarget(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    /*
+     * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
+     * target bitmap per register
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
+}
+
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
+{
+    uint32_t bank, tmp;
+
+    /*
+     * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
+     * configuration per register
+     */
+    bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
+    config &= 3;
+
+    id = (id & 0xf) << 1;
+
+    tmp = gicd.GICD_ICFGR[bank];
+    tmp &= ~(3 << id);
+    tmp |= config << id;
+    gicd.GICD_ICFGR[bank] = tmp;
+}
+
+void SetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ISPENDR[bank] = 1 << id;
+}
+
+void ClearSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ICPENDR[bank] = 1 << id;
+}
+
+uint32_t GetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    return (gicd.GICD_ICPENDR[bank] >> id) & 1;
+}
+
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
+{
+    uint32_t bank, groupmod;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicd.GICD_IGROUPR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGROUPR[bank] &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicd.GICD_IGRPMODR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
+}
+
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
+{
+    uint32_t groupmod;
+    const uint32_t nbits = (sizeof group * 8) - 1;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
+
+    /*
+     * get each bit of group config duplicated over all 32-bits in a word
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicd.GICD_IGROUPR[block] = group;
+    gicd.GICD_IGRPMODR[block] = groupmod;
+}
+
+void SetSPISecurityAll(GICIGROUPRBits_t group)
+{
+    uint32_t block;
+
+    /*
+     * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
+     * want to iterate over all blocks excluding 0 (which are the
+     * SGI/PPI interrupts, and not relevant here)
+     */
+    for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
+	SetSPISecurityBlock(block, group);
+}
+
+/* EOF GICv3_gicd.c */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c
new file mode 100644
index 00000000..b0d22c40
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c
@@ -0,0 +1,308 @@
+/*
+ * GICv3_gicr.c - generic driver code for GICv3 redistributor
+ *
+ * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include "GICv3.h"
+
+/*
+ * physical LPI Redistributor register map
+ */
+typedef struct
+{
+        volatile uint32_t GICR_CTLR;             // +0x0000 - RW - Redistributor Control Register
+  const volatile uint32_t GICR_IIDR;             // +0x0004 - RO - Implementer Identification Register
+  const volatile uint32_t GICR_TYPER[2];         // +0x0008 - RO - Redistributor Type Register
+        volatile uint32_t GICR_STATUSR;          // +0x0010 - RW - Error Reporting Status Register, optional
+        volatile uint32_t GICR_WAKER;            // +0x0014 - RW - Redistributor Wake Register
+  const volatile uint32_t padding1[2];           // +0x0018 - RESERVED
+#ifndef USE_GIC600
+        volatile uint32_t IMPDEF1[8];            // +0x0020 - ?? - IMPLEMENTATION DEFINED
+#else
+        volatile uint32_t GICR_FCTLR;            // +0x0020 - RW - Function Control Register
+        volatile uint32_t GICR_PWRR;             // +0x0024 - RW - Power Management Control Register
+        volatile uint32_t GICR_CLASS;            // +0x0028 - RW - Class Register
+  const volatile uint32_t padding2[5];           // +0x002C - RESERVED
+#endif
+        volatile uint64_t GICR_SETLPIR;          // +0x0040 - WO - Set LPI Pending Register
+        volatile uint64_t GICR_CLRLPIR;          // +0x0048 - WO - Clear LPI Pending Register
+  const volatile uint32_t padding3[8];           // +0x0050 - RESERVED
+        volatile uint64_t GICR_PROPBASER;        // +0x0070 - RW - Redistributor Properties Base Address Register
+        volatile uint64_t GICR_PENDBASER;        // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
+  const volatile uint32_t padding4[8];           // +0x0080 - RESERVED
+        volatile uint64_t GICR_INVLPIR;          // +0x00A0 - WO - Redistributor Invalidate LPI Register
+  const volatile uint32_t padding5[2];           // +0x00A8 - RESERVED
+        volatile uint64_t GICR_INVALLR;          // +0x00B0 - WO - Redistributor Invalidate All Register
+  const volatile uint32_t padding6[2];           // +0x00B8 - RESERVED
+        volatile uint64_t GICR_SYNCR;            // +0x00C0 - RO - Redistributor Synchronize Register
+  const volatile uint32_t padding7[2];           // +0x00C8 - RESERVED
+  const volatile uint32_t padding8[12];          // +0x00D0 - RESERVED
+        volatile uint64_t IMPDEF2;               // +0x0100 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding9[2];           // +0x0108 - RESERVED
+        volatile uint64_t IMPDEF3;               // +0x0110 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding10[2];          // +0x0118 - RESERVED
+} GICv3_redistributor_RD;
+
+/*
+ * SGI and PPI Redistributor register map
+ */
+typedef struct
+{
+  const volatile uint32_t padding1[32];          // +0x0000 - RESERVED
+        volatile uint32_t GICR_IGROUPR0;         // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
+  const volatile uint32_t padding2[31];          // +0x0084 - RESERVED
+        volatile uint32_t GICR_ISENABLER;        // +0x0100 - RW - Interrupt Set-Enable Registers
+  const volatile uint32_t padding3[31];          // +0x0104 - RESERVED
+        volatile uint32_t GICR_ICENABLER;        // +0x0180 - RW - Interrupt Clear-Enable Registers
+  const volatile uint32_t padding4[31];          // +0x0184 - RESERVED
+        volatile uint32_t GICR_ISPENDR;          // +0x0200 - RW - Interrupt Set-Pending Registers
+  const volatile uint32_t padding5[31];          // +0x0204 - RESERVED
+        volatile uint32_t GICR_ICPENDR;          // +0x0280 - RW - Interrupt Clear-Pending Registers
+  const volatile uint32_t padding6[31];          // +0x0284 - RESERVED
+        volatile uint32_t GICR_ISACTIVER;        // +0x0300 - RW - Interrupt Set-Active Register
+  const volatile uint32_t padding7[31];          // +0x0304 - RESERVED
+        volatile uint32_t GICR_ICACTIVER;        // +0x0380 - RW - Interrupt Clear-Active Register
+  const volatile uint32_t padding8[31];          // +0x0184 - RESERVED
+        volatile uint8_t  GICR_IPRIORITYR[32];   // +0x0400 - RW - Interrupt Priority Registers
+  const volatile uint32_t padding9[504];         // +0x0420 - RESERVED
+        volatile uint32_t GICR_ICnoFGR[2];       // +0x0C00 - RW - Interrupt Configuration Registers
+  const volatile uint32_t padding10[62];         // +0x0C08 - RESERVED
+        volatile uint32_t GICR_IGRPMODR0;        // +0x0D00 - RW - ????
+  const volatile uint32_t padding11[63];         // +0x0D04 - RESERVED
+        volatile uint32_t GICR_NSACR;            // +0x0E00 - RW - Non-Secure Access Control Register
+} GICv3_redistributor_SGI;
+
+/*
+ * We have a multiplicity of GIC Redistributors; on the GIC-AEM and
+ * GIC-500 they are arranged as one 128KB region per redistributor: one
+ * 64KB page of GICR LPI registers, and one 64KB page of GICR Private
+ * Int registers
+ */
+typedef struct
+{
+    union
+    {
+        GICv3_redistributor_RD RD_base;
+        uint8_t padding[64 * 1024];
+    } RDblock;
+
+    union
+    {
+        GICv3_redistributor_SGI SGI_base;
+        uint8_t padding[64 * 1024];
+    } SGIblock;
+} GICv3_GICR;
+
+/*
+ * use the scatter file to place GIC Redistributor base address
+ *
+ * although this code doesn't know how many Redistributor banks
+ * a particular system will have, we declare gicrbase as an array
+ * to avoid unwanted compiler optimisations when calculating the
+ * base of a particular Redistributor bank
+ */
+static const GICv3_GICR gicrbase[2] __attribute__((section (".gicr")));
+
+/**********************************************************************/
+
+/*
+ * utility functions to calculate base of a particular
+ * Redistributor bank
+ */
+
+static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
+{
+    GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
+
+    return &((arraybase + gicr)->RDblock.RD_base);
+}
+
+static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
+{
+    GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
+
+    return &(arraybase[gicr].SGIblock.SGI_base);
+}
+
+/**********************************************************************/
+
+// This function walks a block of RDs to find one with the matching affinity
+uint32_t GetGICR(uint32_t affinity)
+{
+  GICv3_redistributor_RD* gicr;
+  uint32_t index = 0;
+
+  do
+  {
+    gicr = getgicrRD(index);
+    if (gicr->GICR_TYPER[1] == affinity)
+       return index;
+
+    index++;
+  }
+  while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block
+
+  return 0xFFFFFFFF; // return -1 to signal not RD found
+}
+
+void WakeupGICR(uint32_t gicr)
+{
+    GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
+#ifdef USE_GIC600
+    //Power up Re-distributor for GIC-600
+    gicrRD->GICR_PWRR = 0x2;
+#endif
+
+    /*
+     * step 1 - ensure GICR_WAKER.ProcessorSleep is off
+     */
+    gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
+
+    /*
+     * step 2 - wait for children asleep to be cleared
+     */
+    while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
+        continue;
+
+    /*
+     * OK, GICR is go
+     */
+    return;
+}
+
+void EnablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISENABLER = 1 << id;
+}
+
+void DisablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICENABLER = 1 << id;
+}
+
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    gicrSGI->GICR_IPRIORITYR[id] = priority;
+}
+
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
+}
+
+void SetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISPENDR = 1 << id;
+}
+
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ICPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICPENDR = 1 << id;
+}
+
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
+}
+
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    uint32_t groupmod;
+
+    /*
+     * GICR_IGROUPR0 is one 32-bit register
+     */
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+        gicrSGI->GICR_IGROUPR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+        gicrSGI->GICR_IGRPMODR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
+}
+
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    const uint32_t nbits = (sizeof group * 8) - 1;
+    uint32_t groupmod;
+
+    /*
+     * get each bit of group config duplicated over all 32 bits
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicrSGI->GICR_IGROUPR0 = group;
+    gicrSGI->GICR_IGRPMODR0 = groupmod;
+}
+
+/* EOF GICv3_gicr.c */
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S
new file mode 100644
index 00000000..e7f95aa7
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S
@@ -0,0 +1,133 @@
+//
+// Armv8-A AArch64 - Basic Mutex Example
+// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global _mutex_initialize
+    .global _mutex_acquire
+    .global _mutex_release
+
+//
+// These routines implement the mutex management functions required for running
+// the Arm C library in a multi-threaded environment.
+//
+// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
+//
+// **********************************************************************
+//
+
+    .type _mutex_initialize, "function"
+    .cfi_startproc
+_mutex_initialize:
+
+    //
+    // mark the mutex as unlocked
+    //
+    mov     w1, #0
+    str     w1, [x0]
+
+    //
+    // we are running multi-threaded, so set a non-zero return
+    // value (function prototype says use 1)
+    //
+    mov     w0, #1
+    ret
+    .cfi_endproc
+
+#if !defined(USE_LSE_ATOMIC)
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+
+    //
+    // send ourselves an event, so we don't stick on the wfe at the
+    // top of the loop
+    //
+    sevl
+
+    //
+    // wait until the mutex is available
+    //
+loop:
+    wfe
+    ldaxr   w1, [x0]
+    cbnz    w1, loop
+
+    //
+    // mutex is (at least, it was) available - try to claim it
+    //
+    mov     w1, #1
+    stxr    w2, w1, [x0]
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+
+    mov     w1, #0
+    stlr    w1, [x0]
+    ret
+    .cfi_endproc
+
+#else  // LSE version
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+    // This uses a "ticket lock".  The lock is stored as a 32-bit value: 
+    // - the upper 16-bits record the thread's ticket number ("take a ticket")
+    // - the lower 16-bits record the ticket being served    ("now serving")
+
+    // atomically load then increment the thread's ticket number ("take a ticket")
+    mov w3, #(1 << 16)
+    ldadda w3, w1, [x0]
+
+    // is the ticket now being served?
+    eor w2, w1, w1, ror #16
+    cbz w2, loop_exit
+
+    // no, so wait for the ticket to be served
+
+    // send a local event to avoid missing an unlock before the exclusive load
+    sevl
+
+loop:
+    wfe
+    ldaxrh  w3, [x0]
+    eor w2, w3, w1, lsr #16
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+loop_exit:
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+    mov     w1, #1
+    staddlh w1, [x0]
+    ret
+    .cfi_endproc
+#endif
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h
new file mode 100644
index 00000000..ec1a1d28
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h
@@ -0,0 +1,66 @@
+/*
+ * Armv8-A AArch64 - Basic Mutex Example
+ *
+ * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef MP_MUTEX_H
+#define MP_MUTEX_H
+
+/*
+ * The Arm C library calls-out to these functions to manage multithreading.
+ * They can also be called by user application code.
+ *
+ * Mutex type is specified by the Arm C library
+ *
+ * Declare function prototypes for libc mutex routines
+ */
+typedef signed int *mutex;
+
+/*
+ * int _mutex_initialize(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  0 - application is non-threaded
+ *  1 - application is threaded
+ *  The C library uses the return result to indicate whether it is being used in a multithreaded environment.
+ */
+int _mutex_initialize(mutex *m);
+
+/*
+ * void _mutex_acquire(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  <nothing>
+ *
+ * Side Effects
+ *  Routine does not return until the mutex has been claimed. A load-acquire
+ *  is used to guarantee that the mutex claim is properly ordered with
+ *  respect to any accesses to the resource protected by the mutex
+ */
+void _mutex_acquire(mutex *m);
+
+/*
+ * void _mutex_release(mutex *m)
+ *
+ * Inputs
+ *  mutex *m - pointer to the 32-bit word associated with the mutex
+ *
+ * Returns
+ *  <nothing>
+ *
+ * Side Effects
+ *  A store-release is used to guarantee that the mutex release is properly
+ *  ordered with respect any accesses to the resource protected by the mutex
+ */
+void _mutex_release(mutex *m);
+
+#endif
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h
new file mode 100644
index 00000000..52c9a0fe
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h
@@ -0,0 +1,66 @@
+//
+// Private Peripheral Map for the v8 Architecture Envelope Model
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef PPM_AEM_H
+#define PPM_AEM_H
+
+//
+// Distributor layout
+//
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+//
+// CPU Interface layout
+//
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+
+#endif // PPM_AEM_H
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
new file mode 100644
index 00000000..c7296646
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
@@ -0,0 +1,149 @@
+/* Small demonstration of the ThreadX module manager.  */
+
+#include "tx_api.h"
+#include "txm_module.h"
+#include <stddef.h>
+
+
+/* Define the ThreadX module manager thread and stack...  */
+
+TX_THREAD               module_manager;
+#define MODULE_MANAGER_STACK_SIZE (1024 * 4)
+ALIGN_TYPE              module_manager_stack[MODULE_MANAGER_STACK_SIZE / sizeof(ALIGN_TYPE)];
+
+
+/* Define the module instance object  */
+
+TXM_MODULE_INSTANCE     my_module;
+
+
+/* The module code should be loaded here.  */
+
+#define MODULE_CODE (0x80180000)
+
+
+/* Define the object pool area.  */
+
+UCHAR                   object_memory[1024 * 16];
+
+
+/* Define the module data pool area.  */
+
+#define MODULE_DATA_SIZE (1024 * 32)
+ALIGN_TYPE MODULE_DATA [MODULE_DATA_SIZE / sizeof(ALIGN_TYPE)];
+
+
+/* Define the count of memory faults.  */
+
+ULONG                   memory_faults = 0;
+
+
+/* Define thread prototypes.  */
+
+void    module_manager_entry(ULONG thread_input);
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+UCHAR   event_buffer[65536];
+
+#endif
+
+
+/* Define main entry point.  */
+
+int main(void)
+{
+
+    /* Initialize timer for ThreadX.  */
+    extern void init_timer(void);    /* in timer_interrupts.c  */
+    init_timer();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+
+    /* The functions doesn't really return*/
+    return 0;
+}
+
+ULONG simple_thread_counter = 0;
+TX_THREAD simple_thread;
+#define SIMPLE_THREAD_STACK_SIZE (1024 * 4)
+ALIGN_TYPE simple_thread_stack[SIMPLE_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)];
+void simple_thread_entry(ULONG thread_input)
+{
+    while(1)
+    {
+        simple_thread_counter++;
+        tx_thread_sleep(2);
+    }
+}
+
+/* Define what the initial system looks like.  */
+
+void tx_application_define(void *first_unused_memory)
+{
+    tx_thread_create(
+            &module_manager,
+            "Module Manager Thread",
+            module_manager_entry, 0,
+            module_manager_stack, MODULE_MANAGER_STACK_SIZE,
+            1, 1,
+            TX_NO_TIME_SLICE,
+            TX_AUTO_START);
+
+    tx_thread_create(
+            &simple_thread,
+            "Simple Thread",
+            simple_thread_entry, 0,
+            simple_thread_stack, SIMPLE_THREAD_STACK_SIZE,
+            1, 1,
+            TX_NO_TIME_SLICE,
+            TX_AUTO_START);
+}
+
+
+/* Define the test threads.  */
+
+void module_manager_entry(ULONG thread_input)
+{
+
+    /* Initialize the module manager.   */
+    txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE);
+
+    txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
+
+    /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download.  */
+    txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
+    
+    /* Start the module.  */
+    txm_module_manager_start(&my_module);
+
+    /* Sleep for a while....  */
+    {
+        int i;
+        for (i = 0; i < 10; i++)
+        {
+            tx_thread_sleep(10);
+        }
+    }
+    
+    /* Stop the module.  */
+    txm_module_manager_stop(&my_module);
+    
+    /* Unload the module.  */
+    txm_module_manager_unload(&my_module);
+
+    /* Load the module again.  */
+    txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
+
+    /* Start the module again.  */
+    txm_module_manager_start(&my_module);
+    
+    /* Now just spin...  */
+    while(1)
+    {
+    
+        tx_thread_sleep(10);
+    }
+}
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
new file mode 100644
index 00000000..530cac1f
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
@@ -0,0 +1,427 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+    <listAttribute key="1685211613816507265.viewid=2">
+        <listEntry value="thread_info"/>
+        <listEntry value="thread_ptr"/>
+        <listEntry value="shell_function"/>
+        <listEntry value="thread_entry_info"/>
+        <listEntry value="module_instance"/>
+        <listEntry value="module_preamble"/>
+        <listEntry value="return_value"/>
+        <listEntry value="status"/>
+        <listEntry value="_entry_param_thread_ptr"/>
+        <listEntry value="data_allocation_size"/>
+        <listEntry value="_txm_module_manager_byte_pool"/>
+        <listEntry value="pool_ptr"/>
+        <listEntry value="&amp;_txm_module_manager_byte_pool"/>
+        <listEntry value="(void*)(_txm_module_manager_byte_pool.tx_byte_pool_start)"/>
+        <listEntry value="(void*)(_txm_module_manager_byte_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size)"/>
+        <listEntry value="_tx_timer_thread"/>
+        <listEntry value="byte_pool_ptr"/>
+        <listEntry value="object_ptr"/>
+        <listEntry value="module_instance -&gt; txm_module_instance_data_start"/>
+        <listEntry value="module_instance -&gt; txm_module_instance_data_end"/>
+        <listEntry value="code_alignment"/>
+    </listAttribute>
+    <mapAttribute key="1685211613816507265.viewid=2.ExpressionsData">
+        <mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,1;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
+        <mapEntry key="1" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
+        <mapEntry key="10" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,96;NODE_TYPE,VALUE;FORMATTER,com.arm.debug.views.common.outline.DefaultDataFormatter"/>
+        <mapEntry key="11" value=""/>
+        <mapEntry key="12" value="NODE_TRANSFER_ELEMENT_COUNT,1;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
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+        <mapEntry key="14" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
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+        <mapEntry key="17" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
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+        <mapEntry key="9" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+    </mapAttribute>
+    <stringAttribute key="1685211613816507265.viewid=2:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;false&#9;423&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;59&#9;-1&#9;true&#9;3&#9;true&#9;false&#9;329&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <listAttribute key="2016305617678564833.viewid=3">
+        <listEntry value="thread_0"/>
+        <listEntry value="thread_1"/>
+        <listEntry value="thread_2"/>
+        <listEntry value="byte_pool_0"/>
+        <listEntry value="block_pool_0"/>
+        <listEntry value="queue_0_sends"/>
+        <listEntry value="semaphore_0_puts"/>
+        <listEntry value="thread_ptr"/>
+        <listEntry value="module_instance"/>
+        <listEntry value="thread_info -&gt; txm_module_thread_entry_info_start_thread"/>
+        <listEntry value="_txm_module_manager_object_pool"/>
+        <listEntry value="code_size"/>
+    </listAttribute>
+    <mapAttribute key="2016305617678564833.viewid=3.ExpressionsData">
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+    </mapAttribute>
+    <stringAttribute key="2016305617678564833.viewid=3:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;255&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;false&#9;257&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <listAttribute key="7759977680573821445.viewid=2">
+        <listEntry value="module_preamble"/>
+        <listEntry value="thread_ptr"/>
+        <listEntry value="thread_info"/>
+    </listAttribute>
+    <mapAttribute key="7759977680573821445.viewid=2.ExpressionsData">
+        <mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,1;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
+        <mapEntry key="1" value="NODE_TRANSFER_ELEMENT_COUNT,1;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
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+    </mapAttribute>
+    <stringAttribute key="7759977680573821445.viewid=2:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;255&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;388&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;320&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;239&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
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+        <mapEntry key="*Fetching Data" value="28174103"/>
+        <mapEntry key="*Fetching Data Model" value="1351942"/>
+        <mapEntry key="*FunctionLoader" value="214992700"/>
+        <mapEntry key="*ListDynamicObjects" value="61100"/>
+        <mapEntry key="*list global low level symbols" value="1300040"/>
+        <mapEntry key="*loading memory from target" value="3032704"/>
+        <mapEntry key="*loading values from target" value="4304277"/>
+        <mapEntry key="*trace" value="83055498"/>
+        <mapEntry key="*updating expressions" value="168732015"/>
+        <mapEntry key="*updating local_variables" value="415040"/>
+        <mapEntry key="*updating registers" value="37820633"/>
+        <mapEntry key="Add Watchpoint" value="17044375"/>
+        <mapEntry key="AddEventObserver" value="2293434"/>
+        <mapEntry key="Evaluate" value="2629321"/>
+        <mapEntry key="SourceToAddress" value="1246996"/>
+        <mapEntry key="areCachesAvailable" value="243888"/>
+        <mapEntry key="backtrace" value="1379940"/>
+        <mapEntry key="break" value="8182853"/>
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+        <mapEntry key="compute execution mode" value="637285"/>
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+        <mapEntry key="console help" value="1037500"/>
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+        <mapEntry key="getValidEncodings" value="255826"/>
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+        <mapEntry key="set watchpoint properties" value="1627827"/>
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+    </listAttribute>
+    <stringAttribute key="debugger.view.ModulesView:DebugOutlineColumnState" value="OutlineConfig1&#9;5&#9;0&#9;true&#9;true&#9;53&#9;-1&#9;true&#9;1&#9;true&#9;true&#9;66&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;63&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;45&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;67&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.NewRegisterView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;117&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;175&#9;-1&#9;true&#9;3&#9;false&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;false&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;false&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.NewRegisterView:_selectedRegisterSet" value="All registers"/>
+    <mapAttribute key="debugger.view.NewRegisterView_registerSets"/>
+    <stringAttribute key="debugger.view.StackView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;64&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;59&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <listAttribute key="debugger.view.TraceView:TRACE_EXPORT_FILTERS"/>
+    <stringAttribute key="debugger.view.VariableTreeView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;197&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;137&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <booleanAttribute key="debugger.view.expression.DrawAsHex" value="false"/>
+    <booleanAttribute key="debugger.view.register.DrawAsHex" value="false"/>
+    <stringAttribute key="debugger.view.symbols.FunctionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;53&#9;1&#9;true&#9;1&#9;false&#9;true&#9;103&#9;-1&#9;true&#9;2&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;90&#9;0&#9;true&#9;4&#9;true&#9;true&#9;86&#9;-1&#9;true&#9;5&#9;false&#9;true&#9;41&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;112&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;54&#9;-1&#9;true"/>
+    <booleanAttribute key="debugger.view.variable.DrawAsHex" value="false"/>
+    <stringAttribute key="dtsl_config" value="DtslScript"/>
+    <stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
+    <stringAttribute key="dtsl_options_file" value="default"/>
+    <stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
+    <stringAttribute key="launch_configuration_version" value="2020.0"/>
+    <booleanAttribute key="linuxOS" value="false"/>
+    <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
+    <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
+    <booleanAttribute key="runAfterConnect" value="false"/>
+    <mapAttribute key="scripts_view_script_links">
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.ds" value=""/>
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager_debug.ds" value=""/>
+    </mapAttribute>
+    <listAttribute key="setup">
+        <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
+        <listEntry value="&quot;FVP_Base_Cortex-A35x1&quot;"/>
+    </listAttribute>
+    <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
+    <stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
+</launchConfiguration>
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld
new file mode 100644
index 00000000..eec8f12b
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld
@@ -0,0 +1,245 @@
+/* Linker script to place sections and symbol values.
+ * It references following symbols, which must be defined in code:
+ *   start64 : Entry point
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __cs3_peripherals
+ *   __code_start
+ *   __exidx_start
+ *   __exidx_end
+ *   __data_start
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   __stack
+ *   __el3_stack
+ *   __ttb0_l1
+ *   __ttb0_l2_ram
+ *   __ttb0_l2_private
+ *   __ttb0_l2_periph
+ *   __top_of_ram
+ */
+
+ENTRY(start64)
+
+SECTIONS
+{
+    /*
+     * CS3 Peripherals is a 64MB region from 0x1c000000
+     * that includes the following:
+     * System Registers             at 0x1C010000
+     * UART0 (PL011)                at 0x1C090000
+     * Color LCD Controller (PL111) at 0x1C1F0000
+     * plus a number of others.
+     * CS3_PERIPHERALS is used by the startup code for page-table generation
+     * This region is not truly empty, but we have no
+     * predefined objects that live within it
+     */
+    __cs3_peripherals  = 0x1c000000;
+
+    /*
+     * GICv3 distributor
+     */
+    .gicd 0x2f000000 (NOLOAD):
+    {
+        *(.gicd)
+    }
+
+    /*
+     * GICv3 redistributors
+     * 128KB for each redistributor in the system
+     */
+    .gicr 0x2f100000 (NOLOAD):
+    {
+        *(.gicr)
+    }
+
+    .vectors 0x80000000:
+    {
+        __code_start = .;
+        KEEP(*(StartUp))
+        KEEP(*(EL1VECTORS EL2VECTORS EL3VECTORS))
+    }
+
+    .init :
+    {
+        KEEP (*(SORT_NONE(.init)))
+    }
+
+    .text :
+    {
+        *(.text*)
+    }
+
+    .fini :
+    {
+        KEEP (*(SORT_NONE(.fini)))
+    }
+
+    .rodata :
+    {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+    }
+
+    .eh_frame :
+    {
+        KEEP (*(.eh_frame))
+    }
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    }
+
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    }
+
+    .preinit_array :
+    {
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+    }
+
+    .init_array :
+    {
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array ))
+        PROVIDE_HIDDEN (__init_array_end = .);
+    }
+
+    .fini_array :
+    {
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP (*(SORT(.fini_array.*)))
+        KEEP (*(.fini_array ))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+    }
+
+    .ctors :
+    {
+        /* gcc uses crtbegin.o to find the start of
+           the constructors, so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtbegin.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtbegin.o
+           is in.  */
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*crtbegin?.o(.ctors))
+        /* We don't want to include the .ctor section from
+           the crtend.o file until after the sorted ctors.
+           The .ctor section from the crtend file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+    }
+
+    .dtors :
+    {
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*crtbegin?.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+    }
+
+    .jcr :
+    {
+        KEEP (*(.jcr))
+    }
+
+    .data :
+    {
+        __data_start = . ;
+        *(.data .data.* .gnu.linkonce.d.*)
+        SORT(CONSTRUCTORS)
+    }
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    }
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(64);
+        __end__ = .;
+        PROVIDE(end = .);
+        . = . + 0x1000;
+    }
+
+    .stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 8 * 0x4000;
+        __handler_stack = .;
+    }
+
+    .stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 8 * 0x4000;
+        __stack = .;
+    }
+
+    .el3_stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 8 * 0x1000;
+        __el3_stack = .;
+    }
+
+    .ttb0_l1 (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l1 = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_ram (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_ram = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_private (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_private = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_periph (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_periph = .;
+        . = . + 0x1000;
+    }
+
+    /*
+     * The startup code uses the end of this region to calculate
+     * the top of memory - don't place any RAM regions after it
+     */
+    __top_of_ram = .;
+}
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c
new file mode 100644
index 00000000..4dc009b2
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c
@@ -0,0 +1,122 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "sp804_timer.h"
+
+#define TIMER_SP804_CTRL_TIMEREN     (1 << 7)
+#define TIMER_SP804_CTRL_TIMERMODE   (1 << 6)        // Bit 6:
+#define TIMER_SP804_CTRL_INTENABLE   (1 << 5)
+#define TIMER_SP804_CTRL_TIMERSIZE   (1 << 1)        // Bit 1: 0=16-bit, 1=32-bit
+#define TIMER_SP804_CTRL_ONESHOT     (1 << 0)        // Bit 0: 0=wrapping, 1=one-shot
+
+#define TIMER_SP804_CTRL_PRESCALE_1  (0 << 2)        // clk/1
+#define TIMER_SP804_CTRL_PRESCALE_4  (1 << 2)        // clk/4
+#define TIMER_SP804_CTRL_PRESCALE_8  (2 << 2)        // clk/8
+
+struct sp804_timer
+{
+        volatile uint32_t Time1Load;     // +0x00
+  const volatile uint32_t Time1Value;    // +0x04 - RO
+        volatile uint32_t Timer1Control; // +0x08
+        volatile uint32_t Timer1IntClr;  // +0x0C - WO
+  const volatile uint32_t Timer1RIS;     // +0x10 - RO
+  const volatile uint32_t Timer1MIS;     // +0x14 - RO
+        volatile uint32_t Timer1BGLoad;  // +0x18
+
+        volatile uint32_t Time2Load;     // +0x20
+        volatile uint32_t Time2Value;    // +0x24
+        volatile uint8_t  Timer2Control; // +0x28
+        volatile uint32_t Timer2IntClr;  // +0x2C - WO
+  const volatile uint32_t Timer2RIS;     // +0x30 - RO
+  const volatile uint32_t Timer2MIS;     // +0x34 - RO
+        volatile uint32_t Timer2BGLoad;  // +0x38
+
+  // Not including ID registers
+
+};
+
+// Instance of the dual timer, will be placed using the scatter file
+struct sp804_timer* dual_timer;
+
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address)
+{
+  dual_timer = (struct sp804_timer*)address;
+  return;
+}
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
+{
+  uint32_t tmp = 0;
+
+  dual_timer->Time1Load = load_value;
+
+  // Fixed setting: 32-bit, no prescaling
+  tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
+
+  // Settings from parameters: interrupt generation & reload
+  tmp = tmp | interrupt | auto_reload;
+
+  // Write control register
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Starts the timer
+void startTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp | TIMER_SP804_CTRL_TIMEREN;      // Set TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Stops the timer
+void stopTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN;     // Clear TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void)
+{
+  return dual_timer->Time1Value;
+}
+
+
+void clearTimerIrq(void)
+{
+  // A write to this register, of any value, clears the interrupt
+  dual_timer->Timer1IntClr = 1;
+}
+
+
+// ------------------------------------------------------------
+// End of sp804_timer.c
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h
new file mode 100644
index 00000000..777062cc
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h
@@ -0,0 +1,53 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+// Header Filer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#ifndef _SP804_TIMER_
+#define _SP804_TIMER_
+
+#include <stdint.h>
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address);
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+
+#define SP804_AUTORELOAD   (0)
+#define SP804_SINGLESHOT   (1)
+#define SP804_GENERATE_IRQ (1 << 5)
+#define SP804_NO_IRQ       (0)
+
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
+
+
+// Starts the timer
+void startTimer(void);
+
+
+// Stops the timer
+void stopTimer(void);
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void);
+
+
+// Clears the timer interrupt
+void clearTimerIrq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of sp804_timer.h
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S
new file mode 100644
index 00000000..67dd8a6a
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S
@@ -0,0 +1,787 @@
+// ------------------------------------------------------------
+// Armv8-A MPCore EL3 AArch64 Startup Code
+//
+// Basic Vectors, MMU, caches and GICv3 initialization
+//
+// Exits in EL1 AArch64
+//
+// Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_mmu.h"
+#include "v8_system.h"
+#include "GICv3_aliases.h"
+
+    .section StartUp, "ax"
+    .balign 4
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+
+    .global InvalidateUDCaches
+    .global ZeroBlock
+
+    .global SetPrivateIntSecurityBlock
+    .global SetSPISecurityAll
+    .global SetPrivateIntPriority
+
+    .global GetGICR
+    .global WakeupGICR
+    .global SyncAREinGICD
+    .global EnableGICD
+    .global EnablePrivateInt
+    .global GetPrivateIntPending
+    .global ClearPrivateIntPending
+
+    .global _start
+    .global MainApp
+
+    .global __code_start
+    .global __ttb0_l1
+    .global __ttb0_l2_ram
+    .global __ttb0_l2_periph
+    .global __top_of_ram
+    .global gicd
+    .global __stack
+    .global __el3_stack
+    .global __cs3_peripherals
+
+
+
+
+// ------------------------------------------------------------
+
+    .global start64
+    .type start64, "function"
+start64:
+
+    //
+    // program the VBARs
+    //
+    ldr x1, =el1_vectors
+    msr VBAR_EL1, x1
+
+    ldr x1, =el2_vectors
+    msr VBAR_EL2, x1
+
+    ldr x1, =el3_vectors
+    msr VBAR_EL3, x1
+
+
+    // GIC-500 comes out of reset in GICv2 compatibility mode - first set
+    // system register enables for all relevant exception levels, and
+    // select GICv3 operating mode
+    //
+    msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL3, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
+
+    //
+    // set lower exception levels as non-secure, with no access
+    // back to EL2 or EL3, and are AArch64 capable
+    //
+    mov x3, #(SCR_EL3_RW  | \
+              SCR_EL3_SMD | \
+              SCR_EL3_NS)      // Set NS bit, to access Non-secure registers
+    msr SCR_EL3, x3
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL2, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
+
+
+    //
+    // no traps or VM modifications from the Hypervisor, EL1 is AArch64
+    //
+    mov x2, #HCR_EL2_RW
+    msr HCR_EL2, x2
+
+    //
+    // VMID is still significant, even when virtualisation is not
+    // being used, so ensure VTTBR_EL2 is properly initialised
+    //
+    msr VTTBR_EL2, xzr
+
+    //
+    // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
+    //  VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
+    // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
+    // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
+    // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
+    //
+    mrs x0, MPIDR_EL1
+    msr VMPIDR_EL2, x0
+    mrs x0, MIDR_EL1
+    msr VPIDR_EL2, x0
+
+    // extract the core number from MPIDR_EL1 and store it in
+    // x19 (defined by the AAPCS as callee-saved), so we can re-use
+    // the number later
+    //
+    bl GetCPUID
+    mov x19, x0
+
+    //
+    // neither EL3 nor EL2 trap floating point or accesses to CPACR
+    //
+    msr CPTR_EL3, xzr
+    msr CPTR_EL2, xzr
+
+    //
+    // SCTLR_ELx may come out of reset with UNKNOWN values so we will
+    // set the fields to 0 except, possibly, the endianess field(s).
+    // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
+    // is not strictly needed, since we're never in EL2 or EL0
+    //
+#ifdef __ARM_BIG_ENDIAN
+    mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
+#else
+    mov x0, #0
+#endif
+    msr SCTLR_EL3, x0
+    msr SCTLR_EL2, x0
+    msr SCTLR_EL1, x0
+
+#ifdef CORTEXA
+    //
+    // Configure ACTLR_EL[23]
+    // ----------------------
+    //
+    // These bits are IMPLEMENTATION DEFINED, so are different for
+    // different processors
+    //
+    // For Cortex-A57, the controls we set are:
+    //
+    //  Enable lower level access to CPUACTLR_EL1
+    //  Enable lower level access to CPUECTLR_EL1
+    //  Enable lower level access to L2CTLR_EL1
+    //  Enable lower level access to L2ECTLR_EL1
+    //  Enable lower level access to L2ACTLR_EL1
+    //
+    mov x0, #((1 << 0) | \
+              (1 << 1) | \
+              (1 << 4) | \
+              (1 << 5) | \
+              (1 << 6))
+
+    msr ACTLR_EL3, x0
+    msr ACTLR_EL2, x0
+
+    //
+    // configure CPUECTLR_EL1
+    //
+    // These bits are IMP DEF, so need to different for different
+    // processors
+    //
+    // SMPEN - bit 6 - Enables the processor to receive cache
+    //                 and TLB maintenance operations
+    //
+    // Note: For Cortex-A57/53 SMPEN should be set before enabling
+    //       the caches and MMU, or performing any cache and TLB
+    //       maintenance operations.
+    //
+    //       This register has a defined reset value, so we use a
+    //       read-modify-write sequence to set SMPEN
+    //
+    mrs x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
+    orr x0, x0, #(1 << 6)  // Set the SMPEN bit
+    msr S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
+
+    isb
+#endif
+
+    //
+    // That's the last of the control settings for now
+    //
+    // Note: no ISB after all these changes, as registers won't be
+    // accessed until after an exception return, which is itself a
+    // context synchronisation event
+    //
+
+    //
+    // Setup some EL3 stack space, ready for calling some subroutines, below.
+    //
+    // Stack space allocation is CPU-specific, so use CPU
+    // number already held in x19
+    //
+    // 2^12 bytes per CPU for the EL3 stacks
+    //
+    ldr x0, =__el3_stack
+    sub x0, x0, x19, lsl #12
+    mov sp, x0
+
+    //
+    // we need to configure the GIC while still in secure mode, specifically
+    // all PPIs and SPIs have to be programmed as Group1 interrupts
+    //
+
+    //
+    // Before the GIC can be reliably programmed, we need to
+    // enable Affinity Routing, as this affects where the configuration
+    // registers are (with Affinity Routing enabled, some registers are
+    // in the Redistributor, whereas those same registers are in the
+    // Distributor with Affinity Routing disabled (i.e. when in GICv2
+    // compatibility mode).
+    //
+    mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
+    mov x1, x19
+    bl  SyncAREinGICD
+
+    //
+    // The Redistributor comes out of reset assuming the processor is
+    // asleep - correct that assumption
+    //
+    bl  GetAffinity
+    bl  GetGICR
+    mov w20, w0     // Keep a copy for later
+    bl  WakeupGICR
+
+    //
+    // Now we're ready to set security and other initialisations
+    //
+    // This is a per-CPU configuration for these interrupts
+    //
+    // for the first cluster, CPU number is the redistributor index
+    //
+    mov w0, w20
+    mov w1, #1    // gicigroupr_G1NS
+    bl  SetPrivateIntSecurityBlock
+
+    //
+    // While we're in the Secure World, set the priority mask low enough
+    // for it to be writable in the Non-Secure World
+    //
+    //mov x0, #16 << 3    // 5 bits of priority in the Secure world
+    mov x0, #0xFF  // for Non-Secure interrupts
+    msr ICC_PMR_EL1, x0
+
+    //
+    // there's more GIC setup to do, but only for the primary CPU
+    //
+    cbnz x19, drop_to_el1
+
+    //
+    // There's more to do to the GIC - call the utility routine to set
+    // all SPIs to Group1
+    //
+    mov w0, #1    // gicigroupr_G1NS
+    bl  SetSPISecurityAll
+
+    //
+    // Set up EL1 entry point and "dummy" exception return information,
+    // then perform exception return to enter EL1
+    //
+    .global drop_to_el1
+drop_to_el1:
+    adr x1, el1_entry_aarch64
+    msr ELR_EL3, x1
+    mov x1, #(AARCH64_SPSR_EL1h | \
+              AARCH64_SPSR_F  | \
+              AARCH64_SPSR_I  | \
+              AARCH64_SPSR_A)
+    msr SPSR_EL3, x1
+    eret
+
+
+
+// ------------------------------------------------------------
+// EL1 - Common start-up code
+// ------------------------------------------------------------
+
+    .global el1_entry_aarch64
+    .type el1_entry_aarch64, "function"
+el1_entry_aarch64:
+
+    //
+    // Now we're in EL1, setup the application stack
+    // the scatter file allocates 2^14 bytes per app stack
+    //
+    ldr x0, =__handler_stack
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+    MSR     SPSel, #0
+    ISB
+    ldr x0, =__stack
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+
+    //
+    // Enable floating point
+    //
+    mov x0, #CPACR_EL1_FPEN
+    msr CPACR_EL1, x0
+
+    //
+    // Invalidate caches and TLBs for all stage 1
+    // translations used at EL1
+    //
+    // Cortex-A processors automatically invalidate their caches on reset
+    // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
+    // It is therefore not necessary for software to invalidate the caches 
+    // on startup, however, this is done here in case of a warm reset.
+    bl  InvalidateUDCaches
+    tlbi VMALLE1
+
+
+    //
+    // Set TTBR0 Base address
+    //
+    // The CPUs share one set of translation tables that are
+    // generated by CPU0 at run-time
+    //
+    // TTBR1_EL1 is not used in this example
+    //
+    ldr x1, =__ttb0_l1
+    msr TTBR0_EL1, x1
+
+
+    //
+    // Set up memory attributes
+    //
+    // These equate to:
+    //
+    // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
+    // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
+    // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
+    //
+    mov  x1, #0xff44
+    movk x1, #4, LSL #16    // equiv to: movk x1, #0x0000000000040000
+    msr MAIR_EL1, x1
+
+
+    //
+    // Set up TCR_EL1
+    //
+    // We're using only TTBR0 (EPD1 = 1), and the page table entries:
+    //  - are using an 8-bit ASID from TTBR0
+    //  - have a 4K granularity (TG0 = 0b00)
+    //  - are outer-shareable (SH0 = 0b10)
+    //  - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
+    //  - map
+    //      + 32 bits of VA space (T0SZ = 0x20)
+    //      + into a 32-bit PA space (IPS = 0b000)
+    //
+    //     36   32   28   24   20   16   12    8    4    0
+    //  -----+----+----+----+----+----+----+----+----+----+
+    //       |    |    |OOII|    |    |    |OOII|    |    |
+    //    TT |    |    |RRRR|E T |   T|    |RRRR|E T |   T|
+    //    BB | I I|TTSS|GGGG|P 1 |   1|TTSS|GGGG|P 0 |   0|
+    //    IIA| P P|GGHH|NNNN|DAS |   S|GGHH|NNNN|D S |   S|
+    //    10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
+    //
+    //    000 0000 0000 0000 1000 0000 0010 0101 0010 0000
+    //
+    //                    0x    8    0    2    5    2    0
+    //
+    // Note: the ISB is needed to ensure the changes to system
+    //       context are before the write of SCTLR_EL1.M to enable
+    //       the MMU. It is likely on a "real" implementation that
+    //       this setup would work without an ISB, due to the
+    //       amount of code that gets executed before enabling the
+    //       MMU, but that would not be architecturally correct.
+    //
+    ldr x1, =0x0000000000802520
+    msr TCR_EL1, x1
+    isb
+
+    //
+    // x19 already contains the CPU number, so branch to secondary
+    // code if we're not on CPU0
+    //
+    cbnz x19, el1_secondary
+
+    //
+    // Fall through to primary code
+    //
+
+
+//
+// ------------------------------------------------------------
+//
+// EL1 - primary CPU init code
+//
+// This code is run on CPU0, while the other CPUs are in the
+// holding pen
+//
+
+    .global el1_primary
+    .type el1_primary, "function"
+el1_primary:
+
+    //
+    // Turn on the banked GIC distributor enable,
+    // ready for individual CPU enables later
+    //
+    mov w0, #(1 << 1)  // gicdctlr_EnableGrp1A
+    bl  EnableGICD
+
+    //
+    // Generate TTBR0 L1
+    //
+    // at 4KB granularity, 32-bit VA space, table lookup starts at
+    // L1, with 1GB regions
+    //
+    // we are going to create entries pointing to L2 tables for a
+    // couple of these 1GB regions, the first of which is the
+    // RAM on the VE board model - get the table addresses and
+    // start by emptying out the L1 page tables (4 entries at L1
+    // for a 4K granularity)
+    //
+    // x21 = address of L1 tables
+    //
+    ldr x21, =__ttb0_l1
+    mov x0, x21
+    mov x1, #(4 << 3)
+    bl  ZeroBlock
+
+    //
+    // time to start mapping the RAM regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // x22 = address of L2 tables, needs to be remembered in case
+    //       we want to re-use the tables for mapping peripherals
+    //
+    ldr x22, =__ttb0_l2_ram
+    mov x1, #(512 << 3)
+    mov x0, x22
+    bl  ZeroBlock
+
+    //
+    // Get the start address of RAM (the EXEC region) into x4
+    // and calculate the offset into the L1 table (1GB per region,
+    // max 4GB)
+    //
+    // x23 = L1 table offset, saved for later comparison against
+    //       peripheral offset
+    //
+    ldr x4, =__code_start
+    ubfx x23, x4, #30, #2
+
+    orr x1, x22, #TT_S1_ATTR_PAGE
+    str x1, [x21, x23, lsl #3]
+
+    //
+    // we've already used the RAM start address in x4 - we now need
+    // to get this in terms of an offset into the L2 page tables,
+    // where each entry covers 2MB
+    //
+    ubfx x2, x4, #21, #9
+
+    //
+    // TOP_OF_RAM in the scatter file marks the end of the
+    // Execute region in RAM: convert the end of this region to an
+    // offset too, being careful to round up, then calculate the
+    // number of entries to write
+    //
+    ldr x5, =__top_of_ram
+    sub  x3, x5, #1
+    ubfx x3, x3, #21, #9
+    add  x3, x3, #1
+    sub  x3, x3, x2
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as Shared, Normal WBWA (MAIR[1]) with a flat
+    // VA->PA translation
+    //
+    bic x4, x4, #((1 << 21) - 1)
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (1 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_SH_INNER | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // factor the offset into the page table address and then write
+    // the entries
+    //
+    add x0, x22, x2, lsl #3
+
+loop1:
+    subs x3, x3, #1
+    str x1, [x0], #8
+    add x1, x1, #0x200, LSL #12    // equiv to add x1, x1, #(1 << 21)  // 2MB per entry
+    bne loop1
+
+
+    //
+    // now mapping the Peripheral regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // The assumption here is that all peripherals live within
+    // a common 1GB region (i.e. that there's a single set of
+    // L2 pages for all the peripherals). We only use a UART
+    // and the GIC in this example, so the assumption is sound
+    //
+    // x24 = address of L2 peripheral tables
+    //
+    ldr x24, =__ttb0_l2_periph
+
+    //
+    // get the GICD address into x4 and calculate
+    // the offset into the L1 table
+    //
+    // x25 = L1 table offset
+    //
+    ldr x4, =gicd
+    ubfx x25, x4, #30, #2
+
+    //
+    // here's the tricky bit: it's possible that the peripherals are
+    // in the same 1GB region as the RAM, in which case we don't need
+    // to prime a separate set of L2 page tables, nor add them to the
+    // L1 tables
+    //
+    // if we're going to re-use the TTB0_L2_RAM tables, get their
+    // address into x24, which is used later on to write the PTEs
+    //
+    cmp x25, x23
+    csel x24, x22, x24, EQ
+    b.eq nol2setup
+
+    //
+    // Peripherals are in a separate 1GB region, and so have their own
+    // set of L2 tables - clean out the tables and add them to the L1
+    // table
+    //
+    mov x0, x24
+    mov x1, #512 << 3
+    bl  ZeroBlock
+
+    orr x1, x24, #TT_S1_ATTR_PAGE
+    str x1, [x21, x25, lsl #3]
+
+    //
+    // there's only going to be a single 2MB region for GICD (in
+    // x4) - get this in terms of an offset into the L2 page tables
+    //
+    // with larger systems, it is possible that the GIC redistributor
+    // registers require extra 2MB pages, in which case extra code
+    // would be required here
+    //
+nol2setup:
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry for this, so no loop as we have for RAM, above
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // we have CS3_PERIPHERALS that include the UART controller
+    //
+    // Again, the code is making assumptions - this time that the CS3_PERIPHERALS
+    // region uses the same 1GB portion of the address space as the GICD,
+    // and thus shares the same set of L2 page tables
+    //
+    // Get CS3_PERIPHERALS address into x4 and calculate the offset into the
+    // L2 tables
+    //
+    ldr x4, =__cs3_peripherals
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    ldr x1, =(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry again - write it
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // issue a barrier to ensure all table entry writes are complete
+    //
+    dsb ish
+
+    //
+    // Enable the MMU.  Caches will be enabled later, after scatterloading.
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // The Arm Architecture Reference Manual for Armv8-A states:
+    //
+    //     Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
+    //     Correspondingly, the sequence for ensuring that modifications to instructions are available
+    //     for execution must include invalidation of the modified locations from the instruction cache,
+    //     even if the instructions are held in Normal Non-cacheable memory.
+    //     This includes cases where the instruction cache is disabled.
+    //
+
+    dsb ish     // ensure all previous stores have completed before invalidating
+    ic  ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
+    dsb ish     // ensure completion on inner shareable domain   (which includes secondary cores)
+    isb
+
+    // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    msr SCTLR_EL1, x1
+    isb
+
+    // Zero the bss
+    ldr x0, =__bss_start__ // Start of block
+    mov x1, #0             // Fill value
+    ldr x2, =__bss_end__   // End of block
+    sub x2, x2, x0         // Length of block
+    bl  memset
+
+    // Set up the standard file handles
+    bl  initialise_monitor_handles
+
+    // Set up _fini and fini_array to be called at exit
+    ldr x0, =__libc_fini_array
+    bl  atexit
+
+    // Call preinit_array, _init and init_array
+    bl  __libc_init_array
+
+    // Set argc = 1, argv[0] = "" and then call main
+    .pushsection .data
+    .align 3
+argv:
+    .dword arg0
+    .dword 0
+arg0:
+    .byte 0
+    .popsection
+
+    mov x0, #1
+    ldr x1, =argv
+    bl main
+
+    b exit // Will not return
+
+// ------------------------------------------------------------
+// EL1 - secondary CPU init code
+//
+// This code is run on CPUs 1, 2, 3 etc....
+// ------------------------------------------------------------
+
+    .global el1_secondary
+    .type el1_secondary, "function"
+el1_secondary:
+
+    //
+    // the primary CPU is going to use SGI 15 as a wakeup event
+    // to let us know when it is OK to proceed, so prepare for
+    // receiving that interrupt
+    //
+    // NS interrupt priorities run from 0 to 15, with 15 being
+    // too low a priority to ever raise an interrupt, so let's
+    // use 14
+    //
+    mov w0, w20
+    mov w1, #15
+    mov w2, #14 << 4    // we're in NS world, so 4 bits of priority,
+                        // 8-bit field, - 4 = 4-bit shift
+    bl SetPrivateIntPriority
+
+    mov w0, w20
+    mov w1, #15
+    bl  EnablePrivateInt
+
+    //
+    // set priority mask as low as possible; although,being in the
+    // NS World, we can't set bit[7] of the priority, we still
+    // write all 8-bits of priority to an ICC register
+    //
+    mov x0, #31 << 3
+    msr ICC_PMR_EL1, x0
+
+    //
+    // set global enable and wait for our interrupt to arrive
+    //
+    mov x0, #1
+    msr ICC_IGRPEN1_EL1, x0
+    isb
+
+loop_wfi:
+    dsb SY      // Clear all pending data accesses
+    wfi         // Go to sleep
+
+    //
+    // something woke us from our wait, was it the required interrupt?
+    //
+    mov w0, w20
+    mov w1, #15
+    bl  GetPrivateIntPending
+    cbz w0, loop_wfi
+
+    //
+    // it was - there's no need to actually take the interrupt,
+    // so just clear it
+    //
+    mov w0, w20
+    mov w1, #15
+    bl  ClearPrivateIntPending
+
+    //
+    // Enable the MMU and caches
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // Branch to thread start
+    //
+    //B  MainApp
+
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/timer_interrupts.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/timer_interrupts.c
new file mode 100644
index 00000000..8f522217
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/timer_interrupts.c
@@ -0,0 +1,152 @@
+/* Bare-metal example for Armv8-A FVP Base model */
+
+/* Timer and interrupts */
+
+/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */
+/* Use, modification and redistribution of this file is subject to your possession of a     */
+/* valid End User License Agreement for the Arm Product of which these examples are part of */
+/* and your compliance with all applicable terms and conditions of such licence agreement.  */
+
+#include <stdio.h>
+
+#include "GICv3.h"
+#include "GICv3_gicc.h"
+#include "sp804_timer.h"
+
+void   _tx_timer_interrupt(void);
+
+// LED Base address
+#define LED_BASE (volatile unsigned int *)0x1C010008
+
+
+void nudge_leds(void) // Move LEDs along
+{
+    static int state = 1;
+    static int value = 1;
+
+    if (state)
+    {
+        int max = (1 << 7);
+        value <<= 1;
+        if (value == max)
+            state = 0;
+    }
+    else
+    {
+        value >>= 1;
+        if (value == 1)
+            state = 1;
+    }
+
+    *LED_BASE = value;  // Update LEDs hardware
+}
+
+
+// Initialize Timer 0 and Interrupt Controller
+void init_timer(void)
+{
+    // Enable interrupts
+    __asm("MSR DAIFClr, #0xF");
+    setICC_IGRPEN1_EL1(igrpEnable);
+
+    // Configure the SP804 timer to generate an interrupt
+    setTimerBaseAddress(0x1C110000);
+    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
+    startTimer();
+
+    // The SP804 timer generates SPI INTID 34.  Enable
+    // this ID, and route it to core 0.0.0.0 (this one!)
+    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
+    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
+    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
+    EnableSPI(34);                                   // Enable INTID 34
+}
+
+
+// --------------------------------------------------------
+
+void irqHandler(void)
+{
+  unsigned int ID;
+
+  ID = getICC_IAR1(); // readIntAck();
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+      //printf("irqHandler() - Reserved INTID %d\n\n", ID);
+      return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("irqHandler() - External timer interrupt\n\n");
+      nudge_leds();
+      clearTimerIrq();
+
+      /* Call ThreadX timer interrupt processing.  */
+      _tx_timer_interrupt();
+
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("irqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
+
+// --------------------------------------------------------
+
+// Not actually used in this example, but provided for completeness
+
+void fiqHandler(void)
+{
+  unsigned int ID;
+  unsigned int aliased = 0;
+
+  ID = getICC_IAR0(); // readIntAck();
+  //printf("fiqHandler() - Read %d from IAR0\n", ID);
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+    //printf("fiqHandler() - Reserved INTID %d\n\n", ID);
+    ID = getICC_IAR1(); // readAliasedIntAck();
+    //printf("fiqHandler() - Read %d from AIAR\n", ID);
+    aliased = 1;
+
+    // If still spurious then simply return
+    if ((1020 <= ID) && (ID <= 1023))
+        return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("fiqHandler() - External timer interrupt\n\n");
+      clearTimerIrq();
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  // NOTE: If the ID was read from the Aliased IAR, then
+  // the aliased EOI register must be used
+  if (aliased == 0)
+    setICC_EOIR0(ID); // writeEOI(ID);
+  else
+    setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S
new file mode 100644
index 00000000..f467b8a7
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S
@@ -0,0 +1,95 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+	.text
+	.align 3
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_initialize_low_level                          Cortex-A35/GNU    */ 
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is responsible for any low-level processor            */ 
+/*    initialization, including setting up interrupt vectors, setting     */ 
+/*    up a periodic timer interrupt source, saving the system stack       */ 
+/*    pointer for use in ISR processing later, and finding the first      */ 
+/*    available RAM memory address for tx_application_define.             */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_initialize_low_level(VOID)
+{ */
+    .global  _tx_initialize_low_level
+    .type    _tx_initialize_low_level, @function
+_tx_initialize_low_level:
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+
+    /* Save the system stack pointer.  */
+    /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp);  */
+
+    LDR     x0, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    MOV     x1, sp                              // Pickup SP
+    BIC     x1, x1, #0xF                        // Get 16-bit alignment
+    STR     x1, [x0]                            // Store system stack
+
+    /* Save the first available memory address.  */
+    /* _tx_initialize_unused_memory =  (VOID_PTR) Image$$ZI$$Limit;  */
+
+    LDR     x0, =_tx_initialize_unused_memory   // Pickup address of unused memory ptr
+    LDR     x1, =__top_of_ram                   // Pickup unused memory address
+    LDR     x1, [x1]                            //
+    STR     x1, [x0]                            // Store unused memory address
+
+    /* Done, return to caller.  */
+
+    RET                                         // Return to caller
+/* } */
+
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S
new file mode 100644
index 00000000..f8db3bfe
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S
@@ -0,0 +1,179 @@
+// ------------------------------------------------------------
+// Armv8-A AArch64 - Common helper functions
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global EnableCachesEL1
+    .global DisableCachesEL1
+    .global InvalidateUDCaches
+    .global GetMIDR
+    .global GetMPIDR
+    .global GetAffinity
+    .global GetCPUID
+
+// ------------------------------------------------------------
+
+//
+// void EnableCachesEL1(void)
+//
+//    enable Instruction and Data caches
+//
+    .type EnableCachesEL1, "function"
+    .cfi_startproc
+EnableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    orr x0, x0, #SCTLR_ELx_I
+    orr x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+    .type DisableCachesEL1, "function"
+    .cfi_startproc
+DisableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    bic x0, x0, #SCTLR_ELx_I
+    bic x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// void InvalidateUDCaches(void)
+//
+//    Invalidate data and unified caches
+//
+    .type InvalidateUDCaches, "function"
+    .cfi_startproc
+InvalidateUDCaches:
+    // From the Armv8-A Architecture Reference Manual
+
+    dmb  ish                   // ensure all prior inner-shareable accesses have been observed
+
+    mrs  x0, CLIDR_EL1
+    and  w3, w0, #0x07000000   // get 2 x level of coherence
+    lsr  w3, w3, #23
+    cbz  w3, finished
+    mov  w10, #0               // w10 = 2 x cache level
+    mov  w8, #1                // w8 = constant 0b1
+loop_level:
+    add  w2, w10, w10, lsr #1  // calculate 3 x cache level
+    lsr  w1, w0, w2            // extract 3-bit cache type for this level
+    and  w1, w1, #0x7
+    cmp  w1, #2
+    b.lt next_level            // no data or unified cache at this level
+    msr  CSSELR_EL1, x10       // select this cache level
+    isb                        // synchronize change of csselr
+    mrs  x1, CCSIDR_EL1        // read ccsidr
+    and  w2, w1, #7            // w2 = log2(linelen)-4
+    add  w2, w2, #4            // w2 = log2(linelen)
+    ubfx w4, w1, #3, #10       // w4 = max way number, right aligned
+    clz  w5, w4                // w5 = 32-log2(ways), bit position of way in dc operand
+    lsl  w9, w4, w5            // w9 = max way number, aligned to position in dc operand
+    lsl  w16, w8, w5           // w16 = amount to decrement way number per iteration
+loop_way:
+    ubfx w7, w1, #13, #15      // w7 = max set number, right aligned
+    lsl  w7, w7, w2            // w7 = max set number, aligned to position in dc operand
+    lsl  w17, w8, w2           // w17 = amount to decrement set number per iteration
+loop_set:
+    orr  w11, w10, w9          // w11 = combine way number and cache number ...
+    orr  w11, w11, w7          // ... and set number for dc operand
+    dc   isw, x11              // do data cache invalidate by set and way
+    subs w7, w7, w17           // decrement set number
+    b.ge loop_set
+    subs x9, x9, x16           // decrement way number
+    b.ge loop_way
+next_level:
+    add  w10, w10, #2          // increment 2 x cache level
+    cmp  w3, w10
+    b.gt loop_level
+    dsb  sy                    // ensure completion of previous cache maintenance operation
+    isb
+finished:
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// ID Register functions
+//
+
+    .type GetMIDR, "function"
+    .cfi_startproc
+GetMIDR:
+
+    mrs x0, MIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetMPIDR, "function"
+    .cfi_startproc
+GetMPIDR:
+
+    mrs x0, MPIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetAffinity, "function"
+    .cfi_startproc
+GetAffinity:
+
+    mrs x0, MPIDR_EL1
+    ubfx x1, x0, #32, #8
+    bfi  w0, w1, #24, #8
+    ret
+    .cfi_endproc
+
+
+    .type GetCPUID, "function"
+    .cfi_startproc
+GetCPUID:
+
+    mrs x0, MIDR_EL1
+    ubfx    x0, x0, #4, #12 // extract PartNum
+    cmp x0, #0xD0D          // Cortex-A77
+    b.eq DynamIQ
+    cmp x0, #0xD0B          // Cortex-A76
+    b.eq DynamIQ
+    cmp x0, #0xD0A          // Cortex-A75
+    b.eq DynamIQ
+    cmp x0, #0xD05          // Cortex-A55
+    b.eq DynamIQ
+    b Others
+DynamIQ:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+
+Others:
+    mrs x0, MPIDR_EL1
+    ubfx    x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
+    ubfx    x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    add     x0, x1, x2, LSL #2
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h
new file mode 100644
index 00000000..b09079a4
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h
@@ -0,0 +1,103 @@
+/*
+ *
+ * Armv8-A AArch64 common helper functions
+ *
+ * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+
+#ifndef V8_AARCH64_H
+#define V8_AARCH64_H
+
+/*
+ * Parameters for data barriers
+ */
+#define OSHLD   1
+#define OSHST   2
+#define OSH     3
+#define NSHLD   5
+#define NSHST   6
+#define NSH     7
+#define ISHLD   9
+#define ISHST  10
+#define ISH    11
+#define LD     13
+#define ST     14
+#define SY     15
+
+/**********************************************************************/
+
+/*
+ * function prototypes
+ */
+
+/*
+ * void InvalidateUDCaches(void)
+ *   invalidates all Unified and Data Caches
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   <nothing>
+ *
+ * Side Effects
+ *   guarantees that all levels of cache will be invalidated before
+ *   returning to caller
+ */
+void InvalidateUDCaches(void);
+
+/*
+ * unsigned long long EnableCachesEL1(void)
+ *   enables I- and D- caches at EL1
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   New value of SCTLR_EL1
+ *
+ * Side Effects
+ *   context will be synchronised before returning to caller
+ */
+unsigned long long EnableCachesEL1(void);
+
+/*
+ * unsigned long long GetMIDR(void)
+ *   returns the contents of MIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MIDR_EL0
+ */
+unsigned long long GetMIDR(void);
+
+/*
+ * unsigned long long GetMPIDR(void)
+ *   returns the contents of MPIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MPIDR_EL0
+ */
+unsigned long long GetMPIDR(void);
+
+/*
+ * unsigned int GetCPUID(void)
+ *   returns the Aff0 field of MPIDR_EL0
+ *
+ * Inputs
+ *   <none>
+ *
+ * Returns
+ *   MPIDR_EL0[7:0]
+ */
+unsigned int GetCPUID(void);
+
+#endif
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h
new file mode 100644
index 00000000..ee8834fa
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h
@@ -0,0 +1,128 @@
+//
+// Defines for v8 Memory Model
+//
+// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_MMU_H
+#define V8_MMU_H
+
+//
+// Translation Control Register fields
+//
+// RGN field encodings
+//
+#define TCR_RGN_NC   0b00
+#define TCR_RGN_WBWA 0b01
+#define TCR_RGN_WT   0b10
+#define TCR_RGN_WBRA 0b11
+
+//
+// Shareability encodings
+//
+#define TCR_SHARE_NONE  0b00
+#define TCR_SHARE_OUTER 0b10
+#define TCR_SHARE_INNER 0b11
+
+//
+// Granule size encodings
+//
+#define TCR_GRANULE_4K  0b00
+#define TCR_GRANULE_64K 0b01
+#define TCR_GRANULE_16K 0b10
+
+//
+// Physical Address sizes
+//
+#define TCR_SIZE_4G   0b000
+#define TCR_SIZE_64G  0b001
+#define TCR_SIZE_1T   0b010
+#define TCR_SIZE_4T   0b011
+#define TCR_SIZE_16T  0b100
+#define TCR_SIZE_256T 0b101
+
+//
+// Translation Control Register fields
+//
+#define TCR_EL1_T0SZ_SHIFT   0
+#define TCR_EL1_EPD0  (1 << 7)
+#define TCR_EL1_IRGN0_SHIFT  8
+#define TCR_EL1_ORGN0_SHIFT 10
+#define TCR_EL1_SH0_SHIFT   12
+#define TCR_EL1_TG0_SHIFT   14
+
+#define TCR_EL1_T1SZ_SHIFT  16
+#define TCR_EL1_A1   (1 << 22)
+#define TCR_EL1_EPD1 (1 << 23)
+#define TCR_EL1_IRGN1_SHIFT 24
+#define TCR_EL1_ORGN1_SHIFT 26
+#define TCR_EL1_SH1_SHIFT   28
+#define TCR_EL1_TG1_SHIFT   30
+#define TCR_EL1_IPS_SHIFT   32
+#define TCR_EL1_AS   (1 << 36)
+#define TCR_EL1_TBI0 (1 << 37)
+#define TCR_EL1_TBI1 (1 << 38)
+
+//
+// Stage 1 Translation Table descriptor fields
+//
+#define TT_S1_ATTR_FAULT (0b00 << 0)
+#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
+#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
+#define TT_S1_ATTR_PAGE  (0b11 << 0) // Level 3
+
+#define TT_S1_ATTR_MATTR_LSB 2
+
+#define TT_S1_ATTR_NS (1 << 5)
+
+#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
+#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
+#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
+#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
+
+#define TT_S1_ATTR_SH_NONE   (0b00 << 8)
+#define TT_S1_ATTR_SH_OUTER  (0b10 << 8)
+#define TT_S1_ATTR_SH_INNER  (0b11 << 8)
+
+#define TT_S1_ATTR_AF (1 << 10)
+#define TT_S1_ATTR_nG (1 << 11)
+
+// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48]
+// and bits[47:16] are bits[47:16] of the output address for a page of memory
+
+#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0
+
+#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0
+
+#define TT_S1_ATTR_CONTIG (1 << 52)
+#define TT_S1_ATTR_PXN    (1 << 53)
+#define TT_S1_ATTR_UXN    (1 << 54)
+
+// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits 
+// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED
+
+#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
+#define TT_S1_MAIR_DEV_nGnRE  0b00000100
+#define TT_S1_MAIR_DEV_nGRE   0b00001000
+#define TT_S1_MAIR_DEV_GRE    0b00001100
+
+//
+// Inner and Outer Normal memory attributes use the same bit patterns
+// Outer attributes just need to be shifted up
+//
+#define TT_S1_MAIR_OUTER_SHIFT 4
+
+#define TT_S1_MAIR_WT_TRANS_RA  0b0010
+
+#define TT_S1_MAIR_WB_TRANS_RA  0b0110
+#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
+
+#define TT_S1_MAIR_WT_RA  0b1010
+
+#define TT_S1_MAIR_WB_RA  0b1110
+#define TT_S1_MAIR_WB_RWA 0b1111
+
+#endif // V8_MMU_H
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h
new file mode 100644
index 00000000..ff96deff
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h
@@ -0,0 +1,115 @@
+//
+// Defines for v8 System Registers
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_SYSTEM_H
+#define V8_SYSTEM_H
+
+//
+// AArch64 SPSR
+//
+#define AARCH64_SPSR_EL3h 0b1101
+#define AARCH64_SPSR_EL3t 0b1100
+#define AARCH64_SPSR_EL2h 0b1001
+#define AARCH64_SPSR_EL2t 0b1000
+#define AARCH64_SPSR_EL1h 0b0101
+#define AARCH64_SPSR_EL1t 0b0100
+#define AARCH64_SPSR_EL0t 0b0000
+#define AARCH64_SPSR_RW (1 << 4)
+#define AARCH64_SPSR_F  (1 << 6)
+#define AARCH64_SPSR_I  (1 << 7)
+#define AARCH64_SPSR_A  (1 << 8)
+#define AARCH64_SPSR_D  (1 << 9)
+#define AARCH64_SPSR_IL (1 << 20)
+#define AARCH64_SPSR_SS (1 << 21)
+#define AARCH64_SPSR_V  (1 << 28)
+#define AARCH64_SPSR_C  (1 << 29)
+#define AARCH64_SPSR_Z  (1 << 30)
+#define AARCH64_SPSR_N  (1 << 31)
+
+//
+// Multiprocessor Affinity Register
+//
+#define MPIDR_EL1_AFF3_LSB 32
+#define MPIDR_EL1_U  (1 << 30)
+#define MPIDR_EL1_MT (1 << 24)
+#define MPIDR_EL1_AFF2_LSB 16
+#define MPIDR_EL1_AFF1_LSB  8
+#define MPIDR_EL1_AFF0_LSB  0
+#define MPIDR_EL1_AFF_WIDTH 8
+
+//
+// Data Cache Zero ID Register
+//
+#define DCZID_EL0_BS_LSB   0
+#define DCZID_EL0_BS_WIDTH 4
+#define DCZID_EL0_DZP_LSB  5
+#define DCZID_EL0_DZP (1 << 5)
+
+//
+// System Control Register
+//
+#define SCTLR_EL1_UCI     (1 << 26)
+#define SCTLR_ELx_EE      (1 << 25)
+#define SCTLR_EL1_E0E     (1 << 24)
+#define SCTLR_ELx_WXN     (1 << 19)
+#define SCTLR_EL1_nTWE    (1 << 18)
+#define SCTLR_EL1_nTWI    (1 << 16)
+#define SCTLR_EL1_UCT     (1 << 15)
+#define SCTLR_EL1_DZE     (1 << 14)
+#define SCTLR_ELx_I       (1 << 12)
+#define SCTLR_EL1_UMA     (1 << 9)
+#define SCTLR_EL1_SED     (1 << 8)
+#define SCTLR_EL1_ITD     (1 << 7)
+#define SCTLR_EL1_THEE    (1 << 6)
+#define SCTLR_EL1_CP15BEN (1 << 5)
+#define SCTLR_EL1_SA0     (1 << 4)
+#define SCTLR_ELx_SA      (1 << 3)
+#define SCTLR_ELx_C       (1 << 2)
+#define SCTLR_ELx_A       (1 << 1)
+#define SCTLR_ELx_M       (1 << 0)
+
+//
+// Architectural Feature Access Control Register
+//
+#define CPACR_EL1_TTA     (1 << 28)
+#define CPACR_EL1_FPEN    (3 << 20)
+
+//
+// Architectural Feature Trap Register
+//
+#define CPTR_ELx_TCPAC (1 << 31)
+#define CPTR_ELx_TTA   (1 << 20)
+#define CPTR_ELx_TFP   (1 << 10)
+
+//
+// Secure Configuration Register
+//
+#define SCR_EL3_TWE  (1 << 13)
+#define SCR_EL3_TWI  (1 << 12)
+#define SCR_EL3_ST   (1 << 11)
+#define SCR_EL3_RW   (1 << 10)
+#define SCR_EL3_SIF  (1 << 9)
+#define SCR_EL3_HCE  (1 << 8)
+#define SCR_EL3_SMD  (1 << 7)
+#define SCR_EL3_EA   (1 << 3)
+#define SCR_EL3_FIQ  (1 << 2)
+#define SCR_EL3_IRQ  (1 << 1)
+#define SCR_EL3_NS   (1 << 0)
+
+//
+// Hypervisor Configuration Register
+//
+#define HCR_EL2_ID   (1 << 33)
+#define HCR_EL2_CD   (1 << 32)
+#define HCR_EL2_RW   (1 << 31)
+#define HCR_EL2_TRVM (1 << 30)
+#define HCR_EL2_HVC  (1 << 29)
+#define HCR_EL2_TDZ  (1 << 28)
+
+#endif // V8_SYSTEM_H
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S
new file mode 100644
index 00000000..f0fcef26
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S
@@ -0,0 +1,69 @@
+//
+// Simple utility routines for baremetal v8 code
+//
+// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//
+// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
+//
+// Zero fill a block of memory
+//   Fill memory pages or similar structures with zeros.
+//   The byte count must be a multiple of the block fill size (16 bytes)
+//
+//  Inputs:
+//    blockPtr - base address of block to fill
+//    nBytes - block size, in bytes
+//
+//  Returns:
+//    pointer to just filled block, NULL if nBytes is
+//  incompatible with block fill size
+//
+    .global ZeroBlock
+    .type ZeroBlock, "function"
+    .cfi_startproc
+ZeroBlock:
+
+    //
+    // we fill data by steam, 16 bytes at a time: check that
+    // blocksize is a multiple of that
+    //
+    ubfx x2, x1, #0, #4
+    cbnz x2, incompatible
+
+    //
+    // we already have one register full of zeros, get another
+    //
+    mov x3, x2
+
+    //
+    // OK, set temporary pointer and away we go
+    //
+    add x0, x0, x1
+
+loop0:
+    subs x1, x1, #16
+    stp  x2, x3, [x0, #-16]!
+    b.ne loop0
+
+    //
+    // that's all - x0 will be back to its start value
+    //
+    ret
+
+    //
+    // parameters are incompatible with block size - return
+    // an indication that this is so
+    //
+incompatible:
+    mov x0,#0
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S
new file mode 100644
index 00000000..9e60e001
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S
@@ -0,0 +1,252 @@
+// ------------------------------------------------------------
+// Armv8-A Vector tables
+//
+// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+    .global c0sync1
+    .global irqHandler
+    .global fiqHandler
+    .global irqFirstLevelHandler
+    .global fiqFirstLevelHandler
+
+    .section  EL1VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el1_vectors:
+c0sync1: B c0sync1
+
+    .balign 0x80
+c0irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr1: B c0serr1
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync1: B cxsync1
+
+    .balign 0x80
+cxirq1: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr1: B cxserr1
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync1: B l64sync1
+
+    .balign 0x80
+l64irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr1: B l64serr1
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync1: B l32sync1
+
+    .balign 0x80
+l32irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr1: B l32serr1
+
+//----------------------------------------------------------------
+
+    .section  EL2VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el2_vectors:
+c0sync2: B c0sync2
+
+    .balign 0x80
+c0irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr2: B c0serr2
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync2: B cxsync2
+
+    .balign 0x80
+cxirq2: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr2: B cxserr2
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync2: B l64sync2
+
+    .balign 0x80
+l64irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr2: B l64serr2
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync2: B l32sync2
+
+    .balign 0x80
+l32irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr2: B l32serr2
+
+//----------------------------------------------------------------
+
+    .section  EL3VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el3_vectors:
+c0sync3: B c0sync3
+
+    .balign 0x80
+c0irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr3: B c0serr3
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync3: B cxsync3
+
+    .balign 0x80
+cxirq3: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr3: B cxserr3
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync3: B l64sync3
+
+    .balign 0x80
+l64irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr3: B l64serr3
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync3: B l32sync3
+
+    .balign 0x80
+l32irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr3: B l32serr3
+
+
+    .section InterruptHandlers, "ax"
+    .balign 4
+
+    .type irqFirstLevelHandler, "function"
+irqFirstLevelHandler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+  BL       irqHandler
+  B        _tx_thread_context_restore
+
+    .type fiqFirstLevelHandler, "function"
+fiqFirstLevelHandler:
+  STP      x29, x30, [sp, #-16]!
+  STP      x18, x19, [sp, #-16]!
+  STP      x16, x17, [sp, #-16]!
+  STP      x14, x15, [sp, #-16]!
+  STP      x12, x13, [sp, #-16]!
+  STP      x10, x11, [sp, #-16]!
+  STP      x8, x9, [sp, #-16]!
+  STP      x6, x7, [sp, #-16]!
+  STP      x4, x5, [sp, #-16]!
+  STP      x2, x3, [sp, #-16]!
+  STP      x0, x1, [sp, #-16]!
+
+  BL       fiqHandler
+
+  LDP      x0, x1, [sp], #16
+  LDP      x2, x3, [sp], #16
+  LDP      x4, x5, [sp], #16
+  LDP      x6, x7, [sp], #16
+  LDP      x8, x9, [sp], #16
+  LDP      x10, x11, [sp], #16
+  LDP      x12, x13, [sp], #16
+  LDP      x14, x15, [sp], #16
+  LDP      x16, x17, [sp], #16
+  LDP      x18, x19, [sp], #16
+  LDP      x29, x30, [sp], #16
+  ERET
diff --git a/ports_module/cortex_a35/gnu/example_build/tx/.cproject b/ports_module/cortex_a35/gnu/example_build/tx/.cproject
new file mode 100644
index 00000000..e3b8bf79
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/tx/.cproject
@@ -0,0 +1,258 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1652432530" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1652432530.1250098983" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/tx}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.408478790" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1755052156" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.281590127" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym.1254489229" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.1541383646" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_modules}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.379931340" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" value="gnu.c.optimization.level.none" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch.1065567578" name="Architecture (-march)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.fpu.976967573" name="FPU (-mfpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.fpu" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.11119542" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.1308248336" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.842447027" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" value="gnu.c.optimization.level.none" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool command="aarch64-elf-gcc.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.2113642977" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.1603138513" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym.1797095306" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.1075418381" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.arch.7920486" name="Architecture (-march)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.arch" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.fpu.562016944" name="FPU (-mfpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.fpu" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.93700751" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool command="aarch64-elf-ar.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.1983468481" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.1806767239" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="-r" valueType="string"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input.1298708086" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input">
+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                								
+                                <outputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.output.478221475" outputPrefix="lib" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.output"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.2101445430" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.1756490450" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="src_generic/tx_misra.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.release.base.979090268">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.release.base.979090268" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.release.base.979090268" name="Release" parent="com.arm.eclipse.build.config.v6.lib.release.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.release.base.979090268." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.423324903" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6">
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.423324903.1130606835" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1266548138" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1044032924" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.297151373" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
+                                								
+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.1163793161" superClass="com.arm.tool.c.compiler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.370619180" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.570633086" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1018315840" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.1395216260" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.273247708" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.904926956" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="src_generic/tx_misra.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="tx.com.arm.eclipse.build.project.v6.lib.1209080418" name="Static Library"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        		
+        <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.lib.debug.base.332565915;com.arm.eclipse.build.config.v6.lib.debug.base.332565915.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1755052156;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.11119542">
+            			
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+            		
+        </scannerConfigBuildInfo>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/gnu/example_build/tx/.project b/ports_module/cortex_a35/gnu/example_build/tx/.project
new file mode 100644
index 00000000..8f71f94d
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/tx/.project
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>tx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_modules</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
+		</link>
+		<link>
+			<name>src_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/src</locationURI>
+		</link>
+		<link>
+			<name>src_port</name>
+			<type>2</type>
+			<locationURI>PARENT-2-PROJECT_LOC/module_manager/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35/gnu/example_build/txm/.cproject b/ports_module/cortex_a35/gnu/example_build/txm/.cproject
new file mode 100644
index 00000000..267cf889
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/txm/.cproject
@@ -0,0 +1,198 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings>
+                    					
+                    <externalSetting>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/>
+                        					
+                    </externalSetting>
+                    				
+                </externalSettings>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1940578560" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1940578560.1206339987" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/txm}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.577302939" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.948279352" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.808254157" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic_module_manager}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1147593988" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.581062876" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.269490798" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch.168537148" name="Architecture (-march)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym.841907083" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.846815502" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.1779346429" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.730893571" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1685004753" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.933436547" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.2021469141" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" valueType="boolean"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.arch.1802198374" name="Architecture (-march)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.arch" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym.477939538" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.1013171365" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.1844101184" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool command="aarch64-elf-ar.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.1278004178" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.1900478654" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="-r" valueType="string"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input.824702411" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input">
+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                								
+                                <outputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.output.478843545" outputPrefix="lib" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.output"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.494963401" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.276907065" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/txm"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        		
+        <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551;com.arm.eclipse.build.config.v6.lib.debug.base.1507005551.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.948279352;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.846815502">
+            			
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+            		
+        </scannerConfigBuildInfo>
+        	
+    </storageModule>
+    
+</cproject>
diff --git a/ports_module/cortex_a35/gnu/example_build/txm/.project b/ports_module/cortex_a35/gnu/example_build/txm/.project
new file mode 100644
index 00000000..8b510516
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/example_build/txm/.project
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>txm</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_generic_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_generic_modules</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
+		</link>
+		<link>
+			<name>src_generic_module_lib</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_lib/src</locationURI>
+		</link>
+		<link>
+			<name>src_port_module_lib</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/module_lib/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35/gnu/inc/tx_port.h b/ports_module/cortex_a35/gnu/inc/tx_port.h
new file mode 100644
index 00000000..a05d95fb
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/inc/tx_port.h
@@ -0,0 +1,396 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include <stdlib.h>
+#include <string.h>
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef int                                     LONG;
+typedef unsigned int                            ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Override the alignment type to use 64-bit alignment and storage for pointers.  */
+
+#define ALIGN_TYPE_DEFINED
+typedef unsigned long long                      ALIGN_TYPE;
+
+
+/* Override the free block marker for byte pools to be a 64-bit constant.   */
+
+#define TX_BYTE_BLOCK_FREE                      ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE)
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              4096        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex ARMv8 port.  */ 
+
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ & FIQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#else
+#ifndef TX_TRACE_TIME_SOURCE
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0
+#define TX_THREAD_EXTENSION_1
+#define TX_THREAD_EXTENSION_2               ULONG   tx_thread_fp_enable;
+#define TX_THREAD_EXTENSION_3               VOID    *tx_thread_extension_ptr;               \
+                                            VOID    *tx_thread_module_instance_ptr;         \
+                                            VOID    *tx_thread_module_entry_info_ptr;       \
+                                            ULONG   tx_thread_module_current_user_mode;     \
+                                            ULONG   tx_thread_module_user_mode;             \
+                                            ULONG   tx_thread_module_saved_lr;              \
+                                            VOID    *tx_thread_module_kernel_stack_start;   \
+                                            VOID    *tx_thread_module_kernel_stack_end;     \
+                                            ULONG   tx_thread_module_kernel_stack_size;     \
+                                            VOID    *tx_thread_module_stack_ptr;            \
+                                            VOID    *tx_thread_module_stack_start;          \
+                                            VOID    *tx_thread_module_stack_end;            \
+                                            ULONG   tx_thread_module_stack_size;            \
+                                            VOID    *tx_thread_module_reserved;
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       b =  (UINT) __builtin_ctz((unsigned int) m);
+
+#endif
+
+
+/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout
+   can figure out what thread timeout to process.  */
+   
+#define TX_TIMER_INTERNAL_EXTENSION             VOID    *tx_timer_internal_thread_timeout_ptr;
+
+
+/* Define the thread timeout setup logic in _tx_thread_create.  */
+
+#define TX_THREAD_CREATE_TIMEOUT_SETUP(t)    (t) -> tx_thread_timer.tx_timer_internal_timeout_function =    &(_tx_thread_timeout);            \
+                                             (t) -> tx_thread_timer.tx_timer_internal_timeout_param =       0;                                \
+                                             (t) -> tx_thread_timer.tx_timer_internal_thread_timeout_ptr =  (VOID *) (t);
+
+
+/* Define the thread timeout pointer setup in _tx_thread_timeout.  */
+
+#define TX_THREAD_TIMEOUT_POINTER_SETUP(t)   (t) =  (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr;
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifndef TX_DISABLE_INLINE
+
+/* Define macros, with in-line assembly for performance.  */
+
+__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void)
+{
+
+unsigned long long  daif_value;
+
+    __asm__ volatile (" MRS  %0, DAIF ": "=r" (daif_value) );
+    __asm__ volatile (" MSR  DAIFSet, 0x3" : : : "memory" );
+    return((unsigned int) daif_value);
+}
+
+__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int daif_value)
+{
+
+unsigned long long temp;
+
+    temp =  (unsigned long long) daif_value;
+    __asm__ volatile (" MSR  DAIF,%0": : "r" (temp): "memory" );
+}
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+#define TX_DISABLE                              interrupt_save =  __disable_interrupts();
+#define TX_RESTORE                              __restore_interrupts(interrupt_save);
+
+#else
+
+unsigned int   _tx_thread_interrupt_disable(void);
+unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+#endif
+
+
+/* Define FP extension for the Cortex-A35.  Each is assumed to be called in the context of the executing
+   thread.  */
+
+#ifndef TX_SOURCE_CODE
+#define tx_thread_fp_enable                     _tx_thread_fp_enable
+#define tx_thread_fp_disable                    _tx_thread_fp_disable
+#endif
+
+VOID    tx_thread_fp_enable(VOID);
+VOID    tx_thread_fp_disable(VOID);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Modules Cortex-A35/GNU Version 6.1.3 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
diff --git a/ports_module/cortex_a35/gnu/inc/txm_module_port.h b/ports_module/cortex_a35/gnu/inc/txm_module_port.h
new file mode 100644
index 00000000..ea6cf2fc
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/inc/txm_module_port.h
@@ -0,0 +1,284 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
+/*                                                                        */
+/*    txm_module_port.h                                 Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file defines the basic module constants, interface structures, */
+/*    and function prototypes.                                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TXM_MODULE_PORT_H
+#define TXM_MODULE_PORT_H
+
+/* Determine if the optional Modules user define file should be used.  */
+
+#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in txm_module_user.h. The defines in this file may
+   alternately be defined on the command line.  */
+
+#include "txm_module_user.h"
+#endif
+
+/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
+  following extensions to the ThreadX thread control block (this code should replace
+  the corresponding macro define in tx_port.h):
+
+#define TX_THREAD_EXTENSION_2               VOID    *tx_thread_module_instance_ptr;         \
+                                            VOID    *tx_thread_module_entry_info_ptr;       \
+                                            ULONG   tx_thread_module_current_user_mode;     \
+                                            ULONG   tx_thread_module_user_mode;             \
+                                            ULONG   tx_thread_module_saved_lr;              \
+                                            VOID    *tx_thread_module_kernel_stack_start;   \
+                                            VOID    *tx_thread_module_kernel_stack_end;     \
+                                            ULONG   tx_thread_module_kernel_stack_size;     \
+                                            VOID    *tx_thread_module_stack_ptr;            \
+                                            VOID    *tx_thread_module_stack_start;          \
+                                            VOID    *tx_thread_module_stack_end;            \
+                                            ULONG   tx_thread_module_stack_size;            \
+                                            VOID    *tx_thread_module_reserved;
+
+The following extensions must also be defined in tx_port.h:
+
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+*/
+
+/* Define the kernel stack size for a module thread.  */
+#ifndef TXM_MODULE_KERNEL_STACK_SIZE
+#define TXM_MODULE_KERNEL_STACK_SIZE            768
+#endif
+
+/* Define constants specific to the tools the module can be built with for this particular modules port.  */
+
+#define TXM_MODULE_IAR_COMPILER                 0x00000000
+#define TXM_MODULE_RVDS_COMPILER                0x01000000
+#define TXM_MODULE_GNU_COMPILER                 0x02000000
+#define TXM_MODULE_COMPILER_MASK                0xFF000000
+#define TXM_MODULE_OPTIONS_MASK                 0x000000FF
+
+
+/* Define the properties for this particular module port.  */
+
+#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
+
+#ifdef  TXM_MODULE_MEMORY_PROTECTION_ENABLED
+#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
+#else
+#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
+#endif
+
+#define TXM_MODULE_USER_MODE                        0x00000001
+#define TXM_MODULE_MEMORY_PROTECTION                0x00000002
+#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS    0x00000004
+
+
+/* Define the supported options for this module.   */
+
+#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS    (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
+#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS     0
+
+
+/* Define offset adjustments according to the compiler used to build the module.  */
+
+#define TXM_MODULE_IAR_SHELL_ADJUST             24
+#define TXM_MODULE_IAR_START_ADJUST             28
+#define TXM_MODULE_IAR_STOP_ADJUST              32
+#define TXM_MODULE_IAR_CALLBACK_ADJUST          44
+
+#define TXM_MODULE_RVDS_SHELL_ADJUST            0
+#define TXM_MODULE_RVDS_START_ADJUST            0
+#define TXM_MODULE_RVDS_STOP_ADJUST             0
+#define TXM_MODULE_RVDS_CALLBACK_ADJUST         0
+
+#define TXM_MODULE_GNU_SHELL_ADJUST             24
+#define TXM_MODULE_GNU_START_ADJUST             28
+#define TXM_MODULE_GNU_STOP_ADJUST              32
+#define TXM_MODULE_GNU_CALLBACK_ADJUST          44
+
+
+/* Define other module port-specific constants.  */
+
+/* Define INLINE_DECLARE to inline for ARM compiler.  */
+
+#define INLINE_DECLARE inline
+
+
+/* Define the port-extensions to the module manager instance structure.  */
+
+#define TXM_MODULE_MANAGER_PORT_EXTENSION
+
+
+/* Define the memory fault information structure that is populated when a memory fault occurs.  */
+
+typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
+{
+    TX_THREAD           *txm_module_manager_memory_fault_info_thread_ptr;
+    VOID                *txm_module_manager_memory_fault_info_code_location;
+    ULONG               txm_module_manager_memory_fault_info_shcsr;
+    ULONG               txm_module_manager_memory_fault_info_cfsr;
+    ULONG               txm_module_manager_memory_fault_info_mmfar;
+    ULONG               txm_module_manager_memory_fault_info_bfar;
+    ULONG               txm_module_manager_memory_fault_info_control;
+    ULONG               txm_module_manager_memory_fault_info_sp;
+    ULONG               txm_module_manager_memory_fault_info_r0;
+    ULONG               txm_module_manager_memory_fault_info_r1;
+    ULONG               txm_module_manager_memory_fault_info_r2;
+    ULONG               txm_module_manager_memory_fault_info_r3;
+    ULONG               txm_module_manager_memory_fault_info_r4;
+    ULONG               txm_module_manager_memory_fault_info_r5;
+    ULONG               txm_module_manager_memory_fault_info_r6;
+    ULONG               txm_module_manager_memory_fault_info_r7;
+    ULONG               txm_module_manager_memory_fault_info_r8;
+    ULONG               txm_module_manager_memory_fault_info_r9;
+    ULONG               txm_module_manager_memory_fault_info_r10;
+    ULONG               txm_module_manager_memory_fault_info_r11;
+    ULONG               txm_module_manager_memory_fault_info_r12;
+    ULONG               txm_module_manager_memory_fault_info_lr;
+    ULONG               txm_module_manager_memory_fault_info_xpsr;
+} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
+
+
+#define TXM_MODULE_MANAGER_FAULT_INFO                                               \
+    TXM_MODULE_MANAGER_MEMORY_FAULT_INFO    _txm_module_manager_memory_fault_info;
+
+/* Define the macro to check the code alignment.  */
+
+#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment)    \
+    {                                                                               \
+        ALIGN_TYPE   temp;                                                          \
+        temp =  (ALIGN_TYPE) module_location;                                       \
+        temp =  temp & (code_alignment - 1);                                        \
+        if (temp)                                                                   \
+        {                                                                           \
+            _tx_mutex_put(&_txm_module_manager_mutex);                              \
+            return(TXM_MODULE_ALIGNMENT_ERROR);                                     \
+        }                                                                           \
+    }
+
+
+/* Define the macro to adjust the alignment and size for code/data areas.  */
+
+#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) \
+    {                                                                                                              \
+        code_size = (code_size % 32) ? ((code_size + 32) & ~32) : (code_size);                                     \
+        code_alignment = 32;                                                                                       \
+        data_size = (data_size % 32) ? ((data_size + 32) & ~32) : (data_size);                                     \
+        data_alignment = 32;                                                                                       \
+    }
+
+
+/* Define the macro to adjust the symbols in the module preamble.  */
+
+#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
+    if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER)         \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_IAR_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_IAR_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_IAR_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_IAR_CALLBACK_ADJUST;                 \
+    }                                                                               \
+    else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER)   \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_RVDS_SHELL_ADJUST;                   \
+        start_function_adjust =     TXM_MODULE_RVDS_START_ADJUST;                   \
+        stop_function_adjust =      TXM_MODULE_RVDS_STOP_ADJUST;                    \
+        callback_function_adjust =  TXM_MODULE_RVDS_CALLBACK_ADJUST;                \
+    }                                                                               \
+    else                                                                            \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_GNU_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_GNU_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_GNU_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_GNU_CALLBACK_ADJUST;                 \
+    }
+
+
+/* Define the macro to populate the thread control block with module port-specific information.
+   Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
+*/
+
+#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance)                                                                    \
+    thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher =   _txm_module_manager_kernel_dispatch;
+
+
+/* Define the macro to populate the module control block with module port-specific information.
+*/
+#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance)
+
+
+/* Define the macro to perform port-specific functions when unloading the module.  */
+/* Nothing needs to be done for this port.  */
+#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
+
+
+/* Define the macros to perform port-specific checks when passing pointers to the kernel.  */
+
+/* Define macro to make sure object is inside the module's data.  */
+#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) (TX_SUCCESS)
+
+/* Define some internal prototypes to this module port.  */
+
+#ifndef TX_SOURCE_CODE
+#define txm_module_manager_memory_fault_notify              _txm_module_manager_memory_fault_notify
+#endif
+
+
+#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES                                                                                                                      \
+VOID  _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment);   \
+ULONG _txm_module_manager_region_size_get(ULONG block_size);                                                                                                          \
+UINT  _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);                                                 \
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2);
+
+#define TXM_MODULE_MANAGER_VERSION_ID   \
+CHAR                            _txm_module_manager_version_id[] =  \
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Module Cortex-A35/GNU Version 6.1.3 *";
+
+#endif
diff --git a/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c
new file mode 100644
index 00000000..f96f5fe4
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c
@@ -0,0 +1,180 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#ifndef TXM_MODULE
+#define TXM_MODULE
+#endif
+
+#ifndef TX_SOURCE_CODE
+#define TX_SOURCE_CODE
+#endif
+
+
+/* Include necessary system files.  */
+
+#include "txm_module.h"
+#include "tx_thread.h"
+
+/* Define the global module entry pointer from the start thread of the module.  */
+
+TXM_MODULE_THREAD_ENTRY_INFO    *_txm_module_entry_info;
+
+
+/* Define the dispatch function pointer used in the module implementation.  */
+
+ALIGN_TYPE                      (*_txm_module_kernel_call_dispatcher)(ULONG type, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param3);
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_thread_shell_entry                   Cortex-A35/GNU     */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function calls the specified entry function of the thread.  It */
+/*    also provides a place for the thread's entry function to return.    */
+/*    If the thread returns, this function places the thread in a         */
+/*    "COMPLETED" state.                                                  */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                        Pointer to current thread         */
+/*    thread_info                       Pointer to thread entry info      */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_initialize            cstartup initialization           */
+/*    thread_entry                      Thread's entry function           */
+/*    tx_thread_resume                  Resume the module callback thread */
+/*    _txm_module_thread_system_suspend Module thread suspension routine  */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Initial thread stack frame                                          */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
+{
+
+TX_INTERRUPT_SAVE_AREA
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+VOID            (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type);
+#endif
+
+
+    /* Perform any additional activities for tool or user purpose.  */
+    TX_THREAD_STARTED_EXTENSION(thread_ptr)
+
+    /* Determine if this is the start thread.  If so, we must prepare the module for
+       execution.  If not, simply skip the C startup code.  */
+    if (thread_info -> txm_module_thread_entry_info_start_thread)
+    {
+        /* Initialize the C library */
+        extern VOID _gcc_setup(TXM_MODULE_INSTANCE *);
+        _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address);
+
+        /* Save the entry info pointer, for later use.  */
+        _txm_module_entry_info =  thread_info;
+
+        /* Save the kernel function dispatch address. This is used to make all resident calls from
+           the module.  */
+        _txm_module_kernel_call_dispatcher =  thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
+
+        /* Ensure that we have a valid pointer.  */
+        while (!_txm_module_kernel_call_dispatcher)
+        {
+            /* Loop here, if an error is present getting the dispatch function pointer!
+               An error here typically indicates the resident portion of _tx_thread_schedule
+               is not supporting the trap to obtain the function pointer.   */
+        }
+        
+        /* Resume the module's callback thread, already created in the manager.  */
+        _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
+    }
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Disable interrupts.  */
+    TX_DISABLE
+
+    /* Pickup the entry/exit application callback routine.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Restore interrupts.  */
+    TX_RESTORE
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has been entered!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
+    }
+#endif
+
+    /* Call current thread's entry function.  */
+    (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
+
+    /* Suspend thread with a "completed" state.  */
+
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Pickup the entry/exit application callback routine again.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has exited!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
+    }
+#endif
+
+    /* Call actual thread suspension routine.  */
+    _txm_module_thread_system_suspend(thread_ptr);
+
+#ifdef TX_SAFETY_CRITICAL
+
+    /* If we ever get here, raise safety critical exception.  */
+    TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
+#endif
+}
+
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..6707597d
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S
@@ -0,0 +1,288 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+/*    .set ENABLE_ARM_FP,1  */
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_restore                        Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function restores the interrupt context if it is processing a  */
+/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+/*    if no thread was running, the function returns to the scheduler.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling routine     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                  Interrupt Service Routines    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_restore(VOID)
+// {
+    .global _tx_thread_context_restore
+    .type   _tx_thread_context_restore, @function
+_tx_thread_context_restore:
+
+    /* Lockout interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR exit function to indicate an ISR is complete.  */
+
+    BL      _tx_execution_isr_exit              // Call the ISR exit function
+#endif
+
+    /* Determine if interrupts are nested.  */
+    // if (--_tx_thread_system_state)
+    // {
+
+    LDR     x3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     w2, [x3, #0]                        // Pickup system state
+    SUB     w2, w2, #1                          // Decrement the counter
+    STR     w2, [x3, #0]                        // Store the counter 
+    CMP     w2, #0                              // Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      // If so, not a nested restore
+
+    /* Interrupts are nested.  */
+
+    /* Just recover the saved registers and return to the point of 
+       interrupt.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+    // }
+__tx_thread_not_nested_restore:
+
+    /* Determine if a thread was interrupted and no preemption is required.  */
+    // else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+    //           || (_tx_thread_preempt_disable))
+    // {
+
+    LDR     x1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     x0, [x1, #0]                        // Pickup actual current thread pointer
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     // Yes, idle system was interrupted
+
+    LDR     x3, =_tx_thread_preempt_disable     // Pickup preempt disable address
+    LDR     w2, [x3, #0]                        // Pickup actual preempt disable flag
+    CMP     w2, #0                              // Is it set?
+    BNE     __tx_thread_no_preempt_restore      // Yes, don't preempt this thread
+    LDR     x3, =_tx_thread_execute_ptr         // Pickup address of execute thread ptr
+    LDR     x2, [x3, #0]                        // Pickup actual execute thread pointer
+    CMP     x0, x2                              // Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore         // No, preemption needs to happen
+
+
+__tx_thread_no_preempt_restore:
+
+    /* Restore interrupted thread or ISR.  */
+
+    /* Pickup the saved stack pointer.  */
+    // sp =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+
+    LDR     x4, [x0, #8]                        // Switch to thread stack pointer
+    MOV     sp, x4                              //
+
+   /* Recover the saved context and return to the point of interrupt.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+    // }
+    // else
+    // {
+__tx_thread_preempt_restore:
+
+    LDR     x4, [x0, #8]                        // Switch to thread stack pointer
+    MOV     sp, x4                              //
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+    STP     x20, x21, [sp, #-16]!               // Save x20, x21
+    STP     x22, x23, [sp, #-16]!               // Save x22, x23
+    STP     x24, x25, [sp, #-16]!               // Save x24, x25
+    STP     x26, x27, [sp, #-16]!               // Save x26, x27
+    STP     x28, x29, [sp, #-16]!               // Save x28, x29
+#ifdef ENABLE_ARM_FP
+    LDR     w3, [x0, #248]                      // Pickup FP enable flag
+    CMP     w3, #0                              // Is FP enabled?
+    BEQ     _skip_fp_save                       // No, skip FP save
+    STP     q0,  q1,  [sp, #-32]!               // Save q0, q1
+    STP     q2,  q3,  [sp, #-32]!               // Save q2, q3
+    STP     q4,  q5,  [sp, #-32]!               // Save q4, q5
+    STP     q6,  q7,  [sp, #-32]!               // Save q6, q7
+    STP     q8,  q9,  [sp, #-32]!               // Save q8, q9
+    STP     q10, q11, [sp, #-32]!               // Save q10, q11
+    STP     q12, q13, [sp, #-32]!               // Save q12, q13
+    STP     q14, q15, [sp, #-32]!               // Save q14, q15
+    STP     q16, q17, [sp, #-32]!               // Save q16, q17
+    STP     q18, q19, [sp, #-32]!               // Save q18, q19
+    STP     q20, q21, [sp, #-32]!               // Save q20, q21
+    STP     q22, q23, [sp, #-32]!               // Save q22, q23
+    STP     q24, q25, [sp, #-32]!               // Save q24, q25
+    STP     q26, q27, [sp, #-32]!               // Save q26, q27
+    STP     q28, q29, [sp, #-32]!               // Save q28, q29
+    STP     q30, q31, [sp, #-32]!               // Save q30, q31
+    MRS     x2, FPSR                            // Pickup FPSR
+    MRS     x3, FPCR                            // Pickup FPCR
+    STP     x2, x3, [sp, #-16]!                 // Save FPSR, FPCR
+_skip_fp_save:
+#endif
+    STP     x4, x5, [sp, #-16]!                 // Save x4 (SPSR_EL3), x5 (ELR_E3)
+
+    MOV     x3, sp                              // Move sp into x3
+    STR     x3, [x0, #8]                        // Save stack pointer in thread control
+                                                //   block
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, #0]                        // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+
+    /* Save the remaining time-slice and disable it.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    LDR     x3, =_tx_timer_time_slice           // Pickup time-slice variable address
+    LDR     w2, [x3, #0]                        // Pickup time-slice
+    CMP     w2, #0                              // Is it active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save it
+
+        /* _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+        _tx_timer_time_slice =  0;  */
+
+    STR     w2, [x0, #36]                       // Save thread's time-slice
+    MOV     w2, #0                              // Clear value
+    STR     w2, [x3, #0]                        // Disable global time-slice flag
+
+    // }
+__tx_thread_dont_save_ts:
+
+
+    /* Clear the current task pointer.  */
+    // _tx_thread_current_ptr =  TX_NULL;
+
+    MOV     x0, #0                              // NULL value
+    STR     x0, [x1, #0]                        // Clear current thread pointer
+
+    /* Return to the scheduler.  */
+    // _tx_thread_schedule();
+
+    // }
+
+__tx_thread_idle_system_restore:
+
+    /* Just return back to the scheduler!  */
+
+    LDR    x1, =_tx_thread_schedule             // Build address for _tx_thread_schedule
+#ifdef EL1
+    MSR    ELR_EL1, x1                          // Setup point of interrupt
+//    MOV    x1, #0x4                             // Setup EL1 return
+//    MSR    spsr_el1, x1                         // Move into SPSR
+#else
+#ifdef EL2
+    MSR    ELR_EL2, x1                          // Setup point of interrupt
+//    MOV    x1, #0x8                             // Setup EL2 return
+//    MSR    spsr_el2, x1                         // Move into SPSR
+#else
+    MSR    ELR_EL3, x1                          // Setup point of interrupt
+//    MOV    x1, #0xC                             // Setup EL3 return
+//    MSR    spsr_el3, x1                         // Move into SPSR
+#endif
+#endif
+    ERET                                        // Return to scheduler
+// }
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S
new file mode 100644
index 00000000..62f5923a
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S
@@ -0,0 +1,217 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_save                           Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves the context of an executing thread in the       */
+/*    beginning of interrupt processing.  The function also ensures that  */
+/*    the system stack is used upon return to the calling ISR.            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_save(VOID)
+// {
+    .global _tx_thread_context_save
+    .type   _tx_thread_context_save, @function
+_tx_thread_context_save:
+
+    /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked
+       out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, 
+       and all other registers are intact.  */
+
+    /* Check for a nested interrupt condition.  */
+    // if (_tx_thread_system_state++)
+    // {
+
+    STP     x0, x1, [sp, #-16]!                 // Save x0, x1
+    STP     x2, x3, [sp, #-16]!                 // Save x2, x3
+    LDR     x3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     w2, [x3, #0]                        // Pickup system state
+    CMP     w2, #0                              // Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         // Yes, not a nested context save
+
+    /* Nested interrupt condition.  */
+
+    ADD     w2, w2, #1                          // Increment the nested interrupt counter
+    STR     w2, [x3, #0]                        // Store it back in the variable
+
+   /* Save the rest of the scratch registers on the stack and return to the
+      calling ISR.  */
+
+    STP     x4, x5, [sp, #-16]!                 // Save x4, x5
+    STP     x6, x7, [sp, #-16]!                 // Save x6, x7
+    STP     x8, x9, [sp, #-16]!                 // Save x8, x9
+    STP     x10, x11, [sp, #-16]!               // Save x10, x11
+    STP     x12, x13, [sp, #-16]!               // Save x12, x13
+    STP     x14, x15, [sp, #-16]!               // Save x14, x15
+    STP     x16, x17, [sp, #-16]!               // Save x16, x17
+    STP     x18, x19, [sp, #-16]!               // Save x18, x19
+#ifdef EL1
+    MRS     x0, SPSR_EL1                        // Pickup SPSR
+    MRS     x1, ELR_EL1                         // Pickup ELR (point of interrupt)
+#else
+#ifdef EL2
+    MRS     x0, SPSR_EL2                        // Pickup SPSR
+    MRS     x1, ELR_EL2                         // Pickup ELR (point of interrupt)
+#else
+    MRS     x0, SPSR_EL3                        // Pickup SPSR
+    MRS     x1, ELR_EL3                         // Pickup ELR (point of interrupt)
+#endif
+#endif
+    STP     x0, x1, [sp, #-16]!                 // Save SPSR, ELR
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    /* Return to the ISR.  */
+
+    RET                                         // Return to ISR
+
+__tx_thread_not_nested_save:
+    // }
+
+    /* Otherwise, not nested, check to see if a thread was running.  */
+    // else if (_tx_thread_current_ptr)
+    // {
+
+    ADD     w2, w2, #1                          // Increment the interrupt counter
+    STR     w2, [x3, #0]                        // Store it back in the variable
+    LDR     x1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     x0, [x1, #0]                        // Pickup current thread pointer
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_save        // If so, interrupt occurred in 
+                                                //   scheduling loop - nothing needs saving!
+
+    /* Save minimal context of interrupted thread.  */
+
+    STP     x4, x5, [sp, #-16]!                 // Save x4, x5
+    STP     x6, x7, [sp, #-16]!                 // Save x6, x7
+    STP     x8, x9, [sp, #-16]!                 // Save x8, x9
+    STP     x10, x11, [sp, #-16]!               // Save x10, x11
+    STP     x12, x13, [sp, #-16]!               // Save x12, x13
+    STP     x14, x15, [sp, #-16]!               // Save x14, x15
+    STP     x16, x17, [sp, #-16]!               // Save x16, x17
+    STP     x18, x19, [sp, #-16]!               // Save x18, x19
+#ifdef EL1
+    MRS     x4, SPSR_EL1                        // Pickup SPSR
+    MRS     x5, ELR_EL1                         // Pickup ELR (point of interrupt)
+#else
+#ifdef EL2
+    MRS     x4, SPSR_EL2                        // Pickup SPSR
+    MRS     x5, ELR_EL2                         // Pickup ELR (point of interrupt)
+#else
+    MRS     x4, SPSR_EL3                        // Pickup SPSR
+    MRS     x5, ELR_EL3                         // Pickup ELR (point of interrupt)
+#endif
+#endif
+    STP     x4, x5, [sp, #-16]!                 // Save SPSR, ELR
+
+    /* Save the current stack pointer in the thread's control block.  */
+    // _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+
+    MOV     x4, sp                              //
+    STR     x4, [x0, #8]                        // Save thread stack pointer
+
+    /* Switch to the system stack.  */
+    // sp =  _tx_thread_system_stack_ptr
+
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, #0]                        // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    RET                                         // Return to caller
+
+    // }
+    // else
+    // {
+
+__tx_thread_idle_system_save:
+
+    /* Interrupt occurred in the scheduling loop.  */
+
+    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+       processing.  */
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    ADD     sp, sp, #48                         // Recover saved registers
+    RET                                         // Continue IRQ processing  
+
+    // }
+// } 
+
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c
new file mode 100644
index 00000000..7030ad59
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c
@@ -0,0 +1,94 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fp_disable                             Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function disables the FP for the currently executing thread.   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_fp_disable(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+ULONG       system_state;
+
+
+    /* Pickup the current thread pointer.  */
+    TX_THREAD_GET_CURRENT(thread_ptr);
+
+    /* Get the system state.  */
+    system_state =  TX_THREAD_GET_SYSTEM_STATE();
+
+    /* Make sure it is not NULL. */
+    if (thread_ptr != TX_NULL)
+    {
+        
+        /* Thread is running... make sure the call is from the thread context.  */
+        if (system_state == 0)
+        {
+        
+            /* Yes, now set the FP enable flag to false in the TX_THREAD structure.  */
+            thread_ptr -> tx_thread_fp_enable =  TX_FALSE;
+        }
+    }
+}
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c
new file mode 100644
index 00000000..98b5551f
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c
@@ -0,0 +1,94 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fp_enable                              Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function enabled the FP for the currently executing thread.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_fp_enable(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+ULONG       system_state;
+
+
+    /* Pickup the current thread pointer.  */
+    TX_THREAD_GET_CURRENT(thread_ptr);
+
+    /* Get the system state.  */
+    system_state =  TX_THREAD_GET_SYSTEM_STATE();
+
+    /* Make sure it is not NULL. */
+    if (thread_ptr != TX_NULL)
+    {
+        
+        /* Thread is running... make sure the call is from the thread context.  */
+        if (system_state == 0)
+        {
+        
+            /* Yes, now setup the FP enable flag in the TX_THREAD structure.  */
+            thread_ptr -> tx_thread_fp_enable =  TX_TRUE;
+        }
+    }
+}
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..875627f8
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S
@@ -0,0 +1,80 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_control                      Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for changing the interrupt lockout     */
+/*    posture of the system.                                              */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    new_posture                           New interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_control(UINT new_posture)
+// {
+    .global  _tx_thread_interrupt_control
+    .type    _tx_thread_interrupt_control, @function
+_tx_thread_interrupt_control:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     x1, DAIF                            // Pickup current interrupt posture
+
+    /* Apply the new interrupt posture.  */
+
+    MSR     DAIF, x0                            // Set new interrupt posture
+    MOV     x0, x1                              // Setup return value
+    RET                                         // Return to caller
+// }
+
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S
new file mode 100644
index 00000000..cc30b5c7
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S
@@ -0,0 +1,78 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_disable                      Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for disabling interrupts               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_disable(void)
+// {
+    .global _tx_thread_interrupt_disable
+    .type   _tx_thread_interrupt_disable, @function
+_tx_thread_interrupt_disable:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     x0, DAIF                            // Pickup current interrupt lockout posture
+
+    /* Mask interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    RET                                         // Return to caller
+// }
+
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S
new file mode 100644
index 00000000..b87100f8
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S
@@ -0,0 +1,75 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_restore                      Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for restoring interrupts to the state  */
+/*    returned by a previous _tx_thread_interrupt_disable call.           */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_restore(UINT old_posture)
+// {
+    .global _tx_thread_interrupt_restore
+    .type   _tx_thread_interrupt_restore, @function
+_tx_thread_interrupt_restore:
+
+    /* Restore the old interrupt posture.  */
+
+    MSR     DAIF, x0                            // Setup the old posture
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S
new file mode 100644
index 00000000..2d733c92
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S
@@ -0,0 +1,225 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_schedule                               Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function waits for a thread control block pointer to appear in */
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+/*    in the variable, the corresponding thread is resumed.               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+/*    _tx_thread_system_return             Return to system from thread   */
+/*    _tx_thread_context_restore           Restore thread's context       */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_schedule(VOID)
+// {
+    .global _tx_thread_schedule
+    .type   _tx_thread_schedule, @function
+_tx_thread_schedule:
+
+    /* Enable interrupts.  */
+
+    MSR     DAIFClr, 0x3                        // Enable interrupts
+
+    // Wait for a thread to execute.  */
+    // do
+    // {
+    
+    LDR     x1, =_tx_thread_execute_ptr         // Address of thread execute ptr
+
+#ifdef TX_ENABLE_WFI
+__tx_thread_schedule_loop:
+    LDR     x0, [x1, #0]                        // Pickup next thread to execute
+    CMP     x0, #0                              // Is it NULL?
+    BNE     _tx_thread_schedule_thread          // 
+    WFI                                         // 
+    B       __tx_thread_schedule_loop           // Keep looking for a thread
+_tx_thread_schedule_thread:
+#else
+__tx_thread_schedule_loop:
+    LDR     x0, [x1, #0]                        // Pickup next thread to execute
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_schedule_loop           // If so, keep looking for a thread
+#endif
+
+    // }
+    // while(_tx_thread_execute_ptr == TX_NULL);
+    
+    /* Yes! We have a thread to execute.  Lockout interrupts and
+       transfer control to it.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    /* Setup the current thread pointer.  */
+    // _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+
+    LDR     x1, =_tx_thread_current_ptr         // Pickup address of current thread 
+    STR     x0, [x1, #0]                        // Setup current thread pointer
+
+    /* Increment the run count for this thread.  */
+    // _tx_thread_current_ptr -> tx_thread_run_count++;
+
+    LDR     w2, [x0, #4]                        // Pickup run counter
+    LDR     w3, [x0, #36]                       // Pickup time-slice for this thread
+    ADD     w2, w2, #1                          // Increment thread run-counter
+    STR     w2, [x0, #4]                        // Store the new run counter
+
+    /* Setup time-slice, if present.  */
+    // _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+
+    LDR     x2, =_tx_timer_time_slice           // Pickup address of time slice 
+                                                //   variable
+    LDR     x4, [x0, #8]                        // Switch stack pointers
+    MOV     sp, x4                              //
+    STR     w3, [x2, #0]                        // Setup time-slice
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread entry function to indicate the thread is executing.  */
+
+    MOV     x19, x0                             // Save x0
+    BL      _tx_execution_thread_enter          // Call the thread execution enter function
+    MOV     x0, x19                             // Restore x0
+#endif
+
+    /* Switch to the thread's stack.  */
+    // sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+
+    /* Determine if an interrupt frame or a synchronous task suspension frame
+       is present.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+    CMP     x5, #0                              // Check for synchronous context switch (ELR_EL1 = NULL)
+    BEQ     _tx_solicited_return
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+#ifdef ENABLE_ARM_FP
+    LDR     w1, [x0, #248]                      // Pickup FP enable flag
+    CMP     w1, #0                              // Is FP enabled?
+    BEQ     _skip_interrupt_fp_restore          // No, skip FP restore
+    LDP     x0, x1,   [sp], #16                 // Pickup FPSR, FPCR
+    MSR     FPSR, x0                            // Recover FPSR
+    MSR     FPCR, x1                            // Recover FPCR
+    LDP     q30, q31, [sp], #32                 // Recover q30, q31
+    LDP     q28, q29, [sp], #32                 // Recover q28, q29
+    LDP     q26, q27, [sp], #32                 // Recover q26, q27
+    LDP     q24, q25, [sp], #32                 // Recover q24, q25
+    LDP     q22, q23, [sp], #32                 // Recover q22, q23
+    LDP     q20, q21, [sp], #32                 // Recover q20, q21
+    LDP     q18, q19, [sp], #32                 // Recover q18, q19
+    LDP     q16, q17, [sp], #32                 // Recover q16, q17
+    LDP     q14, q15, [sp], #32                 // Recover q14, q15
+    LDP     q12, q13, [sp], #32                 // Recover q12, q13
+    LDP     q10, q11, [sp], #32                 // Recover q10, q11
+    LDP     q8,  q9,  [sp], #32                 // Recover q8, q9
+    LDP     q6,  q7,  [sp], #32                 // Recover q6, q7
+    LDP     q4,  q5,  [sp], #32                 // Recover q4, q5
+    LDP     q2,  q3,  [sp], #32                 // Recover q2, q3
+    LDP     q0,  q1,  [sp], #32                 // Recover q0, q1
+_skip_interrupt_fp_restore:
+#endif
+    LDP     x28, x29, [sp], #16                 // Recover x28
+    LDP     x26, x27, [sp], #16                 // Recover x26, x27
+    LDP     x24, x25, [sp], #16                 // Recover x24, x25
+    LDP     x22, x23, [sp], #16                 // Recover x22, x23
+    LDP     x20, x21, [sp], #16                 // Recover x20, x21
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+_tx_solicited_return:
+
+#ifdef ENABLE_ARM_FP
+    LDR     w1, [x0, #248]                      // Pickup FP enable flag
+    CMP     w1, #0                              // Is FP enabled?
+    BEQ     _skip_solicited_fp_restore          // No, skip FP restore
+    LDP     x0, x1,   [sp], #16                 // Pickup FPSR, FPCR
+    MSR     FPSR, x0                            // Recover FPSR
+    MSR     FPCR, x1                            // Recover FPCR
+    LDP     q14, q15, [sp], #32                 // Recover q14, q15
+    LDP     q12, q13, [sp], #32                 // Recover q12, q13
+    LDP     q10, q11, [sp], #32                 // Recover q10, q11
+    LDP     q8,  q9,  [sp], #32                 // Recover q8, q9
+_skip_solicited_fp_restore:
+#endif
+    LDP     x27, x28, [sp], #16                 // Recover x27, x28
+    LDP     x25, x26, [sp], #16                 // Recover x25, x26
+    LDP     x23, x24, [sp], #16                 // Recover x23, x24
+    LDP     x21, x22, [sp], #16                 // Recover x21, x22
+    LDP     x19, x20, [sp], #16                 // Recover x19, x20
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    MSR     DAIF, x4                            // Recover DAIF
+    RET                                         // Return to caller
+// }
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..e3fbf8e5
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S
@@ -0,0 +1,157 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_stack_build                            Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread control blk */
+/*    function_ptr                          Pointer to entry function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+// {
+    .global _tx_thread_stack_build
+    .type   _tx_thread_stack_build, @function
+_tx_thread_stack_build:
+
+
+    /* Build an interrupt frame.  On Cortex-A35 it should look like this:
+
+       Stack Top:      SSPR        Initial SSPR
+                       ELR         Point of interrupt
+                       x28         Initial value for x28
+                       not used    Not used
+                       x26         Initial value for x26
+                       x27         Initial value for x27
+                       x24         Initial value for x24
+                       x25         Initial value for x25
+                       x22         Initial value for x22
+                       x23         Initial value for x23
+                       x20         Initial value for x20
+                       x21         Initial value for x21
+                       x18         Initial value for x18
+                       x19         Initial value for x19
+                       x16         Initial value for x16
+                       x17         Initial value for x17
+                       x14         Initial value for x14
+                       x15         Initial value for x15
+                       x12         Initial value for x12
+                       x13         Initial value for x13
+                       x10         Initial value for x10
+                       x11         Initial value for x11
+                       x8          Initial value for x8
+                       x9          Initial value for x9
+                       x6          Initial value for x6
+                       x7          Initial value for x7
+                       x4          Initial value for x4
+                       x5          Initial value for x5
+                       x2          Initial value for x2
+                       x3          Initial value for x3
+                       x0          Initial value for x0
+                       x1          Initial value for x1
+                       x29         Initial value for x29 (frame pointer)
+                       x30         Initial value for x30 (link register)
+                       0           For stack backtracing
+
+       Stack Bottom: (higher memory address)
+    */
+
+    LDR     x4, [x0, #24]                       // Pickup end of stack area
+    BIC     x4, x4, #0xF                        // Ensure 16-byte alignment
+
+    /* Actually build the stack frame.  */
+
+    MOV     x2, #0                              // Build clear value
+    MOV     x3, #0                              //
+
+    STP     x2, x3, [x4, #-16]!                 // Set backtrace to 0
+    STP     x2, x3, [x4, #-16]!                 // Set initial x29, x30
+    STP     x2, x3, [x4, #-16]!                 // Set initial x0, x1
+    STP     x2, x3, [x4, #-16]!                 // Set initial x2, x3
+    STP     x2, x3, [x4, #-16]!                 // Set initial x4, x5
+    STP     x2, x3, [x4, #-16]!                 // Set initial x6, x7
+    STP     x2, x3, [x4, #-16]!                 // Set initial x8, x9
+    STP     x2, x3, [x4, #-16]!                 // Set initial x10, x11
+    STP     x2, x3, [x4, #-16]!                 // Set initial x12, x13
+    STP     x2, x3, [x4, #-16]!                 // Set initial x14, x15
+    STP     x2, x3, [x4, #-16]!                 // Set initial x16, x17
+    STP     x2, x3, [x4, #-16]!                 // Set initial x18, x19
+    STP     x2, x3, [x4, #-16]!                 // Set initial x20, x21
+    STP     x2, x3, [x4, #-16]!                 // Set initial x22, x23
+    STP     x2, x3, [x4, #-16]!                 // Set initial x24, x25
+    STP     x2, x3, [x4, #-16]!                 // Set initial x26, x27
+    STP     x2, x3, [x4, #-16]!                 // Set initial x28
+#ifdef EL1
+    MOV     x2, #0x4                            // Build initial SPSR  (EL1)
+#else
+#ifdef EL2
+    MOV     x2, #0x8                            // Build initial SPSR  (EL2)
+#else
+    MOV     x2, #0xC                            // Build initial SPSR  (EL3)
+#endif
+#endif
+    MOV     x3, x1                              // Build initial ELR
+    STP     x2, x3, [x4, #-16]!                 // Set initial SPSR & ELR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  x2;  */
+
+    STR     x4, [x0, #8]                        // Save stack pointer in thread's
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S
new file mode 100644
index 00000000..b0b4a7d7
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S
@@ -0,0 +1,151 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_system_return                          Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is target processor specific.  It is used to transfer */
+/*    control from a thread back to the ThreadX system.  Only a           */
+/*    minimal context is saved since the compiler assumes temp registers  */
+/*    are going to get slicked by a function call anyway.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling loop        */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_system_return(VOID)
+// {
+    .global _tx_thread_system_return
+    .type   _tx_thread_system_return, @function
+_tx_thread_system_return:
+
+    /* Save minimal context on the stack.  */
+
+    MRS     x0, DAIF                            // Pickup DAIF
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    STP     x29, x30, [sp, #-16]!               // Save x29 (frame pointer), x30 (link register)
+    STP     x19, x20, [sp, #-16]!               // Save x19, x20
+    STP     x21, x22, [sp, #-16]!               // Save x21, x22
+    STP     x23, x24, [sp, #-16]!               // Save x23, x24
+    STP     x25, x26, [sp, #-16]!               // Save x25, x26
+    STP     x27, x28, [sp, #-16]!               // Save x27, x28
+    LDR     x5, =_tx_thread_current_ptr         // Pickup address of current ptr
+    LDR     x6, [x5, #0]                        // Pickup current thread pointer
+
+#ifdef ENABLE_ARM_FP
+    LDR     w7, [x6, #248]                      // Pickup FP enable flag
+    CMP     w7, #0                              // Is FP enabled?
+    BEQ     _skip_fp_save                       // No, skip FP save
+    STP     q8,  q9,  [sp, #-32]!               // Save q8, q9
+    STP     q10, q11, [sp, #-32]!               // Save q10, q11
+    STP     q12, q13, [sp, #-32]!               // Save q12, q13
+    STP     q14, q15, [sp, #-32]!               // Save q14, q15
+    MRS     x2, FPSR                            // Pickup FPSR
+    MRS     x3, FPCR                            // Pickup FPCR
+    STP     x2, x3, [sp, #-16]!                 // Save FPSR, FPCR
+_skip_fp_save:
+#endif
+
+    MOV     x1, #0                              // Clear x1
+    STP     x0, x1, [sp, #-16]!                 // Save DAIF and clear value for ELR_EK1
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread exit function to indicate the thread is no longer executing.  */
+
+    MOV     x19, x5                             // Save x5
+    MOV     x20, x6                             // Save x6
+    BL      _tx_execution_thread_exit           // Call the thread exit function
+    MOV     x5, x19                             // Restore x5
+    MOV     x6, x20                             // Restore x6
+#endif
+
+    LDR     x2, =_tx_timer_time_slice           // Pickup address of time slice
+    LDR     w1, [x2, #0]                        // Pickup current time slice
+
+    /* Save current stack and switch to system stack.  */
+    // _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+    // sp = _tx_thread_system_stack_ptr;
+
+    MOV     x4, sp                              //
+    STR     x4, [x6, #8]                        // Save thread stack pointer
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, #0]                        // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+    /* Determine if the time-slice is active.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    MOV     x4, #0                              // Build clear value
+    CMP     w1, #0                              // Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save the time-slice
+
+       /* Save the current remaining time-slice.  */
+       // _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+       // _tx_timer_time_slice =  0;
+
+    STR     w4, [x2, #0]                        // Clear time-slice
+    STR     w1, [x6, #36]                       // Store current time-slice
+
+    // }
+__tx_thread_dont_save_ts:
+
+    /* Clear the current thread pointer.  */
+    // _tx_thread_current_ptr =  TX_NULL;
+
+    STR     x4, [x5, #0]                        // Clear current thread pointer
+
+    B       _tx_thread_schedule                 // Jump to scheduler!
+
+// }
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..d54b9b7f
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S
@@ -0,0 +1,228 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_timer_interrupt                               Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function processes the hardware timer interrupt.  This         */
+/*    processing includes incrementing the system clock and checking for  */
+/*    time slice and/or timer expiration.  If either is found, the        */
+/*    interrupt context save/restore functions are called along with the  */
+/*    expiration functions.                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_timer_expiration_process          Timer expiration processing   */
+/*    _tx_thread_time_slice                 Time slice interrupted thread */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    interrupt vector                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_timer_interrupt(VOID)
+// {
+    .global _tx_timer_interrupt
+    .type   _tx_timer_interrupt, @function
+_tx_timer_interrupt:
+
+    /* Upon entry to this routine, it is assumed that context save has already
+       been called, and therefore the compiler scratch registers are available
+       for use.  */
+
+    /* Increment the system clock.  */
+    // _tx_timer_system_clock++;
+
+    LDR     x1, =_tx_timer_system_clock         // Pickup address of system clock
+    LDR     w0, [x1, #0]                        // Pickup system clock
+    ADD     w0, w0, #1                          // Increment system clock
+    STR     w0, [x1, #0]                        // Store new system clock
+
+    /* Test for time-slice expiration.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    LDR     x3, =_tx_timer_time_slice           // Pickup address of time-slice 
+    LDR     w2, [x3, #0]                        // Pickup time-slice
+    CMP     w2, #0                              // Is it non-active?
+    BEQ     __tx_timer_no_time_slice            // Yes, skip time-slice processing
+
+       /* Decrement the time_slice.  */
+       // _tx_timer_time_slice--;
+
+    SUB     w2, w2, #1                          // Decrement the time-slice
+    STR     w2, [x3, #0]                        // Store new time-slice value
+
+       /* Check for expiration.  */
+       // if (__tx_timer_time_slice == 0)
+
+    CMP     w2, #0                              // Has it expired?
+    BNE     __tx_timer_no_time_slice            // No, skip expiration processing
+
+       /* Set the time-slice expired flag.  */
+       // _tx_timer_expired_time_slice =  TX_TRUE;
+
+    LDR     x3, =_tx_timer_expired_time_slice   // Pickup address of expired flag
+    MOV     w0, #1                              // Build expired value
+    STR     w0, [x3, #0]                        // Set time-slice expiration flag
+
+    /* } */
+
+__tx_timer_no_time_slice:
+
+    /* Test for timer expiration.  */
+    // if (*_tx_timer_current_ptr)
+    // {
+
+    LDR     x1, =_tx_timer_current_ptr          // Pickup current timer pointer addr
+    LDR     x0, [x1, #0]                        // Pickup current timer
+    LDR     x2, [x0, #0]                        // Pickup timer list entry
+    CMP     x2, #0                              // Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 // No, just increment the timer
+
+        /* Set expiration flag.  */
+        // _tx_timer_expired =  TX_TRUE;
+
+    LDR     x3, =_tx_timer_expired              // Pickup expiration flag address
+    MOV     w2, #1                              // Build expired value
+    STR     w2, [x3, #0]                        // Set expired flag
+    B       __tx_timer_done                     // Finished timer processing
+
+    // }
+    // else
+    // {
+__tx_timer_no_timer:
+
+        /* No timer expired, increment the timer pointer.  */
+        // _tx_timer_current_ptr++;
+
+    ADD     x0, x0, #8                          // Move to next timer
+
+        /* Check for wrap-around.  */
+        // if (_tx_timer_current_ptr == _tx_timer_list_end)
+
+    LDR     x3, =_tx_timer_list_end             // Pickup addr of timer list end
+    LDR     x2, [x3, #0]                        // Pickup list end
+    CMP     x0, x2                              // Are we at list end?
+    BNE     __tx_timer_skip_wrap                // No, skip wrap-around logic
+
+            /* Wrap to beginning of list.  */
+            // _tx_timer_current_ptr =  _tx_timer_list_start;
+
+    LDR     x3, =_tx_timer_list_start           // Pickup addr of timer list start
+    LDR     x0, [x3, #0]                        // Set current pointer to list start
+
+__tx_timer_skip_wrap:
+
+    STR     x0, [x1, #0]                        // Store new current timer pointer
+    // }
+
+__tx_timer_done:
+
+
+    /* See if anything has expired.  */
+    // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+    // {
+
+    LDR     x3, =_tx_timer_expired_time_slice   // Pickup addr of expired flag
+    LDR     w2, [x3, #0]                        // Pickup time-slice expired flag
+    CMP     w2, #0                              // Did a time-slice expire?
+    BNE     __tx_something_expired              // If non-zero, time-slice expired
+    LDR     x1, =_tx_timer_expired              // Pickup addr of other expired flag
+    LDR     w0, [x1, #0]                        // Pickup timer expired flag
+    CMP     w0, #0                              // Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          // No, nothing expired
+
+__tx_something_expired:
+
+
+    STP     x29, x30, [sp, #-16]!               // Save x29 (frame pointer), x30 (link register)
+
+    /* Did a timer expire?  */
+    // if (_tx_timer_expired)
+    // {
+
+    LDR     x1, =_tx_timer_expired              // Pickup addr of expired flag
+    LDR     w0, [x1, #0]                        // Pickup timer expired flag
+    CMP     w0, #0                              // Check for timer expiration
+    BEQ     __tx_timer_dont_activate            // If not set, skip timer activation
+
+        /* Process timer expiration.  */
+        // _tx_timer_expiration_process();
+
+    BL      _tx_timer_expiration_process        // Call the timer expiration handling routine
+
+    /* }  */
+__tx_timer_dont_activate:
+
+    /* Did time slice expire?  */
+    // if (_tx_timer_expired_time_slice)
+    // {
+
+    LDR     x3, =_tx_timer_expired_time_slice   // Pickup addr of time-slice expired 
+    LDR     w2, [x3, #0]                        // Pickup the actual flag
+    CMP     w2, #0                              // See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        // No, skip time-slice processing
+
+        /* Time slice interrupted thread.  */
+        // _tx_thread_time_slice();
+
+    BL      _tx_thread_time_slice               // Call time-slice processing
+
+    // }
+
+__tx_timer_not_ts_expiration:
+
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    // }
+
+__tx_timer_nothing_expired:
+
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c
new file mode 100644
index 00000000..b22695f7
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c
@@ -0,0 +1,85 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "txm_module.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_port_dispatch                 Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function dispatches the module's kernel request based upon the */
+/*    ID and parameters specified in the request.                         */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Module pointer                    */
+/*    kernel_request                    Module's kernel request           */
+/*    param_0                           First parameter                   */
+/*    param_1                           Second parameter                  */
+/*    param_2                           Third parameter                   */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    Port-specific ThreadX API Calls                                     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _txm_module_manager_kernel_dispatch                                 */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)
+{
+
+ALIGN_TYPE return_value = TX_NOT_AVAILABLE;
+
+    switch(kernel_request)
+    {
+        default:
+        {
+            /* Unhandled kernel request, return an error!  */
+            break;
+        }
+    }
+    
+    return(return_value);
+}
diff --git a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S
new file mode 100644
index 00000000..08af7371
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S
@@ -0,0 +1,163 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_thread_stack_build            Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread             */
+/*    function_ptr                          Pointer to entry function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
+// {
+    .global  _txm_module_manager_thread_stack_build
+    .type    _txm_module_manager_thread_stack_build, @function
+_txm_module_manager_thread_stack_build:
+
+
+    /* Build an interrupt frame.  On Cortex-A35 it should look like this:
+
+       Stack Top:      SSPR        Initial SSPR
+                       ELR         Point of interrupt
+                       x28         Initial value for x28
+                       not used    Not used
+                       x26         Initial value for x26
+                       x27         Initial value for x27
+                       x24         Initial value for x24
+                       x25         Initial value for x25
+                       x22         Initial value for x22
+                       x23         Initial value for x23
+                       x20         Initial value for x20
+                       x21         Initial value for x21
+                       x18         Initial value for x18
+                       x19         Initial value for x19
+                       x16         Initial value for x16
+                       x17         Initial value for x17
+                       x14         Initial value for x14
+                       x15         Initial value for x15
+                       x12         Initial value for x12
+                       x13         Initial value for x13
+                       x10         Initial value for x10
+                       x11         Initial value for x11
+                       x8          Initial value for x8
+                       x9          Initial value for x9
+                       x6          Initial value for x6
+                       x7          Initial value for x7
+                       x4          Initial value for x4
+                       x5          Initial value for x5
+                       x2          Initial value for x2
+                       x3          Initial value for x3
+                       x0          Initial value for x0
+                       x1          Initial value for x1
+                       x29         Initial value for x29 (frame pointer)
+                       x30         Initial value for x30 (link register)
+                       0           For stack backtracing
+
+       Stack Bottom: (higher memory address)
+    */
+
+    LDR     x4, [x0, #24]                       // Pickup end of stack area
+    BIC     x4, x4, #0xF                        // Ensure 16-byte alignment
+
+    LDR     x5, [x0, #8]                        // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
+                                                //   It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
+                                                //   function with the actual, initial stack pointer.
+
+    /* Actually build the stack frame.  */
+
+    MOV     x2, #0                              // Build clear value
+    MOV     x3, #0                              //
+
+    STP     x2, x3, [x4, #-16]!                 // Set backtrace to 0
+    STP     x2, x3, [x4, #-16]!                 // Set initial x29, x30
+    STP     x0, x5, [x4, #-16]!                 // Set initial x0, x1
+                                                //   x0->x0 is the thread control block pointer
+                                                //   x5->x1 is the thread entry info pointer
+    STP     x2, x3, [x4, #-16]!                 // Set initial x2, x3
+    STP     x2, x3, [x4, #-16]!                 // Set initial x4, x5
+    STP     x2, x3, [x4, #-16]!                 // Set initial x6, x7
+    STP     x2, x3, [x4, #-16]!                 // Set initial x8, x9
+    STP     x2, x3, [x4, #-16]!                 // Set initial x10, x11
+    STP     x2, x3, [x4, #-16]!                 // Set initial x12, x13
+    STP     x2, x3, [x4, #-16]!                 // Set initial x14, x15
+    STP     x2, x3, [x4, #-16]!                 // Set initial x16, x17
+    STP     x2, x3, [x4, #-16]!                 // Set initial x18, x19
+    STP     x2, x3, [x4, #-16]!                 // Set initial x20, x21
+    STP     x2, x3, [x4, #-16]!                 // Set initial x22, x23
+    STP     x2, x3, [x4, #-16]!                 // Set initial x24, x25
+    STP     x2, x3, [x4, #-16]!                 // Set initial x26, x27
+    STP     x2, x3, [x4, #-16]!                 // Set initial x28
+#ifdef EL1
+    MOV     x2, #0x4                            // Build initial SPSR  (EL1)
+#else
+#ifdef EL2
+    MOV     x2, #0x8                            // Build initial SPSR  (EL2)
+#else
+    MOV     x2, #0xC                            // Build initial SPSR  (EL3)
+#endif
+#endif
+    MOV     x3, x1                              // Build initial ELR
+    STP     x2, x3, [x4, #-16]!                 // Set initial SPSR & ELR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  x2;  */
+
+    STR     x4, [x0, #8]                        // Save stack pointer in thread's
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35/gnu/readme_threadx.txt b/ports_module/cortex_a35/gnu/readme_threadx.txt
new file mode 100644
index 00000000..13c2c9c0
--- /dev/null
+++ b/ports_module/cortex_a35/gnu/readme_threadx.txt
@@ -0,0 +1,266 @@
+                     Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 
+
+                           Using the ARM GNU Compiler & DS
+
+1. Import the ThreadX Modules Projects
+
+In order to build the ThreadX library and the ThreadX demonstration, first import 
+the 'tx', 'txm', 'sample_threadx', 'sample_threadx_module' and
+'sample_thread_module_manager' projects (located in the "example_build" directory) 
+into your DS workspace.
+
+
+2.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy; simply select the Eclipse project file 
+"tx" and then select the build button. You should now observe the compilation 
+and assembly of the ThreadX library. This project build produces the ThreadX 
+library file tx.a. To bild the ThreadX Module library select the project "txm"
+and select the build button to produce the file txm.a.
+
+
+3.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the DS debugger on the
+Base_A35x1 Bare Metal simulator.
+
+Building the basic ThreadX demonstration is easy; simply select the sample_threadx project, and
+select the build button. Next, in the sample_threadx project, right-click on the
+sample_threadx.launch file and select 'Debug As -> sample_threadx'.  The debugger is
+setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load
+the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute
+the ThreadX demonstration.
+
+The ThreadX Modules demonstration is composed of a module and a module manager.
+First build the ThreadX sample module project sample_thread_module by selecting it and
+clicking the build button. Next built the ThreadX Module Manager sample by selecting
+sample_threadx_module_manager and clicking the build button.
+
+To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, 
+right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'.  
+The debugger is setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load
+the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute
+the ThreadX demonstration.
+
+
+4.  System Initialization
+
+The entry point in ThreadX for the Cortex-A35 using GCC tools is at label 
+"start64". This is defined within the GCC compiler's startup code. In addition, 
+this is where all static and global pre-set C variable initialization processing 
+takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for determining the 
+first available RAM address for use by the application, which is supplied as the 
+sole input parameter to your application definition function, tx_application_define.
+
+
+5.  Register Usage and Stack Frames
+
+The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers 
+for each function. All other registers used by a C function must be preserved 
+by the function. ThreadX takes advantage of this in situations where a context 
+switch happens as a result of making a ThreadX service call (which is itself a 
+C function). In such cases, the saved context of a thread is only the 
+non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+FP not enabled and TX_THREAD.tx_thread_fp_enable == 0:
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x000                  SPSR                        DAIF
+     0x008                  ELR                         0
+     0x010                  x28                         x27
+     0x018                  reserved                    x28
+     0x020                  x26                         x25
+     0x028                  x27                         x26
+     0x030                  x24                         x23
+     0x038                  x25                         x24
+     0x040                  x22                         x21
+     0x048                  x23                         x22
+     0x050                  x20                         x19
+     0x058                  x21                         x20
+     0x060                  x18                         x29
+     0x068                  x19                         x30
+     0x070                  x16
+     0x078                  x17
+     0x080                  x14
+     0x088                  x15
+     0x090                  x12
+     0x098                  x13
+     0x0A0                  x10
+     0x0A8                  x11
+     0x0B0                  x8
+     0x0B8                  x9
+     0x0C0                  x6
+     0x0C8                  x7
+     0x0D0                  x4
+     0x0D8                  x5
+     0x0E0                  x2
+     0x0E8                  x3
+     0x0F0                  x0
+     0x0F8                  x1
+     0x100                  x29
+     0x108                  x30 
+
+
+FP enabled and TX_THREAD.tx_thread_fp_enable == 1:
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x000                  SPSR                        DAIF
+     0x008                  ELR                         0
+     0x010                  FPSR                        FPSR
+     0x018                  FPCR                        FPCR
+     0x020                  q30                         q14
+     0x030                  q31                         q15
+     0x040                  q28                         q12
+     0x050                  q29                         q13
+     0x060                  q26                         q10
+     0x070                  q27                         q11
+     0x080                  q24                         q8
+     0x090                  q25                         q9
+     0x0A0                  q22                         x27
+     0x0A8                                              x28
+     0x0B0                  q23                         x25
+     0x0B8                                              x26
+     0x0C0                  q20                         x23
+     0x0C8                                              x24
+     0x0D0                  q21                         x21
+     0x0D8                                              x22
+     0x0E0                  q18                         x19
+     0x0E8                                              x20
+     0x0F0                  q19                         x29
+     0x0F8                                              x30
+     0x100                  q16
+     0x110                  q17
+     0x120                  q14
+     0x130                  q15
+     0x140                  q12
+     0x150                  q13
+     0x160                  q10
+     0x170                  q11
+     0x180                  q8
+     0x190                  q9
+     0x1A0                  q6
+     0x1B0                  q7
+     0x1C0                  q4
+     0x1D0                  q5
+     0x1E0                  q2
+     0x1F0                  q3
+     0x200                  q0
+     0x210                  q1
+     0x220                  x28
+     0x228                  reserved
+     0x230                  x26
+     0x238                  x27
+     0x240                  x24
+     0x248                  x25
+     0x250                  x22
+     0x258                  x23
+     0x260                  x20
+     0x268                  x21
+     0x270                  x18
+     0x278                  x19
+     0x280                  x16
+     0x288                  x17
+     0x290                  x14
+     0x298                  x15
+     0x2A0                  x12
+     0x2A8                  x13
+     0x2B0                  x10
+     0x2B8                  x11
+     0x2C0                  x8
+     0x2C8                  x9
+     0x2D0                  x6
+     0x2D8                  x7
+     0x2E0                  x4
+     0x2E8                  x5
+     0x2F0                  x2
+     0x2F8                  x3
+     0x300                  x0
+     0x308                  x1
+     0x310                  x29
+     0x318                  x30
+
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler optimizations. 
+This makes it easy to debug because you can trace or set breakpoints inside of 
+ThreadX itself. Of course, this costs some performance. To make it run faster, 
+you can change the project settings to the desired compiler optimization level.
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-A35
+targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following
+format:
+
+        .global irq_handler
+irq_handler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+
+  /* Your ISR call goes here!  */
+  BL       application_isr_handler
+
+  B        _tx_thread_context_restore
+
+By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 
+and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined.
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, 
+timeouts, and application timers. Without such a timer interrupt source, these services 
+are not functional. However, all other ThreadX services are operational without a 
+periodic timer source.
+
+
+9. ARM FP Support
+
+By default, FP support is disabled for each thread. If saving the context of the FP registers
+is needed, the following API call must be made from the context of the application thread - before 
+the FP usage:
+
+void    tx_thread_fp_enable(void);
+
+After this API is called in the application, FP registers will be saved/restored for this thread if it
+is preempted via an interrupt. All other suspension of the this thread will not require the FP registers
+to be saved/restored.
+
+To disable FP register context saving, simply call the following API:
+
+void    tx_thread_fp_disable(void);
+
+
+10.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+12-31-2020  Initial ThreadX 6.1.3 version for Cortex-A35 using GCC tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject
new file mode 100644
index 00000000..b109c4c5
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject
@@ -0,0 +1,164 @@
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+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.project b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.project
new file mode 100644
index 00000000..a1b15572
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.project
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3.h
new file mode 100644
index 00000000..b04cd97b
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3.h
@@ -0,0 +1,561 @@
+/*
+ * GICv3.h - data types and function prototypes for GICv3 utility routines
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your
+ * possession of a valid DS-5 end user licence agreement and your compliance
+ * with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_h
+#define GICV3_h
+
+#include <stdint.h>
+
+/*
+ * extra flags for GICD enable
+ */
+typedef enum
+{
+    gicdctlr_EnableGrp0 = (1 << 0),
+    gicdctlr_EnableGrp1NS = (1 << 1),
+    gicdctlr_EnableGrp1A = (1 << 1),
+    gicdctlr_EnableGrp1S = (1 << 2),
+    gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
+    gicdctlr_ARE_S = (1 << 4),	/* Enable Secure state affinity routing */
+    gicdctlr_ARE_NS = (1 << 5),	/* Enable Non-Secure state affinity routing */
+    gicdctlr_DS = (1 << 6),	/* Disable Security support */
+    gicdctlr_E1NWF = (1 << 7)	/* Enable "1-of-N" wakeup model */
+} GICDCTLRFlags_t;
+
+/*
+ * modes for SPI routing
+ */
+typedef enum
+{
+    gicdirouter_ModeSpecific = 0,
+    gicdirouter_ModeAny = (1 << 31)
+} GICDIROUTERBits_t;
+
+typedef enum
+{
+    gicdicfgr_Level = 0,
+    gicdicfgr_Edge = (1 << 1)
+} GICDICFGRBits_t;
+
+typedef enum
+{
+    gicigroupr_G0S = 0,
+    gicigroupr_G1NS = (1 << 0),
+    gicigroupr_G1S = (1 << 2)
+} GICIGROUPRBits_t;
+
+typedef enum
+{
+    gicrwaker_ProcessorSleep = (1 << 1),
+    gicrwaker_ChildrenAsleep = (1 << 2)
+} GICRWAKERBits_t;
+
+/**********************************************************************/
+
+/*
+ * Utility macros & functions
+ */
+#define RANGE_LIMIT(x)		((sizeof(x) / sizeof((x)[0])) - 1)
+
+static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
+					 uint32_t aff1, uint32_t aff0)
+{
+    /*
+     * only need to cast aff3 to get type promotion for all affinities
+     */
+    return ((((uint64_t)aff3 & 0xff) << 32) |
+	    ((aff2 & 0xff) << 16) |
+	    ((aff1 & 0xff) << 8) | aff0);
+}
+
+/**********************************************************************/
+
+/*
+ * GIC Distributor Function Prototypes
+ */
+
+/*
+ * ConfigGICD - configure GIC Distributor prior to enabling it
+ *
+ * Inputs:
+ *
+ *  control - control flags
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void ConfigGICD(GICDCTLRFlags_t flags);
+
+/*
+ * EnableGICD - top-level enable for GIC Distributor
+ *
+ * Inputs:
+ *
+ *  flags - new control flags to set
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void EnableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * DisableGICD - top-level disable for GIC Distributor
+ *
+ * Inputs
+ *
+ *  flags - control flags to clear
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void DisableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * SyncAREinGICD - synchronise GICD Address Routing Enable bits
+ *
+ * Inputs
+ *
+ *  flags - absolute flag bits to set in GIC Distributor
+ *
+ *  dosync - flag whether to wait for ARE bits to match passed
+ *      flag field (dosync = true), or whether to set absolute
+ *      flag bits (dosync = false)
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ * This function is used to resolve a race in an MP system whereby secondary
+ * CPUs cannot reliably program all Redistributor registers until the
+ * primary CPU has enabled Address Routing. The primary CPU will call this
+ * function with dosync = false, while the secondaries will call it with
+ * dosync = true.
+ */
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
+
+/*
+ * EnableSPI - enable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnableSPI(uint32_t id);
+
+/*
+ * DisableSPI - disable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisableSPI(uint32_t id);
+
+/*
+ * SetSPIPriority - configure the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetSPIPriority(uint32_t id, uint32_t priority);
+
+/*
+ * GetSPIPriority - determine the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  interrupt priority in the range 0 - 0xff
+ */
+uint32_t GetSPIPriority(uint32_t id);
+
+/*
+ * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  affinity - prepacked "dotted quad" affinity routing. NOTE: use the
+ *      gicv3PackAffinity() helper routine to generate this input
+ *
+ *  mode - select routing mode (specific affinity, or any recipient)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
+
+/*
+ * GetSPIRoute - read ARE-enabled interrupt routing information
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  routing configuration
+ */
+uint64_t GetSPIRoute(uint32_t id);
+
+/*
+ * SetSPITarget - configure the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ *  target - 8-bit target bitmap
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPITarget(uint32_t id, uint32_t target);
+
+/*
+ * GetSPITarget - read the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *  8-bit target bitmap
+ */
+uint32_t GetSPITarget(uint32_t id);
+
+/*
+ * ConfigureSPI - setup an interrupt as edge- or level-triggered
+ *
+ * Inputs
+ *
+ *   id - interrupt identifier
+ *
+ *   config - desired configuration
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
+
+/*
+ * SetSPIPending - mark an interrupt as pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetSPIPending(uint32_t id);
+
+/*
+ * ClearSPIPending - mark an interrupt as not pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearSPIPending(uint32_t id);
+
+/*
+ * GetSPIPending - query whether an interrupt is pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetSPIPending(uint32_t id);
+
+/*
+ * SetSPISecurity - mark a shared peripheral interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityBlock - mark a block of 32 shared peripheral
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  block - which block to mark (e.g. 1 = Ints 32-63)
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityAll - mark all shared peripheral interrupts
+ *     as security <group>
+ *
+ * Inputs:
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityAll(GICIGROUPRBits_t group);
+
+/**********************************************************************/
+
+/*
+ * GIC Re-Distributor Function Prototypes
+ *
+ * The model for calling Redistributor functions is that, rather than
+ * identifying the target redistributor with every function call, the
+ * SelectRedistributor() function is used to identify which redistributor
+ * is to be used for all functions until a different redistributor is
+ * explicitly selected
+ */
+
+/*
+ * WakeupGICR - wake up a Redistributor
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to wakeup
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void WakeupGICR(uint32_t gicr);
+
+/*
+ * EnablePrivateInt - enable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * DisablePrivateInt - disable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
+
+/*
+ * GetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *   Int priority
+ */
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
+
+#endif /* ndef GICV3_h */
+
+/* EOF GICv3.h */
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicc.h
new file mode 100644
index 00000000..bc2da074
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicc.h
@@ -0,0 +1,249 @@
+/*
+ * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your
+ * possession of a valid DS-5 end user licence agreement and your compliance
+ * with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_gicc_h
+#define GICV3_gicc_h
+
+/**********************************************************************/
+
+typedef enum
+{
+    sreSRE = (1 << 0),
+    sreDFB = (1 << 1),
+    sreDIB = (1 << 2),
+    sreEnable = (1 << 3)
+} ICC_SREBits_t;
+
+static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL2(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL2\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL3\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    igrpEnable = (1 << 0),
+    igrpEnableGrp1NS = (1 << 0),
+    igrpEnableGrp1S = (1 << 2)
+} ICC_IGRPBits_t;
+
+static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    ctlrCBPR = (1 << 0),
+    ctlrCBPR_EL1S = (1 << 0),
+    ctlrEOImode = (1 << 1),
+    ctlrCBPR_EL1NS = (1 << 1),
+    ctlrEOImode_EL3 = (1 << 2),
+    ctlrEOImode_EL1S = (1 << 3),
+    ctlrEOImode_EL1NS = (1 << 4),
+    ctlrRM = (1 << 5),
+    ctlrPMHE = (1 << 6)
+} ICC_CTLRBits_t;
+
+static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
+{
+    asm("msr  ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_CTLR_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
+{
+    asm("msr  ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_CTLR_EL3\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+static inline uint64_t getICC_IAR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_IAR0_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_IAR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_IAR1_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_EOIR0(uint32_t interrupt)
+{
+    asm("msr  ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_EOIR1(uint32_t interrupt)
+{
+    asm("msr  ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_DIR(uint32_t interrupt)
+{
+    asm("msr  ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_PMR(uint32_t priority)
+{
+    asm("msr  ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority));
+}
+
+static inline void setICC_BPR0(uint32_t binarypoint)
+{
+    asm("msr  ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline void setICC_BPR1(uint32_t binarypoint)
+{
+    asm("msr  ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline uint64_t getICC_BPR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_BPR0_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_BPR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_BPR1_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_RPR(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_RPR_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    sgirIRMTarget = 0,
+    sgirIRMAll = (1ull << 40)
+} ICC_SGIRBits_t;
+
+static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+#endif /* ndef GICV3_gicc_h */
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicd.c
new file mode 100644
index 00000000..e176b206
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicd.c
@@ -0,0 +1,339 @@
+/*
+ * GICv3_gicd.c - generic driver code for GICv3 distributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your
+ * possession of a valid DS-5 end user licence agreement and your compliance
+ * with all applicable terms and conditions of such licence agreement.
+ */
+#include <stdint.h>
+
+#include "GICv3.h"
+
+typedef struct
+{
+        volatile uint32_t GICD_CTLR;              // +0x0000
+  const volatile uint32_t GICD_TYPER;             // +0x0004
+  const volatile uint32_t GICD_IIDR;              // +0x0008
+
+  const volatile uint32_t padding0;               // +0x000c
+
+        volatile uint32_t GICD_STATUSR;           // +0x0010
+
+  const volatile uint32_t padding1[3];            // +0x0014
+
+        volatile uint32_t IMP_DEF[8];             // +0x0020
+
+        volatile uint32_t GICD_SETSPI_NSR;        // +0x0040
+  const volatile uint32_t padding2;               // +0x0044
+        volatile uint32_t GICD_CLRSPI_NSR;        // +0x0048
+  const volatile uint32_t padding3;               // +0x004c
+        volatile uint32_t GICD_SETSPI_SR;         // +0x0050
+  const volatile uint32_t padding4;               // +0x0054
+        volatile uint32_t GICD_CLRSPI_SR;         // +0x0058
+
+  const volatile uint32_t padding5[3];            // +0x005c
+
+        volatile uint32_t GICD_SEIR;              // +0x0068
+
+  const volatile uint32_t padding6[5];            // +0x006c
+
+        volatile uint32_t GICD_IGROUPR[32];       // +0x0080
+
+        volatile uint32_t GICD_ISENABLER[32];     // +0x0100
+        volatile uint32_t GICD_ICENABLER[32];     // +0x0180
+        volatile uint32_t GICD_ISPENDR[32];       // +0x0200
+        volatile uint32_t GICD_ICPENDR[32];       // +0x0280
+        volatile uint32_t GICD_ISACTIVER[32];     // +0x0300
+        volatile uint32_t GICD_ICACTIVER[32];     // +0x0380
+
+        volatile uint8_t  GICD_IPRIORITYR[1024];  // +0x0400
+        volatile uint8_t  GICD_ITARGETSR[1024];   // +0x0800
+        volatile uint32_t GICD_ICFGR[64];         // +0x0c00
+        volatile uint32_t GICD_IGRPMODR[32];      // +0x0d00
+  const volatile uint32_t padding7[32];           // +0x0d80
+        volatile uint32_t GICD_NSACR[64];         // +0x0e00
+
+        volatile uint32_t GICD_SGIR;              // +0x0f00
+
+  const volatile uint32_t padding8[3];            // +0x0f04
+
+        volatile uint32_t GICD_CPENDSGIR[4];      // +0x0f10
+        volatile uint32_t GICD_SPENDSGIR[4];      // +0x0f20
+
+  const volatile uint32_t padding9[52];           // +0x0f30
+  const volatile uint32_t padding10[5120];        // +0x1000
+
+        volatile uint64_t GICD_IROUTER[1024];     // +0x6000
+} GICv3_distributor;
+
+/*
+ * use the scatter file to place GICD
+ */
+static GICv3_distributor __attribute__((section(".bss.distributor"))) gicd;
+
+void ConfigGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR = flags;
+}
+
+void EnableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR |= flags;
+}
+
+void DisableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR &= ~flags;
+}
+
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
+{
+    if (dosync)
+    {
+	const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
+	const uint32_t tval = flags & tmask;
+
+	while ((gicd.GICD_CTLR & tmask) != tval)
+	    continue;
+    }
+    else
+	gicd.GICD_CTLR = flags;
+}
+
+void EnableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ISENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void DisableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ICENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void SetSPIPriority(uint32_t id, uint32_t priority)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    gicd.GICD_IPRIORITYR[bank] = priority;
+}
+
+uint32_t GetSPIPriority(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
+}
+
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
+}
+
+uint64_t GetSPIRoute(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    return gicd.GICD_IROUTER[bank];
+}
+
+void SetSPITarget(uint32_t id, uint32_t target)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    gicd.GICD_ITARGETSR[bank] = target;
+}
+
+uint32_t GetSPITarget(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    /*
+     * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
+     * target bitmap per register
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
+}
+
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
+{
+    uint32_t bank, tmp;
+
+    /*
+     * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
+     * configuration per register
+     */
+    bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
+    config &= 3;
+
+    id = (id & 0xf) << 1;
+
+    tmp = gicd.GICD_ICFGR[bank];
+    tmp &= ~(3 << id);
+    tmp |= config << id;
+    gicd.GICD_ICFGR[bank] = tmp;
+}
+
+void SetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ISPENDR[bank] = 1 << id;
+}
+
+void ClearSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ICPENDR[bank] = 1 << id;
+}
+
+uint32_t GetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    return (gicd.GICD_ICPENDR[bank] >> id) & 1;
+}
+
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
+{
+    uint32_t bank, groupmod;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicd.GICD_IGROUPR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGROUPR[bank] &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicd.GICD_IGRPMODR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
+}
+
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
+{
+    uint32_t groupmod;
+    const uint32_t nbits = (sizeof group * 8) - 1;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
+
+    /*
+     * get each bit of group config duplicated over all 32-bits in a word
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicd.GICD_IGROUPR[block] = group;
+    gicd.GICD_IGRPMODR[block] = groupmod;
+}
+
+void SetSPISecurityAll(GICIGROUPRBits_t group)
+{
+    uint32_t block;
+
+    /*
+     * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
+     * want to iterate over all blocks excluding 0 (which are the
+     * SGI/PPI interrupts, and not relevant here)
+     */
+    for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
+	SetSPISecurityBlock(block, group);
+}
+
+/* EOF GICv3_gicd.c */
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicr.c
new file mode 100644
index 00000000..59ed616a
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicr.c
@@ -0,0 +1,279 @@
+/*
+ * GICv3_gicr.c - generic driver code for GICv3 redistributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your
+ * possession of a valid DS-5 end user licence agreement and your compliance
+ * with all applicable terms and conditions of such licence agreement.
+ */
+#include "GICv3.h"
+
+/*
+ * physical LPI Redistributor register map
+ */
+typedef struct
+{
+        volatile uint32_t GICR_CTLR;             // +0x0000 - RW - Redistributor Control Register
+  const volatile uint32_t GICR_IIDR;             // +0x0004 - RO - Implementer Identification Register
+  const volatile uint32_t GICR_TYPER[2];         // +0x0008 - RO - Redistributor Type Register
+        volatile uint32_t GICR_STATUSR;          // +0x0010 - RW - Error Reporting Status Register, optional
+        volatile uint32_t GICR_WAKER;            // +0x0014 - RW - Redistributor Wake Register
+  const volatile uint32_t padding1[2];           // +0x0018 - RESERVED
+        volatile uint32_t IMPDEF1   ;            // +0x0020 - ?? - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding2[7];           // +0x0024 - RESERVED
+        volatile uint64_t GICR_SETLPIR;          // +0x0040 - WO - Set LPI Pending Register
+        volatile uint64_t GICR_CLRLPIR;          // +0x0048 - WO - Clear LPI Pending Register
+  const volatile uint32_t padding3[8];           // +0x0050 - RESERVED
+        volatile uint64_t GICR_PROPBASER;        // +0x0070 - RW - Redistributor Properties Base Address Register
+        volatile uint64_t GICR_PENDBASER;        // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
+  const volatile uint32_t padding4[8];           // +0x0080 - RESERVED
+        volatile uint64_t GICR_INVLPIR;          // +0x00A0 - WO - Redistributor Invalidate LPI Register
+  const volatile uint32_t padding5[2];           // +0x00A8 - RESERVED
+        volatile uint64_t GICR_INVALLR;          // +0x00B0 - WO - Redistributor Invalidate All Register
+  const volatile uint32_t padding6[2];           // +0x00B8 - RESERVED
+        volatile uint64_t GICR_SYNCR;            // +0x00C0 - RO - Redistributor Synchronize Register
+  const volatile uint32_t padding7[2];           // +0x00C8 - RESERVED
+  const volatile uint32_t padding8[12];          // +0x00D0 - RESERVED
+        volatile uint64_t IMPDEF2;               // +0x0100 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding9[2];           // +0x0108 - RESERVED
+        volatile uint64_t IMPDEF3;               // +0x0110 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding10[2];          // +0x0118 - RESERVED
+} GICv3_redistributor_RD;
+
+/*
+ * SGI and PPI Redistributor register map
+ */
+typedef struct
+{
+  const volatile uint32_t padding1[32];          // +0x0000 - RESERVED
+        volatile uint32_t GICR_IGROUPR0;         // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
+  const volatile uint32_t padding2[31];          // +0x0084 - RESERVED
+        volatile uint32_t GICR_ISENABLER;        // +0x0100 - RW - Interrupt Set-Enable Registers
+  const volatile uint32_t padding3[31];          // +0x0104 - RESERVED
+        volatile uint32_t GICR_ICENABLER;        // +0x0180 - RW - Interrupt Clear-Enable Registers
+  const volatile uint32_t padding4[31];          // +0x0184 - RESERVED
+        volatile uint32_t GICR_ISPENDR;          // +0x0200 - RW - Interrupt Set-Pending Registers
+  const volatile uint32_t padding5[31];          // +0x0204 - RESERVED
+        volatile uint32_t GICR_ICPENDR;          // +0x0280 - RW - Interrupt Clear-Pending Registers
+  const volatile uint32_t padding6[31];          // +0x0284 - RESERVED
+        volatile uint32_t GICR_ISACTIVER;        // +0x0300 - RW - Interrupt Set-Active Register
+  const volatile uint32_t padding7[31];          // +0x0304 - RESERVED
+        volatile uint32_t GICR_ICACTIVER;        // +0x0380 - RW - Interrupt Clear-Active Register
+  const volatile uint32_t padding8[31];          // +0x0184 - RESERVED
+        volatile uint8_t  GICR_IPRIORITYR[32];   // +0x0400 - RW - Interrupt Priority Registers
+  const volatile uint32_t padding9[504];         // +0x0420 - RESERVED
+        volatile uint32_t GICR_ICnoFGR[2];       // +0x0C00 - RW - Interrupt Configuration Registers
+  const volatile uint32_t padding10[62];	 // +0x0C08 - RESERVED
+        volatile uint32_t GICR_IGRPMODR0;        // +0x0D00 - RW - ????
+  const volatile uint32_t padding11[63];	 // +0x0D04 - RESERVED
+        volatile uint32_t GICR_NSACR;            // +0x0E00 - RW - Non-Secure Access Control Register
+} GICv3_redistributor_SGI;
+
+/*
+ * We have a multiplicity of GIC Redistributors; on the GIC-AEM and
+ * GIC-500 they are arranged as one 128KB region per redistributor: one
+ * 64KB page of GICR LPI registers, and one 64KB page of GICR Private
+ * Int registers
+ */
+typedef struct
+{
+    union
+    {
+	GICv3_redistributor_RD RD_base;
+	uint8_t padding[64 * 1024];
+    } RDblock;
+
+    union
+    {
+	GICv3_redistributor_SGI SGI_base;
+	uint8_t padding[64 * 1024];
+    } SGIblock;
+} GICv3_GICR;
+
+/*
+ * use the scatter file to place GIC Redistributor base address
+ *
+ * although this code doesn't know how many Redistributor banks
+ * a particular system will have, we declare gicrbase as an array
+ * to avoid unwanted compiler optimisations when calculating the
+ * base of a particular Redistributor bank
+ */
+static const GICv3_GICR gicrbase[2] __attribute__((section (".bss.redistributor")));
+
+/**********************************************************************/
+
+/*
+ * utility functions to calculate base of a particular
+ * Redistributor bank
+ */
+
+static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
+{
+    GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
+
+    return &((arraybase + gicr)->RDblock.RD_base);
+}
+
+static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
+{
+    GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
+
+    return &(arraybase[gicr].SGIblock.SGI_base);
+}
+
+/**********************************************************************/
+
+void WakeupGICR(uint32_t gicr)
+{
+    GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
+
+    /*
+     * step 1 - ensure GICR_WAKER.ProcessorSleep is off
+     */
+    gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
+
+    /*
+     * step 2 - wait for children asleep to be cleared
+     */
+    while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
+	continue;
+
+    /*
+     * OK, GICR is go
+     */
+    return;
+}
+
+void EnablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISENABLER = 1 << id;
+}
+
+void DisablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICENABLER = 1 << id;
+}
+
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    gicrSGI->GICR_IPRIORITYR[id] = priority;
+}
+
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
+}
+
+void SetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISPENDR = 1 << id;
+}
+
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ICPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICPENDR = 1 << id;
+}
+
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
+}
+
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    uint32_t groupmod;
+
+    /*
+     * GICR_IGROUPR0 is one 32-bit register
+     */
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicrSGI->GICR_IGROUPR0 |= 1 << id;
+    else
+	gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicrSGI->GICR_IGRPMODR0 |= 1 << id;
+    else
+	gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
+}
+
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    const uint32_t nbits = (sizeof group * 8) - 1;
+    uint32_t groupmod;
+
+    /*
+     * get each bit of group config duplicated over all 32-bits
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicrSGI->GICR_IGROUPR0 = group;
+    gicrSGI->GICR_IGRPMODR0 = groupmod;
+}
+
+/* EOF GICv3_gicr.c */
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S
new file mode 100644
index 00000000..d5dfd898
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S
@@ -0,0 +1,86 @@
+//
+// Armv8-A AArch64 - Basic Mutex Example
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global _mutex_initialize
+    .global _mutex_acquire
+    .global _mutex_release
+
+//
+// These routines implement the mutex management functions required for running
+// the Arm C library in a multi-threaded environment.
+//
+// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
+//
+// **********************************************************************
+//
+
+    .type _mutex_initialize, "function"
+    .cfi_startproc
+_mutex_initialize:
+
+    //
+    // mark the mutex as unlocked
+    //
+    mov     w1, #0
+    str     w1, [x0]
+
+    //
+    // we are running multi-threaded, so set a non-zero return
+    // value (function prototype says use 1)
+    //
+    mov     w0, #1
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+
+    //
+    // send ourselves an event, so we don't stick on the wfe at the
+    // top of the loop
+    //
+    sevl
+
+    //
+    // wait until the mutex is available
+    //
+loop:
+    wfe
+    ldaxr   w1, [x0]
+    cbnz    w1, loop
+
+    //
+    // mutex is (at least, it was) available - try to claim it
+    //
+    mov     w1, #1
+    stxr    w2, w1, [x0]
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+
+    mov     w1, #0
+    stlr    w1, [x0]
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/PPM_AEM.h
new file mode 100644
index 00000000..da19e9b1
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/PPM_AEM.h
@@ -0,0 +1,66 @@
+//
+// Private Peripheral Map for the v8 Architecture Envelope Model
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef PPM_AEM_H
+#define PPM_AEM_H
+
+//
+// Distributor layout
+//
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+//
+// CPU Interface layout
+//
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+
+#endif // PPM_AEM_H
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c
new file mode 100644
index 00000000..139a848c
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c
@@ -0,0 +1,392 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+#include <stddef.h>
+
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     0x20000
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define a memory area to create a byte pool in.  */
+
+UCHAR                   memory_area[DEMO_BYTE_POOL_SIZE] __attribute__((aligned (8)));
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_TIMER                timer_0;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+UCHAR   event_buffer[65536];
+
+#endif
+
+
+/* Define main entry point.  */
+
+int main(void)
+{
+
+    /* Initialize timer for ThreadX.  */
+    extern void init_timer(void);    /* in timer_interrupts.c  */
+    init_timer();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+
+    /* The functions doesn't really return*/
+    return 0;
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+    tx_trace_enable(event_buffer, sizeof(event_buffer), 32);
+#endif
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+            
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+            
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.launch b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.launch
new file mode 100644
index 00000000..6723ac8a
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.launch
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+    <listAttribute key="4806419205238742890.viewid=3"/>
+    <mapAttribute key="4806419205238742890.viewid=3.ExpressionsData"/>
+    <stringAttribute key="4806419205238742890.viewid=3:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;255&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;59&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <listAttribute key="8638473516857365454.viewid=2">
+        <listEntry value="(TX_THREAD *) 0x0000000080034378"/>
+        <listEntry value="_tx_thread_preempt_disable"/>
+    </listAttribute>
+    <mapAttribute key="8638473516857365454.viewid=2.ExpressionsData">
+        <mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,1;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
+        <mapEntry key="1" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
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+    <listAttribute key="debugger.view.MemoryView:current">
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+        <listEntry value=""/>
+    </listAttribute>
+    <stringAttribute key="debugger.view.NewRegisterView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;117&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;175&#9;-1&#9;true&#9;3&#9;false&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;false&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;false&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
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+    <stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
+    <stringAttribute key="dtsl_options_file" value="default"/>
+    <stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
+    <booleanAttribute key="linuxOS" value="false"/>
+    <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
+    <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
+    <booleanAttribute key="runAfterConnect" value="false"/>
+    <mapAttribute key="scripts_view_script_links">
+        <mapEntry key="B:\support\broadcom\a53smp_el1_clean_mar25\sample_threadx\use_model_semihosting.ds" value=""/>
+        <mapEntry key="B:\support\broadcom\tx58cortexa53arm\release\threadx\sample_threadx\use_model_semihosting.ds" value=""/>
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+    <listAttribute key="setup">
+        <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
+        <listEntry value="FVP_Base_Cortex-A35x4"/>
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+    <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
+    <stringAttribute key="substitutePath" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;tuplelist&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/sample_threadx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/tx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&lt;/tuplelist&gt;&#10;"/>
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+</launchConfiguration>
diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.sct b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat
similarity index 100%
rename from ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.sct
rename to ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.c
new file mode 100644
index 00000000..4a454f16
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.c
@@ -0,0 +1,122 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "sp804_timer.h"
+
+#define TIMER_SP804_CTRL_TIMEREN     (1 << 7)
+#define TIMER_SP804_CTRL_TIMERMODE   (1 << 6)        // Bit 6:
+#define TIMER_SP804_CTRL_INTENABLE   (1 << 5)
+#define TIMER_SP804_CTRL_TIMERSIZE   (1 << 1)        // Bit 1: 0=16-bit, 1=32-bit
+#define TIMER_SP804_CTRL_ONESHOT     (1 << 0)        // Bit 0: 0=wrapping, 1=one-shot
+
+#define TIMER_SP804_CTRL_PRESCALE_1  (0 << 2)        // clk/1
+#define TIMER_SP804_CTRL_PRESCALE_4  (1 << 2)        // clk/4
+#define TIMER_SP804_CTRL_PRESCALE_8  (2 << 2)        // clk/8
+
+struct sp804_timer
+{
+        volatile uint32_t Time1Load;     // +0x00
+  const volatile uint32_t Time1Value;    // +0x04 - RO
+        volatile uint32_t Timer1Control; // +0x08
+        volatile uint32_t Timer1IntClr;  // +0x0C - WO
+  const volatile uint32_t Timer1RIS;     // +0x10 - RO
+  const volatile uint32_t Timer1MIS;     // +0x14 - RO
+        volatile uint32_t Timer1BGLoad;  // +0x18
+
+        volatile uint32_t Time2Load;     // +0x20
+        volatile uint32_t Time2Value;    // +0x24
+        volatile uint8_t  Timer2Control; // +0x28
+        volatile uint32_t Timer2IntClr;  // +0x2C - WO
+  const volatile uint32_t Timer2RIS;     // +0x30 - RO
+  const volatile uint32_t Timer2MIS;     // +0x34 - RO
+        volatile uint32_t Timer2BGLoad;  // +0x38
+
+  // Not including ID registers
+
+};
+
+// Instance of the dual timer, will be placed using the scatter file
+struct sp804_timer* dual_timer;
+
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address)
+{
+  dual_timer = (struct sp804_timer*)address;
+  return;
+}
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
+{
+  uint32_t tmp = 0;
+
+  dual_timer->Time1Load = load_value;
+
+  // Fixed setting: 32-bit, no prescaling
+  tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
+
+  // Settings from parameters: interrupt generation & reload
+  tmp = tmp | interrupt | auto_reload;
+
+  // Write control register
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Starts the timer
+void startTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp | TIMER_SP804_CTRL_TIMEREN;      // Set TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Stops the timer
+void stopTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN;     // Clear TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void)
+{
+  return dual_timer->Time1Value;
+}
+
+
+void clearTimerIrq(void)
+{
+  // A write to this register, of any value, clears the interrupt
+  dual_timer->Timer1IntClr = 1;
+}
+
+
+// ------------------------------------------------------------
+// End of sp804_timer.c
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.h
new file mode 100644
index 00000000..d4c6d9e2
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.h
@@ -0,0 +1,53 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+// Header Filer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#ifndef _SP804_TIMER_
+#define _SP804_TIMER_
+
+#include <stdint.h>
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address);
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+
+#define SP804_AUTORELOAD   (0)
+#define SP804_SINGLESHOT   (1)
+#define SP804_GENERATE_IRQ (1 << 5)
+#define SP804_NO_IRQ       (0)
+
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
+
+
+// Starts the timer
+void startTimer(void);
+
+
+// Stops the timer
+void stopTimer(void);
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void);
+
+
+// Clears the timer interrupt
+void clearTimerIrq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of sp804_timer.h
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S
new file mode 100644
index 00000000..eea65315
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S
@@ -0,0 +1,803 @@
+// ------------------------------------------------------------
+// Armv8-A MPCore EL3 AArch64 Startup Code
+//
+// Basic Vectors, MMU, caches and GICv3 initialization
+//
+// Exits in EL1 AArch64
+//
+// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_mmu.h"
+#include "v8_system.h"
+
+
+    .section StartUp, "ax"
+    .balign 4
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+
+    .global InvalidateUDCaches
+    .global ZeroBlock
+
+    .global SetPrivateIntSecurityBlock
+    .global SetSPISecurityAll
+    .global SetPrivateIntPriority
+
+    .global WakeupGICR
+    .global SyncAREinGICD
+    .global EnableGICD
+    .global EnablePrivateInt
+    .global GetPrivateIntPending
+    .global ClearPrivateIntPending
+
+    .global __main
+
+    .global Image$$EXEC$$RO$$Base
+    .global Image$$TTB0_L1$$ZI$$Base
+    .global Image$$TTB0_L2_RAM$$ZI$$Base
+    .global Image$$TTB0_L2_PERIPH$$ZI$$Base
+    .global Image$$TOP_OF_RAM$$ZI$$Base
+    .global Image$$GICD$$ZI$$Base
+    .global Image$$ARM_LIB_STACK$$ZI$$Limit
+    .global Image$$EL3_STACKS$$ZI$$Limit
+    .global Image$$CS3_PERIPHERALS$$ZI$$Base
+    // use separate stack and heap, as anticipated by scatter.scat
+    .global __use_two_region_memory
+
+is_mmu_ready:
+.word 0
+
+
+// ------------------------------------------------------------
+
+    .global start64
+    .type start64, "function"
+start64:
+
+    //
+    // program the VBARs
+    //
+    ldr x1, =el1_vectors
+    msr VBAR_EL1, x1
+
+    ldr x1, =el2_vectors
+    msr VBAR_EL2, x1
+
+    ldr x1, =el3_vectors
+    msr VBAR_EL3, x1
+
+
+    // GIC-500 comes out of reset in GICv2 compatibility mode - first set
+    // system register enables for all relevant exception levels, and
+    // select GICv3 operating mode
+    //
+    msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL3, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
+
+    //
+    // set lower exception levels as non-secure, with no access
+    // back to EL2 or EL3, and are AArch64 capable
+    //
+    mov x3, #(SCR_EL3_RW  | \
+              SCR_EL3_SMD | \
+              SCR_EL3_NS)      // Set NS bit, to access Non-secure registers
+    msr SCR_EL3, x3
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL2, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
+
+
+    //
+    // no traps or VM modifications from the Hypervisor, EL1 is AArch64
+    //
+    mov x2, #HCR_EL2_RW
+    msr HCR_EL2, x2
+
+    //
+    // VMID is still significant, even when virtualisation is not
+    // being used, so ensure VTTBR_EL2 is properly initialised
+    //
+    msr VTTBR_EL2, xzr
+
+    //
+    // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
+    //  VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
+    // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
+    // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
+    // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
+    //
+    mrs x0, MPIDR_EL1
+    msr VMPIDR_EL2, x0
+    mrs x0, MIDR_EL1
+    msr VPIDR_EL2, x0
+
+    // extract the core number from MPIDR_EL1 and store it in
+    // x19 (defined by the AAPCS as callee-saved), so we can re-use
+    // the number later
+    //
+    bl GetCPUID
+    mov x19, x0
+
+    //
+    // neither EL3 nor EL2 trap floating point or accesses to CPACR
+    //
+    msr CPTR_EL3, xzr
+    msr CPTR_EL2, xzr
+
+    //
+    // SCTLR_ELx may come out of reset with UNKNOWN values so we will
+    // set the fields to 0 except, possibly, the endianess field(s).
+    // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
+    // is not strictly needed, since we're never in EL2 or EL0
+    //
+#ifdef __ARM_BIG_ENDIAN
+    mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
+#else
+    mov x0, #0
+#endif
+    msr SCTLR_EL3, x0
+    msr SCTLR_EL2, x0
+    msr SCTLR_EL1, x0
+
+#ifdef CORTEXA
+    //
+    // Configure ACTLR_EL[23]
+    // ----------------------
+    //
+    // These bits are IMPLEMENTATION DEFINED, so are different for
+    // different processors
+    //
+    // For Cortex-A57, the controls we set are:
+    //
+    //  Enable lower level access to CPUACTLR_EL1
+    //  Enable lower level access to CPUECTLR_EL1
+    //  Enable lower level access to L2CTLR_EL1
+    //  Enable lower level access to L2ECTLR_EL1
+    //  Enable lower level access to L2ACTLR_EL1
+    //
+    mov x0, #((1 << 0) | \
+              (1 << 1) | \
+              (1 << 4) | \
+              (1 << 5) | \
+              (1 << 6))
+
+    msr ACTLR_EL3, x0
+    msr ACTLR_EL2, x0
+
+    //
+    // configure CPUECTLR_EL1
+    //
+    // These bits are IMP DEF, so need to different for different
+    // processors
+    //
+    // SMPEN - bit 6 - Enables the processor to receive cache
+    //                 and TLB maintenance operations
+    //
+    // Note: For Cortex-A57/53 SMPEN should be set before enabling
+    //       the caches and MMU, or performing any cache and TLB
+    //       maintenance operations.
+    //
+    //       This register has a defined reset value, so we use a
+    //       read-modify-write sequence to set SMPEN
+    //
+    mrs x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
+    orr x0, x0, #(1 << 6)  // Set the SMPEN bit
+    msr S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
+
+    isb
+#endif
+
+    //
+    // That's the last of the control settings for now
+    //
+    // Note: no ISB after all these changes, as registers won't be
+    // accessed until after an exception return, which is itself a
+    // context synchronisation event
+    //
+
+    //
+    // Setup some EL3 stack space, ready for calling some subroutines, below.
+    //
+    // Stack space allocation is CPU-specific, so use CPU
+    // number already held in x19
+    //
+    // 2^12 bytes per CPU for the EL3 stacks
+    //
+    ldr x0, =Image$$EL3_STACKS$$ZI$$Limit
+    sub x0, x0, x19, lsl #12
+    mov sp, x0
+
+    //
+    // we need to configure the GIC while still in secure mode, specifically
+    // all PPIs and SPIs have to be programmed as Group1 interrupts
+    //
+
+    //
+    // Before the GIC can be reliably programmed, we need to
+    // enable Affinity Routing, as this affects where the configuration
+    // registers are (with Affinity Routing enabled, some registers are
+    // in the Redistributor, whereas those same registers are in the
+    // Distributor with Affinity Routing disabled (i.e. when in GICv2
+    // compatibility mode).
+    //
+    mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
+    mov x1, x19
+    bl  SyncAREinGICD
+
+    //
+    // The Redistributor comes out of reset assuming the processor is
+    // asleep - correct that assumption
+    //
+    mov w0, w19
+    bl  WakeupGICR
+
+    //
+    // Now we're ready to set security and other initialisations
+    //
+    // This is a per-CPU configuration for these interrupts
+    //
+    // for the first cluster, CPU number is the redistributor index
+    //
+    mov w0, w19
+    mov w1, #1    // gicigroupr_G1NS
+    bl  SetPrivateIntSecurityBlock
+
+    //
+    // While we're in the Secure World, set the priority mask low enough
+    // for it to be writable in the Non-Secure World
+    //
+    //mov x0, #16 << 3    // 5 bits of priority in the Secure world
+    mov x0, #0xFF  // for Non-Secure interrupts
+    msr ICC_PMR_EL1, x0
+
+    //
+    // there's more GIC setup to do, but only for the primary CPU
+    //
+    cbnz x19, drop_to_el1
+
+    //
+    // There's more to do to the GIC - call the utility routine to set
+    // all SPIs to Group1
+    //
+    mov w0, #1    // gicigroupr_G1NS
+    bl  SetSPISecurityAll
+
+    //
+    // Set up EL1 entry point and "dummy" exception return information,
+    // then perform exception return to enter EL1
+    //
+    .global drop_to_el1
+drop_to_el1:
+    adr x1, el1_entry_aarch64
+    msr ELR_EL3, x1
+    mov x1, #(AARCH64_SPSR_EL1h | \
+              AARCH64_SPSR_F  | \
+              AARCH64_SPSR_I  | \
+              AARCH64_SPSR_A)
+    msr SPSR_EL3, x1
+    eret
+
+
+
+// ------------------------------------------------------------
+// EL1 - Common start-up code
+// ------------------------------------------------------------
+
+    .global el1_entry_aarch64
+    .type el1_entry_aarch64, "function"
+el1_entry_aarch64:
+
+    //
+    // Now we're in EL1, setup the application stack
+    // the scatter file allocates 2^14 bytes per app stack
+    //
+    ldr x0, =Image$$HANDLER_STACK$$ZI$$Limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+    MSR     SPSel, #0
+    ISB
+    ldr x0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+
+    //
+    // Enable floating point
+    //
+    mov x0, #CPACR_EL1_FPEN
+    msr CPACR_EL1, x0
+
+    //
+    // Invalidate caches and TLBs for all stage 1
+    // translations used at EL1
+    //
+    // Cortex-A processors automatically invalidate their caches on reset
+    // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
+    // It is therefore not necessary for software to invalidate the caches 
+    // on startup, however, this is done here in case of a warm reset.
+    bl  InvalidateUDCaches
+    tlbi VMALLE1
+
+
+    //
+    // Set TTBR0 Base address
+    //
+    // The CPUs share one set of translation tables that are
+    // generated by CPU0 at run-time
+    //
+    // TTBR1_EL1 is not used in this example
+    //
+    ldr x1, =Image$$TTB0_L1$$ZI$$Base
+    msr TTBR0_EL1, x1
+
+
+    //
+    // Set up memory attributes
+    //
+    // These equate to:
+    //
+    // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
+    // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
+    // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
+    //
+    mov  x1, #0xff44
+    movk x1, #4, LSL #16    // equiv to: movk x1, #0x0000000000040000
+    msr MAIR_EL1, x1
+
+
+    //
+    // Set up TCR_EL1
+    //
+    // We're using only TTBR0 (EPD1 = 1), and the page table entries:
+    //  - are using an 8-bit ASID from TTBR0
+    //  - have a 4K granularity (TG0 = 0b00)
+    //  - are outer-shareable (SH0 = 0b10)
+    //  - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
+    //  - map
+    //      + 32 bits of VA space (T0SZ = 0x20)
+    //      + into a 32-bit PA space (IPS = 0b000)
+    //
+    //     36   32   28   24   20   16   12    8    4    0
+    //  -----+----+----+----+----+----+----+----+----+----+
+    //       |    |    |OOII|    |    |    |OOII|    |    |
+    //    TT |    |    |RRRR|E T |   T|    |RRRR|E T |   T|
+    //    BB | I I|TTSS|GGGG|P 1 |   1|TTSS|GGGG|P 0 |   0|
+    //    IIA| P P|GGHH|NNNN|DAS |   S|GGHH|NNNN|D S |   S|
+    //    10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
+    //
+    //    000 0000 0000 0000 1000 0000 0010 0101 0010 0000
+    //
+    //                    0x    8    0    2    5    2    0
+    //
+    // Note: the ISB is needed to ensure the changes to system
+    //       context are before the write of SCTLR_EL1.M to enable
+    //       the MMU. It is likely on a "real" implementation that
+    //       this setup would work without an ISB, due to the
+    //       amount of code that gets executed before enabling the
+    //       MMU, but that would not be architecturally correct.
+    //
+    ldr x1, =0x0000000000802520
+    msr TCR_EL1, x1
+    isb
+
+    //
+    // the primary CPU is going to use SGI 15 as a wakeup event
+    // to let us know when it is OK to proceed, so prepare for
+    // receiving that interrupt
+    //
+    // NS interrupt priorities run from 0 to 15, with 15 being
+    // too low a priority to ever raise an interrupt, so let's
+    // use 14
+    //
+    mov w0, w19
+    mov w1, #0
+    mov w2, #14 << 4    // we're in NS world, so 4 bits of priority,
+                        // 8-bit field, - 4 = 4-bit shift
+    bl SetPrivateIntPriority
+
+    mov w0, w19
+    mov w1, #0
+    bl  EnablePrivateInt
+
+    //
+    // set priority mask as low as possible; although,being in the
+    // NS World, we can't set bit[7] of the priority, we still
+    // write all 8-bits of priority to an ICC register
+    //
+    mov x0, #31 << 3
+    msr ICC_PMR_EL1, x0
+
+    //
+    // set global enable and wait for our interrupt to arrive
+    //
+    mov x0, #1
+    msr ICC_IGRPEN1_EL1, x0
+    isb
+
+    //
+    // x19 already contains the CPU number, so branch to secondary
+    // code if we're not on CPU0
+    //
+    cbnz x19, el1_secondary
+
+    //
+    // Fall through to primary code
+    //
+
+
+//
+// ------------------------------------------------------------
+//
+// EL1 - primary CPU init code
+//
+// This code is run on CPU0, while the other CPUs are in the
+// holding pen
+//
+
+    .global el1_primary
+    .type el1_primary, "function"
+el1_primary:
+
+    //
+    // Turn on the banked GIC distributor enable,
+    // ready for individual CPU enables later
+    //
+    mov w0, #(1 << 1)  // gicdctlr_EnableGrp1A
+    bl  EnableGICD
+
+    //
+    // Generate TTBR0 L1
+    //
+    // at 4KB granularity, 32-bit VA space, table lookup starts at
+    // L1, with 1GB regions
+    //
+    // we are going to create entries pointing to L2 tables for a
+    // couple of these 1GB regions, the first of which is the
+    // RAM on the VE board model - get the table addresses and
+    // start by emptying out the L1 page tables (4 entries at L1
+    // for a 4K granularity)
+    //
+    // x21 = address of L1 tables
+    //
+    ldr x21, =Image$$TTB0_L1$$ZI$$Base
+    mov x0, x21
+    mov x1, #(4 << 3)
+    bl  ZeroBlock
+
+    //
+    // time to start mapping the RAM regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // x22 = address of L2 tables, needs to be remembered in case
+    //       we want to re-use the tables for mapping peripherals
+    //
+    ldr x22, =Image$$TTB0_L2_RAM$$ZI$$Base
+    mov x1, #(512 << 3)
+    mov x0, x22
+    bl  ZeroBlock
+
+    //
+    // Get the start address of RAM (the EXEC region) into x4
+    // and calculate the offset into the L1 table (1GB per region,
+    // max 4GB)
+    //
+    // x23 = L1 table offset, saved for later comparison against
+    //       peripheral offset
+    //
+    ldr x4, =Image$$EXEC$$RO$$Base
+    ubfx x23, x4, #30, #2
+
+    orr x1, x22, #TT_S1_ATTR_PAGE
+    str x1, [x21, x23, lsl #3]
+
+    //
+    // we've already used the RAM start address in x4 - we now need
+    // to get this in terms of an offset into the L2 page tables,
+    // where each entry covers 2MB
+    //
+    ubfx x2, x4, #21, #9
+
+    //
+    // TOP_OF_RAM in the scatter file marks the end of the
+    // Execute region in RAM: convert the end of this region to an
+    // offset too, being careful to round up, then calculate the
+    // number of entries to write
+    //
+    ldr x5, =Image$$TOP_OF_RAM$$ZI$$Base
+    sub  x3, x5, #1
+    ubfx x3, x3, #21, #9
+    add  x3, x3, #1
+    sub  x3, x3, x2
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as Shared, Normal WBWA (MAIR[1]) with a flat
+    // VA->PA translation
+    //
+    bic x4, x4, #((1 << 21) - 1)
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (1 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_SH_INNER | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // factor the offset into the page table address and then write
+    // the entries
+    //
+    add x0, x22, x2, lsl #3
+
+loop1:
+    subs x3, x3, #1
+    str x1, [x0], #8
+    add x1, x1, #0x200, LSL #12    // equiv to add x1, x1, #(1 << 21)  // 2MB per entry
+    bne loop1
+
+
+    //
+    // now mapping the Peripheral regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // The assumption here is that all peripherals live within
+    // a common 1GB region (i.e. that there's a single set of
+    // L2 pages for all the peripherals). We only use a UART
+    // and the GIC in this example, so the assumption is sound
+    //
+    // x24 = address of L2 peripheral tables
+    //
+    ldr x24, =Image$$TTB0_L2_PERIPH$$ZI$$Base
+
+    //
+    // get the GICD address into x4 and calculate
+    // the offset into the L1 table
+    //
+    // x25 = L1 table offset
+    //
+    ldr x4, =Image$$GICD$$ZI$$Base
+    ubfx x25, x4, #30, #2
+
+    //
+    // here's the tricky bit: it's possible that the peripherals are
+    // in the same 1GB region as the RAM, in which case we don't need
+    // to prime a separate set of L2 page tables, nor add them to the
+    // L1 tables
+    //
+    // if we're going to re-use the TTB0_L2_RAM tables, get their
+    // address into x24, which is used later on to write the PTEs
+    //
+    cmp x25, x23
+    csel x24, x22, x24, EQ
+    b.eq nol2setup
+
+    //
+    // Peripherals are in a separate 1GB region, and so have their own
+    // set of L2 tables - clean out the tables and add them to the L1
+    // table
+    //
+    mov x0, x24
+    mov x1, #512 << 3
+    bl  ZeroBlock
+
+    orr x1, x24, #TT_S1_ATTR_PAGE
+    str x1, [x21, x25, lsl #3]
+
+    //
+    // there's only going to be a single 2MB region for GICD (in
+    // x4) - get this in terms of an offset into the L2 page tables
+    //
+    // with larger systems, it is possible that the GIC redistributor
+    // registers require extra 2MB pages, in which case extra code
+    // would be required here
+    //
+nol2setup:
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry for this, so no loop as we have for RAM, above
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // we have CS3_PERIPHERALS that include the UART controller
+    //
+    // Again, the code is making assumptions - this time that the CS3_PERIPHERALS
+    // region uses the same 1GB portion of the address space as the GICD,
+    // and thus shares the same set of L2 page tables
+    //
+    // Get CS3_PERIPHERALS address into x4 and calculate the offset into the
+    // L2 tables
+    //
+    ldr x4, =Image$$CS3_PERIPHERALS$$ZI$$Base
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry again - write it
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // issue a barrier to ensure all table entry writes are complete
+    //
+    dsb ish
+
+    ldr x1, =is_mmu_ready
+    mov x2, #1
+    str x2, [x1]
+
+    //
+    // Enable the MMU.  Caches will be enabled later, after scatterloading.
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // Branch to C library init code
+    //
+    b  __main
+
+
+// ------------------------------------------------------------
+
+// AArch64 Arm C library startup add-in:
+
+// The Arm Architecture Reference Manual for Armv8-A states:
+//
+//     Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
+//     Correspondingly, the sequence for ensuring that modifications to instructions are available
+//     for execution must include invalidation of the modified locations from the instruction cache,
+//     even if the instructions are held in Normal Non-cacheable memory.
+//     This includes cases where the instruction cache is disabled.
+//
+// To invalidate the AArch64 instruction cache after scatter-loading and before initialization of the stack and heap,
+// it is necessary for the user to:
+//
+// * Implement instruction cache invalidation code in _platform_pre_stackheap_init.
+// * Ensure all code on the path from the program entry up to and including _platform_pre_stackheap_init is located in a root region.
+//
+// In this example, this function is only called once, by the primary core
+
+    .global _platform_pre_stackheap_init
+    .type _platform_pre_stackheap_init, "function"
+    .cfi_startproc
+_platform_pre_stackheap_init:
+    dsb ish     // ensure all previous stores have completed before invalidating
+    ic  ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
+    dsb ish     // ensure completion on inner shareable domain   (which includes secondary cores)
+    isb
+
+    // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    msr SCTLR_EL1, x1
+    isb
+
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+// EL1 - secondary CPU init code
+//
+// This code is run on CPUs 1, 2, 3 etc....
+// ------------------------------------------------------------
+
+    .global el1_secondary
+    .type el1_secondary, "function"
+el1_secondary:
+
+wait_for_mmu_ready:
+    ldr x1, =is_mmu_ready
+    ldr x1, [x1]
+    cmp x1, #1
+    b.ne wait_for_mmu_ready
+
+    //
+    // Enable the MMU and caches
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+	/* EL: Secondary core entrance.  */
+    B       _tx_thread_smp_initialize_wait
+
+loop_wfi:
+    dsb SY      // Clear all pending data accesses
+    wfi         // Go to sleep
+
+    //
+    // something woke us from our wait, was it the required interrupt?
+    //
+    mov w0, w19
+    mov w1, #15
+    bl  GetPrivateIntPending
+    cbz w0, loop_wfi
+
+    //
+    // it was - there's no need to actually take the interrupt,
+    // so just clear it
+    //
+    mov w0, w19
+    mov w1, #15
+    bl  ClearPrivateIntPending
+
+    //
+    // Branch to thread start
+    //
+    // B  MainApp
+
+    /**
+     * Retargeted to prevent the C library from doing its own stack and heap
+     * initialisation.
+     */
+    .type __user_setup_stackheap, @function
+__user_setup_stackheap:
+    ADRP    X0, Image$$SYS_STACK$$ZI$$Limit
+    MOV     SP, X0
+    ADRP    X0, Image$$ARM_LIB_HEAP$$ZI$$Base
+    ADRP    X2, Image$$ARM_LIB_HEAP$$ZI$$Limit
+    RET
+    
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/timer_interrupts.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/timer_interrupts.c
new file mode 100644
index 00000000..434d9189
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/timer_interrupts.c
@@ -0,0 +1,152 @@
+/* Bare-metal example for Armv8-A FVP Base model */
+
+/* Timer and interrupts */
+
+/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */
+/* Use, modification and redistribution of this file is subject to your      */
+/* possession of a valid DS-5 end user licence agreement and your compliance */
+/* with all applicable terms and conditions of such licence agreement.       */
+
+#include <stdio.h>
+
+#include "GICv3.h"
+#include "GICv3_gicc.h"
+#include "sp804_timer.h"
+
+void   _tx_timer_interrupt(void);
+
+// LED Base address
+#define LED_BASE (volatile unsigned int *)0x1C010008
+
+
+void nudge_leds(void) // Move LEDs along
+{
+    static int state = 1;
+    static int value = 1;
+
+    if (state)
+    {
+        int max = (1 << 7);
+        value <<= 1;
+        if (value == max)
+            state = 0;
+    }
+    else
+    {
+        value >>= 1;
+        if (value == 1)
+            state = 1;
+    }
+
+    *LED_BASE = value;  // Update LEDs hardware
+}
+
+
+// Initialize Timer 0 and Interrupt Controller
+void init_timer(void)
+{
+    // Enable interrupts
+    __asm("MSR DAIFClr, #0xF");
+    setICC_IGRPEN1_EL1(igrpEnable);
+
+    // Configure the SP804 timer to generate an interrupt
+    setTimerBaseAddress(0x1C110000);
+    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
+    startTimer();
+
+    // The SP804 timer generates SPI INTID 34.  Enable
+    // this ID, and route it to core 0.0.0.0 (this one!)
+    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
+    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
+    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
+    EnableSPI(34);                                   // Enable INTID 34
+}
+
+
+// --------------------------------------------------------
+
+void irqHandler(void)
+{
+  unsigned int ID;
+
+  ID = getICC_IAR1(); // readIntAck();
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+      //printf("irqHandler() - Reserved INTID %d\n\n", ID);
+      return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("irqHandler() - External timer interrupt\n\n");
+      nudge_leds();
+      clearTimerIrq();
+
+      /* Call ThreadX timer interrupt processing.  */
+      _tx_timer_interrupt();
+
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("irqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
+
+// --------------------------------------------------------
+
+// Not actually used in this example, but provided for completeness
+
+void fiqHandler(void)
+{
+  unsigned int ID;
+  unsigned int aliased = 0;
+
+  ID = getICC_IAR0(); // readIntAck();
+  //printf("fiqHandler() - Read %d from IAR0\n", ID);
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+    //printf("fiqHandler() - Reserved INTID %d\n\n", ID);
+    ID = getICC_IAR1(); // readAliasedIntAck();
+    //printf("fiqHandler() - Read %d from AIAR\n", ID);
+    aliased = 1;
+
+    // If still spurious then simply return
+    if ((1020 <= ID) && (ID <= 1023))
+        return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("fiqHandler() - External timer interrupt\n\n");
+      clearTimerIrq();
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  // NOTE: If the ID was read from the Aliased IAR, then
+  // the aliased EOI register must be used
+  if (aliased == 0)
+    setICC_EOIR0(ID); // writeEOI(ID);
+  else
+    setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.S
new file mode 100644
index 00000000..e2d81e5e
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.S
@@ -0,0 +1,161 @@
+// ------------------------------------------------------------
+// Armv8-A AArch64 - Common helper functions
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global EnableCachesEL1
+    .global DisableCachesEL1
+    .global InvalidateUDCaches
+    .global GetMIDR
+    .global GetMPIDR
+    .global GetCPUID
+
+// ------------------------------------------------------------
+
+//
+// void EnableCachesEL1(void)
+//
+//    enable Instruction and Data caches
+//
+    .type EnableCachesEL1, "function"
+    .cfi_startproc
+EnableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    orr x0, x0, #SCTLR_ELx_I
+    orr x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+    .type DisableCachesEL1, "function"
+    .cfi_startproc
+DisableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    bic x0, x0, #SCTLR_ELx_I
+    bic x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// void InvalidateUDCaches(void)
+//
+//    Invalidate data and unified caches
+//
+    .type InvalidateUDCaches, "function"
+    .cfi_startproc
+InvalidateUDCaches:
+    // From the Armv8-A Architecture Reference Manual
+
+    dmb  ish                   // ensure all prior inner-shareable accesses have been observed
+
+    mrs  x0, CLIDR_EL1
+    and  w3, w0, #0x07000000   // get 2 x level of coherence
+    lsr  w3, w3, #23
+    cbz  w3, finished
+    mov  w10, #0               // w10 = 2 x cache level
+    mov  w8, #1                // w8 = constant 0b1
+loop_level:
+    add  w2, w10, w10, lsr #1  // calculate 3 x cache level
+    lsr  w1, w0, w2            // extract 3-bit cache type for this level
+    and  w1, w1, #0x7
+    cmp  w1, #2
+    b.lt next_level            // no data or unified cache at this level
+    msr  CSSELR_EL1, x10       // select this cache level
+    isb                        // synchronize change of csselr
+    mrs  x1, CCSIDR_EL1        // read ccsidr
+    and  w2, w1, #7            // w2 = log2(linelen)-4
+    add  w2, w2, #4            // w2 = log2(linelen)
+    ubfx w4, w1, #3, #10       // w4 = max way number, right aligned
+    clz  w5, w4                // w5 = 32-log2(ways), bit position of way in dc operand
+    lsl  w9, w4, w5            // w9 = max way number, aligned to position in dc operand
+    lsl  w16, w8, w5           // w16 = amount to decrement way number per iteration
+loop_way:
+    ubfx w7, w1, #13, #15      // w7 = max set number, right aligned
+    lsl  w7, w7, w2            // w7 = max set number, aligned to position in dc operand
+    lsl  w17, w8, w2           // w17 = amount to decrement set number per iteration
+loop_set:
+    orr  w11, w10, w9          // w11 = combine way number and cache number ...
+    orr  w11, w11, w7          // ... and set number for dc operand
+    dc   isw, x11              // do data cache invalidate by set and way
+    subs w7, w7, w17           // decrement set number
+    b.ge loop_set
+    subs x9, x9, x16           // decrement way number
+    b.ge loop_way
+next_level:
+    add  w10, w10, #2          // increment 2 x cache level
+    cmp  w3, w10
+    b.gt loop_level
+    dsb  sy                    // ensure completion of previous cache maintenance operation
+    isb
+finished:
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// ID Register functions
+//
+
+    .type GetMIDR, "function"
+    .cfi_startproc
+GetMIDR:
+
+    mrs x0, MIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetMPIDR, "function"
+    .cfi_startproc
+GetMPIDR:
+
+    mrs x0, MPIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetCPUID, "function"
+    .cfi_startproc
+GetCPUID:
+
+    mrs x0, MIDR_EL1
+    ubfx    x0, x0, #4, #12 // extract PartNum
+    cmp x0, #0xD0A          // Cortex-A75
+    b.eq DynamIQ
+    cmp x0, #0xD05          // Cortex-A55
+    b.eq DynamIQ
+    b Others
+DynamIQ:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+
+Others:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h
new file mode 100644
index 00000000..afb8b923
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h
@@ -0,0 +1,118 @@
+//
+// Defines for v8 Memory Model
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_MMU_H
+#define V8_MMU_H
+
+//
+// Translation Control Register fields
+//
+// RGN field encodings
+//
+#define TCR_RGN_NC   0b00
+#define TCR_RGN_WBWA 0b01
+#define TCR_RGN_WT   0b10
+#define TCR_RGN_WBRA 0b11
+
+//
+// Shareability encodings
+//
+#define TCR_SHARE_NONE  0b00
+#define TCR_SHARE_OUTER 0b10
+#define TCR_SHARE_INNER 0b11
+
+//
+// Granule size encodings
+//
+#define TCR_GRANULE_4K  0b00
+#define TCR_GRANULE_64K 0b01
+#define TCR_GRANULE_16K 0b10
+
+//
+// Physical Address sizes
+//
+#define TCR_SIZE_4G   0b000
+#define TCR_SIZE_64G  0b001
+#define TCR_SIZE_1T   0b010
+#define TCR_SIZE_4T   0b011
+#define TCR_SIZE_16T  0b100
+#define TCR_SIZE_256T 0b101
+
+//
+// Translation Control Register fields
+//
+#define TCR_EL1_T0SZ_SHIFT   0
+#define TCR_EL1_EPD0  (1 << 7)
+#define TCR_EL1_IRGN0_SHIFT  8
+#define TCR_EL1_ORGN0_SHIFT 10
+#define TCR_EL1_SH0_SHIFT   12
+#define TCR_EL1_TG0_SHIFT   14
+
+#define TCR_EL1_T1SZ_SHIFT  16
+#define TCR_EL1_A1   (1 << 22)
+#define TCR_EL1_EPD1 (1 << 23)
+#define TCR_EL1_IRGN1_SHIFT 24
+#define TCR_EL1_ORGN1_SHIFT 26
+#define TCR_EL1_SH1_SHIFT   28
+#define TCR_EL1_TG1_SHIFT   30
+#define TCR_EL1_IPS_SHIFT   32
+#define TCR_EL1_AS   (1 << 36)
+#define TCR_EL1_TBI0 (1 << 37)
+#define TCR_EL1_TBI1 (1 << 38)
+
+//
+// Stage 1 Translation Table descriptor fields
+//
+#define TT_S1_ATTR_FAULT (0b00 << 0)
+#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
+#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
+#define TT_S1_ATTR_PAGE  (0b11 << 0) // Level 3
+
+#define TT_S1_ATTR_MATTR_LSB 2
+
+#define TT_S1_ATTR_NS (1 << 5)
+
+#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
+#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
+#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
+#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
+
+#define TT_S1_ATTR_SH_NONE   (0b00 << 8)
+#define TT_S1_ATTR_SH_OUTER  (0b10 << 8)
+#define TT_S1_ATTR_SH_INNER  (0b11 << 8)
+
+#define TT_S1_ATTR_AF (1 << 10)
+#define TT_S1_ATTR_nG (1 << 11)
+
+#define TT_S1_ATTR_CONTIG (1 << 52)
+#define TT_S1_ATTR_PXN    (1 << 53)
+#define TT_S1_ATTR_UXN    (1 << 54)
+
+#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
+#define TT_S1_MAIR_DEV_nGnRE  0b00000100
+#define TT_S1_MAIR_DEV_nGRE   0b00001000
+#define TT_S1_MAIR_DEV_GRE    0b00001100
+
+//
+// Inner and Outer Normal memory attributes use the same bit patterns
+// Outer attributes just need to be shifted up
+//
+#define TT_S1_MAIR_OUTER_SHIFT 4
+
+#define TT_S1_MAIR_WT_TRANS_RA  0b0010
+
+#define TT_S1_MAIR_WB_TRANS_RA  0b0110
+#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
+
+#define TT_S1_MAIR_WT_RA  0b1010
+
+#define TT_S1_MAIR_WB_RA  0b1110
+#define TT_S1_MAIR_WB_RWA 0b1111
+
+#endif // V8_MMU_H
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_system.h
new file mode 100644
index 00000000..e54f2fc7
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_system.h
@@ -0,0 +1,115 @@
+//
+// Defines for v8 System Registers
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_SYSTEM_H
+#define V8_SYSTEM_H
+
+//
+// AArch64 SPSR
+//
+#define AARCH64_SPSR_EL3h 0b1101
+#define AARCH64_SPSR_EL3t 0b1100
+#define AARCH64_SPSR_EL2h 0b1001
+#define AARCH64_SPSR_EL2t 0b1000
+#define AARCH64_SPSR_EL1h 0b0101
+#define AARCH64_SPSR_EL1t 0b0100
+#define AARCH64_SPSR_EL0t 0b0000
+#define AARCH64_SPSR_RW (1 << 4)
+#define AARCH64_SPSR_F  (1 << 6)
+#define AARCH64_SPSR_I  (1 << 7)
+#define AARCH64_SPSR_A  (1 << 8)
+#define AARCH64_SPSR_D  (1 << 9)
+#define AARCH64_SPSR_IL (1 << 20)
+#define AARCH64_SPSR_SS (1 << 21)
+#define AARCH64_SPSR_V  (1 << 28)
+#define AARCH64_SPSR_C  (1 << 29)
+#define AARCH64_SPSR_Z  (1 << 30)
+#define AARCH64_SPSR_N  (1 << 31)
+
+//
+// Multiprocessor Affinity Register
+//
+#define MPIDR_EL1_AFF3_LSB 32
+#define MPIDR_EL1_U  (1 << 30)
+#define MPIDR_EL1_MT (1 << 24)
+#define MPIDR_EL1_AFF2_LSB 16
+#define MPIDR_EL1_AFF1_LSB  8
+#define MPIDR_EL1_AFF0_LSB  0
+#define MPIDR_EL1_AFF_WIDTH 8
+
+//
+// Data Cache Zero ID Register
+//
+#define DCZID_EL0_BS_LSB   0
+#define DCZID_EL0_BS_WIDTH 4
+#define DCZID_EL0_DZP_LSB  5
+#define DCZID_EL0_DZP (1 << 5)
+
+//
+// System Control Register
+//
+#define SCTLR_EL1_UCI     (1 << 26)
+#define SCTLR_ELx_EE      (1 << 25)
+#define SCTLR_EL1_E0E     (1 << 24)
+#define SCTLR_ELx_WXN     (1 << 19)
+#define SCTLR_EL1_nTWE    (1 << 18)
+#define SCTLR_EL1_nTWI    (1 << 16)
+#define SCTLR_EL1_UCT     (1 << 15)
+#define SCTLR_EL1_DZE     (1 << 14)
+#define SCTLR_ELx_I       (1 << 12)
+#define SCTLR_EL1_UMA     (1 << 9)
+#define SCTLR_EL1_SED     (1 << 8)
+#define SCTLR_EL1_ITD     (1 << 7)
+#define SCTLR_EL1_THEE    (1 << 6)
+#define SCTLR_EL1_CP15BEN (1 << 5)
+#define SCTLR_EL1_SA0     (1 << 4)
+#define SCTLR_ELx_SA      (1 << 3)
+#define SCTLR_ELx_C       (1 << 2)
+#define SCTLR_ELx_A       (1 << 1)
+#define SCTLR_ELx_M       (1 << 0)
+
+//
+// Architectural Feature Access Control Register
+//
+#define CPACR_EL1_TTA     (1 << 28)
+#define CPACR_EL1_FPEN    (3 << 20)
+
+//
+// Architectural Feature Trap Register
+//
+#define CPTR_ELx_TCPAC (1 << 31)
+#define CPTR_ELx_TTA   (1 << 20)
+#define CPTR_ELx_TFP   (1 << 10)
+
+//
+// Secure Configuration Register
+//
+#define SCR_EL3_TWE  (1 << 13)
+#define SCR_EL3_TWI  (1 << 12)
+#define SCR_EL3_ST   (1 << 11)
+#define SCR_EL3_RW   (1 << 10)
+#define SCR_EL3_SIF  (1 << 9)
+#define SCR_EL3_HCE  (1 << 8)
+#define SCR_EL3_SMD  (1 << 7)
+#define SCR_EL3_EA   (1 << 3)
+#define SCR_EL3_FIQ  (1 << 2)
+#define SCR_EL3_IRQ  (1 << 1)
+#define SCR_EL3_NS   (1 << 0)
+
+//
+// Hypervisor Configuration Register
+//
+#define HCR_EL2_ID   (1 << 33)
+#define HCR_EL2_CD   (1 << 32)
+#define HCR_EL2_RW   (1 << 31)
+#define HCR_EL2_TRVM (1 << 30)
+#define HCR_EL2_HVC  (1 << 29)
+#define HCR_EL2_TDZ  (1 << 28)
+
+#endif // V8_SYSTEM_H
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_utils.S
new file mode 100644
index 00000000..750488b7
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/v8_utils.S
@@ -0,0 +1,69 @@
+//
+// Simple utility routines for baremetal v8 code
+//
+// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//
+// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
+//
+// Zero fill a block of memory
+//   Fill memory pages or similar structures with zeros.
+//   The byte count must be a multiple of the block fill size (16 bytes)
+//
+//  Inputs:
+//    blockPtr - base address of block to fill
+//    nBytes - block size, in bytes
+//
+//  Returns:
+//    pointer to just filled block, NULL if nBytes is
+//  incompatible with block fill size
+//
+    .global ZeroBlock
+    .type ZeroBlock, "function"
+    .cfi_startproc
+ZeroBlock:
+
+    //
+    // we fill data by steam, 16 bytes at a time: check that
+    // blocksize is a multiple of that
+    //
+    ubfx x2, x1, #0, #4
+    cbnz x2, incompatible
+
+    //
+    // we already have one register full of zeros, get another
+    //
+    mov x3, x2
+
+    //
+    // OK, set temporary pointer and away we go
+    //
+    add x0, x0, x1
+
+loop0:
+    subs x1, x1, #16
+    stp  x2, x3, [x0, #-16]!
+    b.ne loop0
+
+    //
+    // that's all - x0 will be back to its start value
+    //
+    ret
+
+    //
+    // parameters are incompatible with block size - return
+    // an indication that this is so
+    //
+incompatible:
+    mov x0,#0
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/vectors.S
new file mode 100644
index 00000000..be6d28a3
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/vectors.S
@@ -0,0 +1,252 @@
+// ------------------------------------------------------------
+// Armv8-A Vector tables
+//
+// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+    .global c0sync1
+    .global irqHandler
+    .global fiqHandler
+    .global irqFirstLevelHandler
+    .global fiqFirstLevelHandler
+
+    .section  EL1VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el1_vectors:
+c0sync1: B c0sync1
+
+    .balign 0x80
+c0irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr1: B c0serr1
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync1: B cxsync1
+
+    .balign 0x80
+cxirq1: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr1: B cxserr1
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync1: B l64sync1
+
+    .balign 0x80
+l64irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr1: B l64serr1
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync1: B l32sync1
+
+    .balign 0x80
+l32irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr1: B l32serr1
+
+//----------------------------------------------------------------
+
+    .section  EL2VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el2_vectors:
+c0sync2: B c0sync2
+
+    .balign 0x80
+c0irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr2: B c0serr2
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync2: B cxsync2
+
+    .balign 0x80
+cxirq2: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr2: B cxserr2
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync2: B l64sync2
+
+    .balign 0x80
+l64irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr2: B l64serr2
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync2: B l32sync2
+
+    .balign 0x80
+l32irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr2: B l32serr2
+
+//----------------------------------------------------------------
+
+    .section  EL3VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el3_vectors:
+c0sync3: B c0sync3
+
+    .balign 0x80
+c0irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr3: B c0serr3
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync3: B cxsync3
+
+    .balign 0x80
+cxirq3: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr3: B cxserr3
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync3: B l64sync3
+
+    .balign 0x80
+l64irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr3: B l64serr3
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync3: B l32sync3
+
+    .balign 0x80
+l32irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr3: B l32serr3
+
+
+    .section InterruptHandlers, "ax"
+    .balign 4
+
+    .type irqFirstLevelHandler, "function"
+irqFirstLevelHandler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+  BL       irqHandler
+  B        _tx_thread_context_restore
+
+    .type fiqFirstLevelHandler, "function"
+fiqFirstLevelHandler:
+  STP      x29, x30, [sp, #-16]!
+  STP      x18, x19, [sp, #-16]!
+  STP      x16, x17, [sp, #-16]!
+  STP      x14, x15, [sp, #-16]!
+  STP      x12, x13, [sp, #-16]!
+  STP      x10, x11, [sp, #-16]!
+  STP      x8, x9, [sp, #-16]!
+  STP      x6, x7, [sp, #-16]!
+  STP      x4, x5, [sp, #-16]!
+  STP      x2, x3, [sp, #-16]!
+  STP      x0, x1, [sp, #-16]!
+
+  BL       fiqHandler
+
+  LDP      x0, x1, [sp], #16
+  LDP      x2, x3, [sp], #16
+  LDP      x4, x5, [sp], #16
+  LDP      x6, x7, [sp], #16
+  LDP      x8, x9, [sp], #16
+  LDP      x10, x11, [sp], #16
+  LDP      x12, x13, [sp], #16
+  LDP      x14, x15, [sp], #16
+  LDP      x16, x17, [sp], #16
+  LDP      x18, x19, [sp], #16
+  LDP      x29, x30, [sp], #16
+  ERET
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject
new file mode 100644
index 00000000..c27fce90
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
+                        						
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+                                								
+                                <option id="com.arm.tool.linker.v6.option.useMicroLib.755943199" name="Use microlib" superClass="com.arm.tool.linker.v6.option.useMicroLib" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.1298703983" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/txm/Debug/txm.a}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.c.linker.option.callgraph.580370920" name="Generate call graph (--callgraph)" superClass="com.arm.tool.c.linker.option.callgraph" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.verbose.37337082" name="Verbose output (--verbose)" superClass="com.arm.tool.c.linker.option.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.totals.832607305" name="List total code and data sizes of output image (--info=totals)" superClass="com.arm.tool.c.linker.option.totals" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.elim.994414938" name="List unused sections that are eliminated (--info=unused)" superClass="com.arm.tool.c.linker.option.elim" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.compress.597638838" name="Print RW compression information (--info=compression)" superClass="com.arm.tool.c.linker.option.compress" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.inlineinfo.1002296295" name="List functions inlined by linker (--info=inline)" superClass="com.arm.tool.c.linker.option.inlineinfo" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.stack.663754292" name="List stack usage of global symbols (--info=stack)" superClass="com.arm.tool.c.linker.option.stack" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.graphfile.1079396865" name="Callgraph file (--callgraph_file)" superClass="com.arm.tool.c.linker.option.graphfile" useByScannerDiscovery="false" value="callgraph.html" valueType="string"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.project b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.project
new file mode 100644
index 00000000..17f6aba3
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx_module</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.arm.debug.ds.nature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c
new file mode 100644
index 00000000..a974cdf1
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c
@@ -0,0 +1,467 @@
+/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes 
+   examples of eight threads of different priorities, using a message queue, semaphore, mutex, 
+   event flags group, byte pool, and block pool.  */
+
+/* Specify that this is a module!  */
+
+#define TXM_MODULE
+
+
+/* Include the ThreadX module definitions.  */
+
+#include "txm_module.h"
+
+
+/* Define constants.  */
+
+#define DEMO_BYTE_POOL_SIZE     (1024 * 48)
+#define DEMO_STACK_SIZE         (1024 * 4)
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the pool space in the bss section of the module. ULONG is used to 
+   get the word alignment.  */
+
+ULONG                   demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)];
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               *thread_0;
+TX_THREAD               *thread_1;
+TX_THREAD               *thread_2;
+TX_THREAD               *thread_3;
+TX_THREAD               *thread_4;
+TX_THREAD               *thread_5;
+TX_THREAD               *thread_6;
+TX_THREAD               *thread_7;
+TX_QUEUE                *queue_0;
+TX_SEMAPHORE            *semaphore_0;
+TX_MUTEX                *mutex_0;
+TX_EVENT_FLAGS_GROUP    *event_flags_0;
+TX_BYTE_POOL            *byte_pool_0;
+TX_BLOCK_POOL           *block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter = 0;
+ULONG           thread_1_counter = 0;
+ULONG           thread_1_messages_sent = 0;
+ULONG           thread_2_counter = 0;
+ULONG           thread_2_messages_received = 0;
+ULONG           thread_3_counter = 0;
+ULONG           thread_4_counter = 0;
+ULONG           thread_5_counter = 0;
+ULONG           thread_6_counter = 0;
+ULONG           thread_7_counter = 0;
+ULONG           semaphore_0_puts = 0;
+ULONG           event_0_sets = 0;
+ULONG           queue_0_sends = 0;
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+void  semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
+{
+
+    if (semaphore_ptr == semaphore_0)
+        semaphore_0_puts++;
+}
+
+
+void  event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
+{
+
+    if (event_flag_group_ptr == event_flags_0)
+        event_0_sets++;
+}
+
+
+void  queue_0_notify(TX_QUEUE *queue_ptr)
+{
+
+    if (queue_ptr == queue_0)
+        queue_0_sends++;
+}
+
+
+/* Define the module start function.  */
+
+void    demo_module_start(ULONG id)
+{
+
+UINT    status;
+CHAR    *pointer;
+
+
+    /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within
+       their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting 
+       the control block(s).  */
+    status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
+    while (status != TX_SUCCESS);
+                               
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
+    while (status != TX_SUCCESS);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the message queue.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    status = tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+    while (status != TX_SUCCESS);
+
+    status = tx_queue_send_notify(queue_0, queue_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    status = tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
+    while (status != TX_SUCCESS);
+
+    status = tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    status = tx_event_flags_create(event_flags_0, "module event flags 0");
+    while (status != TX_SUCCESS);
+
+    status = tx_event_flags_set_notify(event_flags_0, event_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    status = tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the memory for a small block pool.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    status = tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+    while (status != TX_SUCCESS);
+
+    /* Allocate a block and release the block memory.  */
+    status = tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Release the block back to the pool.  */
+    status = tx_block_release(pointer);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 0.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create the main thread.  */
+    status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 1.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 2.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 3.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 4.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 5.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 6.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 7.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+}
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+    
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+       
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S
new file mode 100644
index 00000000..f05656c3
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S
@@ -0,0 +1,63 @@
+    .text
+    .align 4
+    .section Init
+    
+    // External references
+    .global  _txm_module_thread_shell_entry
+    .global  _txm_module_callback_request_thread_entry
+    .global  demo_module_start
+    .global  Image$$ER_RO$$Length
+    .global  Image$$ER_RW$$Length
+    .global  Image$$ER_ZI$$Length
+
+    .global __txm_module_preamble
+__txm_module_preamble:
+    .dc.l   0x4D4F4455                                          // Module ID
+    .dc.l   0x6                                                 // Module Major Version
+    .dc.l   0x1                                                 // Module Minor Version
+    .dc.l   32                                                  // Module Preamble Size in 32-bit words
+    .dc.l   0x12345678                                          // Module ID (application defined)
+    .dc.l   0x01000000                                          // Module Properties where:
+                                                                //   Bits 31-24: Compiler ID
+                                                                //           0 -> IAR
+                                                                //           1 -> ARM
+                                                                //           2 -> GNU
+                                                                //   Bit 0:  0 -> Privileged mode execution
+                                                                //           1 -> User mode execution
+                                                                //   Bit 1:  0 -> No MPU protection
+                                                                //           1 -> MPU protection (must have user mode selected)
+                                                                //   Bit 2:  0 -> Disable shared/external memory access
+                                                                //           1 -> Enable shared/external memory access
+    .dc.l   _txm_module_thread_shell_entry                      // Module Shell Entry Point
+    .dc.l   demo_module_start                                   // Module Start Thread Entry Point
+    .dc.l   0                                                   // Module Stop Thread Entry Point
+    .dc.l   1                                                   // Module Start/Stop Thread Priority
+    .dc.l   4096                                                // Module Start/Stop Thread Stack Size
+    .dc.l   _txm_module_callback_request_thread_entry           // Module Callback Thread Entry
+    .dc.l   1                                                   // Module Callback Thread Priority
+    .dc.l   4096                                                // Module Callback Thread Stack Size
+    .dc.l   Image$$ER_RO$$Length                                // Module Code Size
+    .dc.l   Image$$ER_ZI$$Length                                // Module Data Size
+    .dc.l   0                                                   // Reserved 0
+    .dc.l   0                                                   // Reserved 1
+    .dc.l   0                                                   // Reserved 2
+    .dc.l   0                                                   // Reserved 3
+    .dc.l   0                                                   // Reserved 4
+    .dc.l   0                                                   // Reserved 5
+    .dc.l   0                                                   // Reserved 6
+    .dc.l   0                                                   // Reserved 7
+    .dc.l   0                                                   // Reserved 8
+    .dc.l   0                                                   // Reserved 9
+    .dc.l   0                                                   // Reserved 10
+    .dc.l   0                                                   // Reserved 11
+    .dc.l   0                                                   // Reserved 12
+    .dc.l   0                                                   // Reserved 13
+    .dc.l   0                                                   // Reserved 14
+    .dc.l   0                                                   // Reserved 15
+
+.image__er_ro__length:
+    .quad Image$$ER_RO$$Length
+.image__er_rw__length:
+    .quad Image$$ER_RW$$Length
+.image__er_zi__length:
+    .quad Image$$ER_ZI$$Length
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject
new file mode 100644
index 00000000..1eba821f
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject
@@ -0,0 +1,244 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6">
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.debug.level.2012923809" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371.1548806269" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx_module_manager}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1721512389" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.cpu.1798518755" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.defmac.663509616" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="TX_THREAD_SMP_CLUSTERS=2"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/sample_threadx_module_manager/inc_common_module_manager}&quot;"/>
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+                                </option>
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.904753152" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
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+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1069377025" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
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+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.target.1007894450" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="aarch64-arm-none-eabi" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.cpu.1820500228" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.fpu.969773893" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.inst.1333768272" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.auto" valueType="enumerated"/>
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+                                <option id="com.arm.tool.assembler.v6.base.options.debug.level.429021326" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.incpath.1361570371" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.defmac.1224282672" name="Define macro (-D)" superClass="com.arm.tool.assembler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="TX_THREAD_SMP_CLUSTERS=2"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.assembler.v6.base.option.force.preproc.70495432" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.linker.option.entry.1032206829" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="start64" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.scatter.1463218579" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="../sample_threadx_module_manager.scat" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.libs.402211535" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="..\..\tx\Debug\tx.a"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.tool.linker.v6.option.suppress.1394753016" name="Suppress (--diag_suppress)" superClass="com.arm.tool.linker.v6.option.suppress" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.verbose.1037588003" name="Verbose output (--verbose)" superClass="com.arm.tool.c.linker.option.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.imagemap.288784399" name="Generate image map (--map)" superClass="com.arm.tool.c.linker.option.imagemap" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.callgraph.790189508" name="Generate call graph (--callgraph)" superClass="com.arm.tool.c.linker.option.callgraph" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.graphfile.1499920530" name="Callgraph file (--callgraph_file)" superClass="com.arm.tool.c.linker.option.graphfile" useByScannerDiscovery="false" value="callgraph.html" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.totals.202338982" name="List total code and data sizes of output image (--info=totals)" superClass="com.arm.tool.c.linker.option.totals" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.elim.906699010" name="List unused sections that are eliminated (--info=unused)" superClass="com.arm.tool.c.linker.option.elim" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.compress.146553876" name="Print RW compression information (--info=compression)" superClass="com.arm.tool.c.linker.option.compress" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.stack.1124843323" name="List stack usage of global symbols (--info=stack)" superClass="com.arm.tool.c.linker.option.stack" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.inlineinfo.1507799506" name="List functions inlined by linker (--info=inline)" superClass="com.arm.tool.c.linker.option.inlineinfo" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.redirectoutput.1150221552" name="Redirect diagnostics output to file (--list)" superClass="com.arm.tool.c.linker.option.redirectoutput" useByScannerDiscovery="false" value="sample_threadx_module_manager.map" valueType="string"/>
+                                								
+                                <option id="com.arm.tool.c.linker.option.eleminate.2049531669" name="Eliminate unused sections (--remove)" superClass="com.arm.tool.c.linker.option.eleminate" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520.574595573" name="/" resourcePath="src_common_module_manager">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.1223583858" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6" unusedChildren="">
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986.1006506546" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.debug.level.2012923809.1155748230" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level.2012923809"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1927525577" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258">
+                                								
+                                <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1304794003" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/>
+                                								
+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.1502156310" superClass="com.arm.tool.c.compiler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.1573521907" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072">
+                                								
+                                <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1807654698" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1808081220" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179">
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.579682311" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.641966454" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.616745103" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx_module_manager.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.project b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.project
new file mode 100644
index 00000000..310289aa
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.project
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx_module_manager</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_common_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
+		</link>
+		<link>
+			<name>src_common_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3.h
new file mode 100644
index 00000000..b04cd97b
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3.h
@@ -0,0 +1,561 @@
+/*
+ * GICv3.h - data types and function prototypes for GICv3 utility routines
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your
+ * possession of a valid DS-5 end user licence agreement and your compliance
+ * with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_h
+#define GICV3_h
+
+#include <stdint.h>
+
+/*
+ * extra flags for GICD enable
+ */
+typedef enum
+{
+    gicdctlr_EnableGrp0 = (1 << 0),
+    gicdctlr_EnableGrp1NS = (1 << 1),
+    gicdctlr_EnableGrp1A = (1 << 1),
+    gicdctlr_EnableGrp1S = (1 << 2),
+    gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
+    gicdctlr_ARE_S = (1 << 4),	/* Enable Secure state affinity routing */
+    gicdctlr_ARE_NS = (1 << 5),	/* Enable Non-Secure state affinity routing */
+    gicdctlr_DS = (1 << 6),	/* Disable Security support */
+    gicdctlr_E1NWF = (1 << 7)	/* Enable "1-of-N" wakeup model */
+} GICDCTLRFlags_t;
+
+/*
+ * modes for SPI routing
+ */
+typedef enum
+{
+    gicdirouter_ModeSpecific = 0,
+    gicdirouter_ModeAny = (1 << 31)
+} GICDIROUTERBits_t;
+
+typedef enum
+{
+    gicdicfgr_Level = 0,
+    gicdicfgr_Edge = (1 << 1)
+} GICDICFGRBits_t;
+
+typedef enum
+{
+    gicigroupr_G0S = 0,
+    gicigroupr_G1NS = (1 << 0),
+    gicigroupr_G1S = (1 << 2)
+} GICIGROUPRBits_t;
+
+typedef enum
+{
+    gicrwaker_ProcessorSleep = (1 << 1),
+    gicrwaker_ChildrenAsleep = (1 << 2)
+} GICRWAKERBits_t;
+
+/**********************************************************************/
+
+/*
+ * Utility macros & functions
+ */
+#define RANGE_LIMIT(x)		((sizeof(x) / sizeof((x)[0])) - 1)
+
+static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
+					 uint32_t aff1, uint32_t aff0)
+{
+    /*
+     * only need to cast aff3 to get type promotion for all affinities
+     */
+    return ((((uint64_t)aff3 & 0xff) << 32) |
+	    ((aff2 & 0xff) << 16) |
+	    ((aff1 & 0xff) << 8) | aff0);
+}
+
+/**********************************************************************/
+
+/*
+ * GIC Distributor Function Prototypes
+ */
+
+/*
+ * ConfigGICD - configure GIC Distributor prior to enabling it
+ *
+ * Inputs:
+ *
+ *  control - control flags
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void ConfigGICD(GICDCTLRFlags_t flags);
+
+/*
+ * EnableGICD - top-level enable for GIC Distributor
+ *
+ * Inputs:
+ *
+ *  flags - new control flags to set
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void EnableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * DisableGICD - top-level disable for GIC Distributor
+ *
+ * Inputs
+ *
+ *  flags - control flags to clear
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void DisableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * SyncAREinGICD - synchronise GICD Address Routing Enable bits
+ *
+ * Inputs
+ *
+ *  flags - absolute flag bits to set in GIC Distributor
+ *
+ *  dosync - flag whether to wait for ARE bits to match passed
+ *      flag field (dosync = true), or whether to set absolute
+ *      flag bits (dosync = false)
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ * This function is used to resolve a race in an MP system whereby secondary
+ * CPUs cannot reliably program all Redistributor registers until the
+ * primary CPU has enabled Address Routing. The primary CPU will call this
+ * function with dosync = false, while the secondaries will call it with
+ * dosync = true.
+ */
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
+
+/*
+ * EnableSPI - enable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnableSPI(uint32_t id);
+
+/*
+ * DisableSPI - disable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisableSPI(uint32_t id);
+
+/*
+ * SetSPIPriority - configure the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetSPIPriority(uint32_t id, uint32_t priority);
+
+/*
+ * GetSPIPriority - determine the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  interrupt priority in the range 0 - 0xff
+ */
+uint32_t GetSPIPriority(uint32_t id);
+
+/*
+ * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  affinity - prepacked "dotted quad" affinity routing. NOTE: use the
+ *      gicv3PackAffinity() helper routine to generate this input
+ *
+ *  mode - select routing mode (specific affinity, or any recipient)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
+
+/*
+ * GetSPIRoute - read ARE-enabled interrupt routing information
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  routing configuration
+ */
+uint64_t GetSPIRoute(uint32_t id);
+
+/*
+ * SetSPITarget - configure the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ *  target - 8-bit target bitmap
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPITarget(uint32_t id, uint32_t target);
+
+/*
+ * GetSPITarget - read the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *  8-bit target bitmap
+ */
+uint32_t GetSPITarget(uint32_t id);
+
+/*
+ * ConfigureSPI - setup an interrupt as edge- or level-triggered
+ *
+ * Inputs
+ *
+ *   id - interrupt identifier
+ *
+ *   config - desired configuration
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
+
+/*
+ * SetSPIPending - mark an interrupt as pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetSPIPending(uint32_t id);
+
+/*
+ * ClearSPIPending - mark an interrupt as not pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearSPIPending(uint32_t id);
+
+/*
+ * GetSPIPending - query whether an interrupt is pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetSPIPending(uint32_t id);
+
+/*
+ * SetSPISecurity - mark a shared peripheral interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityBlock - mark a block of 32 shared peripheral
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  block - which block to mark (e.g. 1 = Ints 32-63)
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityAll - mark all shared peripheral interrupts
+ *     as security <group>
+ *
+ * Inputs:
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityAll(GICIGROUPRBits_t group);
+
+/**********************************************************************/
+
+/*
+ * GIC Re-Distributor Function Prototypes
+ *
+ * The model for calling Redistributor functions is that, rather than
+ * identifying the target redistributor with every function call, the
+ * SelectRedistributor() function is used to identify which redistributor
+ * is to be used for all functions until a different redistributor is
+ * explicitly selected
+ */
+
+/*
+ * WakeupGICR - wake up a Redistributor
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to wakeup
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void WakeupGICR(uint32_t gicr);
+
+/*
+ * EnablePrivateInt - enable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * DisablePrivateInt - disable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
+
+/*
+ * GetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *   Int priority
+ */
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
+
+#endif /* ndef GICV3_h */
+
+/* EOF GICv3.h */
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h
new file mode 100644
index 00000000..bc2da074
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h
@@ -0,0 +1,249 @@
+/*
+ * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your
+ * possession of a valid DS-5 end user licence agreement and your compliance
+ * with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_gicc_h
+#define GICV3_gicc_h
+
+/**********************************************************************/
+
+typedef enum
+{
+    sreSRE = (1 << 0),
+    sreDFB = (1 << 1),
+    sreDIB = (1 << 2),
+    sreEnable = (1 << 3)
+} ICC_SREBits_t;
+
+static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL2(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL2\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
+{
+    asm("msr  ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_SRE_EL3\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    igrpEnable = (1 << 0),
+    igrpEnableGrp1NS = (1 << 0),
+    igrpEnableGrp1S = (1 << 2)
+} ICC_IGRPBits_t;
+
+static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
+{
+    asm("msr  ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    ctlrCBPR = (1 << 0),
+    ctlrCBPR_EL1S = (1 << 0),
+    ctlrEOImode = (1 << 1),
+    ctlrCBPR_EL1NS = (1 << 1),
+    ctlrEOImode_EL3 = (1 << 2),
+    ctlrEOImode_EL1S = (1 << 3),
+    ctlrEOImode_EL1NS = (1 << 4),
+    ctlrRM = (1 << 5),
+    ctlrPMHE = (1 << 6)
+} ICC_CTLRBits_t;
+
+static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
+{
+    asm("msr  ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_CTLR_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
+{
+    asm("msr  ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_CTLR_EL3\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+static inline uint64_t getICC_IAR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_IAR0_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_IAR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_IAR1_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_EOIR0(uint32_t interrupt)
+{
+    asm("msr  ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_EOIR1(uint32_t interrupt)
+{
+    asm("msr  ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_DIR(uint32_t interrupt)
+{
+    asm("msr  ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_PMR(uint32_t priority)
+{
+    asm("msr  ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority));
+}
+
+static inline void setICC_BPR0(uint32_t binarypoint)
+{
+    asm("msr  ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline void setICC_BPR1(uint32_t binarypoint)
+{
+    asm("msr  ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline uint64_t getICC_BPR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_BPR0_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_BPR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_BPR1_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_RPR(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, ICC_RPR_EL1\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    sgirIRMTarget = 0,
+    sgirIRMAll = (1ull << 40)
+} ICC_SGIRBits_t;
+
+static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits));
+}
+
+#endif /* ndef GICV3_gicc_h */
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c
new file mode 100644
index 00000000..e176b206
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c
@@ -0,0 +1,339 @@
+/*
+ * GICv3_gicd.c - generic driver code for GICv3 distributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your
+ * possession of a valid DS-5 end user licence agreement and your compliance
+ * with all applicable terms and conditions of such licence agreement.
+ */
+#include <stdint.h>
+
+#include "GICv3.h"
+
+typedef struct
+{
+        volatile uint32_t GICD_CTLR;              // +0x0000
+  const volatile uint32_t GICD_TYPER;             // +0x0004
+  const volatile uint32_t GICD_IIDR;              // +0x0008
+
+  const volatile uint32_t padding0;               // +0x000c
+
+        volatile uint32_t GICD_STATUSR;           // +0x0010
+
+  const volatile uint32_t padding1[3];            // +0x0014
+
+        volatile uint32_t IMP_DEF[8];             // +0x0020
+
+        volatile uint32_t GICD_SETSPI_NSR;        // +0x0040
+  const volatile uint32_t padding2;               // +0x0044
+        volatile uint32_t GICD_CLRSPI_NSR;        // +0x0048
+  const volatile uint32_t padding3;               // +0x004c
+        volatile uint32_t GICD_SETSPI_SR;         // +0x0050
+  const volatile uint32_t padding4;               // +0x0054
+        volatile uint32_t GICD_CLRSPI_SR;         // +0x0058
+
+  const volatile uint32_t padding5[3];            // +0x005c
+
+        volatile uint32_t GICD_SEIR;              // +0x0068
+
+  const volatile uint32_t padding6[5];            // +0x006c
+
+        volatile uint32_t GICD_IGROUPR[32];       // +0x0080
+
+        volatile uint32_t GICD_ISENABLER[32];     // +0x0100
+        volatile uint32_t GICD_ICENABLER[32];     // +0x0180
+        volatile uint32_t GICD_ISPENDR[32];       // +0x0200
+        volatile uint32_t GICD_ICPENDR[32];       // +0x0280
+        volatile uint32_t GICD_ISACTIVER[32];     // +0x0300
+        volatile uint32_t GICD_ICACTIVER[32];     // +0x0380
+
+        volatile uint8_t  GICD_IPRIORITYR[1024];  // +0x0400
+        volatile uint8_t  GICD_ITARGETSR[1024];   // +0x0800
+        volatile uint32_t GICD_ICFGR[64];         // +0x0c00
+        volatile uint32_t GICD_IGRPMODR[32];      // +0x0d00
+  const volatile uint32_t padding7[32];           // +0x0d80
+        volatile uint32_t GICD_NSACR[64];         // +0x0e00
+
+        volatile uint32_t GICD_SGIR;              // +0x0f00
+
+  const volatile uint32_t padding8[3];            // +0x0f04
+
+        volatile uint32_t GICD_CPENDSGIR[4];      // +0x0f10
+        volatile uint32_t GICD_SPENDSGIR[4];      // +0x0f20
+
+  const volatile uint32_t padding9[52];           // +0x0f30
+  const volatile uint32_t padding10[5120];        // +0x1000
+
+        volatile uint64_t GICD_IROUTER[1024];     // +0x6000
+} GICv3_distributor;
+
+/*
+ * use the scatter file to place GICD
+ */
+static GICv3_distributor __attribute__((section(".bss.distributor"))) gicd;
+
+void ConfigGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR = flags;
+}
+
+void EnableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR |= flags;
+}
+
+void DisableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR &= ~flags;
+}
+
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
+{
+    if (dosync)
+    {
+	const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
+	const uint32_t tval = flags & tmask;
+
+	while ((gicd.GICD_CTLR & tmask) != tval)
+	    continue;
+    }
+    else
+	gicd.GICD_CTLR = flags;
+}
+
+void EnableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ISENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void DisableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ICENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void SetSPIPriority(uint32_t id, uint32_t priority)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    gicd.GICD_IPRIORITYR[bank] = priority;
+}
+
+uint32_t GetSPIPriority(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
+}
+
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
+}
+
+uint64_t GetSPIRoute(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    return gicd.GICD_IROUTER[bank];
+}
+
+void SetSPITarget(uint32_t id, uint32_t target)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    gicd.GICD_ITARGETSR[bank] = target;
+}
+
+uint32_t GetSPITarget(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    /*
+     * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
+     * target bitmap per register
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
+}
+
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
+{
+    uint32_t bank, tmp;
+
+    /*
+     * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
+     * configuration per register
+     */
+    bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
+    config &= 3;
+
+    id = (id & 0xf) << 1;
+
+    tmp = gicd.GICD_ICFGR[bank];
+    tmp &= ~(3 << id);
+    tmp |= config << id;
+    gicd.GICD_ICFGR[bank] = tmp;
+}
+
+void SetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ISPENDR[bank] = 1 << id;
+}
+
+void ClearSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ICPENDR[bank] = 1 << id;
+}
+
+uint32_t GetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    return (gicd.GICD_ICPENDR[bank] >> id) & 1;
+}
+
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
+{
+    uint32_t bank, groupmod;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicd.GICD_IGROUPR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGROUPR[bank] &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicd.GICD_IGRPMODR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
+}
+
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
+{
+    uint32_t groupmod;
+    const uint32_t nbits = (sizeof group * 8) - 1;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
+
+    /*
+     * get each bit of group config duplicated over all 32-bits in a word
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicd.GICD_IGROUPR[block] = group;
+    gicd.GICD_IGRPMODR[block] = groupmod;
+}
+
+void SetSPISecurityAll(GICIGROUPRBits_t group)
+{
+    uint32_t block;
+
+    /*
+     * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
+     * want to iterate over all blocks excluding 0 (which are the
+     * SGI/PPI interrupts, and not relevant here)
+     */
+    for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
+	SetSPISecurityBlock(block, group);
+}
+
+/* EOF GICv3_gicd.c */
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c
new file mode 100644
index 00000000..59ed616a
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c
@@ -0,0 +1,279 @@
+/*
+ * GICv3_gicr.c - generic driver code for GICv3 redistributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your
+ * possession of a valid DS-5 end user licence agreement and your compliance
+ * with all applicable terms and conditions of such licence agreement.
+ */
+#include "GICv3.h"
+
+/*
+ * physical LPI Redistributor register map
+ */
+typedef struct
+{
+        volatile uint32_t GICR_CTLR;             // +0x0000 - RW - Redistributor Control Register
+  const volatile uint32_t GICR_IIDR;             // +0x0004 - RO - Implementer Identification Register
+  const volatile uint32_t GICR_TYPER[2];         // +0x0008 - RO - Redistributor Type Register
+        volatile uint32_t GICR_STATUSR;          // +0x0010 - RW - Error Reporting Status Register, optional
+        volatile uint32_t GICR_WAKER;            // +0x0014 - RW - Redistributor Wake Register
+  const volatile uint32_t padding1[2];           // +0x0018 - RESERVED
+        volatile uint32_t IMPDEF1   ;            // +0x0020 - ?? - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding2[7];           // +0x0024 - RESERVED
+        volatile uint64_t GICR_SETLPIR;          // +0x0040 - WO - Set LPI Pending Register
+        volatile uint64_t GICR_CLRLPIR;          // +0x0048 - WO - Clear LPI Pending Register
+  const volatile uint32_t padding3[8];           // +0x0050 - RESERVED
+        volatile uint64_t GICR_PROPBASER;        // +0x0070 - RW - Redistributor Properties Base Address Register
+        volatile uint64_t GICR_PENDBASER;        // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
+  const volatile uint32_t padding4[8];           // +0x0080 - RESERVED
+        volatile uint64_t GICR_INVLPIR;          // +0x00A0 - WO - Redistributor Invalidate LPI Register
+  const volatile uint32_t padding5[2];           // +0x00A8 - RESERVED
+        volatile uint64_t GICR_INVALLR;          // +0x00B0 - WO - Redistributor Invalidate All Register
+  const volatile uint32_t padding6[2];           // +0x00B8 - RESERVED
+        volatile uint64_t GICR_SYNCR;            // +0x00C0 - RO - Redistributor Synchronize Register
+  const volatile uint32_t padding7[2];           // +0x00C8 - RESERVED
+  const volatile uint32_t padding8[12];          // +0x00D0 - RESERVED
+        volatile uint64_t IMPDEF2;               // +0x0100 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding9[2];           // +0x0108 - RESERVED
+        volatile uint64_t IMPDEF3;               // +0x0110 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding10[2];          // +0x0118 - RESERVED
+} GICv3_redistributor_RD;
+
+/*
+ * SGI and PPI Redistributor register map
+ */
+typedef struct
+{
+  const volatile uint32_t padding1[32];          // +0x0000 - RESERVED
+        volatile uint32_t GICR_IGROUPR0;         // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
+  const volatile uint32_t padding2[31];          // +0x0084 - RESERVED
+        volatile uint32_t GICR_ISENABLER;        // +0x0100 - RW - Interrupt Set-Enable Registers
+  const volatile uint32_t padding3[31];          // +0x0104 - RESERVED
+        volatile uint32_t GICR_ICENABLER;        // +0x0180 - RW - Interrupt Clear-Enable Registers
+  const volatile uint32_t padding4[31];          // +0x0184 - RESERVED
+        volatile uint32_t GICR_ISPENDR;          // +0x0200 - RW - Interrupt Set-Pending Registers
+  const volatile uint32_t padding5[31];          // +0x0204 - RESERVED
+        volatile uint32_t GICR_ICPENDR;          // +0x0280 - RW - Interrupt Clear-Pending Registers
+  const volatile uint32_t padding6[31];          // +0x0284 - RESERVED
+        volatile uint32_t GICR_ISACTIVER;        // +0x0300 - RW - Interrupt Set-Active Register
+  const volatile uint32_t padding7[31];          // +0x0304 - RESERVED
+        volatile uint32_t GICR_ICACTIVER;        // +0x0380 - RW - Interrupt Clear-Active Register
+  const volatile uint32_t padding8[31];          // +0x0184 - RESERVED
+        volatile uint8_t  GICR_IPRIORITYR[32];   // +0x0400 - RW - Interrupt Priority Registers
+  const volatile uint32_t padding9[504];         // +0x0420 - RESERVED
+        volatile uint32_t GICR_ICnoFGR[2];       // +0x0C00 - RW - Interrupt Configuration Registers
+  const volatile uint32_t padding10[62];	 // +0x0C08 - RESERVED
+        volatile uint32_t GICR_IGRPMODR0;        // +0x0D00 - RW - ????
+  const volatile uint32_t padding11[63];	 // +0x0D04 - RESERVED
+        volatile uint32_t GICR_NSACR;            // +0x0E00 - RW - Non-Secure Access Control Register
+} GICv3_redistributor_SGI;
+
+/*
+ * We have a multiplicity of GIC Redistributors; on the GIC-AEM and
+ * GIC-500 they are arranged as one 128KB region per redistributor: one
+ * 64KB page of GICR LPI registers, and one 64KB page of GICR Private
+ * Int registers
+ */
+typedef struct
+{
+    union
+    {
+	GICv3_redistributor_RD RD_base;
+	uint8_t padding[64 * 1024];
+    } RDblock;
+
+    union
+    {
+	GICv3_redistributor_SGI SGI_base;
+	uint8_t padding[64 * 1024];
+    } SGIblock;
+} GICv3_GICR;
+
+/*
+ * use the scatter file to place GIC Redistributor base address
+ *
+ * although this code doesn't know how many Redistributor banks
+ * a particular system will have, we declare gicrbase as an array
+ * to avoid unwanted compiler optimisations when calculating the
+ * base of a particular Redistributor bank
+ */
+static const GICv3_GICR gicrbase[2] __attribute__((section (".bss.redistributor")));
+
+/**********************************************************************/
+
+/*
+ * utility functions to calculate base of a particular
+ * Redistributor bank
+ */
+
+static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
+{
+    GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
+
+    return &((arraybase + gicr)->RDblock.RD_base);
+}
+
+static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
+{
+    GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
+
+    return &(arraybase[gicr].SGIblock.SGI_base);
+}
+
+/**********************************************************************/
+
+void WakeupGICR(uint32_t gicr)
+{
+    GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
+
+    /*
+     * step 1 - ensure GICR_WAKER.ProcessorSleep is off
+     */
+    gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
+
+    /*
+     * step 2 - wait for children asleep to be cleared
+     */
+    while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
+	continue;
+
+    /*
+     * OK, GICR is go
+     */
+    return;
+}
+
+void EnablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISENABLER = 1 << id;
+}
+
+void DisablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICENABLER = 1 << id;
+}
+
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    gicrSGI->GICR_IPRIORITYR[id] = priority;
+}
+
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
+}
+
+void SetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISPENDR = 1 << id;
+}
+
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ICPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICPENDR = 1 << id;
+}
+
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
+}
+
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    uint32_t groupmod;
+
+    /*
+     * GICR_IGROUPR0 is one 32-bit register
+     */
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicrSGI->GICR_IGROUPR0 |= 1 << id;
+    else
+	gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicrSGI->GICR_IGRPMODR0 |= 1 << id;
+    else
+	gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
+}
+
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    const uint32_t nbits = (sizeof group * 8) - 1;
+    uint32_t groupmod;
+
+    /*
+     * get each bit of group config duplicated over all 32-bits
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicrSGI->GICR_IGROUPR0 = group;
+    gicrSGI->GICR_IGRPMODR0 = groupmod;
+}
+
+/* EOF GICv3_gicr.c */
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S
new file mode 100644
index 00000000..d5dfd898
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S
@@ -0,0 +1,86 @@
+//
+// Armv8-A AArch64 - Basic Mutex Example
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global _mutex_initialize
+    .global _mutex_acquire
+    .global _mutex_release
+
+//
+// These routines implement the mutex management functions required for running
+// the Arm C library in a multi-threaded environment.
+//
+// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
+//
+// **********************************************************************
+//
+
+    .type _mutex_initialize, "function"
+    .cfi_startproc
+_mutex_initialize:
+
+    //
+    // mark the mutex as unlocked
+    //
+    mov     w1, #0
+    str     w1, [x0]
+
+    //
+    // we are running multi-threaded, so set a non-zero return
+    // value (function prototype says use 1)
+    //
+    mov     w0, #1
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+
+    //
+    // send ourselves an event, so we don't stick on the wfe at the
+    // top of the loop
+    //
+    sevl
+
+    //
+    // wait until the mutex is available
+    //
+loop:
+    wfe
+    ldaxr   w1, [x0]
+    cbnz    w1, loop
+
+    //
+    // mutex is (at least, it was) available - try to claim it
+    //
+    mov     w1, #1
+    stxr    w2, w1, [x0]
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+
+    mov     w1, #0
+    stlr    w1, [x0]
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h
new file mode 100644
index 00000000..da19e9b1
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h
@@ -0,0 +1,66 @@
+//
+// Private Peripheral Map for the v8 Architecture Envelope Model
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef PPM_AEM_H
+#define PPM_AEM_H
+
+//
+// Distributor layout
+//
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+//
+// CPU Interface layout
+//
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+
+#endif // PPM_AEM_H
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
new file mode 100644
index 00000000..c7296646
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
@@ -0,0 +1,149 @@
+/* Small demonstration of the ThreadX module manager.  */
+
+#include "tx_api.h"
+#include "txm_module.h"
+#include <stddef.h>
+
+
+/* Define the ThreadX module manager thread and stack...  */
+
+TX_THREAD               module_manager;
+#define MODULE_MANAGER_STACK_SIZE (1024 * 4)
+ALIGN_TYPE              module_manager_stack[MODULE_MANAGER_STACK_SIZE / sizeof(ALIGN_TYPE)];
+
+
+/* Define the module instance object  */
+
+TXM_MODULE_INSTANCE     my_module;
+
+
+/* The module code should be loaded here.  */
+
+#define MODULE_CODE (0x80180000)
+
+
+/* Define the object pool area.  */
+
+UCHAR                   object_memory[1024 * 16];
+
+
+/* Define the module data pool area.  */
+
+#define MODULE_DATA_SIZE (1024 * 32)
+ALIGN_TYPE MODULE_DATA [MODULE_DATA_SIZE / sizeof(ALIGN_TYPE)];
+
+
+/* Define the count of memory faults.  */
+
+ULONG                   memory_faults = 0;
+
+
+/* Define thread prototypes.  */
+
+void    module_manager_entry(ULONG thread_input);
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+UCHAR   event_buffer[65536];
+
+#endif
+
+
+/* Define main entry point.  */
+
+int main(void)
+{
+
+    /* Initialize timer for ThreadX.  */
+    extern void init_timer(void);    /* in timer_interrupts.c  */
+    init_timer();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+
+    /* The functions doesn't really return*/
+    return 0;
+}
+
+ULONG simple_thread_counter = 0;
+TX_THREAD simple_thread;
+#define SIMPLE_THREAD_STACK_SIZE (1024 * 4)
+ALIGN_TYPE simple_thread_stack[SIMPLE_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)];
+void simple_thread_entry(ULONG thread_input)
+{
+    while(1)
+    {
+        simple_thread_counter++;
+        tx_thread_sleep(2);
+    }
+}
+
+/* Define what the initial system looks like.  */
+
+void tx_application_define(void *first_unused_memory)
+{
+    tx_thread_create(
+            &module_manager,
+            "Module Manager Thread",
+            module_manager_entry, 0,
+            module_manager_stack, MODULE_MANAGER_STACK_SIZE,
+            1, 1,
+            TX_NO_TIME_SLICE,
+            TX_AUTO_START);
+
+    tx_thread_create(
+            &simple_thread,
+            "Simple Thread",
+            simple_thread_entry, 0,
+            simple_thread_stack, SIMPLE_THREAD_STACK_SIZE,
+            1, 1,
+            TX_NO_TIME_SLICE,
+            TX_AUTO_START);
+}
+
+
+/* Define the test threads.  */
+
+void module_manager_entry(ULONG thread_input)
+{
+
+    /* Initialize the module manager.   */
+    txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE);
+
+    txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
+
+    /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download.  */
+    txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
+    
+    /* Start the module.  */
+    txm_module_manager_start(&my_module);
+
+    /* Sleep for a while....  */
+    {
+        int i;
+        for (i = 0; i < 10; i++)
+        {
+            tx_thread_sleep(10);
+        }
+    }
+    
+    /* Stop the module.  */
+    txm_module_manager_stop(&my_module);
+    
+    /* Unload the module.  */
+    txm_module_manager_unload(&my_module);
+
+    /* Load the module again.  */
+    txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
+
+    /* Start the module again.  */
+    txm_module_manager_start(&my_module);
+    
+    /* Now just spin...  */
+    while(1)
+    {
+    
+        tx_thread_sleep(10);
+    }
+}
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
new file mode 100644
index 00000000..dba4c8c8
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
@@ -0,0 +1,513 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+    <listAttribute key="1685211613816507265.viewid=2">
+        <listEntry value="thread_info"/>
+        <listEntry value="thread_ptr"/>
+        <listEntry value="shell_function"/>
+        <listEntry value="thread_entry_info"/>
+        <listEntry value="module_instance"/>
+        <listEntry value="module_preamble"/>
+        <listEntry value="return_value"/>
+        <listEntry value="status"/>
+        <listEntry value="_entry_param_thread_ptr"/>
+        <listEntry value="data_allocation_size"/>
+        <listEntry value="_txm_module_manager_byte_pool"/>
+        <listEntry value="pool_ptr"/>
+        <listEntry value="&amp;_txm_module_manager_byte_pool"/>
+        <listEntry value="(void*)(_txm_module_manager_byte_pool.tx_byte_pool_start)"/>
+        <listEntry value="(void*)(_txm_module_manager_byte_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size)"/>
+        <listEntry value="_tx_timer_thread"/>
+        <listEntry value="byte_pool_ptr"/>
+        <listEntry value="object_ptr"/>
+        <listEntry value="module_instance -&gt; txm_module_instance_data_start"/>
+        <listEntry value="module_instance -&gt; txm_module_instance_data_end"/>
+        <listEntry value="code_alignment"/>
+    </listAttribute>
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+    <listAttribute key="2016305617678564833.viewid=3">
+        <listEntry value="thread_0"/>
+        <listEntry value="thread_1"/>
+        <listEntry value="thread_2"/>
+        <listEntry value="byte_pool_0"/>
+        <listEntry value="block_pool_0"/>
+        <listEntry value="queue_0_sends"/>
+        <listEntry value="semaphore_0_puts"/>
+        <listEntry value="thread_ptr"/>
+        <listEntry value="module_instance"/>
+        <listEntry value="thread_info -&gt; txm_module_thread_entry_info_start_thread"/>
+        <listEntry value="_txm_module_manager_object_pool"/>
+        <listEntry value="code_size"/>
+    </listAttribute>
+    <mapAttribute key="2016305617678564833.viewid=3.ExpressionsData">
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+        <listEntry value="(my_module).txm_module_instance_start_stop_thread"/>
+    </listAttribute>
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+        <listEntry value="shell_function"/>
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+        <listEntry value="available_cores"/>
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+    </listAttribute>
+    <stringAttribute key="debugger.view.ModulesView:DebugOutlineColumnState" value="OutlineConfig1&#9;5&#9;0&#9;true&#9;true&#9;53&#9;-1&#9;true&#9;1&#9;true&#9;true&#9;66&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;63&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;45&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;67&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.NewRegisterView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;117&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;175&#9;-1&#9;true&#9;3&#9;false&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;false&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;false&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.NewRegisterView:_selectedRegisterSet" value="All registers"/>
+    <mapAttribute key="debugger.view.NewRegisterView_registerSets"/>
+    <stringAttribute key="debugger.view.StackView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;149&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;159&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;75&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;240&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <listAttribute key="debugger.view.TraceView:TRACE_EXPORT_FILTERS"/>
+    <stringAttribute key="debugger.view.VariableTreeView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;197&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;137&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;54&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;84&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <booleanAttribute key="debugger.view.expression.DrawAsHex" value="false"/>
+    <booleanAttribute key="debugger.view.register.DrawAsHex" value="false"/>
+    <stringAttribute key="debugger.view.symbols.FunctionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;53&#9;1&#9;true&#9;1&#9;false&#9;true&#9;103&#9;-1&#9;true&#9;2&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;90&#9;0&#9;true&#9;4&#9;true&#9;true&#9;86&#9;-1&#9;true&#9;5&#9;false&#9;true&#9;41&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;112&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;54&#9;-1&#9;true"/>
+    <booleanAttribute key="debugger.view.variable.DrawAsHex" value="false"/>
+    <stringAttribute key="dtsl_config" value="DtslScript"/>
+    <stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
+    <stringAttribute key="dtsl_options_file" value="default"/>
+    <stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
+    <stringAttribute key="launch_configuration_version" value="2020.0"/>
+    <booleanAttribute key="linuxOS" value="false"/>
+    <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
+    <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
+    <booleanAttribute key="runAfterConnect" value="false"/>
+    <mapAttribute key="scripts_view_script_links">
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.ds" value=""/>
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager_debug.ds" value=""/>
+    </mapAttribute>
+    <listAttribute key="setup">
+        <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
+        <listEntry value="FVP_Base_Cortex-A35x4"/>
+    </listAttribute>
+    <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
+    <stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
+</launchConfiguration>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat
new file mode 100644
index 00000000..1288a328
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat
@@ -0,0 +1,262 @@
+;********************************************************
+; Scatter file for Armv8-A Startup code on FVP Base model
+; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+; Use, modification and redistribution of this file is subject to your
+; possession of a valid DS-5 end user licence agreement and your compliance
+; with all applicable terms and conditions of such licence agreement.
+;********************************************************
+
+LOAD 0x80000000
+{
+    EXEC +0
+    {
+        startup.o (StartUp, +FIRST)
+        * (+RO, +RW, +ZI)
+        
+    }
+    ;XTABLES +0 ALIGN 0x1000
+    ;{
+    ;   xtables.o (*) 
+    ;}
+    
+    SYS_STACK +0 ALIGN 8 EMPTY 0x1000
+    {
+    }
+
+    ;
+    ; Separate heap - import symbol __use_two_region_memory
+    ; in source code for this to work correctly
+    ;
+    ARM_LIB_HEAP     +0 ALIGN 64 EMPTY 0xA0000 {}
+
+    ;
+    ; App stacks for all CPUs
+    ; All stacks and heap are aligned to a cache-line boundary
+    ;
+    ARM_LIB_STACK    +0 ALIGN 64 EMPTY 4 * 0x4000 {}
+    
+    ;
+    ; Handler stacks for all CPUs
+    ; All stacks and heap are aligned to a cache-line boundary
+    ;
+    HANDLER_STACK    +0 ALIGN 64 EMPTY 4 * 0x4000 {}
+    
+    ;
+    ; Stacks for EL3
+    ;
+    EL3_STACKS       +0 ALIGN 64 EMPTY 4 * 0x1000 {}
+    ;
+    ; Strictly speaking, the L1 tables don't need to
+    ; be so strongly aligned, but no matter
+    ;
+    TTB0_L1          +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    ;
+    ; Various sets of L2 tables
+    ;
+    ; Alignment is 4KB, since the code uses a 4K page
+    ; granularity - larger granularities would require
+    ; correspondingly stricter alignment
+    ;
+    TTB0_L2_RAM      +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    TTB0_L2_PRIVATE  +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    TTB0_L2_PERIPH   +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    ;
+    ; The startup code uses the end of this region to calculate
+    ; the top of memory - don't place any RAM regions after it
+    ;
+    TOP_OF_RAM  +0 EMPTY 4 {}
+
+    ;
+    ; CS3 Peripherals is a 64MB region from 0x1c000000
+    ; that includes the following:
+    ; System Registers             at 0x1C010000
+    ; UART0 (PL011)                at 0x1C090000
+    ; Color LCD Controller (PL111) at 0x1C1F0000
+    ; plus a number of others.
+    ; CS3_PERIPHERALS is used by the startup code for page-table generation
+    ; This region is not truly empty, but we have no
+    ; predefined objects that live within it
+    ;
+    CS3_PERIPHERALS  0x1c000000 EMPTY 0x90000 {}
+
+    ;
+    ; Place the UART peripheral registers data structure
+    ; This is only really needed if USE_SERIAL_PORT is defined, but
+    ; the linker will remove unused sections if not needed
+;    PL011  0x1c090000 UNINIT 0x1000
+;    {
+;        uart.o (+ZI)
+;    }
+    ; Note that some other CS3_PERIPHERALS follow this
+
+    ;
+    ; GICv3 distributor
+    ;
+    GICD  0x2f000000 UNINIT 0x8000
+    {
+        GICv3_gicd.o (.bss.distributor)
+    }
+
+    ;
+    ; GICv3 redistributors
+    ; 128KB for each redistributor in the system
+    ;
+    GICR  0x2f100000 UNINIT 0x80000
+    {
+        GICv3_gicr.o (.bss.redistributor)
+    }
+}
+
+
+
+
+
+; Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+;
+; Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without specific
+; prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+
+;RO AlignExpr(0x80000000, 0x1000)
+;{
+;    C_SYNCH_SP0 +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_synch_sp0)
+;    }
+;    C_IRQ_SP0 +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_irq_sp0)
+;    }
+;    C_FIQ_SP0 +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_fiq_sp0)
+;    }
+;    C_SERROR_SP0 +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_serror_sp0)
+;    }
+;
+;    C_SYNCH_SPX +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_synch_spx)
+;    }
+;    C_IRQ_SPX +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_irq_spx)
+;    }
+;    C_FIQ_SPX +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_fiq_spx)
+;    }
+;    C_SERROR_SPX +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_serror_spx)
+;    }
+;
+;    L64_SYNCH +0 ALIGN 0x80
+;    {
+;        vectors.o (_l64_synch)
+;    }
+;    L64_IRQ +0 ALIGN 0x80
+;    {
+;        vectors.o (_l64_irq)
+;    }
+;    L64_FIQ +0 ALIGN 0x80
+;    {
+;        vectors.o (_l64_fiq)
+;    }
+;    L64_SERROR +0 ALIGN 0x80
+;    {
+;        vectors.o (_l64_serror)
+;    }
+;
+;    L32_SYNCH +0 ALIGN 0x80
+;    {
+;        vectors.o (_l32_synch)
+;    }
+;    L32_IRQ +0 ALIGN 0x80
+;    {
+;        vectors.o (_l32_irq)
+;    }
+;    L32_FIQ +0 ALIGN 0x80
+;    {
+;        vectors.o (_l32_fiq)
+;    }
+;    L32_SERROR +0 ALIGN 0x80
+;    {
+;        vectors.o (_l32_serror)
+;    }
+;
+;    ROSEC +0 ALIGN 8
+;    {
+;        *( +RO )
+;    }
+;    
+;    XTABLES +0 ALIGN 0x1000
+;    {
+;        xtables.o (*) 
+;    }
+;}
+;
+;RW AlignExpr(ImageLimit(XTABLES), 0x1000)
+;{   
+;    RWSEC +0
+;    {
+;        *( +RW )
+;    }
+;    
+;    ZISEC +0
+;    {
+;        *( +ZI )
+;    }
+;    
+;    SYS_STACK +0 ALIGN 8 EMPTY 0x1000
+;    {
+;    }
+;    
+;    ; 512 MiB heap
+;    HEAP +0 ALIGN 8 EMPTY 0x10000000
+;    {
+;    }
+;    
+;    ; Free Memory section
+;    FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000
+;    {
+;    }
+;
+;    ; Per-CPU 128 MiB task stacks
+;    TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000)
+;    {
+;    }
+;    
+;    ; Per-CPU 128 MiB handler stacks
+;    HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000)
+;    {
+;    }
+;}
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sp804_timer.c
new file mode 100644
index 00000000..4a454f16
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sp804_timer.c
@@ -0,0 +1,122 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "sp804_timer.h"
+
+#define TIMER_SP804_CTRL_TIMEREN     (1 << 7)
+#define TIMER_SP804_CTRL_TIMERMODE   (1 << 6)        // Bit 6:
+#define TIMER_SP804_CTRL_INTENABLE   (1 << 5)
+#define TIMER_SP804_CTRL_TIMERSIZE   (1 << 1)        // Bit 1: 0=16-bit, 1=32-bit
+#define TIMER_SP804_CTRL_ONESHOT     (1 << 0)        // Bit 0: 0=wrapping, 1=one-shot
+
+#define TIMER_SP804_CTRL_PRESCALE_1  (0 << 2)        // clk/1
+#define TIMER_SP804_CTRL_PRESCALE_4  (1 << 2)        // clk/4
+#define TIMER_SP804_CTRL_PRESCALE_8  (2 << 2)        // clk/8
+
+struct sp804_timer
+{
+        volatile uint32_t Time1Load;     // +0x00
+  const volatile uint32_t Time1Value;    // +0x04 - RO
+        volatile uint32_t Timer1Control; // +0x08
+        volatile uint32_t Timer1IntClr;  // +0x0C - WO
+  const volatile uint32_t Timer1RIS;     // +0x10 - RO
+  const volatile uint32_t Timer1MIS;     // +0x14 - RO
+        volatile uint32_t Timer1BGLoad;  // +0x18
+
+        volatile uint32_t Time2Load;     // +0x20
+        volatile uint32_t Time2Value;    // +0x24
+        volatile uint8_t  Timer2Control; // +0x28
+        volatile uint32_t Timer2IntClr;  // +0x2C - WO
+  const volatile uint32_t Timer2RIS;     // +0x30 - RO
+  const volatile uint32_t Timer2MIS;     // +0x34 - RO
+        volatile uint32_t Timer2BGLoad;  // +0x38
+
+  // Not including ID registers
+
+};
+
+// Instance of the dual timer, will be placed using the scatter file
+struct sp804_timer* dual_timer;
+
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address)
+{
+  dual_timer = (struct sp804_timer*)address;
+  return;
+}
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
+{
+  uint32_t tmp = 0;
+
+  dual_timer->Time1Load = load_value;
+
+  // Fixed setting: 32-bit, no prescaling
+  tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
+
+  // Settings from parameters: interrupt generation & reload
+  tmp = tmp | interrupt | auto_reload;
+
+  // Write control register
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Starts the timer
+void startTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp | TIMER_SP804_CTRL_TIMEREN;      // Set TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Stops the timer
+void stopTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN;     // Clear TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void)
+{
+  return dual_timer->Time1Value;
+}
+
+
+void clearTimerIrq(void)
+{
+  // A write to this register, of any value, clears the interrupt
+  dual_timer->Timer1IntClr = 1;
+}
+
+
+// ------------------------------------------------------------
+// End of sp804_timer.c
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sp804_timer.h
new file mode 100644
index 00000000..d4c6d9e2
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sp804_timer.h
@@ -0,0 +1,53 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+// Header Filer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#ifndef _SP804_TIMER_
+#define _SP804_TIMER_
+
+#include <stdint.h>
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address);
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+
+#define SP804_AUTORELOAD   (0)
+#define SP804_SINGLESHOT   (1)
+#define SP804_GENERATE_IRQ (1 << 5)
+#define SP804_NO_IRQ       (0)
+
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
+
+
+// Starts the timer
+void startTimer(void);
+
+
+// Stops the timer
+void stopTimer(void);
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void);
+
+
+// Clears the timer interrupt
+void clearTimerIrq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of sp804_timer.h
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/startup.S
new file mode 100644
index 00000000..eea65315
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/startup.S
@@ -0,0 +1,803 @@
+// ------------------------------------------------------------
+// Armv8-A MPCore EL3 AArch64 Startup Code
+//
+// Basic Vectors, MMU, caches and GICv3 initialization
+//
+// Exits in EL1 AArch64
+//
+// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_mmu.h"
+#include "v8_system.h"
+
+
+    .section StartUp, "ax"
+    .balign 4
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+
+    .global InvalidateUDCaches
+    .global ZeroBlock
+
+    .global SetPrivateIntSecurityBlock
+    .global SetSPISecurityAll
+    .global SetPrivateIntPriority
+
+    .global WakeupGICR
+    .global SyncAREinGICD
+    .global EnableGICD
+    .global EnablePrivateInt
+    .global GetPrivateIntPending
+    .global ClearPrivateIntPending
+
+    .global __main
+
+    .global Image$$EXEC$$RO$$Base
+    .global Image$$TTB0_L1$$ZI$$Base
+    .global Image$$TTB0_L2_RAM$$ZI$$Base
+    .global Image$$TTB0_L2_PERIPH$$ZI$$Base
+    .global Image$$TOP_OF_RAM$$ZI$$Base
+    .global Image$$GICD$$ZI$$Base
+    .global Image$$ARM_LIB_STACK$$ZI$$Limit
+    .global Image$$EL3_STACKS$$ZI$$Limit
+    .global Image$$CS3_PERIPHERALS$$ZI$$Base
+    // use separate stack and heap, as anticipated by scatter.scat
+    .global __use_two_region_memory
+
+is_mmu_ready:
+.word 0
+
+
+// ------------------------------------------------------------
+
+    .global start64
+    .type start64, "function"
+start64:
+
+    //
+    // program the VBARs
+    //
+    ldr x1, =el1_vectors
+    msr VBAR_EL1, x1
+
+    ldr x1, =el2_vectors
+    msr VBAR_EL2, x1
+
+    ldr x1, =el3_vectors
+    msr VBAR_EL3, x1
+
+
+    // GIC-500 comes out of reset in GICv2 compatibility mode - first set
+    // system register enables for all relevant exception levels, and
+    // select GICv3 operating mode
+    //
+    msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL3, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
+
+    //
+    // set lower exception levels as non-secure, with no access
+    // back to EL2 or EL3, and are AArch64 capable
+    //
+    mov x3, #(SCR_EL3_RW  | \
+              SCR_EL3_SMD | \
+              SCR_EL3_NS)      // Set NS bit, to access Non-secure registers
+    msr SCR_EL3, x3
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL2, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
+
+
+    //
+    // no traps or VM modifications from the Hypervisor, EL1 is AArch64
+    //
+    mov x2, #HCR_EL2_RW
+    msr HCR_EL2, x2
+
+    //
+    // VMID is still significant, even when virtualisation is not
+    // being used, so ensure VTTBR_EL2 is properly initialised
+    //
+    msr VTTBR_EL2, xzr
+
+    //
+    // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
+    //  VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
+    // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
+    // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
+    // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
+    //
+    mrs x0, MPIDR_EL1
+    msr VMPIDR_EL2, x0
+    mrs x0, MIDR_EL1
+    msr VPIDR_EL2, x0
+
+    // extract the core number from MPIDR_EL1 and store it in
+    // x19 (defined by the AAPCS as callee-saved), so we can re-use
+    // the number later
+    //
+    bl GetCPUID
+    mov x19, x0
+
+    //
+    // neither EL3 nor EL2 trap floating point or accesses to CPACR
+    //
+    msr CPTR_EL3, xzr
+    msr CPTR_EL2, xzr
+
+    //
+    // SCTLR_ELx may come out of reset with UNKNOWN values so we will
+    // set the fields to 0 except, possibly, the endianess field(s).
+    // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
+    // is not strictly needed, since we're never in EL2 or EL0
+    //
+#ifdef __ARM_BIG_ENDIAN
+    mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
+#else
+    mov x0, #0
+#endif
+    msr SCTLR_EL3, x0
+    msr SCTLR_EL2, x0
+    msr SCTLR_EL1, x0
+
+#ifdef CORTEXA
+    //
+    // Configure ACTLR_EL[23]
+    // ----------------------
+    //
+    // These bits are IMPLEMENTATION DEFINED, so are different for
+    // different processors
+    //
+    // For Cortex-A57, the controls we set are:
+    //
+    //  Enable lower level access to CPUACTLR_EL1
+    //  Enable lower level access to CPUECTLR_EL1
+    //  Enable lower level access to L2CTLR_EL1
+    //  Enable lower level access to L2ECTLR_EL1
+    //  Enable lower level access to L2ACTLR_EL1
+    //
+    mov x0, #((1 << 0) | \
+              (1 << 1) | \
+              (1 << 4) | \
+              (1 << 5) | \
+              (1 << 6))
+
+    msr ACTLR_EL3, x0
+    msr ACTLR_EL2, x0
+
+    //
+    // configure CPUECTLR_EL1
+    //
+    // These bits are IMP DEF, so need to different for different
+    // processors
+    //
+    // SMPEN - bit 6 - Enables the processor to receive cache
+    //                 and TLB maintenance operations
+    //
+    // Note: For Cortex-A57/53 SMPEN should be set before enabling
+    //       the caches and MMU, or performing any cache and TLB
+    //       maintenance operations.
+    //
+    //       This register has a defined reset value, so we use a
+    //       read-modify-write sequence to set SMPEN
+    //
+    mrs x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
+    orr x0, x0, #(1 << 6)  // Set the SMPEN bit
+    msr S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
+
+    isb
+#endif
+
+    //
+    // That's the last of the control settings for now
+    //
+    // Note: no ISB after all these changes, as registers won't be
+    // accessed until after an exception return, which is itself a
+    // context synchronisation event
+    //
+
+    //
+    // Setup some EL3 stack space, ready for calling some subroutines, below.
+    //
+    // Stack space allocation is CPU-specific, so use CPU
+    // number already held in x19
+    //
+    // 2^12 bytes per CPU for the EL3 stacks
+    //
+    ldr x0, =Image$$EL3_STACKS$$ZI$$Limit
+    sub x0, x0, x19, lsl #12
+    mov sp, x0
+
+    //
+    // we need to configure the GIC while still in secure mode, specifically
+    // all PPIs and SPIs have to be programmed as Group1 interrupts
+    //
+
+    //
+    // Before the GIC can be reliably programmed, we need to
+    // enable Affinity Routing, as this affects where the configuration
+    // registers are (with Affinity Routing enabled, some registers are
+    // in the Redistributor, whereas those same registers are in the
+    // Distributor with Affinity Routing disabled (i.e. when in GICv2
+    // compatibility mode).
+    //
+    mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
+    mov x1, x19
+    bl  SyncAREinGICD
+
+    //
+    // The Redistributor comes out of reset assuming the processor is
+    // asleep - correct that assumption
+    //
+    mov w0, w19
+    bl  WakeupGICR
+
+    //
+    // Now we're ready to set security and other initialisations
+    //
+    // This is a per-CPU configuration for these interrupts
+    //
+    // for the first cluster, CPU number is the redistributor index
+    //
+    mov w0, w19
+    mov w1, #1    // gicigroupr_G1NS
+    bl  SetPrivateIntSecurityBlock
+
+    //
+    // While we're in the Secure World, set the priority mask low enough
+    // for it to be writable in the Non-Secure World
+    //
+    //mov x0, #16 << 3    // 5 bits of priority in the Secure world
+    mov x0, #0xFF  // for Non-Secure interrupts
+    msr ICC_PMR_EL1, x0
+
+    //
+    // there's more GIC setup to do, but only for the primary CPU
+    //
+    cbnz x19, drop_to_el1
+
+    //
+    // There's more to do to the GIC - call the utility routine to set
+    // all SPIs to Group1
+    //
+    mov w0, #1    // gicigroupr_G1NS
+    bl  SetSPISecurityAll
+
+    //
+    // Set up EL1 entry point and "dummy" exception return information,
+    // then perform exception return to enter EL1
+    //
+    .global drop_to_el1
+drop_to_el1:
+    adr x1, el1_entry_aarch64
+    msr ELR_EL3, x1
+    mov x1, #(AARCH64_SPSR_EL1h | \
+              AARCH64_SPSR_F  | \
+              AARCH64_SPSR_I  | \
+              AARCH64_SPSR_A)
+    msr SPSR_EL3, x1
+    eret
+
+
+
+// ------------------------------------------------------------
+// EL1 - Common start-up code
+// ------------------------------------------------------------
+
+    .global el1_entry_aarch64
+    .type el1_entry_aarch64, "function"
+el1_entry_aarch64:
+
+    //
+    // Now we're in EL1, setup the application stack
+    // the scatter file allocates 2^14 bytes per app stack
+    //
+    ldr x0, =Image$$HANDLER_STACK$$ZI$$Limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+    MSR     SPSel, #0
+    ISB
+    ldr x0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+
+    //
+    // Enable floating point
+    //
+    mov x0, #CPACR_EL1_FPEN
+    msr CPACR_EL1, x0
+
+    //
+    // Invalidate caches and TLBs for all stage 1
+    // translations used at EL1
+    //
+    // Cortex-A processors automatically invalidate their caches on reset
+    // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
+    // It is therefore not necessary for software to invalidate the caches 
+    // on startup, however, this is done here in case of a warm reset.
+    bl  InvalidateUDCaches
+    tlbi VMALLE1
+
+
+    //
+    // Set TTBR0 Base address
+    //
+    // The CPUs share one set of translation tables that are
+    // generated by CPU0 at run-time
+    //
+    // TTBR1_EL1 is not used in this example
+    //
+    ldr x1, =Image$$TTB0_L1$$ZI$$Base
+    msr TTBR0_EL1, x1
+
+
+    //
+    // Set up memory attributes
+    //
+    // These equate to:
+    //
+    // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
+    // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
+    // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
+    //
+    mov  x1, #0xff44
+    movk x1, #4, LSL #16    // equiv to: movk x1, #0x0000000000040000
+    msr MAIR_EL1, x1
+
+
+    //
+    // Set up TCR_EL1
+    //
+    // We're using only TTBR0 (EPD1 = 1), and the page table entries:
+    //  - are using an 8-bit ASID from TTBR0
+    //  - have a 4K granularity (TG0 = 0b00)
+    //  - are outer-shareable (SH0 = 0b10)
+    //  - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
+    //  - map
+    //      + 32 bits of VA space (T0SZ = 0x20)
+    //      + into a 32-bit PA space (IPS = 0b000)
+    //
+    //     36   32   28   24   20   16   12    8    4    0
+    //  -----+----+----+----+----+----+----+----+----+----+
+    //       |    |    |OOII|    |    |    |OOII|    |    |
+    //    TT |    |    |RRRR|E T |   T|    |RRRR|E T |   T|
+    //    BB | I I|TTSS|GGGG|P 1 |   1|TTSS|GGGG|P 0 |   0|
+    //    IIA| P P|GGHH|NNNN|DAS |   S|GGHH|NNNN|D S |   S|
+    //    10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
+    //
+    //    000 0000 0000 0000 1000 0000 0010 0101 0010 0000
+    //
+    //                    0x    8    0    2    5    2    0
+    //
+    // Note: the ISB is needed to ensure the changes to system
+    //       context are before the write of SCTLR_EL1.M to enable
+    //       the MMU. It is likely on a "real" implementation that
+    //       this setup would work without an ISB, due to the
+    //       amount of code that gets executed before enabling the
+    //       MMU, but that would not be architecturally correct.
+    //
+    ldr x1, =0x0000000000802520
+    msr TCR_EL1, x1
+    isb
+
+    //
+    // the primary CPU is going to use SGI 15 as a wakeup event
+    // to let us know when it is OK to proceed, so prepare for
+    // receiving that interrupt
+    //
+    // NS interrupt priorities run from 0 to 15, with 15 being
+    // too low a priority to ever raise an interrupt, so let's
+    // use 14
+    //
+    mov w0, w19
+    mov w1, #0
+    mov w2, #14 << 4    // we're in NS world, so 4 bits of priority,
+                        // 8-bit field, - 4 = 4-bit shift
+    bl SetPrivateIntPriority
+
+    mov w0, w19
+    mov w1, #0
+    bl  EnablePrivateInt
+
+    //
+    // set priority mask as low as possible; although,being in the
+    // NS World, we can't set bit[7] of the priority, we still
+    // write all 8-bits of priority to an ICC register
+    //
+    mov x0, #31 << 3
+    msr ICC_PMR_EL1, x0
+
+    //
+    // set global enable and wait for our interrupt to arrive
+    //
+    mov x0, #1
+    msr ICC_IGRPEN1_EL1, x0
+    isb
+
+    //
+    // x19 already contains the CPU number, so branch to secondary
+    // code if we're not on CPU0
+    //
+    cbnz x19, el1_secondary
+
+    //
+    // Fall through to primary code
+    //
+
+
+//
+// ------------------------------------------------------------
+//
+// EL1 - primary CPU init code
+//
+// This code is run on CPU0, while the other CPUs are in the
+// holding pen
+//
+
+    .global el1_primary
+    .type el1_primary, "function"
+el1_primary:
+
+    //
+    // Turn on the banked GIC distributor enable,
+    // ready for individual CPU enables later
+    //
+    mov w0, #(1 << 1)  // gicdctlr_EnableGrp1A
+    bl  EnableGICD
+
+    //
+    // Generate TTBR0 L1
+    //
+    // at 4KB granularity, 32-bit VA space, table lookup starts at
+    // L1, with 1GB regions
+    //
+    // we are going to create entries pointing to L2 tables for a
+    // couple of these 1GB regions, the first of which is the
+    // RAM on the VE board model - get the table addresses and
+    // start by emptying out the L1 page tables (4 entries at L1
+    // for a 4K granularity)
+    //
+    // x21 = address of L1 tables
+    //
+    ldr x21, =Image$$TTB0_L1$$ZI$$Base
+    mov x0, x21
+    mov x1, #(4 << 3)
+    bl  ZeroBlock
+
+    //
+    // time to start mapping the RAM regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // x22 = address of L2 tables, needs to be remembered in case
+    //       we want to re-use the tables for mapping peripherals
+    //
+    ldr x22, =Image$$TTB0_L2_RAM$$ZI$$Base
+    mov x1, #(512 << 3)
+    mov x0, x22
+    bl  ZeroBlock
+
+    //
+    // Get the start address of RAM (the EXEC region) into x4
+    // and calculate the offset into the L1 table (1GB per region,
+    // max 4GB)
+    //
+    // x23 = L1 table offset, saved for later comparison against
+    //       peripheral offset
+    //
+    ldr x4, =Image$$EXEC$$RO$$Base
+    ubfx x23, x4, #30, #2
+
+    orr x1, x22, #TT_S1_ATTR_PAGE
+    str x1, [x21, x23, lsl #3]
+
+    //
+    // we've already used the RAM start address in x4 - we now need
+    // to get this in terms of an offset into the L2 page tables,
+    // where each entry covers 2MB
+    //
+    ubfx x2, x4, #21, #9
+
+    //
+    // TOP_OF_RAM in the scatter file marks the end of the
+    // Execute region in RAM: convert the end of this region to an
+    // offset too, being careful to round up, then calculate the
+    // number of entries to write
+    //
+    ldr x5, =Image$$TOP_OF_RAM$$ZI$$Base
+    sub  x3, x5, #1
+    ubfx x3, x3, #21, #9
+    add  x3, x3, #1
+    sub  x3, x3, x2
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as Shared, Normal WBWA (MAIR[1]) with a flat
+    // VA->PA translation
+    //
+    bic x4, x4, #((1 << 21) - 1)
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (1 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_SH_INNER | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // factor the offset into the page table address and then write
+    // the entries
+    //
+    add x0, x22, x2, lsl #3
+
+loop1:
+    subs x3, x3, #1
+    str x1, [x0], #8
+    add x1, x1, #0x200, LSL #12    // equiv to add x1, x1, #(1 << 21)  // 2MB per entry
+    bne loop1
+
+
+    //
+    // now mapping the Peripheral regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // The assumption here is that all peripherals live within
+    // a common 1GB region (i.e. that there's a single set of
+    // L2 pages for all the peripherals). We only use a UART
+    // and the GIC in this example, so the assumption is sound
+    //
+    // x24 = address of L2 peripheral tables
+    //
+    ldr x24, =Image$$TTB0_L2_PERIPH$$ZI$$Base
+
+    //
+    // get the GICD address into x4 and calculate
+    // the offset into the L1 table
+    //
+    // x25 = L1 table offset
+    //
+    ldr x4, =Image$$GICD$$ZI$$Base
+    ubfx x25, x4, #30, #2
+
+    //
+    // here's the tricky bit: it's possible that the peripherals are
+    // in the same 1GB region as the RAM, in which case we don't need
+    // to prime a separate set of L2 page tables, nor add them to the
+    // L1 tables
+    //
+    // if we're going to re-use the TTB0_L2_RAM tables, get their
+    // address into x24, which is used later on to write the PTEs
+    //
+    cmp x25, x23
+    csel x24, x22, x24, EQ
+    b.eq nol2setup
+
+    //
+    // Peripherals are in a separate 1GB region, and so have their own
+    // set of L2 tables - clean out the tables and add them to the L1
+    // table
+    //
+    mov x0, x24
+    mov x1, #512 << 3
+    bl  ZeroBlock
+
+    orr x1, x24, #TT_S1_ATTR_PAGE
+    str x1, [x21, x25, lsl #3]
+
+    //
+    // there's only going to be a single 2MB region for GICD (in
+    // x4) - get this in terms of an offset into the L2 page tables
+    //
+    // with larger systems, it is possible that the GIC redistributor
+    // registers require extra 2MB pages, in which case extra code
+    // would be required here
+    //
+nol2setup:
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry for this, so no loop as we have for RAM, above
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // we have CS3_PERIPHERALS that include the UART controller
+    //
+    // Again, the code is making assumptions - this time that the CS3_PERIPHERALS
+    // region uses the same 1GB portion of the address space as the GICD,
+    // and thus shares the same set of L2 page tables
+    //
+    // Get CS3_PERIPHERALS address into x4 and calculate the offset into the
+    // L2 tables
+    //
+    ldr x4, =Image$$CS3_PERIPHERALS$$ZI$$Base
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry again - write it
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // issue a barrier to ensure all table entry writes are complete
+    //
+    dsb ish
+
+    ldr x1, =is_mmu_ready
+    mov x2, #1
+    str x2, [x1]
+
+    //
+    // Enable the MMU.  Caches will be enabled later, after scatterloading.
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    //
+    // Branch to C library init code
+    //
+    b  __main
+
+
+// ------------------------------------------------------------
+
+// AArch64 Arm C library startup add-in:
+
+// The Arm Architecture Reference Manual for Armv8-A states:
+//
+//     Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
+//     Correspondingly, the sequence for ensuring that modifications to instructions are available
+//     for execution must include invalidation of the modified locations from the instruction cache,
+//     even if the instructions are held in Normal Non-cacheable memory.
+//     This includes cases where the instruction cache is disabled.
+//
+// To invalidate the AArch64 instruction cache after scatter-loading and before initialization of the stack and heap,
+// it is necessary for the user to:
+//
+// * Implement instruction cache invalidation code in _platform_pre_stackheap_init.
+// * Ensure all code on the path from the program entry up to and including _platform_pre_stackheap_init is located in a root region.
+//
+// In this example, this function is only called once, by the primary core
+
+    .global _platform_pre_stackheap_init
+    .type _platform_pre_stackheap_init, "function"
+    .cfi_startproc
+_platform_pre_stackheap_init:
+    dsb ish     // ensure all previous stores have completed before invalidating
+    ic  ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
+    dsb ish     // ensure completion on inner shareable domain   (which includes secondary cores)
+    isb
+
+    // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    msr SCTLR_EL1, x1
+    isb
+
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+// EL1 - secondary CPU init code
+//
+// This code is run on CPUs 1, 2, 3 etc....
+// ------------------------------------------------------------
+
+    .global el1_secondary
+    .type el1_secondary, "function"
+el1_secondary:
+
+wait_for_mmu_ready:
+    ldr x1, =is_mmu_ready
+    ldr x1, [x1]
+    cmp x1, #1
+    b.ne wait_for_mmu_ready
+
+    //
+    // Enable the MMU and caches
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+	/* EL: Secondary core entrance.  */
+    B       _tx_thread_smp_initialize_wait
+
+loop_wfi:
+    dsb SY      // Clear all pending data accesses
+    wfi         // Go to sleep
+
+    //
+    // something woke us from our wait, was it the required interrupt?
+    //
+    mov w0, w19
+    mov w1, #15
+    bl  GetPrivateIntPending
+    cbz w0, loop_wfi
+
+    //
+    // it was - there's no need to actually take the interrupt,
+    // so just clear it
+    //
+    mov w0, w19
+    mov w1, #15
+    bl  ClearPrivateIntPending
+
+    //
+    // Branch to thread start
+    //
+    // B  MainApp
+
+    /**
+     * Retargeted to prevent the C library from doing its own stack and heap
+     * initialisation.
+     */
+    .type __user_setup_stackheap, @function
+__user_setup_stackheap:
+    ADRP    X0, Image$$SYS_STACK$$ZI$$Limit
+    MOV     SP, X0
+    ADRP    X0, Image$$ARM_LIB_HEAP$$ZI$$Base
+    ADRP    X2, Image$$ARM_LIB_HEAP$$ZI$$Limit
+    RET
+    
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/timer_interrupts.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/timer_interrupts.c
new file mode 100644
index 00000000..434d9189
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/timer_interrupts.c
@@ -0,0 +1,152 @@
+/* Bare-metal example for Armv8-A FVP Base model */
+
+/* Timer and interrupts */
+
+/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */
+/* Use, modification and redistribution of this file is subject to your      */
+/* possession of a valid DS-5 end user licence agreement and your compliance */
+/* with all applicable terms and conditions of such licence agreement.       */
+
+#include <stdio.h>
+
+#include "GICv3.h"
+#include "GICv3_gicc.h"
+#include "sp804_timer.h"
+
+void   _tx_timer_interrupt(void);
+
+// LED Base address
+#define LED_BASE (volatile unsigned int *)0x1C010008
+
+
+void nudge_leds(void) // Move LEDs along
+{
+    static int state = 1;
+    static int value = 1;
+
+    if (state)
+    {
+        int max = (1 << 7);
+        value <<= 1;
+        if (value == max)
+            state = 0;
+    }
+    else
+    {
+        value >>= 1;
+        if (value == 1)
+            state = 1;
+    }
+
+    *LED_BASE = value;  // Update LEDs hardware
+}
+
+
+// Initialize Timer 0 and Interrupt Controller
+void init_timer(void)
+{
+    // Enable interrupts
+    __asm("MSR DAIFClr, #0xF");
+    setICC_IGRPEN1_EL1(igrpEnable);
+
+    // Configure the SP804 timer to generate an interrupt
+    setTimerBaseAddress(0x1C110000);
+    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
+    startTimer();
+
+    // The SP804 timer generates SPI INTID 34.  Enable
+    // this ID, and route it to core 0.0.0.0 (this one!)
+    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
+    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
+    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
+    EnableSPI(34);                                   // Enable INTID 34
+}
+
+
+// --------------------------------------------------------
+
+void irqHandler(void)
+{
+  unsigned int ID;
+
+  ID = getICC_IAR1(); // readIntAck();
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+      //printf("irqHandler() - Reserved INTID %d\n\n", ID);
+      return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("irqHandler() - External timer interrupt\n\n");
+      nudge_leds();
+      clearTimerIrq();
+
+      /* Call ThreadX timer interrupt processing.  */
+      _tx_timer_interrupt();
+
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("irqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
+
+// --------------------------------------------------------
+
+// Not actually used in this example, but provided for completeness
+
+void fiqHandler(void)
+{
+  unsigned int ID;
+  unsigned int aliased = 0;
+
+  ID = getICC_IAR0(); // readIntAck();
+  //printf("fiqHandler() - Read %d from IAR0\n", ID);
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+    //printf("fiqHandler() - Reserved INTID %d\n\n", ID);
+    ID = getICC_IAR1(); // readAliasedIntAck();
+    //printf("fiqHandler() - Read %d from AIAR\n", ID);
+    aliased = 1;
+
+    // If still spurious then simply return
+    if ((1020 <= ID) && (ID <= 1023))
+        return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("fiqHandler() - External timer interrupt\n\n");
+      clearTimerIrq();
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  // NOTE: If the ID was read from the Aliased IAR, then
+  // the aliased EOI register must be used
+  if (aliased == 0)
+    setICC_EOIR0(ID); // writeEOI(ID);
+  else
+    setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S
new file mode 100644
index 00000000..e2d81e5e
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S
@@ -0,0 +1,161 @@
+// ------------------------------------------------------------
+// Armv8-A AArch64 - Common helper functions
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global EnableCachesEL1
+    .global DisableCachesEL1
+    .global InvalidateUDCaches
+    .global GetMIDR
+    .global GetMPIDR
+    .global GetCPUID
+
+// ------------------------------------------------------------
+
+//
+// void EnableCachesEL1(void)
+//
+//    enable Instruction and Data caches
+//
+    .type EnableCachesEL1, "function"
+    .cfi_startproc
+EnableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    orr x0, x0, #SCTLR_ELx_I
+    orr x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+    .type DisableCachesEL1, "function"
+    .cfi_startproc
+DisableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    bic x0, x0, #SCTLR_ELx_I
+    bic x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// void InvalidateUDCaches(void)
+//
+//    Invalidate data and unified caches
+//
+    .type InvalidateUDCaches, "function"
+    .cfi_startproc
+InvalidateUDCaches:
+    // From the Armv8-A Architecture Reference Manual
+
+    dmb  ish                   // ensure all prior inner-shareable accesses have been observed
+
+    mrs  x0, CLIDR_EL1
+    and  w3, w0, #0x07000000   // get 2 x level of coherence
+    lsr  w3, w3, #23
+    cbz  w3, finished
+    mov  w10, #0               // w10 = 2 x cache level
+    mov  w8, #1                // w8 = constant 0b1
+loop_level:
+    add  w2, w10, w10, lsr #1  // calculate 3 x cache level
+    lsr  w1, w0, w2            // extract 3-bit cache type for this level
+    and  w1, w1, #0x7
+    cmp  w1, #2
+    b.lt next_level            // no data or unified cache at this level
+    msr  CSSELR_EL1, x10       // select this cache level
+    isb                        // synchronize change of csselr
+    mrs  x1, CCSIDR_EL1        // read ccsidr
+    and  w2, w1, #7            // w2 = log2(linelen)-4
+    add  w2, w2, #4            // w2 = log2(linelen)
+    ubfx w4, w1, #3, #10       // w4 = max way number, right aligned
+    clz  w5, w4                // w5 = 32-log2(ways), bit position of way in dc operand
+    lsl  w9, w4, w5            // w9 = max way number, aligned to position in dc operand
+    lsl  w16, w8, w5           // w16 = amount to decrement way number per iteration
+loop_way:
+    ubfx w7, w1, #13, #15      // w7 = max set number, right aligned
+    lsl  w7, w7, w2            // w7 = max set number, aligned to position in dc operand
+    lsl  w17, w8, w2           // w17 = amount to decrement set number per iteration
+loop_set:
+    orr  w11, w10, w9          // w11 = combine way number and cache number ...
+    orr  w11, w11, w7          // ... and set number for dc operand
+    dc   isw, x11              // do data cache invalidate by set and way
+    subs w7, w7, w17           // decrement set number
+    b.ge loop_set
+    subs x9, x9, x16           // decrement way number
+    b.ge loop_way
+next_level:
+    add  w10, w10, #2          // increment 2 x cache level
+    cmp  w3, w10
+    b.gt loop_level
+    dsb  sy                    // ensure completion of previous cache maintenance operation
+    isb
+finished:
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// ID Register functions
+//
+
+    .type GetMIDR, "function"
+    .cfi_startproc
+GetMIDR:
+
+    mrs x0, MIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetMPIDR, "function"
+    .cfi_startproc
+GetMPIDR:
+
+    mrs x0, MPIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetCPUID, "function"
+    .cfi_startproc
+GetCPUID:
+
+    mrs x0, MIDR_EL1
+    ubfx    x0, x0, #4, #12 // extract PartNum
+    cmp x0, #0xD0A          // Cortex-A75
+    b.eq DynamIQ
+    cmp x0, #0xD05          // Cortex-A55
+    b.eq DynamIQ
+    b Others
+DynamIQ:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+
+Others:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_mmu.h
new file mode 100644
index 00000000..afb8b923
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_mmu.h
@@ -0,0 +1,118 @@
+//
+// Defines for v8 Memory Model
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_MMU_H
+#define V8_MMU_H
+
+//
+// Translation Control Register fields
+//
+// RGN field encodings
+//
+#define TCR_RGN_NC   0b00
+#define TCR_RGN_WBWA 0b01
+#define TCR_RGN_WT   0b10
+#define TCR_RGN_WBRA 0b11
+
+//
+// Shareability encodings
+//
+#define TCR_SHARE_NONE  0b00
+#define TCR_SHARE_OUTER 0b10
+#define TCR_SHARE_INNER 0b11
+
+//
+// Granule size encodings
+//
+#define TCR_GRANULE_4K  0b00
+#define TCR_GRANULE_64K 0b01
+#define TCR_GRANULE_16K 0b10
+
+//
+// Physical Address sizes
+//
+#define TCR_SIZE_4G   0b000
+#define TCR_SIZE_64G  0b001
+#define TCR_SIZE_1T   0b010
+#define TCR_SIZE_4T   0b011
+#define TCR_SIZE_16T  0b100
+#define TCR_SIZE_256T 0b101
+
+//
+// Translation Control Register fields
+//
+#define TCR_EL1_T0SZ_SHIFT   0
+#define TCR_EL1_EPD0  (1 << 7)
+#define TCR_EL1_IRGN0_SHIFT  8
+#define TCR_EL1_ORGN0_SHIFT 10
+#define TCR_EL1_SH0_SHIFT   12
+#define TCR_EL1_TG0_SHIFT   14
+
+#define TCR_EL1_T1SZ_SHIFT  16
+#define TCR_EL1_A1   (1 << 22)
+#define TCR_EL1_EPD1 (1 << 23)
+#define TCR_EL1_IRGN1_SHIFT 24
+#define TCR_EL1_ORGN1_SHIFT 26
+#define TCR_EL1_SH1_SHIFT   28
+#define TCR_EL1_TG1_SHIFT   30
+#define TCR_EL1_IPS_SHIFT   32
+#define TCR_EL1_AS   (1 << 36)
+#define TCR_EL1_TBI0 (1 << 37)
+#define TCR_EL1_TBI1 (1 << 38)
+
+//
+// Stage 1 Translation Table descriptor fields
+//
+#define TT_S1_ATTR_FAULT (0b00 << 0)
+#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
+#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
+#define TT_S1_ATTR_PAGE  (0b11 << 0) // Level 3
+
+#define TT_S1_ATTR_MATTR_LSB 2
+
+#define TT_S1_ATTR_NS (1 << 5)
+
+#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
+#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
+#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
+#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
+
+#define TT_S1_ATTR_SH_NONE   (0b00 << 8)
+#define TT_S1_ATTR_SH_OUTER  (0b10 << 8)
+#define TT_S1_ATTR_SH_INNER  (0b11 << 8)
+
+#define TT_S1_ATTR_AF (1 << 10)
+#define TT_S1_ATTR_nG (1 << 11)
+
+#define TT_S1_ATTR_CONTIG (1 << 52)
+#define TT_S1_ATTR_PXN    (1 << 53)
+#define TT_S1_ATTR_UXN    (1 << 54)
+
+#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
+#define TT_S1_MAIR_DEV_nGnRE  0b00000100
+#define TT_S1_MAIR_DEV_nGRE   0b00001000
+#define TT_S1_MAIR_DEV_GRE    0b00001100
+
+//
+// Inner and Outer Normal memory attributes use the same bit patterns
+// Outer attributes just need to be shifted up
+//
+#define TT_S1_MAIR_OUTER_SHIFT 4
+
+#define TT_S1_MAIR_WT_TRANS_RA  0b0010
+
+#define TT_S1_MAIR_WB_TRANS_RA  0b0110
+#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
+
+#define TT_S1_MAIR_WT_RA  0b1010
+
+#define TT_S1_MAIR_WB_RA  0b1110
+#define TT_S1_MAIR_WB_RWA 0b1111
+
+#endif // V8_MMU_H
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_system.h
new file mode 100644
index 00000000..e54f2fc7
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_system.h
@@ -0,0 +1,115 @@
+//
+// Defines for v8 System Registers
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_SYSTEM_H
+#define V8_SYSTEM_H
+
+//
+// AArch64 SPSR
+//
+#define AARCH64_SPSR_EL3h 0b1101
+#define AARCH64_SPSR_EL3t 0b1100
+#define AARCH64_SPSR_EL2h 0b1001
+#define AARCH64_SPSR_EL2t 0b1000
+#define AARCH64_SPSR_EL1h 0b0101
+#define AARCH64_SPSR_EL1t 0b0100
+#define AARCH64_SPSR_EL0t 0b0000
+#define AARCH64_SPSR_RW (1 << 4)
+#define AARCH64_SPSR_F  (1 << 6)
+#define AARCH64_SPSR_I  (1 << 7)
+#define AARCH64_SPSR_A  (1 << 8)
+#define AARCH64_SPSR_D  (1 << 9)
+#define AARCH64_SPSR_IL (1 << 20)
+#define AARCH64_SPSR_SS (1 << 21)
+#define AARCH64_SPSR_V  (1 << 28)
+#define AARCH64_SPSR_C  (1 << 29)
+#define AARCH64_SPSR_Z  (1 << 30)
+#define AARCH64_SPSR_N  (1 << 31)
+
+//
+// Multiprocessor Affinity Register
+//
+#define MPIDR_EL1_AFF3_LSB 32
+#define MPIDR_EL1_U  (1 << 30)
+#define MPIDR_EL1_MT (1 << 24)
+#define MPIDR_EL1_AFF2_LSB 16
+#define MPIDR_EL1_AFF1_LSB  8
+#define MPIDR_EL1_AFF0_LSB  0
+#define MPIDR_EL1_AFF_WIDTH 8
+
+//
+// Data Cache Zero ID Register
+//
+#define DCZID_EL0_BS_LSB   0
+#define DCZID_EL0_BS_WIDTH 4
+#define DCZID_EL0_DZP_LSB  5
+#define DCZID_EL0_DZP (1 << 5)
+
+//
+// System Control Register
+//
+#define SCTLR_EL1_UCI     (1 << 26)
+#define SCTLR_ELx_EE      (1 << 25)
+#define SCTLR_EL1_E0E     (1 << 24)
+#define SCTLR_ELx_WXN     (1 << 19)
+#define SCTLR_EL1_nTWE    (1 << 18)
+#define SCTLR_EL1_nTWI    (1 << 16)
+#define SCTLR_EL1_UCT     (1 << 15)
+#define SCTLR_EL1_DZE     (1 << 14)
+#define SCTLR_ELx_I       (1 << 12)
+#define SCTLR_EL1_UMA     (1 << 9)
+#define SCTLR_EL1_SED     (1 << 8)
+#define SCTLR_EL1_ITD     (1 << 7)
+#define SCTLR_EL1_THEE    (1 << 6)
+#define SCTLR_EL1_CP15BEN (1 << 5)
+#define SCTLR_EL1_SA0     (1 << 4)
+#define SCTLR_ELx_SA      (1 << 3)
+#define SCTLR_ELx_C       (1 << 2)
+#define SCTLR_ELx_A       (1 << 1)
+#define SCTLR_ELx_M       (1 << 0)
+
+//
+// Architectural Feature Access Control Register
+//
+#define CPACR_EL1_TTA     (1 << 28)
+#define CPACR_EL1_FPEN    (3 << 20)
+
+//
+// Architectural Feature Trap Register
+//
+#define CPTR_ELx_TCPAC (1 << 31)
+#define CPTR_ELx_TTA   (1 << 20)
+#define CPTR_ELx_TFP   (1 << 10)
+
+//
+// Secure Configuration Register
+//
+#define SCR_EL3_TWE  (1 << 13)
+#define SCR_EL3_TWI  (1 << 12)
+#define SCR_EL3_ST   (1 << 11)
+#define SCR_EL3_RW   (1 << 10)
+#define SCR_EL3_SIF  (1 << 9)
+#define SCR_EL3_HCE  (1 << 8)
+#define SCR_EL3_SMD  (1 << 7)
+#define SCR_EL3_EA   (1 << 3)
+#define SCR_EL3_FIQ  (1 << 2)
+#define SCR_EL3_IRQ  (1 << 1)
+#define SCR_EL3_NS   (1 << 0)
+
+//
+// Hypervisor Configuration Register
+//
+#define HCR_EL2_ID   (1 << 33)
+#define HCR_EL2_CD   (1 << 32)
+#define HCR_EL2_RW   (1 << 31)
+#define HCR_EL2_TRVM (1 << 30)
+#define HCR_EL2_HVC  (1 << 29)
+#define HCR_EL2_TDZ  (1 << 28)
+
+#endif // V8_SYSTEM_H
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_utils.S
new file mode 100644
index 00000000..750488b7
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/v8_utils.S
@@ -0,0 +1,69 @@
+//
+// Simple utility routines for baremetal v8 code
+//
+// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+//
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//
+// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
+//
+// Zero fill a block of memory
+//   Fill memory pages or similar structures with zeros.
+//   The byte count must be a multiple of the block fill size (16 bytes)
+//
+//  Inputs:
+//    blockPtr - base address of block to fill
+//    nBytes - block size, in bytes
+//
+//  Returns:
+//    pointer to just filled block, NULL if nBytes is
+//  incompatible with block fill size
+//
+    .global ZeroBlock
+    .type ZeroBlock, "function"
+    .cfi_startproc
+ZeroBlock:
+
+    //
+    // we fill data by steam, 16 bytes at a time: check that
+    // blocksize is a multiple of that
+    //
+    ubfx x2, x1, #0, #4
+    cbnz x2, incompatible
+
+    //
+    // we already have one register full of zeros, get another
+    //
+    mov x3, x2
+
+    //
+    // OK, set temporary pointer and away we go
+    //
+    add x0, x0, x1
+
+loop0:
+    subs x1, x1, #16
+    stp  x2, x3, [x0, #-16]!
+    b.ne loop0
+
+    //
+    // that's all - x0 will be back to its start value
+    //
+    ret
+
+    //
+    // parameters are incompatible with block size - return
+    // an indication that this is so
+    //
+incompatible:
+    mov x0,#0
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/vectors.S
new file mode 100644
index 00000000..be6d28a3
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/vectors.S
@@ -0,0 +1,252 @@
+// ------------------------------------------------------------
+// Armv8-A Vector tables
+//
+// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your
+// possession of a valid DS-5 end user licence agreement and your compliance
+// with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+    .global c0sync1
+    .global irqHandler
+    .global fiqHandler
+    .global irqFirstLevelHandler
+    .global fiqFirstLevelHandler
+
+    .section  EL1VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el1_vectors:
+c0sync1: B c0sync1
+
+    .balign 0x80
+c0irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr1: B c0serr1
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync1: B cxsync1
+
+    .balign 0x80
+cxirq1: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr1: B cxserr1
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync1: B l64sync1
+
+    .balign 0x80
+l64irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr1: B l64serr1
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync1: B l32sync1
+
+    .balign 0x80
+l32irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr1: B l32serr1
+
+//----------------------------------------------------------------
+
+    .section  EL2VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el2_vectors:
+c0sync2: B c0sync2
+
+    .balign 0x80
+c0irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr2: B c0serr2
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync2: B cxsync2
+
+    .balign 0x80
+cxirq2: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr2: B cxserr2
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync2: B l64sync2
+
+    .balign 0x80
+l64irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr2: B l64serr2
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync2: B l32sync2
+
+    .balign 0x80
+l32irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr2: B l32serr2
+
+//----------------------------------------------------------------
+
+    .section  EL3VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el3_vectors:
+c0sync3: B c0sync3
+
+    .balign 0x80
+c0irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr3: B c0serr3
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync3: B cxsync3
+
+    .balign 0x80
+cxirq3: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr3: B cxserr3
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync3: B l64sync3
+
+    .balign 0x80
+l64irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr3: B l64serr3
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync3: B l32sync3
+
+    .balign 0x80
+l32irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr3: B l32serr3
+
+
+    .section InterruptHandlers, "ax"
+    .balign 4
+
+    .type irqFirstLevelHandler, "function"
+irqFirstLevelHandler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+  BL       irqHandler
+  B        _tx_thread_context_restore
+
+    .type fiqFirstLevelHandler, "function"
+fiqFirstLevelHandler:
+  STP      x29, x30, [sp, #-16]!
+  STP      x18, x19, [sp, #-16]!
+  STP      x16, x17, [sp, #-16]!
+  STP      x14, x15, [sp, #-16]!
+  STP      x12, x13, [sp, #-16]!
+  STP      x10, x11, [sp, #-16]!
+  STP      x8, x9, [sp, #-16]!
+  STP      x6, x7, [sp, #-16]!
+  STP      x4, x5, [sp, #-16]!
+  STP      x2, x3, [sp, #-16]!
+  STP      x0, x1, [sp, #-16]!
+
+  BL       fiqHandler
+
+  LDP      x0, x1, [sp], #16
+  LDP      x2, x3, [sp], #16
+  LDP      x4, x5, [sp], #16
+  LDP      x6, x7, [sp], #16
+  LDP      x8, x9, [sp], #16
+  LDP      x10, x11, [sp], #16
+  LDP      x12, x13, [sp], #16
+  LDP      x14, x15, [sp], #16
+  LDP      x16, x17, [sp], #16
+  LDP      x18, x19, [sp], #16
+  LDP      x29, x30, [sp], #16
+  ERET
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject
new file mode 100644
index 00000000..e31673c3
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject
@@ -0,0 +1,314 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944." name="/" resourcePath="">
+                        						
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+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1684503312.2127819066" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.218588332" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/>
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+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.1039746527" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.782830388">
+                                								
+                                <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1452341850" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1199548922" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1403694095">
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.231591469" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.55701478" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1809021405"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1927377141" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1906007863"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="src_generic/tx_misra.c|src_generic/tx_thread_timeout.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.release.base.597173224">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.release.base.597173224" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.release.base.597173224" name="Release" parent="com.arm.eclipse.build.config.v6.lib.release.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.release.base.597173224." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.1176479246" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6">
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.1176479246.1337532818" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1329350735" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.599090274" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.1379419239" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
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+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.1827794426" superClass="com.arm.tool.c.compiler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.681809063" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.1575069010" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
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+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.541732194" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.1308655066" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1174783096" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.121864210" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="src_generic/tx_misra.c|src_generic/tx_thread_timeout.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="tx.com.arm.eclipse.build.project.v6.lib.1209080418" name="Static Library"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/tx/.project b/ports_module/cortex_a35_smp/ac6/example_build/tx/.project
new file mode 100644
index 00000000..7e68cb5c
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/tx/.project
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>tx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_modules</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
+		</link>
+		<link>
+			<name>src_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/src</locationURI>
+		</link>
+		<link>
+			<name>src_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/module_manager/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject
new file mode 100644
index 00000000..fb4f25bb
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject
@@ -0,0 +1,238 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings>
+                    					
+                    <externalSetting>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/>
+                        					
+                    </externalSetting>
+                    				
+                </externalSettings>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6">
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.688166309" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/>
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+                            <option id="com.arm.toolchain.v6.base.options.floatabi.197203083" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.floatabi.auto" valueType="enumerated"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.inst.552700328" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.inst.auto" valueType="enumerated"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.debug.level.1623863720" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766.195306460" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1164059605" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/>
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+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.100103692" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.target.775437314" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="aarch64-arm-none-eabi" valueType="string"/>
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+                                <option id="com.arm.tool.c.compiler.v6.base.option.cpu.957518664" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/>
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+                                <option id="com.arm.tool.c.compiler.v6.base.option.inst.36110020" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.auto" valueType="enumerated"/>
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+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498990421" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
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+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_port}&quot;"/>
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+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic_module_manager}&quot;"/>
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+                                <inputType id="com.arm.tool.assembler.v6.base.input.1847017761" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1124663047" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1439633481" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551.123734872" name="/" resourcePath="src_generic_module_lib">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.420950976" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6" unusedChildren="">
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.688166309.645127862" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu.688166309"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.floatabi.197203083.946078511" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi.197203083"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.inst.552700328.299662774" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst.552700328"/>
+                            							
+                            <option id="com.arm.toolchain.v6.base.options.debug.level.1623863720.1171787490" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level.1623863720"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.632471296" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.100103692">
+                                								
+                                <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.70957166" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/>
+                                								
+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.1757831855" superClass="com.arm.tool.c.compiler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.1146259691" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.262825882">
+                                								
+                                <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.696836314" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.18755829" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.596919840">
+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.1428309965" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.852511731" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1124663047"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.674747855" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1439633481"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/txm"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/ac6/example_build/txm/.project b/ports_module/cortex_a35_smp/ac6/example_build/txm/.project
new file mode 100644
index 00000000..ad1957cd
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/example_build/txm/.project
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>txm</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_generic_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_generic_modules</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
+		</link>
+		<link>
+			<name>src_generic_module_lib</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_lib/src</locationURI>
+		</link>
+		<link>
+			<name>src_port_module_lib</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/module_lib/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h
new file mode 100644
index 00000000..4d354f97
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h
@@ -0,0 +1,450 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                        Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/************* Define ThreadX SMP constants.  *************/
+
+#define TX_THREAD_SMP                           1
+
+
+/* Define the ThreadX SMP maximum number of cores.  */
+
+#ifndef TX_THREAD_SMP_MAX_CORES
+#define TX_THREAD_SMP_MAX_CORES                 4
+#endif
+
+
+/* Define the ThreadX SMP core mask. */
+
+#ifndef TX_THREAD_SMP_CORE_MASK
+#define TX_THREAD_SMP_CORE_MASK                 0xF            /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc.  */
+#endif
+
+
+/* Define INLINE_DECLARE to whitespace for ARM compiler.  */
+
+#define INLINE_DECLARE
+
+
+/* Define ThreadX SMP initialization macro.  */
+
+#define TX_PORT_SPECIFIC_PRE_INITIALIZATION                 
+
+
+/* Define ThreadX SMP pre-scheduler initialization.  */
+
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION       
+
+
+/* Enable the inter-core interrupt logic.  */
+
+#define TX_THREAD_SMP_INTER_CORE_INTERRUPT
+
+
+/* Determine if there is customer-specific wakeup logic needed.  */
+
+#ifdef TX_THREAD_SMP_WAKEUP_LOGIC
+
+/* Include customer-specific wakeup code.  */
+
+#include "tx_thread_smp_core_wakeup.h"
+#else
+
+#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC
+
+/* Default wakeup code.  */
+#define TX_THREAD_SMP_WAKEUP_LOGIC
+#define TX_THREAD_SMP_WAKEUP(i)                _tx_thread_smp_core_preempt(i)
+#endif
+#endif
+
+
+/* Ensure that the in-line resume/suspend define is not allowed.  */
+
+#ifdef TX_INLINE_THREAD_RESUME_SUSPEND
+#undef TX_INLINE_THREAD_RESUME_SUSPEND
+#endif
+
+
+/************* End ThreadX SMP constants.  *************/
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include <stdlib.h>
+#include <string.h>
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef int                                     LONG;
+typedef unsigned int                            ULONG;
+typedef unsigned long long                      ULONG64;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Override the alignment type to use 64-bit alignment and storage for pointers.  */
+
+#define ALIGN_TYPE_DEFINED
+typedef unsigned long long                      ALIGN_TYPE;
+
+
+/* Override the free block marker for byte pools to be a 64-bit constant.   */
+
+#define TX_BYTE_BLOCK_FREE                      ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE)
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              4096        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex ARMv8 port.  */ 
+
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ & FIQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    _tx_thread_smp_time_get()
+#endif
+#else
+#ifndef TX_TRACE_TIME_SOURCE
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0
+#define TX_THREAD_EXTENSION_1
+#define TX_THREAD_EXTENSION_2               ULONG   tx_thread_fp_enable;
+#define TX_THREAD_EXTENSION_3               VOID    *tx_thread_extension_ptr;               \
+                                            VOID    *tx_thread_module_instance_ptr;         \
+                                            VOID    *tx_thread_module_entry_info_ptr;       \
+                                            ULONG   tx_thread_module_current_user_mode;     \
+                                            ULONG   tx_thread_module_user_mode;             \
+                                            ULONG   tx_thread_module_saved_lr;              \
+                                            VOID    *tx_thread_module_kernel_stack_start;   \
+                                            VOID    *tx_thread_module_kernel_stack_end;     \
+                                            ULONG   tx_thread_module_kernel_stack_size;     \
+                                            VOID    *tx_thread_module_stack_ptr;            \
+                                            VOID    *tx_thread_module_stack_start;          \
+                                            VOID    *tx_thread_module_stack_end;            \
+                                            ULONG   tx_thread_module_stack_size;            \
+                                            VOID    *tx_thread_module_reserved;
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       b =  (UINT) __builtin_ctz((unsigned int) m);
+
+#endif
+
+
+/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout
+   can figure out what thread timeout to process.  */
+   
+#define TX_TIMER_INTERNAL_EXTENSION             VOID    *tx_timer_internal_thread_timeout_ptr;
+
+
+/* Define the thread timeout setup logic in _tx_thread_create.  */
+
+#define TX_THREAD_CREATE_TIMEOUT_SETUP(t)    (t) -> tx_thread_timer.tx_timer_internal_timeout_function =    &(_tx_thread_timeout);            \
+                                             (t) -> tx_thread_timer.tx_timer_internal_timeout_param =       0;                                \
+                                             (t) -> tx_thread_timer.tx_timer_internal_thread_timeout_ptr =  (VOID *) (t);
+
+
+/* Define the thread timeout pointer setup in _tx_thread_timeout.  */
+
+#define TX_THREAD_TIMEOUT_POINTER_SETUP(t)   (t) =  (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr;
+
+
+/************* Define ThreadX SMP data types and function prototypes.  *************/
+
+struct TX_THREAD_STRUCT;
+
+
+/* Define the ThreadX SMP protection structure.   */
+
+typedef struct TX_THREAD_SMP_PROTECT_STRUCT
+{
+    ULONG           tx_thread_smp_protect_in_force;
+    ULONG           tx_thread_smp_protect_core;
+    ULONG           tx_thread_smp_protect_count;
+    ULONG           tx_thread_smp_protect_pad_0;
+    ULONG           tx_thread_smp_protect_pad_1;
+    ULONG           tx_thread_smp_protect_pad_2;    
+    ULONG           tx_thread_smp_protect_pad_3;    
+} TX_THREAD_SMP_PROTECT;
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_smp_protect();
+#define TX_RESTORE                              _tx_thread_smp_unprotect(interrupt_save);
+
+/************* End ThreadX SMP data type and function prototype definitions.  *************/
+
+
+/* Define FP extension for the Cortex-A35.  Each is assumed to be called in the context of the executing
+   thread.  */
+
+#ifndef TX_SOURCE_CODE
+#define tx_thread_fp_enable                     _tx_thread_fp_enable
+#define tx_thread_fp_disable                    _tx_thread_fp_disable
+#endif
+
+VOID    tx_thread_fp_enable(VOID);
+VOID    tx_thread_fp_disable(VOID);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Modules Cortex-A35-SMP/AC6 Version 6.1.3 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
diff --git a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h
new file mode 100644
index 00000000..84d87ace
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h
@@ -0,0 +1,279 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
+/*                                                                        */
+/*    txm_module_port.h                                 Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file defines the basic module constants, interface structures, */
+/*    and function prototypes.                                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TXM_MODULE_PORT_H
+#define TXM_MODULE_PORT_H
+
+/* Determine if the optional Modules user define file should be used.  */
+
+#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in txm_module_user.h. The defines in this file may
+   alternately be defined on the command line.  */
+
+#include "txm_module_user.h"
+#endif
+
+/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
+  following extensions to the ThreadX thread control block (this code should replace
+  the corresponding macro define in tx_port.h):
+
+#define TX_THREAD_EXTENSION_2               VOID    *tx_thread_module_instance_ptr;         \
+                                            VOID    *tx_thread_module_entry_info_ptr;       \
+                                            ULONG   tx_thread_module_current_user_mode;     \
+                                            ULONG   tx_thread_module_user_mode;             \
+                                            ULONG   tx_thread_module_saved_lr;              \
+                                            VOID    *tx_thread_module_kernel_stack_start;   \
+                                            VOID    *tx_thread_module_kernel_stack_end;     \
+                                            ULONG   tx_thread_module_kernel_stack_size;     \
+                                            VOID    *tx_thread_module_stack_ptr;            \
+                                            VOID    *tx_thread_module_stack_start;          \
+                                            VOID    *tx_thread_module_stack_end;            \
+                                            ULONG   tx_thread_module_stack_size;            \
+                                            VOID    *tx_thread_module_reserved;
+
+The following extensions must also be defined in tx_port.h:
+
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+*/
+
+/* Define the kernel stack size for a module thread.  */
+#ifndef TXM_MODULE_KERNEL_STACK_SIZE
+#define TXM_MODULE_KERNEL_STACK_SIZE            768
+#endif
+
+/* Define constants specific to the tools the module can be built with for this particular modules port.  */
+
+#define TXM_MODULE_IAR_COMPILER                 0x00000000
+#define TXM_MODULE_RVDS_COMPILER                0x01000000
+#define TXM_MODULE_GNU_COMPILER                 0x02000000
+#define TXM_MODULE_COMPILER_MASK                0xFF000000
+#define TXM_MODULE_OPTIONS_MASK                 0x000000FF
+
+
+/* Define the properties for this particular module port.  */
+
+#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
+
+#ifdef  TXM_MODULE_MEMORY_PROTECTION_ENABLED
+#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
+#else
+#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
+#endif
+
+#define TXM_MODULE_USER_MODE                        0x00000001
+#define TXM_MODULE_MEMORY_PROTECTION                0x00000002
+#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS    0x00000004
+
+
+/* Define the supported options for this module.   */
+
+#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS    (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
+#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS     0
+
+
+/* Define offset adjustments according to the compiler used to build the module.  */
+
+#define TXM_MODULE_IAR_SHELL_ADJUST             24
+#define TXM_MODULE_IAR_START_ADJUST             28
+#define TXM_MODULE_IAR_STOP_ADJUST              32
+#define TXM_MODULE_IAR_CALLBACK_ADJUST          44
+
+#define TXM_MODULE_RVDS_SHELL_ADJUST            0
+#define TXM_MODULE_RVDS_START_ADJUST            0
+#define TXM_MODULE_RVDS_STOP_ADJUST             0
+#define TXM_MODULE_RVDS_CALLBACK_ADJUST         0
+
+#define TXM_MODULE_GNU_SHELL_ADJUST             24
+#define TXM_MODULE_GNU_START_ADJUST             28
+#define TXM_MODULE_GNU_STOP_ADJUST              32
+#define TXM_MODULE_GNU_CALLBACK_ADJUST          44
+
+
+/* Define other module port-specific constants.  */
+
+/* Define the port-extensions to the module manager instance structure.  */
+
+#define TXM_MODULE_MANAGER_PORT_EXTENSION
+
+
+/* Define the memory fault information structure that is populated when a memory fault occurs.  */
+
+typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
+{
+    TX_THREAD           *txm_module_manager_memory_fault_info_thread_ptr;
+    VOID                *txm_module_manager_memory_fault_info_code_location;
+    ULONG               txm_module_manager_memory_fault_info_shcsr;
+    ULONG               txm_module_manager_memory_fault_info_cfsr;
+    ULONG               txm_module_manager_memory_fault_info_mmfar;
+    ULONG               txm_module_manager_memory_fault_info_bfar;
+    ULONG               txm_module_manager_memory_fault_info_control;
+    ULONG               txm_module_manager_memory_fault_info_sp;
+    ULONG               txm_module_manager_memory_fault_info_r0;
+    ULONG               txm_module_manager_memory_fault_info_r1;
+    ULONG               txm_module_manager_memory_fault_info_r2;
+    ULONG               txm_module_manager_memory_fault_info_r3;
+    ULONG               txm_module_manager_memory_fault_info_r4;
+    ULONG               txm_module_manager_memory_fault_info_r5;
+    ULONG               txm_module_manager_memory_fault_info_r6;
+    ULONG               txm_module_manager_memory_fault_info_r7;
+    ULONG               txm_module_manager_memory_fault_info_r8;
+    ULONG               txm_module_manager_memory_fault_info_r9;
+    ULONG               txm_module_manager_memory_fault_info_r10;
+    ULONG               txm_module_manager_memory_fault_info_r11;
+    ULONG               txm_module_manager_memory_fault_info_r12;
+    ULONG               txm_module_manager_memory_fault_info_lr;
+    ULONG               txm_module_manager_memory_fault_info_xpsr;
+} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
+
+
+#define TXM_MODULE_MANAGER_FAULT_INFO                                               \
+    TXM_MODULE_MANAGER_MEMORY_FAULT_INFO    _txm_module_manager_memory_fault_info;
+
+/* Define the macro to check the code alignment.  */
+
+#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment)    \
+    {                                                                               \
+        ALIGN_TYPE   temp;                                                          \
+        temp =  (ALIGN_TYPE) module_location;                                       \
+        temp =  temp & (code_alignment - 1);                                        \
+        if (temp)                                                                   \
+        {                                                                           \
+            _tx_mutex_put(&_txm_module_manager_mutex);                              \
+            return(TXM_MODULE_ALIGNMENT_ERROR);                                     \
+        }                                                                           \
+    }
+
+
+/* Define the macro to adjust the alignment and size for code/data areas.  */
+
+#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) \
+    {                                                                                                              \
+        code_size = (code_size % 32) ? ((code_size + 32) & ~32) : (code_size);                                     \
+        code_alignment = 32;                                                                                       \
+        data_size = (data_size % 32) ? ((data_size + 32) & ~32) : (data_size);                                     \
+        data_alignment = 32;                                                                                       \
+    }
+
+
+/* Define the macro to adjust the symbols in the module preamble.  */
+
+#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
+    if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER)         \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_IAR_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_IAR_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_IAR_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_IAR_CALLBACK_ADJUST;                 \
+    }                                                                               \
+    else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER)   \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_RVDS_SHELL_ADJUST;                   \
+        start_function_adjust =     TXM_MODULE_RVDS_START_ADJUST;                   \
+        stop_function_adjust =      TXM_MODULE_RVDS_STOP_ADJUST;                    \
+        callback_function_adjust =  TXM_MODULE_RVDS_CALLBACK_ADJUST;                \
+    }                                                                               \
+    else                                                                            \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_GNU_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_GNU_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_GNU_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_GNU_CALLBACK_ADJUST;                 \
+    }
+
+
+/* Define the macro to populate the thread control block with module port-specific information.
+   Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
+*/
+
+#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance)                                                                    \
+    thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher =   _txm_module_manager_kernel_dispatch;
+
+
+/* Define the macro to populate the module control block with module port-specific information.
+*/
+#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance)
+
+
+/* Define the macro to perform port-specific functions when unloading the module.  */
+/* Nothing needs to be done for this port.  */
+#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
+
+
+/* Define the macros to perform port-specific checks when passing pointers to the kernel.  */
+
+/* Define macro to make sure object is inside the module's data.  */
+#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) (TX_SUCCESS)
+
+/* Define some internal prototypes to this module port.  */
+
+#ifndef TX_SOURCE_CODE
+#define txm_module_manager_memory_fault_notify              _txm_module_manager_memory_fault_notify
+#endif
+
+
+#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES                                                                                                                      \
+VOID  _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment);   \
+ULONG _txm_module_manager_region_size_get(ULONG block_size);                                                                                                          \
+UINT  _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);                                                 \
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2);
+
+#define TXM_MODULE_MANAGER_VERSION_ID   \
+CHAR                            _txm_module_manager_version_id[] =  \
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Module Cortex-A35/AC6 Version 6.1.3 *";
+
+#endif
diff --git a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S
new file mode 100644
index 00000000..86c3aa4b
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S
@@ -0,0 +1,63 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TXM_MODULE_HEAP_SIZE 512
+
+    .text
+
+// module entry point
+    .align 3
+    .global _txm_module_initialize
+_txm_module_initialize:
+    sub     sp, sp, 16
+    str     x30, [sp]
+    B       __main
+
+// main function called by the C library
+    .align 3
+    .global main
+main:
+    // Do nothing
+    RET
+
+// custom exit, return to the initialization caller
+    .align 3
+    .global exit
+exit:
+    ldr     x30, [sp]
+    add     sp, sp, 16
+    RET
+
+// returns heap start address in  R0
+// returns heap end address in    R2
+// does not touch SP, it is already set up before the module runs
+    .align 3
+    .global __user_setup_stackheap
+__user_setup_stackheap:
+    LDR     x0, =_txm_heap                      // load heap offset
+    MOV     x2, TXM_MODULE_HEAP_SIZE            // load heap size
+    ADD     x2, x2, x0                          // calculate heap end address
+    RET
+
+    .align 8
+_txm_heap:
+    .zero   TXM_MODULE_HEAP_SIZE
diff --git a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c
new file mode 100644
index 00000000..6153e2f7
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c
@@ -0,0 +1,172 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#ifndef TXM_MODULE
+#define TXM_MODULE
+#endif
+
+#ifndef TX_SOURCE_CODE
+#define TX_SOURCE_CODE
+#endif
+
+
+/* Include necessary system files.  */
+
+#include "txm_module.h"
+#include "tx_thread.h"
+
+/* Define the global module entry pointer from the start thread of the module.  */
+
+TXM_MODULE_THREAD_ENTRY_INFO    *_txm_module_entry_info;
+
+
+/* Define the dispatch function pointer used in the module implementation.  */
+
+ALIGN_TYPE                      (*_txm_module_kernel_call_dispatcher)(ULONG type, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param3);
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_thread_shell_entry                   Cortex-A35/AC6     */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function calls the specified entry function of the thread.  It */
+/*    also provides a place for the thread's entry function to return.    */
+/*    If the thread returns, this function places the thread in a         */
+/*    "COMPLETED" state.                                                  */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                        Pointer to current thread         */
+/*    thread_info                       Pointer to thread entry info      */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_initialize            cstartup initialization           */
+/*    thread_entry                      Thread's entry function           */
+/*    tx_thread_resume                  Resume the module callback thread */
+/*    _txm_module_thread_system_suspend Module thread suspension routine  */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Initial thread stack frame                                          */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
+{
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+VOID            (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type);
+#endif
+
+
+    /* Perform any additional activities for tool or user purpose.  */
+    TX_THREAD_STARTED_EXTENSION(thread_ptr)
+
+    /* Determine if this is the start thread.  If so, we must prepare the module for
+       execution.  If not, simply skip the C startup code.  */
+    if (thread_info -> txm_module_thread_entry_info_start_thread)
+    {
+        /* Initialize the C library */
+        extern void _txm_module_initialize(void);
+        _txm_module_initialize();
+
+        /* Save the entry info pointer, for later use.  */
+        _txm_module_entry_info =  thread_info;
+
+        /* Save the kernel function dispatch address. This is used to make all resident calls from
+           the module.  */
+        _txm_module_kernel_call_dispatcher =  thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
+
+        /* Ensure that we have a valid pointer.  */
+        while (!_txm_module_kernel_call_dispatcher)
+        {
+            /* Loop here, if an error is present getting the dispatch function pointer!
+               An error here typically indicates the resident portion of _tx_thread_schedule
+               is not supporting the trap to obtain the function pointer.   */
+        }
+        
+        /* Resume the module's callback thread, already created in the manager.  */
+        _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
+    }
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Pickup the entry/exit application callback routine.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has been entered!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
+    }
+#endif
+
+    /* Call current thread's entry function.  */
+    (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
+
+    /* Suspend thread with a "completed" state.  */
+
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Pickup the entry/exit application callback routine again.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has exited!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
+    }
+#endif
+
+    /* Call actual thread suspension routine.  */
+    _txm_module_thread_system_suspend(thread_ptr);
+
+#ifdef TX_SAFETY_CRITICAL
+
+    /* If we ever get here, raise safety critical exception.  */
+    TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
+#endif
+}
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S
new file mode 100644
index 00000000..2ed464af
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S
@@ -0,0 +1,102 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_initialize_low_level                         Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for any low-level processor            */
+/*    initialization, including setting up interrupt vectors, setting     */
+/*    up a periodic timer interrupt source, saving the system stack       */
+/*    pointer for use in ISR processing later, and finding the first      */
+/*    available RAM memory address for tx_application_define.             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_initialize_low_level(VOID)
+// {
+    .global  _tx_initialize_low_level
+    .type    _tx_initialize_low_level, @function
+_tx_initialize_low_level:
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+
+    /* Save the system stack pointer.  */
+    // _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
+
+    LDR     x0, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    MOV     x1, sp                              // Pickup SP
+    SUB     x1, x1, #15                         //
+    BIC     x1, x1, #0xF                        // Get 16-bit alignment
+    STR     x1, [x0]                            // Store system stack
+
+    /* Save the first available memory address.  */
+    // _tx_initialize_unused_memory =  (VOID_PTR) Image$$HEAP$$ZI$$Limit;
+
+    LDR     x0, =_tx_initialize_unused_memory   // Pickup address of unused memory ptr
+    LDR     x1, =heap_limit                     // Pickup unused memory address - A free
+    LDR     x1, [x1]                            //   memory section must be setup after the
+                                                //   heap section.
+    STR     x1, [x0]                            // Store unused memory address
+
+    /* Done, return to caller.  */
+
+    RET                                         // Return to caller
+// }
+
+    .align 3
+heap_limit:
+    .quad (Image$$TOP_OF_RAM$$ZI$$Limit)
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..56f748f9
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S
@@ -0,0 +1,380 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* Include macros for modifying the wait list.  */
+#include "tx_thread_smp_protection_wait_list_macros.h"
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_restore                       Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function restores the interrupt context if it is processing a  */
+/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+/*    if no thread was running, the function returns to the scheduler.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling routine     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                  Interrupt Service Routines    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_restore(VOID)
+// {
+    .global _tx_thread_context_restore
+    .type   _tx_thread_context_restore, @function
+_tx_thread_context_restore:
+
+    /* Lockout interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR exit function to indicate an ISR is complete.  */
+
+    BL      _tx_execution_isr_exit              // Call the ISR exit function
+#endif
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x8, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x2, x8, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x8, x8, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x8, x8, x2, LSL #2                  // Calculate CPU ID
+#endif
+
+    /* Determine if interrupts are nested.  */
+    // if (--_tx_thread_system_state)
+    // {
+
+    LDR     x3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     w2, [x3, x8, LSL #2]                // Pickup system state
+    SUB     w2, w2, #1                          // Decrement the counter
+    STR     w2, [x3, x8, LSL #2]                // Store the counter 
+    CMP     w2, #0                              // Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      // If so, not a nested restore
+
+    /* Interrupts are nested.  */
+
+    /* Just recover the saved registers and return to the point of 
+       interrupt.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+    // }
+__tx_thread_not_nested_restore:
+
+    /* Determine if a thread was interrupted and no preemption is required.  */
+    // else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
+    //           || (_tx_thread_preempt_disable))
+    // {
+
+    LDR     x1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     x0, [x1, x8, LSL #3]                // Pickup actual current thread pointer
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     // Yes, idle system was interrupted
+    LDR     x3, =_tx_thread_execute_ptr         // Pickup address of execute thread ptr
+    LDR     x2, [x3, x8, LSL #3]                // Pickup actual execute thread pointer
+    CMP     x0, x2                              // Is the same thread highest priority?
+    BEQ     __tx_thread_no_preempt_restore      // Same thread in the execute list, 
+                                                //   no preemption needs to happen
+    LDR     x3, =_tx_thread_smp_protection      // Build address to protection structure
+    LDR     w3, [x3, #4]                        // Pickup the owning core
+    CMP     w3, w8                              // Is it this core?
+    BNE     __tx_thread_preempt_restore         // No, proceed to preempt thread
+
+    LDR     x3, =_tx_thread_preempt_disable     // Pickup preempt disable address
+    LDR     w2, [x3, #0]                        // Pickup actual preempt disable flag
+    CMP     w2, #0                              // Is it set?
+    BEQ     __tx_thread_preempt_restore         // No, okay to preempt this thread
+
+__tx_thread_no_preempt_restore:
+
+    /* Restore interrupted thread or ISR.  */
+
+    /* Pickup the saved stack pointer.  */
+    // sp =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+
+    LDR     x4, [x0, #8]                        // Switch to thread stack pointer
+    MOV     sp, x4                              //
+
+   /* Recover the saved context and return to the point of interrupt.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+    // }
+    // else
+    // {
+__tx_thread_preempt_restore:
+
+    /* Was the thread being preempted waiting for the lock?  */
+    // if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
+    // {
+
+    LDR     x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
+    LDR     w3, [x2, x8, LSL #2]                // Load waiting value for this core
+    CMP     w3, #0
+    BEQ     _nobody_waiting_for_lock            // Is the core waiting for the lock?
+
+    /* Do we not have the lock? This means the ISR never got the inter-core lock.  */
+    // if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
+    // {
+
+    LDR     x2, =_tx_thread_smp_protection      // Load address of protection structure
+    LDR     w3, [x2, #4]                        // Pickup the owning core
+    CMP     w8, w3                              // Compare our core to the owning core
+    BEQ     _this_core_has_lock                 // Do we have the lock?
+
+    /* We don't have the lock. This core should be in the list. Remove it.  */
+    // _tx_thread_smp_protect_wait_list_remove(this_core);
+
+    _tx_thread_smp_protect_wait_list_remove     // Call macro to remove core from the list
+    B       _nobody_waiting_for_lock            // Leave
+
+    // }
+    // else
+    // {
+    /* We have the lock. This means the ISR got the inter-core lock, but
+       never released it because it saw that there was someone waiting.
+       Note this core is not in the list.  */
+
+_this_core_has_lock:
+
+    /* We're no longer waiting. Note that this should be zero since this happens during thread preemption.  */
+    // _tx_thread_smp_protect_wait_counts[core]--;
+
+    LDR     x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
+    LDR     w3, [x2, x8, LSL #2]                // Load waiting value for this core
+    SUB     w3, w3, #1                          // Decrement waiting value. Should be zero now
+    STR     w3, [x2, x8, LSL #2]                // Store new waiting value
+
+    /* Now release the inter-core lock.  */
+
+    /* Set protected core as invalid.  */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
+
+    LDR     x2, =_tx_thread_smp_protection      // Load address of protection structure
+    MOV     w3, #0xFFFFFFFF                     // Build invalid value
+    STR     w3, [x2, #4]                        // Mark the protected core as invalid
+    DMB     ISH                                 // Ensure that accesses to shared resource have completed
+
+    /* Release protection.  */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
+
+    MOV     w3, #0                              // Build release protection value
+    STR     w3, [x2, #0]                        // Release the protection
+    DSB     ISH                                 // To ensure update of the protection occurs before other CPUs awake
+
+    /* Wake up waiting processors. Note interrupts are already enabled.  */
+
+#ifdef TX_ENABLE_WFE
+    SEV                                         // Send event to other CPUs
+#endif
+
+      // }
+    // }
+
+_nobody_waiting_for_lock:
+
+    LDR     x4, [x0, #8]                        // Switch to thread stack pointer
+    MOV     sp, x4                              //
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+    STP     x20, x21, [sp, #-16]!               // Save x20, x21
+    STP     x22, x23, [sp, #-16]!               // Save x22, x23
+    STP     x24, x25, [sp, #-16]!               // Save x24, x25
+    STP     x26, x27, [sp, #-16]!               // Save x26, x27
+    STP     x28, x29, [sp, #-16]!               // Save x28, x29
+#ifdef ENABLE_ARM_FP
+    LDR     w3, [x0, #268]                      // Pickup FP enable flag
+    CMP     w3, #0                              // Is FP enabled?
+    BEQ     _skip_fp_save                       // No, skip FP save
+    STP     q0,  q1,  [sp, #-32]!               // Save q0, q1
+    STP     q2,  q3,  [sp, #-32]!               // Save q2, q3
+    STP     q4,  q5,  [sp, #-32]!               // Save q4, q5
+    STP     q6,  q7,  [sp, #-32]!               // Save q6, q7
+    STP     q8,  q9,  [sp, #-32]!               // Save q8, q9
+    STP     q10, q11, [sp, #-32]!               // Save q10, q11
+    STP     q12, q13, [sp, #-32]!               // Save q12, q13
+    STP     q14, q15, [sp, #-32]!               // Save q14, q15
+    STP     q16, q17, [sp, #-32]!               // Save q16, q17
+    STP     q18, q19, [sp, #-32]!               // Save q18, q19
+    STP     q20, q21, [sp, #-32]!               // Save q20, q21
+    STP     q22, q23, [sp, #-32]!               // Save q22, q23
+    STP     q24, q25, [sp, #-32]!               // Save q24, q25
+    STP     q26, q27, [sp, #-32]!               // Save q26, q27
+    STP     q28, q29, [sp, #-32]!               // Save q28, q29
+    STP     q30, q31, [sp, #-32]!               // Save q30, q31
+    MRS     x2, FPSR                            // Pickup FPSR
+    MRS     x3, FPCR                            // Pickup FPCR
+    STP     x2, x3, [sp, #-16]!                 // Save FPSR, FPCR
+_skip_fp_save:
+#endif
+    STP     x4, x5, [sp, #-16]!                 // Save x4 (SPSR_EL3), x5 (ELR_E3)
+
+    MOV     x3, sp                              // Move sp into x3
+    STR     x3, [x0, #8]                        // Save stack pointer in thread control
+                                                //   block
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, x8, LSL #3]                // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+
+    /* Save the remaining time-slice and disable it.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    LDR     x3, =_tx_timer_time_slice           // Pickup time-slice variable address
+    LDR     w2, [x3, x8, LSL #2]                // Pickup time-slice
+    CMP     w2, #0                              // Is it active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save it
+
+        /* _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+        _tx_timer_time_slice =  0;  */
+
+    STR     w2, [x0, #36]                       // Save thread's time-slice
+    MOV     w2, #0                              // Clear value
+    STR     w2, [x3, x8, LSL #2]                // Disable global time-slice flag
+
+    // }
+__tx_thread_dont_save_ts:
+
+
+    /* Clear the current task pointer.  */
+    // _tx_thread_current_ptr =  TX_NULL;
+
+    MOV     x2, #0                              // NULL value
+    STR     x2, [x1, x8, LSL #3]                // Clear current thread pointer
+
+    /* Set bit indicating this thread is ready for execution.  */
+
+    MOV     x2, #1                              // Build ready flag
+    STR     w2, [x0, #260]                      // Set thread's ready flag
+    DMB     ISH                                 // Ensure that accesses to shared resource have completed
+
+    /* Return to the scheduler.  */
+    // _tx_thread_schedule();
+
+    // }
+
+__tx_thread_idle_system_restore:
+
+    /* Just return back to the scheduler!  */
+
+    LDR    x1, =_tx_thread_schedule             // Build address for _tx_thread_schedule
+#ifdef EL1
+    MSR    ELR_EL1, x1                          // Setup point of interrupt
+//    MOV    x1, #0x4                             // Setup EL1 return
+//    MSR    spsr_el1, x1                         // Move into SPSR
+#else
+#ifdef EL2
+    MSR    ELR_EL2, x1                          // Setup point of interrupt
+//    MOV    x1, #0x8                             // Setup EL2 return
+//    MSR    spsr_el2, x1                         // Move into SPSR
+#else
+    MSR    ELR_EL3, x1                          // Setup point of interrupt
+//    MOV    x1, #0xC                             // Setup EL3 return
+//    MSR    spsr_el3, x1                         // Move into SPSR
+#endif
+#endif
+    ERET                                        // Return to scheduler
+// }
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S
new file mode 100644
index 00000000..533d0eb1
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S
@@ -0,0 +1,238 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_save                          Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves the context of an executing thread in the       */
+/*    beginning of interrupt processing.  The function also ensures that  */
+/*    the system stack is used upon return to the calling ISR.            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_save(VOID)
+// {
+    .global _tx_thread_context_save
+    .type   _tx_thread_context_save, @function
+_tx_thread_context_save:
+
+    /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked
+       out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, 
+       and all other registers are intact.  */
+
+    /* Check for a nested interrupt condition.  */
+    // if (_tx_thread_system_state++)
+    // {
+
+    STP     x0, x1, [sp, #-16]!                 // Save x0, x1
+    STP     x2, x3, [sp, #-16]!                 // Save x2, x3
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x2, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x2, LSL #2                  // Calculate CPU ID
+#endif
+
+    LDR     x3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     w2, [x3, x1, LSL #2]                // Pickup system state
+    CMP     w2, #0                              // Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         // Yes, not a nested context save
+
+    /* Nested interrupt condition.  */
+
+    ADD     w2, w2, #1                          // Increment the nested interrupt counter
+    STR     w2, [x3, x1, LSL #2]                // Store it back in the variable
+
+   /* Save the rest of the scratch registers on the stack and return to the
+      calling ISR.  */
+
+    STP     x4, x5, [sp, #-16]!                 // Save x4, x5
+    STP     x6, x7, [sp, #-16]!                 // Save x6, x7
+    STP     x8, x9, [sp, #-16]!                 // Save x8, x9
+    STP     x10, x11, [sp, #-16]!               // Save x10, x11
+    STP     x12, x13, [sp, #-16]!               // Save x12, x13
+    STP     x14, x15, [sp, #-16]!               // Save x14, x15
+    STP     x16, x17, [sp, #-16]!               // Save x16, x17
+    STP     x18, x19, [sp, #-16]!               // Save x18, x19
+#ifdef EL1
+    MRS     x0, SPSR_EL1                        // Pickup SPSR
+    MRS     x1, ELR_EL1                         // Pickup ELR (point of interrupt)
+#else
+#ifdef EL2
+    MRS     x0, SPSR_EL2                        // Pickup SPSR
+    MRS     x1, ELR_EL2                         // Pickup ELR (point of interrupt)
+#else
+    MRS     x0, SPSR_EL3                        // Pickup SPSR
+    MRS     x1, ELR_EL3                         // Pickup ELR (point of interrupt)
+#endif
+#endif
+    STP     x0, x1, [sp, #-16]!                 // Save SPSR, ELR
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    /* Return to the ISR.  */
+
+    RET                                         // Return to ISR
+
+__tx_thread_not_nested_save:
+    // }
+
+    /* Otherwise, not nested, check to see if a thread was running.  */
+    // else if (_tx_thread_current_ptr)
+    // {
+
+    ADD     w2, w2, #1                          // Increment the interrupt counter
+    STR     w2, [x3, x1, LSL #2]                // Store it back in the variable
+    LDR     x2, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     x0, [x2, x1, LSL #3]                // Pickup current thread pointer
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_save        // If so, interrupt occurred in 
+                                                //   scheduling loop - nothing needs saving!
+
+    /* Save minimal context of interrupted thread.  */
+
+    STP     x4, x5, [sp, #-16]!                 // Save x4, x5
+    STP     x6, x7, [sp, #-16]!                 // Save x6, x7
+    STP     x8, x9, [sp, #-16]!                 // Save x8, x9
+    STP     x10, x11, [sp, #-16]!               // Save x10, x11
+    STP     x12, x13, [sp, #-16]!               // Save x12, x13
+    STP     x14, x15, [sp, #-16]!               // Save x14, x15
+    STP     x16, x17, [sp, #-16]!               // Save x16, x17
+    STP     x18, x19, [sp, #-16]!               // Save x18, x19
+#ifdef EL1
+    MRS     x4, SPSR_EL1                        // Pickup SPSR
+    MRS     x5, ELR_EL1                         // Pickup ELR (point of interrupt)
+#else
+#ifdef EL2
+    MRS     x4, SPSR_EL2                        // Pickup SPSR
+    MRS     x5, ELR_EL2                         // Pickup ELR (point of interrupt)
+#else
+    MRS     x4, SPSR_EL3                        // Pickup SPSR
+    MRS     x5, ELR_EL3                         // Pickup ELR (point of interrupt)
+#endif
+#endif
+    STP     x4, x5, [sp, #-16]!                 // Save SPSR, ELR
+
+    /* Save the current stack pointer in the thread's control block.  */
+    // _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+
+    MOV     x4, sp                              //
+    STR     x4, [x0, #8]                        // Save thread stack pointer
+
+    /* Switch to the system stack.  */
+    // sp =  _tx_thread_system_stack_ptr
+
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x2, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x2, LSL #2                  // Calculate CPU ID
+#endif
+
+    LDR     x4, [x3, x1, LSL #3]                // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    RET                                         // Return to caller
+
+    // }
+    // else
+    // {
+
+__tx_thread_idle_system_save:
+
+    /* Interrupt occurred in the scheduling loop.  */
+
+    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+       processing.  */
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    ADD     sp, sp, #48                         // Recover saved registers
+    RET                                         // Continue IRQ processing  
+
+    // }
+// } 
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c
new file mode 100644
index 00000000..e1ac7c10
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c
@@ -0,0 +1,94 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fp_disable                            Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function disables the FP for the currently executing thread.   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_fp_disable(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+ULONG       system_state;
+
+
+    /* Pickup the current thread pointer.  */
+    TX_THREAD_GET_CURRENT(thread_ptr);
+
+    /* Get the system state.  */
+    system_state =  TX_THREAD_GET_SYSTEM_STATE();
+
+    /* Make sure it is not NULL. */
+    if (thread_ptr != TX_NULL)
+    {
+        
+        /* Thread is running... make sure the call is from the thread context.  */
+        if (system_state == 0)
+        {
+        
+            /* Yes, now set the FP enable flag to false in the TX_THREAD structure.  */
+            thread_ptr -> tx_thread_fp_enable =  TX_FALSE;
+        }
+    }
+}
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c
new file mode 100644
index 00000000..42dda958
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c
@@ -0,0 +1,94 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fp_enable                             Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function enabled the FP for the currently executing thread.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_fp_enable(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+ULONG       system_state;
+
+
+    /* Pickup the current thread pointer.  */
+    TX_THREAD_GET_CURRENT(thread_ptr);
+
+    /* Get the system state.  */
+    system_state =  TX_THREAD_GET_SYSTEM_STATE();
+
+    /* Make sure it is not NULL. */
+    if (thread_ptr != TX_NULL)
+    {
+        
+        /* Thread is running... make sure the call is from the thread context.  */
+        if (system_state == 0)
+        {
+        
+            /* Yes, now setup the FP enable flag in the TX_THREAD structure.  */
+            thread_ptr -> tx_thread_fp_enable =  TX_TRUE;
+        }
+    }
+}
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..c7bb966d
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S
@@ -0,0 +1,80 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_control                     Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for changing the interrupt lockout     */
+/*    posture of the system.                                              */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    new_posture                           New interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_control(UINT new_posture)
+// {
+    .global  _tx_thread_interrupt_control
+    .type    _tx_thread_interrupt_control, @function
+_tx_thread_interrupt_control:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     x1, DAIF                            // Pickup current interrupt posture
+
+    /* Apply the new interrupt posture.  */
+
+    MSR     DAIF, x0                            // Set new interrupt posture
+    MOV     x0, x1                              // Setup return value
+    RET                                         // Return to caller
+// }
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S
new file mode 100644
index 00000000..d2857bf4
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S
@@ -0,0 +1,78 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_disable                     Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for disabling interrupts               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_disable(void)
+// {
+    .global _tx_thread_interrupt_disable
+    .type   _tx_thread_interrupt_disable, @function
+_tx_thread_interrupt_disable:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     x0, DAIF                            // Pickup current interrupt lockout posture
+
+    /* Mask interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    RET                                         // Return to caller
+// }
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S
new file mode 100644
index 00000000..b231b06a
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S
@@ -0,0 +1,75 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_restore                     Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for restoring interrupts to the state  */
+/*    returned by a previous _tx_thread_interrupt_disable call.           */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_restore(UINT old_posture)
+// {
+    .global _tx_thread_interrupt_restore
+    .type   _tx_thread_interrupt_restore, @function
+_tx_thread_interrupt_restore:
+
+    /* Restore the old interrupt posture.  */
+
+    MSR     DAIF, x0                            // Setup the old posture
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S
new file mode 100644
index 00000000..9ce36bda
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S
@@ -0,0 +1,294 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_schedule                              Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function waits for a thread control block pointer to appear in */
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+/*    in the variable, the corresponding thread is resumed.               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+/*    _tx_thread_system_return             Return to system from thread   */
+/*    _tx_thread_context_restore           Restore thread's context       */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_schedule(VOID)
+// {
+    .global _tx_thread_schedule
+    .type   _tx_thread_schedule, @function
+_tx_thread_schedule:
+
+    /* Enable interrupts.  */
+
+    MSR     DAIFClr, 0x3                        // Enable interrupts
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x20, MPIDR_EL1                      // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x1, x20, #8, #8                     // Isolate cluster ID
+#endif
+    UBFX    x20, x20, #0, #8                    // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x20, x20, x1, LSL #2                // Calculate CPU ID
+#endif
+
+    /* Wait for a thread to execute.  */
+    // do
+    // {
+
+    LDR     x1, =_tx_thread_execute_ptr         // Address of thread execute ptr
+
+#ifdef TX_ENABLE_WFI
+__tx_thread_schedule_loop:
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    LDR     x0, [x1, x20, LSL #3]               // Pickup next thread to execute
+    CMP     x0, #0                              // Is it NULL?
+    BNE     _tx_thread_schedule_thread          //
+    MSR     DAIFClr, 0x3                        // Enable interrupts
+    WFI                                         //
+    B       __tx_thread_schedule_loop           // Keep looking for a thread
+_tx_thread_schedule_thread:
+#else
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    LDR     x0, [x1, x20, LSL #3]               // Pickup next thread to execute
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     _tx_thread_schedule                 // Keep looking for a thread
+#endif
+
+    // }
+    // while(_tx_thread_execute_ptr == TX_NULL);
+
+    /* Get the lock for accessing the thread's ready bit.  */
+
+    MOV     w2, #280                            // Build offset to the lock
+    ADD     x2, x0, x2                          // Get the address to the lock
+    LDAXR   w3, [x2]                            // Pickup the lock value
+    CMP     w3, #0                              // Check if it's available
+    BNE     _tx_thread_schedule                 // No, lock not available
+    MOV     w3, #1                              // Build the lock set value
+    STXR    w4, w3, [x2]                        // Try to get the lock
+    CMP     w4, #0                              // Check if we got the lock
+    BNE     _tx_thread_schedule                 // No, another core got it first
+    DMB     ISH                                 // Ensure write to lock completes
+
+    /* Now make sure the thread's ready bit is set.  */
+
+    LDR     w3, [x0, #260]                      // Pickup the thread ready bit
+    CMP     w3, #0                              // Is it set?
+    BNE     _tx_thread_ready_for_execution      // Yes, schedule the thread
+
+    /* The ready bit isn't set. Release the lock and jump back to the scheduler.  */
+
+    MOV     w3, #0                              // Build clear value
+    STR     w3, [x2]                            // Release the lock
+    DMB     ISH                                 // Ensure write to lock completes
+    B       _tx_thread_schedule                 // Jump back to the scheduler
+
+_tx_thread_ready_for_execution:
+
+    /* We have a thread to execute. */
+
+    /* Clear the ready bit and release the lock.  */
+
+    MOV     w3, #0                              // Build clear value
+    STR     w3, [x0, #260]                      // Store it back in the thread control block
+    DMB     ISH
+    MOV     w3, #0                              // Build clear value for the lock
+    STR     w3, [x2]                            // Release the lock
+    DMB     ISH
+
+    /* Setup the current thread pointer.  */
+    // _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+
+    LDR     x2, =_tx_thread_current_ptr         // Pickup address of current thread
+    STR     x0, [x2, x20, LSL #3]               // Setup current thread pointer
+
+    LDR     x1, [x1, x20, LSL #3]               // Reload the execute pointer
+    CMP     w0, w1                              // Did it change?
+    BEQ     _execute_pointer_did_not_change     // If not, skip handling
+
+    /* In the time between reading the execute pointer and assigning
+       it to the current pointer, the execute pointer was changed by
+       some external code.  If the current pointer was still null when
+       the external code checked if a core preempt was necessary, then
+       it wouldn't have done it and a preemption will be missed.  To
+       handle this, undo some things and jump back to the scheduler so
+       it can schedule the new thread.  */
+
+    MOV     w1, #0                              // Build clear value
+    STR     x1, [x2, x20, LSL #3]               // Clear current thread pointer
+
+    MOV     w1, #1                              // Build set value
+    STR     w1, [x0, #260]                      // Re-set the ready bit
+    DMB     ISH                                 //
+
+    B       _tx_thread_schedule                 // Jump back to the scheduler to schedule the new thread
+
+_execute_pointer_did_not_change:
+    /* Increment the run count for this thread.  */
+    // _tx_thread_current_ptr -> tx_thread_run_count++;
+
+    LDR     w2, [x0, #4]                        // Pickup run counter
+    LDR     w3, [x0, #36]                       // Pickup time-slice for this thread
+    ADD     w2, w2, #1                          // Increment thread run-counter
+    STR     w2, [x0, #4]                        // Store the new run counter
+
+    /* Setup time-slice, if present.  */
+    // _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+
+    LDR     x2, =_tx_timer_time_slice           // Pickup address of time slice
+                                                //   variable
+    LDR     x4, [x0, #8]                        // Switch stack pointers
+    MOV     sp, x4                              //
+    STR     w3, [x2, x20, LSL #2]               // Setup time-slice
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread entry function to indicate the thread is executing.  */
+
+    MOV     x19, x0                             // Save x0
+    BL      _tx_execution_thread_enter          // Call the thread execution enter function
+    MOV     x0, x19                             // Restore x0
+#endif
+
+    /* Switch to the thread's stack.  */
+    // sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+
+    /* Determine if an interrupt frame or a synchronous task suspension frame
+       is present.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+    CMP     x5, #0                              // Check for synchronous context switch (ELR_EL1 = NULL)
+    BEQ     _tx_solicited_return
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+#ifdef ENABLE_ARM_FP
+    LDR     w1, [x0, #268]                      // Pickup FP enable flag
+    CMP     w1, #0                              // Is FP enabled?
+    BEQ     _skip_interrupt_fp_restore          // No, skip FP restore
+    LDP     x0, x1,   [sp], #16                 // Pickup FPSR, FPCR
+    MSR     FPSR, x0                            // Recover FPSR
+    MSR     FPCR, x1                            // Recover FPCR
+    LDP     q30, q31, [sp], #32                 // Recover q30, q31
+    LDP     q28, q29, [sp], #32                 // Recover q28, q29
+    LDP     q26, q27, [sp], #32                 // Recover q26, q27
+    LDP     q24, q25, [sp], #32                 // Recover q24, q25
+    LDP     q22, q23, [sp], #32                 // Recover q22, q23
+    LDP     q20, q21, [sp], #32                 // Recover q20, q21
+    LDP     q18, q19, [sp], #32                 // Recover q18, q19
+    LDP     q16, q17, [sp], #32                 // Recover q16, q17
+    LDP     q14, q15, [sp], #32                 // Recover q14, q15
+    LDP     q12, q13, [sp], #32                 // Recover q12, q13
+    LDP     q10, q11, [sp], #32                 // Recover q10, q11
+    LDP     q8,  q9,  [sp], #32                 // Recover q8, q9
+    LDP     q6,  q7,  [sp], #32                 // Recover q6, q7
+    LDP     q4,  q5,  [sp], #32                 // Recover q4, q5
+    LDP     q2,  q3,  [sp], #32                 // Recover q2, q3
+    LDP     q0,  q1,  [sp], #32                 // Recover q0, q1
+_skip_interrupt_fp_restore:
+#endif
+    LDP     x28, x29, [sp], #16                 // Recover x28
+    LDP     x26, x27, [sp], #16                 // Recover x26, x27
+    LDP     x24, x25, [sp], #16                 // Recover x24, x25
+    LDP     x22, x23, [sp], #16                 // Recover x22, x23
+    LDP     x20, x21, [sp], #16                 // Recover x20, x21
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+_tx_solicited_return:
+
+#ifdef ENABLE_ARM_FP
+    LDR     w1, [x0, #268]                      // Pickup FP enable flag
+    CMP     w1, #0                              // Is FP enabled?
+    BEQ     _skip_solicited_fp_restore          // No, skip FP restore
+    LDP     x0, x1,   [sp], #16                 // Pickup FPSR, FPCR
+    MSR     FPSR, x0                            // Recover FPSR
+    MSR     FPCR, x1                            // Recover FPCR
+    LDP     q14, q15, [sp], #32                 // Recover q14, q15
+    LDP     q12, q13, [sp], #32                 // Recover q12, q13
+    LDP     q10, q11, [sp], #32                 // Recover q10, q11
+    LDP     q8,  q9,  [sp], #32                 // Recover q8, q9
+_skip_solicited_fp_restore:
+#endif
+    LDP     x27, x28, [sp], #16                 // Recover x27, x28
+    LDP     x25, x26, [sp], #16                 // Recover x25, x26
+    LDP     x23, x24, [sp], #16                 // Recover x23, x24
+    LDP     x21, x22, [sp], #16                 // Recover x21, x22
+    LDP     x19, x20, [sp], #16                 // Recover x19, x20
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    MSR     DAIF, x4                            // Recover DAIF
+    RET                                         // Return to caller
+// }
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S
new file mode 100644
index 00000000..66532220
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S
@@ -0,0 +1,74 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_core_get                          Cortex-A35-SMP/AC6 */
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function gets the currently running core number and returns it.*/
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    Core ID                                                             */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_core_get
+    .type    _tx_thread_smp_core_get, @function
+_tx_thread_smp_core_get:
+    MRS     x0, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x1, x0, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x0, x0, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x0, x0, x1, LSL #2                  // Calculate CPU ID
+#endif
+    RET
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S
new file mode 100644
index 00000000..99e66b30
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S
@@ -0,0 +1,75 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_core_preempt                      Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function preempts the specified core in situations where the   */
+/*    thread corresponding to this core is no longer ready or when the    */
+/*    core must be used for a higher-priority thread. If the specified is */
+/*    the current core, this processing is skipped since the will give up */
+/*    control subsequently on its own.                                    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    core                                  The core to preempt           */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_core_preempt
+    .type    _tx_thread_smp_core_preempt, @function
+_tx_thread_smp_core_preempt:
+    DSB ISH
+    MOV x2, #0x1                                //
+    LSL x2, x2, x0                              // Shift by the core ID
+    MSR ICC_SGI1R_EL1, x2                       // Issue inter-core interrupt
+    RET
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S
new file mode 100644
index 00000000..8e2208c5
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S
@@ -0,0 +1,80 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_current_state_get                 Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is gets the current state of the calling core.        */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_current_state_get
+    .type    _tx_thread_smp_current_state_get, @function
+_tx_thread_smp_current_state_get:
+
+    MRS     x1, DAIF                            // Pickup current interrupt posture
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    MRS     x2, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x2, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x2, x2, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x2, x2, x3, LSL #2                  // Calculate CPU ID
+#endif
+    LDR     x3, =_tx_thread_system_state        // Pickup the base of the current system state array
+    LDR     w0, [x3, x2, LSL #2]                // Pickup the current system state for this core
+    MSR     DAIF, x1                            // Restore interrupt posture
+    RET
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S
new file mode 100644
index 00000000..45d36825
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S
@@ -0,0 +1,80 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_current_thread_get                Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is gets the current thread of the calling core.       */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_current_thread_get
+    .type    _tx_thread_smp_current_thread_get, @function
+_tx_thread_smp_current_thread_get:
+
+    MRS     x1, DAIF                            // Pickup current interrupt posture
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    MRS     x2, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x2, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x2, x2, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x2, x2, x3, LSL #2                  // Calculate CPU ID
+#endif
+    LDR     x3, =_tx_thread_current_ptr         // Pickup the base of the current thread pointer array
+    LDR     x0, [x3, x2, LSL #3]                // Pickup the current thread pointer for this core
+    MSR     DAIF, x1                            // Restore interrupt posture
+    RET
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S
new file mode 100644
index 00000000..6e25dff4
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S
@@ -0,0 +1,130 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_initialize_wait                   Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is the place where additional cores wait until        */
+/*    initialization is complete before they enter the thread scheduling  */
+/*    loop.                                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling loop        */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Hardware                                                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_initialize_wait
+    .type    _tx_thread_smp_initialize_wait, @function
+_tx_thread_smp_initialize_wait:
+
+    /* Lockout interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    /* Pickup the Core ID.   */
+
+    MRS     x2, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x2, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x2, x2, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x2, x2, x3, LSL #2                  // Calculate CPU ID
+#endif
+
+    /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release 
+       flag.  */
+
+    LDR     w1, =0xF0F0F0F0                     // Build TX_INITIALIZE_IN_PROGRESS flag
+    LDR     x3, =_tx_thread_system_state        // Pickup the base of the current system state array
+wait_for_initialize:
+    LDR     w0, [x3, x2, LSL #2]                // Pickup the current system state for this core
+    CMP     w0, w1                              // Make sure the TX_INITIALIZE_IN_PROGRESS flag is set
+    BNE     wait_for_initialize                 // Not equal, just spin here
+
+    /* Save the system stack pointer for this core.  */
+    
+    LDR     x0, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    MOV     x1, sp                              // Pickup SP
+    SUB     x1, x1, #15                         //
+    BIC     x1, x1, #0xF                        // Get 16-bit alignment
+    STR     x1, [x0, x2, LSL #3]                // Store system stack pointer
+
+
+    /* Pickup the release cores flag.  */
+    
+    LDR     x4, =_tx_thread_smp_release_cores_flag  // Build address of release cores flag
+wait_for_release:    
+    LDR     w0, [x4, #0]                        // Pickup the flag
+    CMP     w0, #0                              // Is it set?
+    BEQ     wait_for_release                    // Wait for the flag to be set
+    
+    /* Core 0 has released this core.  */
+    
+    /* Clear this core's system state variable.  */
+    
+    MOV     x0, #0                              // Build clear value
+    STR     w0, [x3, x2, LSL #2]                // Set the current system state for this core to zero
+    
+    /* Now wait for core 0 to finish it's initialization.  */
+    
+core_0_wait_loop:
+    LDR     w0, [x3, #0]                        // Pickup the current system state for core 0
+    CMP     w0, #0                              // Is it 0?
+    BNE     core_0_wait_loop                    // No, keep waiting for core 0 to finish its initialization
+    
+    /* Initialization is complete, enter the scheduling loop!  */
+    
+    B       _tx_thread_schedule                 // Enter the scheduling loop for this core    
+
+    RET
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S
new file mode 100644
index 00000000..6c625694
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S
@@ -0,0 +1,68 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_low_level_initialize              Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function performs low-level initialization of the booting      */
+/*    core.                                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    number_of_cores                       Number of cores               */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_high_level            ThreadX high-level init        */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_low_level_initialize
+    .type    _tx_thread_smp_low_level_initialize, @function
+_tx_thread_smp_low_level_initialize:
+
+    RET
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S
new file mode 100644
index 00000000..a5070681
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S
@@ -0,0 +1,352 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* Include macros for modifying the wait list.  */
+#include "tx_thread_smp_protection_wait_list_macros.h"
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_protect                           Cortex-A35-SMP/AC6 */
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function gets protection for running inside the ThreadX        */
+/*    source. This is acomplished by a combination of a test-and-set      */
+/*    flag and periodically disabling interrupts.                         */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    Previous Status Register                                            */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_protect
+    .type    _tx_thread_smp_protect, @function
+_tx_thread_smp_protect:
+
+    /* Disable interrupts so we don't get preempted.  */
+
+    MRS     x0, DAIF                            // Pickup current interrupt posture
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x7, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x7, LSL #2                  // Calculate CPU ID
+#endif
+
+    /* Do we already have protection?  */
+    // if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
+    // {
+
+    LDR     x2, =_tx_thread_smp_protection      // Build address to protection structure
+    LDR     w3, [x2, #4]                        // Pickup the owning core
+    CMP     w1, w3                              // Is it not this core?
+    BNE     _protection_not_owned               // No, the protection is not already owned
+
+    /* We already have protection. */
+
+    /* Increment the protection count. */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_count++;
+
+    LDR     w3, [x2, #8]                        // Pickup ownership count
+    ADD     w3, w3, #1                          // Increment ownership count
+    STR     w3, [x2, #8]                        // Store ownership count
+    DMB     ISH
+
+    B       _return
+
+_protection_not_owned:
+
+    /* Is the lock available?  */
+    // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
+    // {
+
+    LDAXR   w3, [x2, #0]                        // Pickup the protection flag
+    CMP     w3, #0
+    BNE     _start_waiting                      // No, protection not available
+
+    /* Is the list empty?  */
+    // if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail)
+    // {
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_head
+    LDR     w3, [x3]
+    LDR     x4, =_tx_thread_smp_protect_wait_list_tail
+    LDR     w4, [x4]
+    CMP     w3, w4
+    BNE     _list_not_empty
+
+    /* Try to get the lock.  */
+    // if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS)
+    // {
+
+    MOV     w3, #1                              // Build lock value
+    STXR    w4, w3, [x2, #0]                    // Attempt to get the protection
+    CMP     w4, #0
+    BNE     _start_waiting                      // Did it fail?
+
+    /* We got the lock! */
+    // _tx_thread_smp_protect_lock_got();
+
+    DMB     ISH                                 // Ensure write to protection finishes
+    _tx_thread_smp_protect_lock_got             // Call the lock got function
+
+    B       _return
+
+_list_not_empty:
+
+    /* Are we at the front of the list?  */
+    // if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
+    // {
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
+    LDR     w3, [x3]                            // Get the value of the head
+    LDR     x4, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    LDR     w4, [x4, x3, LSL #2]                // Get the value at the head index
+
+    CMP     w1, w4
+    BNE     _start_waiting
+
+    /* Is the lock still available?  */
+    // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
+    // {
+
+    LDR     w3, [x2, #0]                        // Pickup the protection flag
+    CMP     w3, #0
+    BNE     _start_waiting                      // No, protection not available
+
+    /* Get the lock.  */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
+
+    MOV     w3, #1                              // Build lock value
+    STR     w3, [x2, #0]                        // Store lock value
+    DMB     ISH                                 //
+
+    /* Got the lock.  */
+    // _tx_thread_smp_protect_lock_got();
+
+    _tx_thread_smp_protect_lock_got
+
+    /* Remove this core from the wait list.  */
+    // _tx_thread_smp_protect_remove_from_front_of_list();
+
+    _tx_thread_smp_protect_remove_from_front_of_list
+
+    B       _return
+
+_start_waiting:
+
+    /* For one reason or another, we didn't get the lock.  */
+
+    /* Increment wait count. */
+    // _tx_thread_smp_protect_wait_counts[this_core]++;
+
+    LDR     x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
+    LDR     w4, [x3, x1, LSL #2]                // Load waiting value for this core
+    ADD     w4, w4, #1                          // Increment wait value
+    STR     w4, [x3, x1, LSL #2]                // Store new wait value
+
+    /* Have we not added ourselves to the list yet? */
+    // if (_tx_thread_smp_protect_wait_counts[this_core] == 1)
+    // {
+
+    CMP     w4, #1
+    BNE     _already_in_list0                   // Is this core already waiting?
+
+    /* Add ourselves to the list.  */
+    // _tx_thread_smp_protect_wait_list_add(this_core);
+
+    _tx_thread_smp_protect_wait_list_add        // Call macro to add ourselves to the list
+
+    // }
+
+_already_in_list0:
+
+    /* Restore interrupts. */
+
+    MSR     DAIF, x0                            // Restore interrupts
+    ISB                                         // 
+#ifdef TX_ENABLE_WFE
+    WFE                                         // Go into standby
+#endif
+
+    /* We do this until we have the lock. */
+    // while (1)
+    // {
+
+_try_to_get_lock:
+
+    /* Disable interrupts so we don't get preempted.  */
+
+    MRS     x0, DAIF                            // Pickup current interrupt posture
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x7, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x7, LSL #2                  // Calculate CPU ID
+#endif
+
+    /* Do we already have protection?  */
+    // if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
+    // {
+
+    LDR     w3, [x2, #4]                        // Pickup the owning core
+    CMP     w3, w1                              // Is it this core?
+    BEQ     _got_lock_after_waiting             // Yes, the protection is already owned. This means
+                                                // an ISR preempted us and got protection
+
+    // }
+
+    /* Are we at the front of the list?  */
+    // if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
+    // {/
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
+    LDR     w3, [x3]                            // Get the value of the head
+    LDR     x4, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    LDR     w4, [x4, x3, LSL #2]                // Get the value at the head index
+
+    CMP     w1, w4
+    BNE     _did_not_get_lock
+
+    /* Is the lock still available? */
+    // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
+    // {
+
+    LDR     w3, [x2, #0]                        // Pickup the protection flag
+    CMP     w3, #0
+    BNE     _did_not_get_lock                   // No, protection not available
+
+    /* Get the lock.  */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
+
+    MOV     w3, #1                              // Build lock value
+    STR     w3, [x2, #0]                        // Store lock value
+    DMB     ISH                                 //
+
+    /* Got the lock.  */
+    // _tx_thread_smp_protect_lock_got();
+
+    _tx_thread_smp_protect_lock_got
+
+    /* Remove this core from the wait list.  */
+    // _tx_thread_smp_protect_remove_from_front_of_list();
+
+    _tx_thread_smp_protect_remove_from_front_of_list
+
+    B       _got_lock_after_waiting
+
+_did_not_get_lock:
+
+    /* For one reason or another, we didn't get the lock.  */
+
+    /* Were we removed from the list? This can happen if we're a thread
+       and we got preempted. */
+    // if (_tx_thread_smp_protect_wait_counts[this_core] == 0)
+    // {
+
+    LDR     x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
+    LDR     w4, [x3, x1, LSL #2]                // Load waiting value for this core
+    CMP     w4, #0
+    BNE     _already_in_list1                   // Is this core already in the list?
+
+    /* Add ourselves to the list.  */
+    // _tx_thread_smp_protect_wait_list_add(this_core);
+
+    _tx_thread_smp_protect_wait_list_add        // Call macro to add ourselves to the list
+
+    /* Our waiting count was also reset when we were preempted. Increment it again. */
+    // _tx_thread_smp_protect_wait_counts[this_core]++;
+
+    LDR     x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
+    LDR     w4, [x3, x1, LSL #2]                // Load waiting value for this core
+    ADD     w4, w4, #1                          // Increment wait value
+    STR     w4, [x3, x1, LSL #2]                // Store new wait value value
+
+    // }
+
+_already_in_list1:
+
+    /* Restore interrupts and try again.  */
+
+    MSR     DAIF, x0                            // Restore interrupts
+    ISB                                         // 
+#ifdef TX_ENABLE_WFE
+    WFE                                         // Go into standby
+#endif
+    B       _try_to_get_lock                    // On waking, restart the protection attempt
+
+_got_lock_after_waiting:
+
+    /* We're no longer waiting.  */
+    // _tx_thread_smp_protect_wait_counts[this_core]--;
+
+    LDR     x3, =_tx_thread_smp_protect_wait_counts // Load waiting list
+    LDR     w4, [x3, x1, LSL #2]                // Load current wait value
+    SUB     w4, w4, #1                          // Decrement wait value
+    STR     w4, [x3, x1, LSL #2]                // Store new wait value value
+
+    /* Restore registers and return.  */
+
+_return:
+
+    RET
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h
new file mode 100644
index 00000000..5c33d940
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h
@@ -0,0 +1,296 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+    .macro _tx_thread_smp_protect_lock_got
+
+    /* Set the currently owned core.  */
+    /* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */
+
+    STR     w1, [x2, #4]                        // Store this core
+
+    /* Increment the protection count. */
+    /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */
+
+    LDR     w3, [x2, #8]                        // Pickup ownership count
+    ADD     w3, w3, #1                          // Increment ownership count
+    STR     w3, [x2, #8]                        // Store ownership count
+    DMB     ISH
+
+    .endm
+
+    .macro _tx_thread_smp_protect_remove_from_front_of_list
+
+    /* Remove ourselves from the list.  */
+    /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] =  0xFFFFFFFF; */
+
+    MOV     w3, #0xFFFFFFFF                     // Build the invalid core value
+    LDR     x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
+    LDR     w5, [x4]                            // Get the value of the head
+    LDR     x6, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    STR     w3, [x6, x5, LSL #2]                // Store the invalid core value
+    ADD     w5, w5, #1                          // Increment the head
+
+    /* Did we wrap?  */
+    /* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
+    { */
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size
+    LDR     w3, [x3]                            // Load the max cores value
+    CMP     w5, w3                              // Compare the head to it
+    BNE     _store_new_head\@                   // Are we at the max?
+
+    /* _tx_thread_smp_protect_wait_list_head = 0; */
+
+    EOR     w5, w5, w5                          // We're at the max. Set it to zero
+
+    /* } */
+
+_store_new_head\@:
+
+    STR     w5, [x4]                            // Store the new head
+
+    /* We have the lock!  */
+    /* return; */
+
+    .endm
+
+
+    .macro _tx_thread_smp_protect_wait_list_lock_get
+/* VOID  _tx_thread_smp_protect_wait_list_lock_get()
+{ */
+    /* We do this until we have the lock.  */
+    /* while (1)
+    { */
+
+_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
+
+    /* Is the list lock available?  */
+    /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */
+
+    LDR     x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
+    LDAXR   w2, [x1]                            // Pickup the protection flag
+
+    /* if (protect_in_force == 0)
+    { */
+
+    CMP     w2, #0
+    BNE     _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available
+
+    /* Try to get the list.  */
+    /* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */
+
+    MOV     w2, #1                              // Build lock value
+    STXR    w3, w2, [x1]                        // Attempt to get the protection
+
+    /* if (status == SUCCESS) */
+
+    CMP     w3, #0
+    BNE     _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again.
+
+    /* We have the lock!  */
+    /* return; */
+
+    .endm
+
+
+    .macro _tx_thread_smp_protect_wait_list_add
+/* VOID  _tx_thread_smp_protect_wait_list_add(UINT new_core)
+{ */
+
+    /* We're about to modify the list, so get the list lock.  */
+    /* _tx_thread_smp_protect_wait_list_lock_get(); */
+
+    STP     x1, x2, [sp, #-16]!                 // Save registers we'll be using
+
+    _tx_thread_smp_protect_wait_list_lock_get
+
+    LDP     x1, x2, [sp], #16
+
+    /* Add this core.  */
+    /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail
+    LDR     w4, [x3]                            // Get the value of tail
+    LDR     x5, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    STR     w1, [x5, x4, LSL #2]                // Store the new core value
+    ADD     w4, w4, #1                          // Increment the tail
+
+    /* Did we wrap?  */
+    /* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
+    { */
+
+    LDR     x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address
+    LDR     w5, [x5]                            // Load max cores value
+    CMP     w4, w5                              // Compare max cores to tail
+    BNE     _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap?
+
+    /* _tx_thread_smp_protect_wait_list_tail = 0; */
+
+    MOV     w4, #0
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_add__no_wrap\@:
+
+    STR     w4, [x3]                            // Store the new tail value.
+
+    /* Release the list lock.  */
+    /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
+
+    MOV     w3, #0                              // Build lock value
+    LDR     x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
+    STR     w3, [x4]                            // Store the new value
+
+    .endm
+
+
+    .macro _tx_thread_smp_protect_wait_list_remove
+/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
+{ */
+
+    /* Get the core index.  */
+    /* UINT core_index;
+    for (core_index = 0;; core_index++) */
+
+    EOR     w4, w4, w4                          // Clear for 'core_index'
+    LDR     x2, =_tx_thread_smp_protect_wait_list // Get the address of the list
+
+    /* { */
+
+_tx_thread_smp_protect_wait_list_remove__check_cur_core\@:
+
+    /* Is this the core?  */
+    /* if (_tx_thread_smp_protect_wait_list[core_index] == core)
+    {
+        break; */
+
+    LDR     w3, [x2, x4, LSL #2]                // Get the value at the current index
+    CMP     w3, w8                              // Did we find the core?
+    BEQ     _tx_thread_smp_protect_wait_list_remove__found_core\@
+
+    /* } */
+
+    ADD     w4, w4, #1                          // Increment cur index
+    B       _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_remove__found_core\@:
+
+    /* We're about to modify the list. Get the lock. We need the lock because another
+       core could be simultaneously adding (a core is simultaneously trying to get
+       the inter-core lock) or removing (a core is simultaneously being preempted,
+       like what is currently happening).  */
+    /* _tx_thread_smp_protect_wait_list_lock_get(); */
+
+    MOV     x6, x1
+    _tx_thread_smp_protect_wait_list_lock_get
+    MOV     x1, x6
+
+    /* We remove by shifting.  */
+    /* while (core_index != _tx_thread_smp_protect_wait_list_tail)
+    { */
+
+_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
+
+    LDR     x2, =_tx_thread_smp_protect_wait_list_tail // Load tail address
+    LDR     w2, [x2]                            // Load tail value
+    CMP     w4, w2                              // Compare cur index and tail
+    BEQ     _tx_thread_smp_protect_wait_list_remove__removed\@
+
+    /* UINT next_index = core_index + 1; */
+
+    MOV     w2, w4                              // Move current index to next index register
+    ADD     w2, w2, #1                          // Add 1
+
+    /* if (next_index == _tx_thread_smp_protect_wait_list_size)
+    { */
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_size
+    LDR     w3, [x3]
+    CMP     w2, w3
+    BNE     _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@
+
+    /* next_index = 0; */
+
+    MOV     w2, #0
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@:
+
+    /* list_cores[core_index] = list_cores[next_index]; */
+
+    LDR     x5, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    LDR     w3, [x5, x2, LSL #2]                // Get the value at the next index
+    STR     w3, [x5, x4, LSL #2]                // Store the value at the current index
+
+    /* core_index = next_index; */
+
+    MOV     w4, w2
+
+    B       _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_remove__removed\@:
+
+    /* Now update the tail.  */
+    /* if (_tx_thread_smp_protect_wait_list_tail == 0)
+    { */
+
+    LDR     x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address
+    LDR     w4, [x5]                            // Load tail value
+    CMP     w4, #0
+    BNE     _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@
+
+    /* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */
+
+    LDR     x2, =_tx_thread_smp_protect_wait_list_size
+    LDR     w4, [x2]
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@:
+
+    /* _tx_thread_smp_protect_wait_list_tail--; */
+
+    SUB     w4, w4, #1
+    STR     w4, [x5]                            // Store new tail value
+
+    /* Release the list lock.  */
+    /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
+
+    MOV     w2, #0                              // Build lock value
+    LDR     x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address
+    STR     w2, [x4]                            // Store the new value
+
+    /* We're no longer waiting. Note that this should be zero since, again,
+       this function is only called when a thread preemption is occurring.  */
+    /* _tx_thread_smp_protect_wait_counts[core]--; */
+    LDR     x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts
+    LDR     w2, [x4, x8, LSL #2]                // Load waiting value
+    SUB     w2, w2, #1                          // Subtract 1
+    STR     w2, [x4, x8, LSL #2]                // Store new waiting value
+
+    .endm
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S
new file mode 100644
index 00000000..bf9dcb0a
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S
@@ -0,0 +1,69 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_time_get                          Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function gets the global time value that is used for debug     */
+/*    information and event tracing.                                      */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    32-bit time stamp                                                   */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_time_get
+    .type    _tx_thread_smp_time_get, @function
+_tx_thread_smp_time_get:
+    MOV     x0, #0          // FIXME: Get timer
+    RET
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S
new file mode 100644
index 00000000..a689ae8b
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S
@@ -0,0 +1,117 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_unprotect                         Cortex-A35-SMP/AC6 */
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function releases previously obtained protection. The supplied */
+/*    previous SR is restored. If the value of _tx_thread_system_state    */
+/*    and _tx_thread_preempt_disable are both zero, then multithreading   */
+/*    is enabled as well.                                                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    Previous Status Register                                            */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_unprotect
+    .type    _tx_thread_smp_unprotect, @function
+_tx_thread_smp_unprotect:
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x2, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x2, LSL #2                  // Calculate CPU ID
+#endif
+
+    LDR     x2,=_tx_thread_smp_protection       // Build address of protection structure
+    LDR     w3, [x2, #4]                        // Pickup the owning core
+    CMP     w1, w3                              // Is it this core?
+    BNE     _still_protected                    // If this is not the owning core, protection is in force elsewhere
+
+    LDR     w3, [x2, #8]                        // Pickup the protection count
+    CMP     w3, #0                              // Check to see if the protection is still active
+    BEQ     _still_protected                    // If the protection count is zero, protection has already been cleared
+
+    SUB     w3, w3, #1                          // Decrement the protection count
+    STR     w3, [x2, #8]                        // Store the new count back
+    CMP     w3, #0                              // Check to see if the protection is still active
+    BNE     _still_protected                    // If the protection count is non-zero, protection is still in force
+    LDR     x2,=_tx_thread_preempt_disable      // Build address of preempt disable flag
+    LDR     w3, [x2]                            // Pickup preempt disable flag
+    CMP     w3, #0                              // Is the preempt disable flag set?
+    BNE     _still_protected                    // Yes, skip the protection release
+
+    LDR     x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
+    LDR     w3, [x2, x1, LSL #2]                // Pickup wait list value
+    CMP     w3, #0                              // Are any entities on this core waiting?
+    BNE     _still_protected                    // Yes, skip the protection release
+
+    LDR     x2,=_tx_thread_smp_protection       // Build address of protection structure
+    MOV     w3, #0xFFFFFFFF                     // Build invalid value
+    STR     w3, [x2, #4]                        // Mark the protected core as invalid
+    DMB     ISH                                 // Ensure that accesses to shared resource have completed
+    MOV     w3, #0                              // Build release protection value
+    STR     w3, [x2, #0]                        // Release the protection
+    DSB     ISH                                 // To ensure update of the protection occurs before other CPUs awake
+
+_still_protected:
+#ifdef TX_ENABLE_WFE
+    SEV                                         // Send event to other CPUs, wakes anyone waiting on the protection (using WFE)
+#endif
+    MSR     DAIF, x0                            // Restore interrupt posture
+    RET
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..abc33806
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S
@@ -0,0 +1,159 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_stack_build                           Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread             */
+/*    function_ptr                          Pointer to entry function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+// {
+    .global _tx_thread_stack_build
+    .type   _tx_thread_stack_build, @function
+_tx_thread_stack_build:
+
+
+    /* Build an interrupt frame.  On Cortex-A35 it should look like this:
+
+       Stack Top:      SSPR        Initial SSPR
+                       ELR         Point of interrupt
+                       x28         Initial value for x28
+                       not used    Not used
+                       x26         Initial value for x26
+                       x27         Initial value for x27
+                       x24         Initial value for x24
+                       x25         Initial value for x25
+                       x22         Initial value for x22
+                       x23         Initial value for x23
+                       x20         Initial value for x20
+                       x21         Initial value for x21
+                       x18         Initial value for x18
+                       x19         Initial value for x19
+                       x16         Initial value for x16
+                       x17         Initial value for x17
+                       x14         Initial value for x14
+                       x15         Initial value for x15
+                       x12         Initial value for x12
+                       x13         Initial value for x13
+                       x10         Initial value for x10
+                       x11         Initial value for x11
+                       x8          Initial value for x8
+                       x9          Initial value for x9
+                       x6          Initial value for x6
+                       x7          Initial value for x7
+                       x4          Initial value for x4
+                       x5          Initial value for x5
+                       x2          Initial value for x2
+                       x3          Initial value for x3
+                       x0          Initial value for x0
+                       x1          Initial value for x1
+                       x29         Initial value for x29 (frame pointer)
+                       x30         Initial value for x30 (link register)
+                       0           For stack backtracing
+
+       Stack Bottom: (higher memory address)
+    */
+
+    LDR     x4, [x0, #24]                       // Pickup end of stack area
+    BIC     x4, x4, #0xF                        // Ensure 16-byte alignment
+
+    /* Actually build the stack frame.  */
+
+    MOV     x2, #0                              // Build clear value
+    MOV     x3, #0                              //
+
+    STP     x2, x3, [x4, #-16]!                 // Set backtrace to 0
+    STP     x2, x3, [x4, #-16]!                 // Set initial x29, x30
+    STP     x2, x3, [x4, #-16]!                 // Set initial x0, x1
+    STP     x2, x3, [x4, #-16]!                 // Set initial x2, x3
+    STP     x2, x3, [x4, #-16]!                 // Set initial x4, x5
+    STP     x2, x3, [x4, #-16]!                 // Set initial x6, x7
+    STP     x2, x3, [x4, #-16]!                 // Set initial x8, x9
+    STP     x2, x3, [x4, #-16]!                 // Set initial x10, x11
+    STP     x2, x3, [x4, #-16]!                 // Set initial x12, x13
+    STP     x2, x3, [x4, #-16]!                 // Set initial x14, x15
+    STP     x2, x3, [x4, #-16]!                 // Set initial x16, x17
+    STP     x2, x3, [x4, #-16]!                 // Set initial x18, x19
+    STP     x2, x3, [x4, #-16]!                 // Set initial x20, x21
+    STP     x2, x3, [x4, #-16]!                 // Set initial x22, x23
+    STP     x2, x3, [x4, #-16]!                 // Set initial x24, x25
+    STP     x2, x3, [x4, #-16]!                 // Set initial x26, x27
+    STP     x2, x3, [x4, #-16]!                 // Set initial x28
+#ifdef EL1
+    MOV     x2, #0x4                            // Build initial SPSR  (EL1)
+#else
+#ifdef EL2
+    MOV     x2, #0x8                            // Build initial SPSR  (EL2)
+#else
+    MOV     x2, #0xC                            // Build initial SPSR  (EL3)
+#endif
+#endif
+    MOV     x3, x1                              // Build initial ELR
+    STP     x2, x3, [x4, #-16]!                 // Set initial SPSR & ELR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  x2;  */
+
+    STR     x4, [x0, #8]                        // Save stack pointer in thread's
+    MOV     x3, #1                              // Build ready flag
+    STR     w3, [x0, #260]                      // Set ready flag
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S
new file mode 100644
index 00000000..83a1217c
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S
@@ -0,0 +1,179 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_system_return                         Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is target processor specific.  It is used to transfer */
+/*    control from a thread back to the ThreadX system.  Only a           */
+/*    minimal context is saved since the compiler assumes temp registers  */
+/*    are going to get slicked by a function call anyway.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling loop        */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_system_return(VOID)
+// {
+    .global _tx_thread_system_return
+    .type   _tx_thread_system_return, @function
+_tx_thread_system_return:
+
+    /* Save minimal context on the stack.  */
+
+    MRS     x0, DAIF                            // Pickup DAIF
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    STP     x29, x30, [sp, #-16]!               // Save x29 (frame pointer), x30 (link register)
+    STP     x19, x20, [sp, #-16]!               // Save x19, x20
+    STP     x21, x22, [sp, #-16]!               // Save x21, x22
+    STP     x23, x24, [sp, #-16]!               // Save x23, x24
+    STP     x25, x26, [sp, #-16]!               // Save x25, x26
+    STP     x27, x28, [sp, #-16]!               // Save x27, x28
+    MRS     x8, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x8, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x8, x8, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x8, x8, x3, LSL #2                  // Calculate CPU ID
+#endif
+    LDR     x5, =_tx_thread_current_ptr         // Pickup address of current ptr
+    LDR     x6, [x5, x8, LSL #3]                // Pickup current thread pointer
+
+#ifdef ENABLE_ARM_FP
+    LDR     w7, [x6, #268]                      // Pickup FP enable flag
+    CMP     w7, #0                              // Is FP enabled?
+    BEQ     _skip_fp_save                       // No, skip FP save
+    STP     q8,  q9,  [sp, #-32]!               // Save q8, q9
+    STP     q10, q11, [sp, #-32]!               // Save q10, q11
+    STP     q12, q13, [sp, #-32]!               // Save q12, q13
+    STP     q14, q15, [sp, #-32]!               // Save q14, q15
+    MRS     x2, FPSR                            // Pickup FPSR
+    MRS     x3, FPCR                            // Pickup FPCR
+    STP     x2, x3, [sp, #-16]!                 // Save FPSR, FPCR
+_skip_fp_save:
+#endif
+
+    MOV     x1, #0                              // Clear x1
+    STP     x0, x1, [sp, #-16]!                 // Save DAIF and clear value for ELR_EK1
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread exit function to indicate the thread is no longer executing.  */
+
+    MOV     x19, x5                             // Save x5
+    MOV     x20, x6                             // Save x6
+    MOV     x21, x8                             // Save x2
+    BL      _tx_execution_thread_exit           // Call the thread exit function
+    MOV     x8, x21                             // Restore x2
+    MOV     x5, x19                             // Restore x5
+    MOV     x6, x20                             // Restore x6
+#endif
+
+    LDR     x2, =_tx_timer_time_slice           // Pickup address of time slice
+    LDR     w1, [x2, x8, LSL #2]                // Pickup current time slice
+
+    /* Save current stack and switch to system stack.  */
+    // _tx_thread_current_ptr[core] -> tx_thread_stack_ptr =  sp;
+    // sp = _tx_thread_system_stack_ptr[core];
+
+    MOV     x4, sp                              //
+    STR     x4, [x6, #8]                        // Save thread stack pointer
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, x8, LSL #3]                // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+    /* Determine if the time-slice is active.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    MOV     x4, #0                              // Build clear value
+    CMP     w1, #0                              // Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save the time-slice
+
+       /* Save the current remaining time-slice.  */
+       // _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+       // _tx_timer_time_slice =  0;
+
+    STR     w4, [x2, x8, LSL #2]                // Clear time-slice
+    STR     w1, [x6, #36]                       // Store current time-slice
+
+    // }
+__tx_thread_dont_save_ts:
+
+    /* Clear the current thread pointer.  */
+    // _tx_thread_current_ptr =  TX_NULL;
+
+    STR     x4, [x5, x8, LSL #3]                // Clear current thread pointer
+
+    /* Set ready bit in thread control block.  */
+    
+    MOV     x3, #1                              // Build ready value
+    STR     w3, [x6, #260]                      // Make the thread ready 
+    DMB     ISH                                 // 
+    
+    /* Now clear protection. It is assumed that protection is in force whenever this routine is called.  */
+    
+    LDR     x3, =_tx_thread_smp_protection      // Pickup address of protection structure
+    LDR     x1, =_tx_thread_preempt_disable     // Build address to preempt disable flag
+    STR     w4, [x1, #0]                        // Clear preempt disable flag
+    STR     w4, [x3, #8]                        // Cear protection count
+    MOV     x1, #0xFFFFFFFF                     // Build invalid value
+    STR     w1, [x3, #4]                        // Set core to an invalid value
+    DMB     ISH                                 // Ensure that accesses to shared resource have completed
+    STR     w4, [x3, #0]                        // Clear protection
+    DSB     ISH                                 // To ensure update of the shared resource occurs before other CPUs awake
+    SEV                                         // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE)
+    B       _tx_thread_schedule                 // Jump to scheduler!
+
+// }
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_timeout.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_timeout.c
new file mode 100644
index 00000000..c8710f9d
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_timeout.c
@@ -0,0 +1,165 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_timeout                                Cortex-A35-SMP    */
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function handles thread timeout processing.  Timeouts occur in */
+/*    two flavors, namely the thread sleep timeout and all other service  */
+/*    call timeouts.  Thread sleep timeouts are processed locally, while  */
+/*    the others are processed by the appropriate suspension clean-up     */
+/*    service.                                                            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    timeout_input                         Contains the thread pointer   */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    Suspension Cleanup Functions                                        */
+/*    _tx_thread_system_resume          Resume thread                     */
+/*    _tx_thread_system_ni_resume       Non-interruptable resume thread   */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_timer_expiration_process          Timer expiration function     */
+/*    _tx_timer_thread_entry                Timer thread function         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_timeout(ULONG timeout_input)
+{
+
+TX_INTERRUPT_SAVE_AREA
+
+TX_THREAD       *thread_ptr;                
+VOID            (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence);
+ULONG           suspension_sequence;
+
+
+    /* Pickup the thread pointer.  */
+    TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr)
+
+    /* Disable interrupts.  */
+    TX_DISABLE
+
+    /* Determine how the thread is currently suspended.  */
+    if (thread_ptr -> tx_thread_state == TX_SLEEP)
+    {
+
+#ifdef TX_NOT_INTERRUPTABLE
+
+        /* Resume the thread!  */
+        _tx_thread_system_ni_resume(thread_ptr);
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#else
+
+        /* Increment the disable preemption flag.  */
+        _tx_thread_preempt_disable++;
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+
+        /* Lift the suspension on the sleeping thread.  */
+        _tx_thread_system_resume(thread_ptr);
+#endif
+    }
+    else
+    {
+
+        /* Process all other suspension timeouts.  */
+
+#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO
+
+        /* Increment the total number of thread timeouts.  */
+        _tx_thread_performance_timeout_count++;
+
+        /* Increment the number of timeouts for this thread.  */
+        thread_ptr -> tx_thread_performance_timeout_count++;
+#endif
+    
+        /* Pickup the cleanup routine address.  */
+        suspend_cleanup =  thread_ptr -> tx_thread_suspend_cleanup;
+
+#ifndef TX_NOT_INTERRUPTABLE
+
+        /* Pickup the suspension sequence number that is used later to verify that the
+           cleanup is still necessary.  */
+        suspension_sequence =  thread_ptr -> tx_thread_suspension_sequence;
+#else
+
+        /* When not interruptable is selected, the suspension sequence is not used - just set to 0.  */
+        suspension_sequence =  ((ULONG) 0);
+#endif
+
+#ifndef TX_NOT_INTERRUPTABLE
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#endif
+
+        /* Call any cleanup routines.  */
+        if (suspend_cleanup != TX_NULL)
+        {
+
+            /* Yes, there is a function to call.  */
+            (suspend_cleanup)(thread_ptr, suspension_sequence);
+        }
+
+#ifdef TX_NOT_INTERRUPTABLE
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#endif
+    }
+}
+
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..85a5e46f
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S
@@ -0,0 +1,187 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_timer_interrupt                              Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function processes the hardware timer interrupt.  This         */
+/*    processing includes incrementing the system clock and checking for  */
+/*    time slice and/or timer expiration.  If either is found, the        */
+/*    interrupt context save/restore functions are called along with the  */
+/*    expiration functions.                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_timer_expiration_process          Timer expiration processing   */
+/*    _tx_thread_time_slice                 Time slice interrupted thread */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    interrupt vector                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_timer_interrupt(VOID)
+// {
+    .global _tx_timer_interrupt
+    .type   _tx_timer_interrupt, @function
+_tx_timer_interrupt:
+
+    MRS     x2, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x2, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x2, x2, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x2, x2, x3, LSL #2                  // Calculate CPU ID
+#endif
+    CMP     x2, #0                              // Is this core 0?
+    BEQ     __tx_process_timer                  // If desired core, continue processing
+    RET                                         // Simply return if different core
+__tx_process_timer:
+
+    /* Upon entry to this routine, it is assumed that context save has already
+       been called, and therefore the compiler scratch registers are available
+       for use.  */
+
+    STP     x27, x28, [sp, #-16]!               // Save x27, x28
+    STP     x29, x30, [sp, #-16]!               // Save x29 (frame pointer), x30 (link register)
+
+    /* Get inter-core protection.  */
+
+    BL      _tx_thread_smp_protect              // Get inter-core protection
+    MOV     x28, x0                             // Save the return value in preserved register
+
+    /* Increment the system clock.  */
+    // _tx_timer_system_clock++;
+
+    LDR     x1, =_tx_timer_system_clock         // Pickup address of system clock
+    LDR     w0, [x1, #0]                        // Pickup system clock
+    ADD     w0, w0, #1                          // Increment system clock
+    STR     w0, [x1, #0]                        // Store new system clock
+
+    /* Test for timer expiration.  */
+    // if (*_tx_timer_current_ptr)
+    // {
+
+    LDR     x1, =_tx_timer_current_ptr          // Pickup current timer pointer addr
+    LDR     x0, [x1, #0]                        // Pickup current timer
+    LDR     x2, [x0, #0]                        // Pickup timer list entry
+    CMP     x2, #0                              // Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 // No, just increment the timer
+
+        /* Set expiration flag.  */
+        // _tx_timer_expired =  TX_TRUE;
+
+    LDR     x3, =_tx_timer_expired              // Pickup expiration flag address
+    MOV     w2, #1                              // Build expired value
+    STR     w2, [x3, #0]                        // Set expired flag
+    B       __tx_timer_done                     // Finished timer processing
+
+    // }
+    // else
+    // {
+__tx_timer_no_timer:
+
+        /* No timer expired, increment the timer pointer.  */
+        // _tx_timer_current_ptr++;
+
+    ADD     x0, x0, #8                          // Move to next timer
+
+        /* Check for wrap-around.  */
+        // if (_tx_timer_current_ptr == _tx_timer_list_end)
+
+    LDR     x3, =_tx_timer_list_end             // Pickup addr of timer list end
+    LDR     x2, [x3, #0]                        // Pickup list end
+    CMP     x0, x2                              // Are we at list end?
+    BNE     __tx_timer_skip_wrap                // No, skip wrap-around logic
+
+            /* Wrap to beginning of list.  */
+            // _tx_timer_current_ptr =  _tx_timer_list_start;
+
+    LDR     x3, =_tx_timer_list_start           // Pickup addr of timer list start
+    LDR     x0, [x3, #0]                        // Set current pointer to list start
+
+__tx_timer_skip_wrap:
+
+    STR     x0, [x1, #0]                        // Store new current timer pointer
+    // }
+
+__tx_timer_done:
+
+    /* Did a timer expire?  */
+    // if (_tx_timer_expired)
+    // {
+
+    LDR     x1, =_tx_timer_expired              // Pickup addr of expired flag
+    LDR     w0, [x1, #0]                        // Pickup timer expired flag
+    CMP     w0, #0                              // Check for timer expiration
+    BEQ     __tx_timer_dont_activate            // If not set, skip timer activation
+
+        /* Process timer expiration.  */
+        // _tx_timer_expiration_process();
+
+    BL      _tx_timer_expiration_process        // Call the timer expiration handling routine
+
+    // }
+
+__tx_timer_dont_activate:
+
+    /* Call time-slice processing.  */
+    // _tx_thread_time_slice();
+    BL      _tx_thread_time_slice               // Call time-slice processing
+
+    /* Release inter-core protection.  */
+    
+    MOV     x0, x28                             // Pass the previous status register back 
+    BL      _tx_thread_smp_unprotect            // Release protection
+
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    LDP     x27, x28, [sp], #16                 // Recover x27, x28
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c
new file mode 100644
index 00000000..39dccb14
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c
@@ -0,0 +1,85 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "txm_module.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_port_dispatch                 Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function dispatches the module's kernel request based upon the */
+/*    ID and parameters specified in the request.                         */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Module pointer                    */
+/*    kernel_request                    Module's kernel request           */
+/*    param_0                           First parameter                   */
+/*    param_1                           Second parameter                  */
+/*    param_2                           Third parameter                   */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    Port-specific ThreadX API Calls                                     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _txm_module_manager_kernel_dispatch                                 */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)
+{
+
+ALIGN_TYPE return_value = TX_NOT_AVAILABLE;
+
+    switch(kernel_request)
+    {
+        default:
+        {
+            /* Unhandled kernel request, return an error!  */
+            break;
+        }
+    }
+    
+    return(return_value);
+}
diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S
new file mode 100644
index 00000000..05e9db86
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S
@@ -0,0 +1,165 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_thread_stack_build           Cortex-A35-SMP/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread             */
+/*    function_ptr                          Pointer to entry function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
+// {
+    .global  _txm_module_manager_thread_stack_build
+    .type    _txm_module_manager_thread_stack_build, @function
+_txm_module_manager_thread_stack_build:
+
+
+    /* Build an interrupt frame.  On Cortex-A35 it should look like this:
+
+       Stack Top:      SSPR        Initial SSPR
+                       ELR         Point of interrupt
+                       x28         Initial value for x28
+                       not used    Not used
+                       x26         Initial value for x26
+                       x27         Initial value for x27
+                       x24         Initial value for x24
+                       x25         Initial value for x25
+                       x22         Initial value for x22
+                       x23         Initial value for x23
+                       x20         Initial value for x20
+                       x21         Initial value for x21
+                       x18         Initial value for x18
+                       x19         Initial value for x19
+                       x16         Initial value for x16
+                       x17         Initial value for x17
+                       x14         Initial value for x14
+                       x15         Initial value for x15
+                       x12         Initial value for x12
+                       x13         Initial value for x13
+                       x10         Initial value for x10
+                       x11         Initial value for x11
+                       x8          Initial value for x8
+                       x9          Initial value for x9
+                       x6          Initial value for x6
+                       x7          Initial value for x7
+                       x4          Initial value for x4
+                       x5          Initial value for x5
+                       x2          Initial value for x2
+                       x3          Initial value for x3
+                       x0          Initial value for x0
+                       x1          Initial value for x1
+                       x29         Initial value for x29 (frame pointer)
+                       x30         Initial value for x30 (link register)
+                       0           For stack backtracing
+
+       Stack Bottom: (higher memory address)
+    */
+
+    LDR     x4, [x0, #24]                       // Pickup end of stack area
+    BIC     x4, x4, #0xF                        // Ensure 16-byte alignment
+
+    LDR     x5, [x0, #8]                        // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
+                                                //   It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
+                                                //   function with the actual, initial stack pointer.
+
+    /* Actually build the stack frame.  */
+
+    MOV     x2, #0                              // Build clear value
+    MOV     x3, #0                              //
+
+    STP     x2, x3, [x4, #-16]!                 // Set backtrace to 0
+    STP     x2, x3, [x4, #-16]!                 // Set initial x29, x30
+    STP     x0, x5, [x4, #-16]!                 // Set initial x0, x1
+                                                //   x0->x0 is the thread control block pointer
+                                                //   x5->x1 is the thread entry info pointer
+    STP     x2, x3, [x4, #-16]!                 // Set initial x2, x3
+    STP     x2, x3, [x4, #-16]!                 // Set initial x4, x5
+    STP     x2, x3, [x4, #-16]!                 // Set initial x6, x7
+    STP     x2, x3, [x4, #-16]!                 // Set initial x8, x9
+    STP     x2, x3, [x4, #-16]!                 // Set initial x10, x11
+    STP     x2, x3, [x4, #-16]!                 // Set initial x12, x13
+    STP     x2, x3, [x4, #-16]!                 // Set initial x14, x15
+    STP     x2, x3, [x4, #-16]!                 // Set initial x16, x17
+    STP     x2, x3, [x4, #-16]!                 // Set initial x18, x19
+    STP     x2, x3, [x4, #-16]!                 // Set initial x20, x21
+    STP     x2, x3, [x4, #-16]!                 // Set initial x22, x23
+    STP     x2, x3, [x4, #-16]!                 // Set initial x24, x25
+    STP     x2, x3, [x4, #-16]!                 // Set initial x26, x27
+    STP     x2, x3, [x4, #-16]!                 // Set initial x28
+#ifdef EL1
+    MOV     x2, #0x4                            // Build initial SPSR  (EL1)
+#else
+#ifdef EL2
+    MOV     x2, #0x8                            // Build initial SPSR  (EL2)
+#else
+    MOV     x2, #0xC                            // Build initial SPSR  (EL3)
+#endif
+#endif
+    MOV     x3, x1                              // Build initial ELR
+    STP     x2, x3, [x4, #-16]!                 // Set initial SPSR & ELR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  x2;  */
+
+    STR     x4, [x0, #8]                        // Save stack pointer in thread's
+    MOV     x3, #1                              // Build ready flag
+    STR     w3, [x0, #260]                      // Set ready flag
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35_smp/ac6/readme_threadx.txt b/ports_module/cortex_a35_smp/ac6/readme_threadx.txt
new file mode 100644
index 00000000..044d2235
--- /dev/null
+++ b/ports_module/cortex_a35_smp/ac6/readme_threadx.txt
@@ -0,0 +1,254 @@
+                   Microsoft's Azure RTOS ThreadX SMP for Cortex-A35 
+
+                          Using the ARM Compiler 6 & DS
+
+1. Import the ThreadX Projects
+
+In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import 
+the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) 
+into your DS workspace.
+
+
+2.  Building the ThreadX SMP run-time Library
+
+Building the ThreadX SMP library is easy; simply select the Eclipse project file 
+"tx" and then select the build button. You should now observe the compilation 
+and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP 
+library file tx.a.
+
+
+3.  Demonstration System
+
+The ThreadX SMP demonstration is designed to execute under the DS debugger on the
+'Debug Cortex-A35x4 SMP' FVP which must be downloaded from the ARM website and
+requires a license.
+
+Building the demonstration is easy; simply select the sample_threadx project, and
+select the build button. Next, in the sample_threadx project, right-click on the
+sample_threadx.launch file and select 'Debug As -> sample_threadx'.  The debugger is
+setup for the Cortex-35x4 SMP FVP, so selecting "Debug" will launch the FVP, load
+the sample_threadx.axf ELF file and run to main. You are now ready to execute the
+ThreadX SMP demonstration.
+
+
+4.  System Initialization
+
+The entry point in ThreadX SMP for the Cortex-A35 using AC6 tools is at label 
+"start64". This is defined within the AC6 compiler's startup code. In addition, 
+this is where all static and global pre-set C variable initialization processing 
+takes place.
+
+The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the 
+first available RAM address for use by the application, which is supplied as the 
+sole input parameter to your application definition function, tx_application_define.
+
+
+5.  Register Usage and Stack Frames
+
+The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers 
+for each function. All other registers used by a C function must be preserved 
+by the function. ThreadX SMP takes advantage of this in situations where a context 
+switch happens as a result of making a ThreadX SMP service call (which is itself a 
+C function). In such cases, the saved context of a thread is only the 
+non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+FP not enabled and TX_THREAD.tx_thread_fp_enable == 0:
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x000                  SPSR                        DAIF
+     0x008                  ELR                         0
+     0x010                  x28                         x27
+     0x018                  reserved                    x28
+     0x020                  x26                         x25
+     0x028                  x27                         x26
+     0x030                  x24                         x23
+     0x038                  x25                         x24
+     0x040                  x22                         x21
+     0x048                  x23                         x22
+     0x050                  x20                         x19
+     0x058                  x21                         x20
+     0x060                  x18                         x29
+     0x068                  x19                         x30
+     0x070                  x16
+     0x078                  x17
+     0x080                  x14
+     0x088                  x15
+     0x090                  x12
+     0x098                  x13
+     0x0A0                  x10
+     0x0A8                  x11
+     0x0B0                  x8
+     0x0B8                  x9
+     0x0C0                  x6
+     0x0C8                  x7
+     0x0D0                  x4
+     0x0D8                  x5
+     0x0E0                  x2
+     0x0E8                  x3
+     0x0F0                  x0
+     0x0F8                  x1
+     0x100                  x29
+     0x108                  x30
+
+
+FP enabled and TX_THREAD.tx_thread_fp_enable == 1:
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x000                  SPSR                        DAIF
+     0x008                  ELR                         0
+     0x010                  FPSR                        FPSR
+     0x018                  FPCR                        FPCR
+     0x020                  q30                         q14
+     0x030                  q31                         q15
+     0x040                  q28                         q12
+     0x050                  q29                         q13
+     0x060                  q26                         q10
+     0x070                  q27                         q11
+     0x080                  q24                         q8
+     0x090                  q25                         q9
+     0x0A0                  q22                         x27
+     0x0A8                                              x28
+     0x0B0                  q23                         x25
+     0x0B8                                              x26
+     0x0C0                  q20                         x23
+     0x0C8                                              x24
+     0x0D0                  q21                         x21
+     0x0D8                                              x22
+     0x0E0                  q18                         x19
+     0x0E8                                              x20
+     0x0F0                  q19                         x29
+     0x0F8                                              x30
+     0x100                  q16
+     0x110                  q17
+     0x120                  q14
+     0x130                  q15
+     0x140                  q12
+     0x150                  q13
+     0x160                  q10
+     0x170                  q11
+     0x180                  q8
+     0x190                  q9
+     0x1A0                  q6
+     0x1B0                  q7
+     0x1C0                  q4
+     0x1D0                  q5
+     0x1E0                  q2
+     0x1F0                  q3
+     0x200                  q0
+     0x210                  q1
+     0x220                  x28
+     0x228                  reserved
+     0x230                  x26
+     0x238                  x27
+     0x240                  x24
+     0x248                  x25
+     0x250                  x22
+     0x258                  x23
+     0x260                  x20
+     0x268                  x21
+     0x270                  x18
+     0x278                  x19
+     0x280                  x16
+     0x288                  x17
+     0x290                  x14
+     0x298                  x15
+     0x2A0                  x12
+     0x2A8                  x13
+     0x2B0                  x10
+     0x2B8                  x11
+     0x2C0                  x8
+     0x2C8                  x9
+     0x2D0                  x6
+     0x2D8                  x7
+     0x2E0                  x4
+     0x2E8                  x5
+     0x2F0                  x2
+     0x2F8                  x3
+     0x300                  x0
+     0x308                  x1
+     0x310                  x29
+     0x318                  x30
+
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX SMP is built without any compiler optimizations. 
+This makes it easy to debug because you can trace or set breakpoints inside of 
+ThreadX SMP itself. Of course, this costs some performance. To make it run faster, 
+you can change the project settings to the desired compiler optimization level.
+
+In addition, you can eliminate the ThreadX SMP basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX SMP provides complete and high-performance interrupt handling for Cortex-A35
+targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following
+format:
+
+        .global irq_handler
+irq_handler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+
+  /* Your ISR call goes here!  */
+  BL       application_isr_handler
+
+  B        _tx_thread_context_restore
+
+By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 
+and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined.
+
+
+8.  ThreadX SMP Timer Interrupt
+
+ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, 
+timeouts, and application timers. Without such a timer interrupt source, these services 
+are not functional. However, all other ThreadX services are operational without a 
+periodic timer source.
+
+
+9. ARM FP Support
+
+By default, FP support is disabled for each thread. If saving the context of the FP registers
+is needed, the following API call must be made from the context of the application thread - before 
+the FP usage:
+
+void    tx_thread_fp_enable(void);
+
+After this API is called in the application, FP registers will be saved/restored for this thread if it
+is preempted via an interrupt. All other suspension of the this thread will not require the FP registers
+to be saved/restored.
+
+To disable FP register context saving, simply call the following API:
+
+void    tx_thread_fp_disable(void);
+
+
+10.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX SMP:
+
+09-30-2020  Initial ThreadX 6.1 version for Cortex-A35 using AC6 tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject
new file mode 100644
index 00000000..9ff6439f
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.1006631269">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.1006631269" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.1006631269" name="Debug" parent="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf">
+                    					
+                    <folderInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.1006631269." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.debug.var.gcc-8.3.0-aarch64-elf.2028792089" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.debug.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.1006631269..772840237" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/sample_threadx}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.1767338327" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1090040185" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1575547072" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1472992242" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.1976318302" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1092691037" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.916235712" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1184930329" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
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+                            <tool command="aarch64-elf-gcc.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.1242503859" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
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+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.69710725" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
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+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.14551747" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="--specs=rdimon.specs" valueType="string"/>
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+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.script.1466766031" name="Linker script" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.script" useByScannerDiscovery="false" value="../sample_threadx.ld" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch.1719925627" name="Library search path (-L)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch" useByScannerDiscovery="false" valueType="libPaths">
+                                    									
+                                    <listOptionValue builtIn="false" value="../../tx/Debug"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libs.2064857147" name="Libraries (-l)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="tx"/>
+                                    								
+                                </option>
+                                								
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+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                							
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+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.2109128657" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.1864382843" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        		
+        <cconfiguration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025">
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+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025" name="Release" parent="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf">
+                    					
+                    <folderInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.release.var.gcc-8.3.0-aarch64-elf.1889558597" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.release.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025..1708553087" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/sample_threadx}/Release" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.416280101" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1917850252" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.most" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1722348869" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1341620364" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1015544157" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.641068181" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.most" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1891867995" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1839498489" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.2025441100" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.685695697" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.205164594" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input.1542192122" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input">
+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.1330330667" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.1377298461" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx.com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.exe.var.gcc-8.3.0-aarch64-elf.875758638" name="Executable" projectType="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.exe.var.gcc-8.3.0-aarch64-elf"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        		
+        <scannerConfigBuildInfo instanceId="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1917850252;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1015544157">
+            			
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+            		
+        </scannerConfigBuildInfo>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.project b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.project
new file mode 100644
index 00000000..a1b15572
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.project
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h
new file mode 100644
index 00000000..23bc7fd8
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h
@@ -0,0 +1,561 @@
+/*
+ * GICv3.h - data types and function prototypes for GICv3 utility routines
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_h
+#define GICV3_h
+
+#include <stdint.h>
+
+/*
+ * extra flags for GICD enable
+ */
+typedef enum
+{
+    gicdctlr_EnableGrp0 = (1 << 0),
+    gicdctlr_EnableGrp1NS = (1 << 1),
+    gicdctlr_EnableGrp1A = (1 << 1),
+    gicdctlr_EnableGrp1S = (1 << 2),
+    gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
+    gicdctlr_ARE_S = (1 << 4),	/* Enable Secure state affinity routing */
+    gicdctlr_ARE_NS = (1 << 5),	/* Enable Non-Secure state affinity routing */
+    gicdctlr_DS = (1 << 6),	/* Disable Security support */
+    gicdctlr_E1NWF = (1 << 7)	/* Enable "1-of-N" wakeup model */
+} GICDCTLRFlags_t;
+
+/*
+ * modes for SPI routing
+ */
+typedef enum
+{
+    gicdirouter_ModeSpecific = 0,
+    gicdirouter_ModeAny = (1 << 31)
+} GICDIROUTERBits_t;
+
+typedef enum
+{
+    gicdicfgr_Level = 0,
+    gicdicfgr_Edge = (1 << 1)
+} GICDICFGRBits_t;
+
+typedef enum
+{
+    gicigroupr_G0S = 0,
+    gicigroupr_G1NS = (1 << 0),
+    gicigroupr_G1S = (1 << 2)
+} GICIGROUPRBits_t;
+
+typedef enum
+{
+    gicrwaker_ProcessorSleep = (1 << 1),
+    gicrwaker_ChildrenAsleep = (1 << 2)
+} GICRWAKERBits_t;
+
+/**********************************************************************/
+
+/*
+ * Utility macros & functions
+ */
+#define RANGE_LIMIT(x)		((sizeof(x) / sizeof((x)[0])) - 1)
+
+static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
+					 uint32_t aff1, uint32_t aff0)
+{
+    /*
+     * only need to cast aff3 to get type promotion for all affinities
+     */
+    return ((((uint64_t)aff3 & 0xff) << 32) |
+	    ((aff2 & 0xff) << 16) |
+	    ((aff1 & 0xff) << 8) | aff0);
+}
+
+/**********************************************************************/
+
+/*
+ * GIC Distributor Function Prototypes
+ */
+
+/*
+ * ConfigGICD - configure GIC Distributor prior to enabling it
+ *
+ * Inputs:
+ *
+ *  control - control flags
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void ConfigGICD(GICDCTLRFlags_t flags);
+
+/*
+ * EnableGICD - top-level enable for GIC Distributor
+ *
+ * Inputs:
+ *
+ *  flags - new control flags to set
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void EnableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * DisableGICD - top-level disable for GIC Distributor
+ *
+ * Inputs
+ *
+ *  flags - control flags to clear
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void DisableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * SyncAREinGICD - synchronise GICD Address Routing Enable bits
+ *
+ * Inputs
+ *
+ *  flags - absolute flag bits to set in GIC Distributor
+ *
+ *  dosync - flag whether to wait for ARE bits to match passed
+ *      flag field (dosync = true), or whether to set absolute
+ *      flag bits (dosync = false)
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ * This function is used to resolve a race in an MP system whereby secondary
+ * CPUs cannot reliably program all Redistributor registers until the
+ * primary CPU has enabled Address Routing. The primary CPU will call this
+ * function with dosync = false, while the secondaries will call it with
+ * dosync = true.
+ */
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
+
+/*
+ * EnableSPI - enable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnableSPI(uint32_t id);
+
+/*
+ * DisableSPI - disable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisableSPI(uint32_t id);
+
+/*
+ * SetSPIPriority - configure the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetSPIPriority(uint32_t id, uint32_t priority);
+
+/*
+ * GetSPIPriority - determine the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  interrupt priority in the range 0 - 0xff
+ */
+uint32_t GetSPIPriority(uint32_t id);
+
+/*
+ * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  affinity - prepacked "dotted quad" affinity routing. NOTE: use the
+ *      gicv3PackAffinity() helper routine to generate this input
+ *
+ *  mode - select routing mode (specific affinity, or any recipient)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
+
+/*
+ * GetSPIRoute - read ARE-enabled interrupt routing information
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  routing configuration
+ */
+uint64_t GetSPIRoute(uint32_t id);
+
+/*
+ * SetSPITarget - configure the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ *  target - 8-bit target bitmap
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPITarget(uint32_t id, uint32_t target);
+
+/*
+ * GetSPITarget - read the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *  8-bit target bitmap
+ */
+uint32_t GetSPITarget(uint32_t id);
+
+/*
+ * ConfigureSPI - setup an interrupt as edge- or level-triggered
+ *
+ * Inputs
+ *
+ *   id - interrupt identifier
+ *
+ *   config - desired configuration
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
+
+/*
+ * SetSPIPending - mark an interrupt as pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetSPIPending(uint32_t id);
+
+/*
+ * ClearSPIPending - mark an interrupt as not pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearSPIPending(uint32_t id);
+
+/*
+ * GetSPIPending - query whether an interrupt is pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetSPIPending(uint32_t id);
+
+/*
+ * SetSPISecurity - mark a shared peripheral interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityBlock - mark a block of 32 shared peripheral
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  block - which block to mark (e.g. 1 = Ints 32-63)
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityAll - mark all shared peripheral interrupts
+ *     as security <group>
+ *
+ * Inputs:
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityAll(GICIGROUPRBits_t group);
+
+/**********************************************************************/
+
+/*
+ * GIC Re-Distributor Function Prototypes
+ *
+ * The model for calling Redistributor functions is that, rather than
+ * identifying the target redistributor with every function call, the
+ * SelectRedistributor() function is used to identify which redistributor
+ * is to be used for all functions until a different redistributor is
+ * explicitly selected
+ */
+
+/*
+ * WakeupGICR - wake up a Redistributor
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to wakeup
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void WakeupGICR(uint32_t gicr);
+
+/*
+ * EnablePrivateInt - enable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * DisablePrivateInt - disable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
+
+/*
+ * GetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *   Int priority
+ */
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
+
+#endif /* ndef GICV3_h */
+
+/* EOF GICv3.h */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h
new file mode 100644
index 00000000..0928d14c
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h
@@ -0,0 +1,113 @@
+//
+// Aliases for GICv3 registers
+//
+// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef GICV3_ALIASES_H
+#define GICV3_ALIASES_H
+
+#ifndef __clang__
+
+/*
+ * Mapping of MSR and MRS to physical and virtual CPU interface registers
+ *
+ * Arm Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3.0 and version 4.0
+ * Table 8-5
+ */
+#define ICC_AP0R0_EL1       S3_0_C12_C8_4
+#define ICC_AP0R1_EL1       S3_0_C12_C8_5
+#define ICC_AP0R2_EL1       S3_0_C12_C8_6
+#define ICC_AP0R3_EL1       S3_0_C12_C8_7
+
+#define ICC_AP1R0_EL1       S3_0_C12_C9_0
+#define ICC_AP1R1_EL1       S3_0_C12_C9_1
+#define ICC_AP1R2_EL1       S3_0_C12_C9_2
+#define ICC_AP1R3_EL1       S3_0_C12_C9_3
+
+#define ICC_ASGI1R_EL1      S3_0_C12_C11_6
+
+#define ICC_BPR0_EL1        S3_0_C12_C8_3
+#define ICC_BPR1_EL1        S3_0_C12_C12_3
+
+#define ICC_CTLR_EL1        S3_0_C12_C12_4
+#define ICC_CTLR_EL3        S3_6_C12_C12_4
+
+#define ICC_DIR_EL1         S3_0_C12_C11_1
+
+#define ICC_EOIR0_EL1       S3_0_C12_C8_1
+#define ICC_EOIR1_EL1       S3_0_C12_C12_1
+
+#define ICC_HPPIR0_EL1      S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1      S3_0_C12_C12_2
+
+#define ICC_IAR0_EL1        S3_0_C12_C8_0
+#define ICC_IAR1_EL1        S3_0_C12_C12_0
+
+#define ICC_IGRPEN0_EL1     S3_0_C12_C12_6
+#define ICC_IGRPEN1_EL1     S3_0_C12_C12_7
+#define ICC_IGRPEN1_EL3     S3_6_C12_C12_7
+
+#define ICC_PMR_EL1         S3_0_C4_C6_0
+#define ICC_RPR_EL1         S3_0_C12_C11_3
+
+#define ICC_SGI0R_EL1       S3_0_C12_C11_7
+#define ICC_SGI1R_EL1       S3_0_C12_C11_5
+
+#define ICC_SRE_EL1         S3_0_C12_C12_5
+#define ICC_SRE_EL2         S3_4_C12_C9_5
+#define ICC_SRE_EL3         S3_6_C12_C12_5
+
+/*
+ * Mapping of MSR and MRS to virtual interface control registers
+ *
+ * Arm Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3.0 and version 4.0
+ * Table 8-6
+ */
+#define ICH_AP0R0_EL2       S3_4_C12_C8_0
+#define ICH_AP0R1_EL2       S3_4_C12_C8_1
+#define ICH_AP0R2_EL2       S3_4_C12_C8_2
+#define ICH_AP0R3_EL2       S3_4_C12_C8_3
+
+#define ICH_AP1R0_EL2       S3_4_C12_C9_0
+#define ICH_AP1R1_EL2       S3_4_C12_C9_1
+#define ICH_AP1R2_EL2       S3_4_C12_C9_2
+#define ICH_AP1R3_EL2       S3_4_C12_C9_3
+
+#define ICH_HCR_EL2         S3_4_C12_C11_0
+
+#define ICH_VTR_EL2         S3_4_C12_C11_1
+
+#define ICH_MISR_EL2        S3_4_C12_C11_2
+
+#define ICH_EISR_EL2        S3_4_C12_C11_3
+
+#define ICH_ELRSR_EL2       S3_4_C12_C11_5
+
+#define ICH_VMCR_EL2        S3_4_C12_C11_7
+
+#define ICH_LR0_EL2         S3_4_C12_C12_0
+#define ICH_LR1_EL2         S3_4_C12_C12_1
+#define ICH_LR2_EL2         S3_4_C12_C12_2
+#define ICH_LR3_EL2         S3_4_C12_C12_3
+#define ICH_LR4_EL2         S3_4_C12_C12_4
+#define ICH_LR5_EL2         S3_4_C12_C12_5
+#define ICH_LR6_EL2         S3_4_C12_C12_6
+#define ICH_LR7_EL2         S3_4_C12_C12_7
+#define ICH_LR8_EL2         S3_4_C12_C13_0
+#define ICH_LR9_EL2         S3_4_C12_C13_1
+#define ICH_LR10_EL2        S3_4_C12_C13_2
+#define ICH_LR11_EL2        S3_4_C12_C13_3
+#define ICH_LR12_EL2        S3_4_C12_C13_4
+#define ICH_LR13_EL2        S3_4_C12_C13_5
+#define ICH_LR14_EL2        S3_4_C12_C13_6
+#define ICH_LR15_EL2        S3_4_C12_C13_7
+
+#endif /* not __clang__ */
+
+#endif /* GICV3_ALIASES */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h
new file mode 100644
index 00000000..2b8a2d3e
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h
@@ -0,0 +1,254 @@
+/*
+ * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_gicc_h
+#define GICV3_gicc_h
+
+#include "GICv3_aliases.h"
+
+#define stringify_no_expansion(x) #x
+#define stringify(x) stringify_no_expansion(x)
+
+/**********************************************************************/
+
+typedef enum
+{
+    sreSRE = (1 << 0),
+    sreDFB = (1 << 1),
+    sreDIB = (1 << 2),
+    sreEnable = (1 << 3)
+} ICC_SREBits_t;
+
+static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL2(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    igrpEnable = (1 << 0),
+    igrpEnableGrp1NS = (1 << 0),
+    igrpEnableGrp1S = (1 << 2)
+} ICC_IGRPBits_t;
+
+static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    ctlrCBPR = (1 << 0),
+    ctlrCBPR_EL1S = (1 << 0),
+    ctlrEOImode = (1 << 1),
+    ctlrCBPR_EL1NS = (1 << 1),
+    ctlrEOImode_EL3 = (1 << 2),
+    ctlrEOImode_EL1S = (1 << 3),
+    ctlrEOImode_EL1NS = (1 << 4),
+    ctlrRM = (1 << 5),
+    ctlrPMHE = (1 << 6)
+} ICC_CTLRBits_t;
+
+static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
+{
+    asm("msr  "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
+{
+    asm("msr  "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+static inline uint64_t getICC_IAR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_IAR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_EOIR0(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_EOIR1(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_DIR(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_PMR(uint32_t priority)
+{
+    asm("msr  "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority));
+}
+
+static inline void setICC_BPR0(uint32_t binarypoint)
+{
+    asm("msr  "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline void setICC_BPR1(uint32_t binarypoint)
+{
+    asm("msr  "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline uint64_t getICC_BPR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_BPR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_RPR(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    sgirIRMTarget = 0,
+    sgirIRMAll = (1ull << 40)
+} ICC_SGIRBits_t;
+
+static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+#endif /* ndef GICV3_gicc_h */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c
new file mode 100644
index 00000000..2cf9e843
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c
@@ -0,0 +1,339 @@
+/*
+ * GICv3_gicd.c - generic driver code for GICv3 distributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include <stdint.h>
+
+#include "GICv3.h"
+
+typedef struct
+{
+        volatile uint32_t GICD_CTLR;              // +0x0000
+  const volatile uint32_t GICD_TYPER;             // +0x0004
+  const volatile uint32_t GICD_IIDR;              // +0x0008
+
+  const volatile uint32_t padding0;               // +0x000c
+
+        volatile uint32_t GICD_STATUSR;           // +0x0010
+
+  const volatile uint32_t padding1[3];            // +0x0014
+
+        volatile uint32_t IMP_DEF[8];             // +0x0020
+
+        volatile uint32_t GICD_SETSPI_NSR;        // +0x0040
+  const volatile uint32_t padding2;               // +0x0044
+        volatile uint32_t GICD_CLRSPI_NSR;        // +0x0048
+  const volatile uint32_t padding3;               // +0x004c
+        volatile uint32_t GICD_SETSPI_SR;         // +0x0050
+  const volatile uint32_t padding4;               // +0x0054
+        volatile uint32_t GICD_CLRSPI_SR;         // +0x0058
+
+  const volatile uint32_t padding5[3];            // +0x005c
+
+        volatile uint32_t GICD_SEIR;              // +0x0068
+
+  const volatile uint32_t padding6[5];            // +0x006c
+
+        volatile uint32_t GICD_IGROUPR[32];       // +0x0080
+
+        volatile uint32_t GICD_ISENABLER[32];     // +0x0100
+        volatile uint32_t GICD_ICENABLER[32];     // +0x0180
+        volatile uint32_t GICD_ISPENDR[32];       // +0x0200
+        volatile uint32_t GICD_ICPENDR[32];       // +0x0280
+        volatile uint32_t GICD_ISACTIVER[32];     // +0x0300
+        volatile uint32_t GICD_ICACTIVER[32];     // +0x0380
+
+        volatile uint8_t  GICD_IPRIORITYR[1024];  // +0x0400
+        volatile uint8_t  GICD_ITARGETSR[1024];   // +0x0800
+        volatile uint32_t GICD_ICFGR[64];         // +0x0c00
+        volatile uint32_t GICD_IGRPMODR[32];      // +0x0d00
+  const volatile uint32_t padding7[32];           // +0x0d80
+        volatile uint32_t GICD_NSACR[64];         // +0x0e00
+
+        volatile uint32_t GICD_SGIR;              // +0x0f00
+
+  const volatile uint32_t padding8[3];            // +0x0f04
+
+        volatile uint32_t GICD_CPENDSGIR[4];      // +0x0f10
+        volatile uint32_t GICD_SPENDSGIR[4];      // +0x0f20
+
+  const volatile uint32_t padding9[52];           // +0x0f30
+  const volatile uint32_t padding10[5120];        // +0x1000
+
+        volatile uint64_t GICD_IROUTER[1024];     // +0x6000
+} GICv3_distributor;
+
+/*
+ * use the scatter file to place GICD
+ */
+GICv3_distributor __attribute__((section(".gicd"))) gicd;
+
+void ConfigGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR = flags;
+}
+
+void EnableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR |= flags;
+}
+
+void DisableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR &= ~flags;
+}
+
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
+{
+    if (dosync)
+    {
+	const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
+	const uint32_t tval = flags & tmask;
+
+	while ((gicd.GICD_CTLR & tmask) != tval)
+	    continue;
+    }
+    else
+	gicd.GICD_CTLR = flags;
+}
+
+void EnableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ISENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void DisableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ICENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void SetSPIPriority(uint32_t id, uint32_t priority)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    gicd.GICD_IPRIORITYR[bank] = priority;
+}
+
+uint32_t GetSPIPriority(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
+}
+
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
+}
+
+uint64_t GetSPIRoute(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    return gicd.GICD_IROUTER[bank];
+}
+
+void SetSPITarget(uint32_t id, uint32_t target)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    gicd.GICD_ITARGETSR[bank] = target;
+}
+
+uint32_t GetSPITarget(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    /*
+     * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
+     * target bitmap per register
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
+}
+
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
+{
+    uint32_t bank, tmp;
+
+    /*
+     * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
+     * configuration per register
+     */
+    bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
+    config &= 3;
+
+    id = (id & 0xf) << 1;
+
+    tmp = gicd.GICD_ICFGR[bank];
+    tmp &= ~(3 << id);
+    tmp |= config << id;
+    gicd.GICD_ICFGR[bank] = tmp;
+}
+
+void SetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ISPENDR[bank] = 1 << id;
+}
+
+void ClearSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ICPENDR[bank] = 1 << id;
+}
+
+uint32_t GetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    return (gicd.GICD_ICPENDR[bank] >> id) & 1;
+}
+
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
+{
+    uint32_t bank, groupmod;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicd.GICD_IGROUPR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGROUPR[bank] &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicd.GICD_IGRPMODR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
+}
+
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
+{
+    uint32_t groupmod;
+    const uint32_t nbits = (sizeof group * 8) - 1;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
+
+    /*
+     * get each bit of group config duplicated over all 32-bits in a word
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicd.GICD_IGROUPR[block] = group;
+    gicd.GICD_IGRPMODR[block] = groupmod;
+}
+
+void SetSPISecurityAll(GICIGROUPRBits_t group)
+{
+    uint32_t block;
+
+    /*
+     * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
+     * want to iterate over all blocks excluding 0 (which are the
+     * SGI/PPI interrupts, and not relevant here)
+     */
+    for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
+	SetSPISecurityBlock(block, group);
+}
+
+/* EOF GICv3_gicd.c */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c
new file mode 100644
index 00000000..ef5c8925
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c
@@ -0,0 +1,289 @@
+/*
+ * GICv3_gicr.c - generic driver code for GICv3 redistributor
+ *
+ * Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include "GICv3.h"
+
+/*
+ * physical LPI Redistributor register map
+ */
+typedef struct
+{
+        volatile uint32_t GICR_CTLR;             // +0x0000 - RW - Redistributor Control Register
+  const volatile uint32_t GICR_IIDR;             // +0x0004 - RO - Implementer Identification Register
+  const volatile uint32_t GICR_TYPER[2];         // +0x0008 - RO - Redistributor Type Register
+        volatile uint32_t GICR_STATUSR;          // +0x0010 - RW - Error Reporting Status Register, optional
+        volatile uint32_t GICR_WAKER;            // +0x0014 - RW - Redistributor Wake Register
+  const volatile uint32_t padding1[2];           // +0x0018 - RESERVED
+#ifndef USE_GIC600
+        volatile uint32_t IMPDEF1[8];            // +0x0020 - ?? - IMPLEMENTATION DEFINED
+#else
+        volatile uint32_t GICR_FCTLR;            // +0x0020 - RW - Function Control Register
+        volatile uint32_t GICR_PWRR;             // +0x0024 - RW - Power Management Control Register
+        volatile uint32_t GICR_CLASS;            // +0x0028 - RW - Class Register
+  const volatile uint32_t padding2[5];           // +0x002C - RESERVED
+#endif
+        volatile uint64_t GICR_SETLPIR;          // +0x0040 - WO - Set LPI Pending Register
+        volatile uint64_t GICR_CLRLPIR;          // +0x0048 - WO - Clear LPI Pending Register
+  const volatile uint32_t padding3[8];           // +0x0050 - RESERVED
+        volatile uint64_t GICR_PROPBASER;        // +0x0070 - RW - Redistributor Properties Base Address Register
+        volatile uint64_t GICR_PENDBASER;        // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
+  const volatile uint32_t padding4[8];           // +0x0080 - RESERVED
+        volatile uint64_t GICR_INVLPIR;          // +0x00A0 - WO - Redistributor Invalidate LPI Register
+  const volatile uint32_t padding5[2];           // +0x00A8 - RESERVED
+        volatile uint64_t GICR_INVALLR;          // +0x00B0 - WO - Redistributor Invalidate All Register
+  const volatile uint32_t padding6[2];           // +0x00B8 - RESERVED
+        volatile uint64_t GICR_SYNCR;            // +0x00C0 - RO - Redistributor Synchronize Register
+  const volatile uint32_t padding7[2];           // +0x00C8 - RESERVED
+  const volatile uint32_t padding8[12];          // +0x00D0 - RESERVED
+        volatile uint64_t IMPDEF2;               // +0x0100 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding9[2];           // +0x0108 - RESERVED
+        volatile uint64_t IMPDEF3;               // +0x0110 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding10[2];          // +0x0118 - RESERVED
+} GICv3_redistributor_RD;
+
+/*
+ * SGI and PPI Redistributor register map
+ */
+typedef struct
+{
+  const volatile uint32_t padding1[32];          // +0x0000 - RESERVED
+        volatile uint32_t GICR_IGROUPR0;         // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
+  const volatile uint32_t padding2[31];          // +0x0084 - RESERVED
+        volatile uint32_t GICR_ISENABLER;        // +0x0100 - RW - Interrupt Set-Enable Registers
+  const volatile uint32_t padding3[31];          // +0x0104 - RESERVED
+        volatile uint32_t GICR_ICENABLER;        // +0x0180 - RW - Interrupt Clear-Enable Registers
+  const volatile uint32_t padding4[31];          // +0x0184 - RESERVED
+        volatile uint32_t GICR_ISPENDR;          // +0x0200 - RW - Interrupt Set-Pending Registers
+  const volatile uint32_t padding5[31];          // +0x0204 - RESERVED
+        volatile uint32_t GICR_ICPENDR;          // +0x0280 - RW - Interrupt Clear-Pending Registers
+  const volatile uint32_t padding6[31];          // +0x0284 - RESERVED
+        volatile uint32_t GICR_ISACTIVER;        // +0x0300 - RW - Interrupt Set-Active Register
+  const volatile uint32_t padding7[31];          // +0x0304 - RESERVED
+        volatile uint32_t GICR_ICACTIVER;        // +0x0380 - RW - Interrupt Clear-Active Register
+  const volatile uint32_t padding8[31];          // +0x0184 - RESERVED
+        volatile uint8_t  GICR_IPRIORITYR[32];   // +0x0400 - RW - Interrupt Priority Registers
+  const volatile uint32_t padding9[504];         // +0x0420 - RESERVED
+        volatile uint32_t GICR_ICnoFGR[2];       // +0x0C00 - RW - Interrupt Configuration Registers
+  const volatile uint32_t padding10[62];         // +0x0C08 - RESERVED
+        volatile uint32_t GICR_IGRPMODR0;        // +0x0D00 - RW - ????
+  const volatile uint32_t padding11[63];         // +0x0D04 - RESERVED
+        volatile uint32_t GICR_NSACR;            // +0x0E00 - RW - Non-Secure Access Control Register
+} GICv3_redistributor_SGI;
+
+/*
+ * We have a multiplicity of GIC Redistributors; on the GIC-AEM and
+ * GIC-500 they are arranged as one 128KB region per redistributor: one
+ * 64KB page of GICR LPI registers, and one 64KB page of GICR Private
+ * Int registers
+ */
+typedef struct
+{
+    union
+    {
+        GICv3_redistributor_RD RD_base;
+        uint8_t padding[64 * 1024];
+    } RDblock;
+
+    union
+    {
+        GICv3_redistributor_SGI SGI_base;
+        uint8_t padding[64 * 1024];
+    } SGIblock;
+} GICv3_GICR;
+
+/*
+ * use the scatter file to place GIC Redistributor base address
+ *
+ * although this code doesn't know how many Redistributor banks
+ * a particular system will have, we declare gicrbase as an array
+ * to avoid unwanted compiler optimisations when calculating the
+ * base of a particular Redistributor bank
+ */
+static const GICv3_GICR gicrbase[2] __attribute__((section (".gicr")));
+
+/**********************************************************************/
+
+/*
+ * utility functions to calculate base of a particular
+ * Redistributor bank
+ */
+
+static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
+{
+    GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
+
+    return &((arraybase + gicr)->RDblock.RD_base);
+}
+
+static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
+{
+    GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
+
+    return &(arraybase[gicr].SGIblock.SGI_base);
+}
+
+/**********************************************************************/
+
+void WakeupGICR(uint32_t gicr)
+{
+    GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
+#ifdef USE_GIC600
+    //Power up Re-distributor for GIC-600
+    gicrRD->GICR_PWRR = 0x2;
+#endif
+
+    /*
+     * step 1 - ensure GICR_WAKER.ProcessorSleep is off
+     */
+    gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
+
+    /*
+     * step 2 - wait for children asleep to be cleared
+     */
+    while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
+        continue;
+
+    /*
+     * OK, GICR is go
+     */
+    return;
+}
+
+void EnablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISENABLER = 1 << id;
+}
+
+void DisablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICENABLER = 1 << id;
+}
+
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    gicrSGI->GICR_IPRIORITYR[id] = priority;
+}
+
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
+}
+
+void SetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISPENDR = 1 << id;
+}
+
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ICPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICPENDR = 1 << id;
+}
+
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
+}
+
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    uint32_t groupmod;
+
+    /*
+     * GICR_IGROUPR0 is one 32-bit register
+     */
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+        gicrSGI->GICR_IGROUPR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+        gicrSGI->GICR_IGRPMODR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
+}
+
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    const uint32_t nbits = (sizeof group * 8) - 1;
+    uint32_t groupmod;
+
+    /*
+     * get each bit of group config duplicated over all 32 bits
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicrSGI->GICR_IGROUPR0 = group;
+    gicrSGI->GICR_IGRPMODR0 = groupmod;
+}
+
+/* EOF GICv3_gicr.c */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S
new file mode 100644
index 00000000..77fa0a0f
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S
@@ -0,0 +1,86 @@
+//
+// Armv8-A AArch64 - Basic Mutex Example
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global _mutex_initialize
+    .global _mutex_acquire
+    .global _mutex_release
+
+//
+// These routines implement the mutex management functions required for running
+// the Arm C library in a multi-threaded environment.
+//
+// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
+//
+// **********************************************************************
+//
+
+    .type _mutex_initialize, "function"
+    .cfi_startproc
+_mutex_initialize:
+
+    //
+    // mark the mutex as unlocked
+    //
+    mov     w1, #0
+    str     w1, [x0]
+
+    //
+    // we are running multi-threaded, so set a non-zero return
+    // value (function prototype says use 1)
+    //
+    mov     w0, #1
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+
+    //
+    // send ourselves an event, so we don't stick on the wfe at the
+    // top of the loop
+    //
+    sevl
+
+    //
+    // wait until the mutex is available
+    //
+loop:
+    wfe
+    ldaxr   w1, [x0]
+    cbnz    w1, loop
+
+    //
+    // mutex is (at least, it was) available - try to claim it
+    //
+    mov     w1, #1
+    stxr    w2, w1, [x0]
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+
+    mov     w1, #0
+    stlr    w1, [x0]
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h
new file mode 100644
index 00000000..52c9a0fe
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h
@@ -0,0 +1,66 @@
+//
+// Private Peripheral Map for the v8 Architecture Envelope Model
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef PPM_AEM_H
+#define PPM_AEM_H
+
+//
+// Distributor layout
+//
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+//
+// CPU Interface layout
+//
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+
+#endif // PPM_AEM_H
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c
new file mode 100644
index 00000000..139a848c
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c
@@ -0,0 +1,392 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+#include <stddef.h>
+
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     0x20000
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define a memory area to create a byte pool in.  */
+
+UCHAR                   memory_area[DEMO_BYTE_POOL_SIZE] __attribute__((aligned (8)));
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_TIMER                timer_0;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+UCHAR   event_buffer[65536];
+
+#endif
+
+
+/* Define main entry point.  */
+
+int main(void)
+{
+
+    /* Initialize timer for ThreadX.  */
+    extern void init_timer(void);    /* in timer_interrupts.c  */
+    init_timer();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+
+    /* The functions doesn't really return*/
+    return 0;
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+    tx_trace_enable(event_buffer, sizeof(event_buffer), 32);
+#endif
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+            
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+            
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.launch b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.launch
new file mode 100644
index 00000000..dd31854e
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.launch
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+    <stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+    <stringAttribute key="ANDROID_APPLICATION" value=""/>
+    <stringAttribute key="ANDROID_APP_DIR" value=""/>
+    <stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+    <mapAttribute key="AverageDurationTracker">
+        <mapEntry key="*Fetching Data" value="89578513"/>
+        <mapEntry key="*Fetching Data Model" value="2493472"/>
+        <mapEntry key="*FunctionLoader" value="137168653"/>
+        <mapEntry key="*list global low level symbols" value="1874854"/>
+        <mapEntry key="*loading memory from target" value="2367919"/>
+        <mapEntry key="*loading values from target" value="14527866"/>
+        <mapEntry key="*trace" value="334742630"/>
+        <mapEntry key="*updating expressions" value="13294796"/>
+        <mapEntry key="*updating local_variables" value="461891"/>
+        <mapEntry key="*updating registers" value="47308607"/>
+        <mapEntry key="*updating variables" value="877039"/>
+        <mapEntry key="AddEventObserver" value="15327360"/>
+        <mapEntry key="Evaluate" value="2889227"/>
+        <mapEntry key="ResumeToHere" value="20159012"/>
+        <mapEntry key="Retrieving globals list" value="21298708"/>
+        <mapEntry key="areCachesAvailable" value="790123"/>
+        <mapEntry key="backtrace" value="2055607"/>
+        <mapEntry key="break" value="9373846"/>
+        <mapEntry key="checking tracepoints" value="356506"/>
+        <mapEntry key="compute execution mode" value="614405"/>
+        <mapEntry key="console" value="11946310"/>
+        <mapEntry key="continue" value="89894665"/>
+        <mapEntry key="core" value="3342238"/>
+        <mapEntry key="directory" value="9093151"/>
+        <mapEntry key="disable" value="2444670"/>
+        <mapEntry key="disassemble" value="102336593"/>
+        <mapEntry key="enable" value="5445745"/>
+        <mapEntry key="evaluate" value="5333036"/>
+        <mapEntry key="evaluate address" value="1056014"/>
+        <mapEntry key="finish" value="20115248"/>
+        <mapEntry key="get byte order" value="633302"/>
+        <mapEntry key="get capabilities" value="391473"/>
+        <mapEntry key="get execution addresss" value="378753"/>
+        <mapEntry key="get source lines" value="433235"/>
+        <mapEntry key="get substitute paths" value="530227"/>
+        <mapEntry key="getValidEncodings" value="1253192"/>
+        <mapEntry key="initialize command help" value="162747357"/>
+        <mapEntry key="interrupt" value="32230330"/>
+        <mapEntry key="list breakpoint options" value="942716"/>
+        <mapEntry key="list breakpoints" value="1662534"/>
+        <mapEntry key="list instruction sets" value="2089700"/>
+        <mapEntry key="list signals" value="2135916"/>
+        <mapEntry key="list source files" value="1035061"/>
+        <mapEntry key="list watchpoint options" value="5077266"/>
+        <mapEntry key="list watchpoints" value="1381601"/>
+        <mapEntry key="loadfile" value="783604485"/>
+        <mapEntry key="next" value="35850257"/>
+        <mapEntry key="query supports threads" value="215433"/>
+        <mapEntry key="remove" value="5206014"/>
+        <mapEntry key="run script" value="119182154"/>
+        <mapEntry key="set $pc" value="7542800"/>
+        <mapEntry key="set CWD" value="19506638"/>
+        <mapEntry key="set breakpoint properties" value="7969728"/>
+        <mapEntry key="set debug-from" value="2212118"/>
+        <mapEntry key="set substitute-path" value="40982781"/>
+        <mapEntry key="source use_model_semihosting.ds" value="21345112"/>
+        <mapEntry key="start" value="67867450"/>
+        <mapEntry key="step" value="37429909"/>
+        <mapEntry key="stepi" value="29574773"/>
+        <mapEntry key="synchronizing trace ranges" value="68477"/>
+        <mapEntry key="target reset" value="32992642"/>
+        <mapEntry key="toggleBreakpoint" value="26265474"/>
+        <mapEntry key="waitForTargetToStop" value="73434147"/>
+        <mapEntry key="write expression" value="21220700"/>
+    </mapAttribute>
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+        <mapEntry key="4" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="5" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="6" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+        <mapEntry key="7" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
+    </mapAttribute>
+    <stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;255&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;159&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;75&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;242&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.MemoryView" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;page&gt;&#10;&#9;&lt;memoryView/&gt;&#10;&lt;/page&gt;&#10;"/>
+    <listAttribute key="debugger.view.MemoryView:current">
+        <listEntry value=""/>
+        <listEntry value=""/>
+    </listAttribute>
+    <stringAttribute key="debugger.view.NewRegisterView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;49&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;45&#9;-1&#9;true&#9;3&#9;false&#9;true&#9;42&#9;-1&#9;true&#9;4&#9;false&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;false&#9;true&#9;62&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
+    <stringAttribute key="debugger.view.NewRegisterView:_selectedRegisterSet" value="All registers"/>
+    <mapAttribute key="debugger.view.NewRegisterView_registerSets"/>
+    <stringAttribute key="debugger.view.StackView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;117&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;108&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;57&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;158&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
+    <listAttribute key="debugger.view.TraceView:TRACE_EXPORT_FILTERS"/>
+    <stringAttribute key="debugger.view.VariableTreeView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;149&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;95&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;42&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;62&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
+    <listAttribute key="debugger.view.VariableTreeView:USER_ADDED_FILE_STATICS"/>
+    <listAttribute key="debugger.view.VariableTreeView:USER_ADDED_GLOBALS"/>
+    <booleanAttribute key="debugger.view.expression.DrawAsHex" value="false"/>
+    <booleanAttribute key="debugger.view.register.DrawAsHex" value="false"/>
+    <stringAttribute key="debugger.view.symbols.FunctionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;53&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;103&#9;-1&#9;true&#9;2&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;90&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;86&#9;-1&#9;true&#9;5&#9;false&#9;true&#9;41&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;112&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;54&#9;-1&#9;true"/>
+    <booleanAttribute key="debugger.view.variable.DrawAsHex" value="false"/>
+    <stringAttribute key="dtsl_config" value="DtslScript"/>
+    <stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
+    <stringAttribute key="dtsl_options_file" value="default"/>
+    <stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
+    <booleanAttribute key="linuxOS" value="false"/>
+    <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
+    <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
+    <booleanAttribute key="runAfterConnect" value="false"/>
+    <stringAttribute key="runTargetInitializationScript" value="${workspace_loc:/sample_threadx/use_model_semihosting.ds}"/>
+    <mapAttribute key="scripts_view_script_links">
+        <mapEntry key="B:\support\broadcom\a53smp_el1_clean_mar25\sample_threadx\use_model_semihosting.ds" value=""/>
+        <mapEntry key="B:\support\broadcom\tx58cortexa53arm\release\threadx\sample_threadx\use_model_semihosting.ds" value=""/>
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35_smp\gnu\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
+        <mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_smp\cortex_a35_smp\gnu\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
+        <mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x_smp\gnu\example_build\common\use_model_semihosting.ds" value=""/>
+        <mapEntry key="D:\Documents\work\get_threadx-smp_cortex-a53_gnu_working\threadx_arm\threadx\common\use_model_semihosting.ds" value=""/>
+        <mapEntry key="D:\Documents\work\get_threadx-smp_cortex-a53_gnu_working\threadx_arm\threadx\sample_threadx\use_model_semihosting.ds" value=""/>
+        <mapEntry key="D:\Documents\work\get_threadx-smp_cortex-a53_gnu_working\threadx_official_workspace_no_sevice_packs\threadx\common\use_model_semihosting.ds" value=""/>
+        <mapEntry key="D:\Documents\work\get_threadx-smp_cortex-a53_gnu_working\threadx_official_workspaces_no_sevice_packs\threadx\common\use_model_semihosting.ds" value=""/>
+    </mapAttribute>
+    <listAttribute key="setup">
+        <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
+        <listEntry value="FVP_Base_Cortex-A35x4"/>
+    </listAttribute>
+    <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
+    <stringAttribute key="substitutePath" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;tuplelist&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;/tmp/dgboter/bbs/dsggnu-vm-1-x86_64--mingw32-i686/buildbot/mingw32-i686--aarch64-elf/build/src/newlib-cygwin/libgloss/aarch64/&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;D:\Documents\work\toolchains\newlib-cygwin\libgloss\aarch64\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/sample_threadx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/tx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&lt;/tuplelist&gt;&#10;"/>
+    <stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
+</launchConfiguration>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld
new file mode 100644
index 00000000..e9b12a82
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld
@@ -0,0 +1,245 @@
+/* Linker script to place sections and symbol values.
+ * It references following symbols, which must be defined in code:
+ *   start64 : Entry point
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __cs3_peripherals
+ *   __code_start
+ *   __exidx_start
+ *   __exidx_end
+ *   __data_start
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   __stack
+ *   __el3_stack
+ *   __ttb0_l1
+ *   __ttb0_l2_ram
+ *   __ttb0_l2_private
+ *   __ttb0_l2_periph
+ *   __top_of_ram
+ */
+
+ENTRY(start64)
+
+SECTIONS
+{
+    /*
+     * CS3 Peripherals is a 64MB region from 0x1c000000
+     * that includes the following:
+     * System Registers             at 0x1C010000
+     * UART0 (PL011)                at 0x1C090000
+     * Color LCD Controller (PL111) at 0x1C1F0000
+     * plus a number of others.
+     * CS3_PERIPHERALS is used by the startup code for page-table generation
+     * This region is not truly empty, but we have no
+     * predefined objects that live within it
+     */
+    __cs3_peripherals  = 0x1c000000;
+
+    /*
+     * GICv3 distributor
+     */
+    .gicd 0x2f000000 (NOLOAD):
+    {
+        *(.gicd)
+    }
+
+    /*
+     * GICv3 redistributors
+     * 128KB for each redistributor in the system
+     */
+    .gicr 0x2f100000 (NOLOAD):
+    {
+        *(.gicr)
+    }
+
+    .vectors 0x80000000:
+    {
+        __code_start = .;
+        KEEP(*(StartUp))
+        KEEP(*(EL1VECTORS EL2VECTORS EL3VECTORS))
+    }
+
+    .init :
+    {
+        KEEP (*(SORT_NONE(.init)))
+    }
+
+    .text :
+    {
+        *(.text*)
+    }
+
+    .fini :
+    {
+        KEEP (*(SORT_NONE(.fini)))
+    }
+
+    .rodata :
+    {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+    }
+
+    .eh_frame :
+    {
+        KEEP (*(.eh_frame))
+    }
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    }
+
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    }
+
+    .preinit_array :
+    {
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+    }
+
+    .init_array :
+    {
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array ))
+        PROVIDE_HIDDEN (__init_array_end = .);
+    }
+
+    .fini_array :
+    {
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP (*(SORT(.fini_array.*)))
+        KEEP (*(.fini_array ))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+    }
+
+    .ctors :
+    {
+        /* gcc uses crtbegin.o to find the start of
+           the constructors, so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtbegin.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtbegin.o
+           is in.  */
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*crtbegin?.o(.ctors))
+        /* We don't want to include the .ctor section from
+           the crtend.o file until after the sorted ctors.
+           The .ctor section from the crtend file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+    }
+
+    .dtors :
+    {
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*crtbegin?.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+    }
+
+    .jcr :
+    {
+        KEEP (*(.jcr))
+    }
+
+    .data :
+    {
+        __data_start = . ;
+        *(.data .data.* .gnu.linkonce.d.*)
+        SORT(CONSTRUCTORS)
+    }
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    }
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(64);
+        __end__ = .;
+        PROVIDE(end = .);
+        . = . + 0x1000;
+    }
+
+    .stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 4 * 0x8000;
+        __stack = .;
+    }
+    
+    .handler_stack_limit (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 4 * 0x4000;
+        handler_stack_limit = .;
+    }
+
+    .el3_stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 4 * 0x1000;
+        __el3_stack = .;
+    }
+
+    .ttb0_l1 (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l1 = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_ram (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_ram = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_private (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_private = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_periph (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_periph = .;
+        . = . + 0x1000;
+    }
+
+    /*
+     * The startup code uses the end of this region to calculate
+     * the top of memory - don't place any RAM regions after it
+     */
+    __top_of_ram = .;
+}
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c
new file mode 100644
index 00000000..4dc009b2
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c
@@ -0,0 +1,122 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "sp804_timer.h"
+
+#define TIMER_SP804_CTRL_TIMEREN     (1 << 7)
+#define TIMER_SP804_CTRL_TIMERMODE   (1 << 6)        // Bit 6:
+#define TIMER_SP804_CTRL_INTENABLE   (1 << 5)
+#define TIMER_SP804_CTRL_TIMERSIZE   (1 << 1)        // Bit 1: 0=16-bit, 1=32-bit
+#define TIMER_SP804_CTRL_ONESHOT     (1 << 0)        // Bit 0: 0=wrapping, 1=one-shot
+
+#define TIMER_SP804_CTRL_PRESCALE_1  (0 << 2)        // clk/1
+#define TIMER_SP804_CTRL_PRESCALE_4  (1 << 2)        // clk/4
+#define TIMER_SP804_CTRL_PRESCALE_8  (2 << 2)        // clk/8
+
+struct sp804_timer
+{
+        volatile uint32_t Time1Load;     // +0x00
+  const volatile uint32_t Time1Value;    // +0x04 - RO
+        volatile uint32_t Timer1Control; // +0x08
+        volatile uint32_t Timer1IntClr;  // +0x0C - WO
+  const volatile uint32_t Timer1RIS;     // +0x10 - RO
+  const volatile uint32_t Timer1MIS;     // +0x14 - RO
+        volatile uint32_t Timer1BGLoad;  // +0x18
+
+        volatile uint32_t Time2Load;     // +0x20
+        volatile uint32_t Time2Value;    // +0x24
+        volatile uint8_t  Timer2Control; // +0x28
+        volatile uint32_t Timer2IntClr;  // +0x2C - WO
+  const volatile uint32_t Timer2RIS;     // +0x30 - RO
+  const volatile uint32_t Timer2MIS;     // +0x34 - RO
+        volatile uint32_t Timer2BGLoad;  // +0x38
+
+  // Not including ID registers
+
+};
+
+// Instance of the dual timer, will be placed using the scatter file
+struct sp804_timer* dual_timer;
+
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address)
+{
+  dual_timer = (struct sp804_timer*)address;
+  return;
+}
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
+{
+  uint32_t tmp = 0;
+
+  dual_timer->Time1Load = load_value;
+
+  // Fixed setting: 32-bit, no prescaling
+  tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
+
+  // Settings from parameters: interrupt generation & reload
+  tmp = tmp | interrupt | auto_reload;
+
+  // Write control register
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Starts the timer
+void startTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp | TIMER_SP804_CTRL_TIMEREN;      // Set TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Stops the timer
+void stopTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN;     // Clear TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void)
+{
+  return dual_timer->Time1Value;
+}
+
+
+void clearTimerIrq(void)
+{
+  // A write to this register, of any value, clears the interrupt
+  dual_timer->Timer1IntClr = 1;
+}
+
+
+// ------------------------------------------------------------
+// End of sp804_timer.c
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h
new file mode 100644
index 00000000..777062cc
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h
@@ -0,0 +1,53 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+// Header Filer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#ifndef _SP804_TIMER_
+#define _SP804_TIMER_
+
+#include <stdint.h>
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address);
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+
+#define SP804_AUTORELOAD   (0)
+#define SP804_SINGLESHOT   (1)
+#define SP804_GENERATE_IRQ (1 << 5)
+#define SP804_NO_IRQ       (0)
+
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
+
+
+// Starts the timer
+void startTimer(void);
+
+
+// Stops the timer
+void stopTimer(void);
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void);
+
+
+// Clears the timer interrupt
+void clearTimerIrq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of sp804_timer.h
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S
new file mode 100644
index 00000000..53f02e37
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S
@@ -0,0 +1,798 @@
+// ------------------------------------------------------------
+// Armv8-A MPCore EL3 AArch64 Startup Code
+//
+// Basic Vectors, MMU, caches and GICv3 initialization
+//
+// Exits in EL1 AArch64
+//
+// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_mmu.h"
+#include "v8_system.h"
+#include "GICv3_aliases.h"
+
+    .section StartUp, "ax"
+    .balign 4
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+
+    .global InvalidateUDCaches
+    .global ZeroBlock
+
+    .global SetPrivateIntSecurityBlock
+    .global SetSPISecurityAll
+    .global SetPrivateIntPriority
+
+    .global WakeupGICR
+    .global SyncAREinGICD
+    .global EnableGICD
+    .global EnablePrivateInt
+    .global GetPrivateIntPending
+    .global ClearPrivateIntPending
+
+    .global _start
+    .global MainApp
+
+    .global __code_start
+    .global __ttb0_l1
+    .global __ttb0_l2_ram
+    .global __ttb0_l2_periph
+    .global __top_of_ram
+    .global gicd
+    .global __stack
+    .global __el3_stack
+    .global __cs3_peripherals
+
+is_mmu_ready:
+.word 0
+
+
+// ------------------------------------------------------------
+
+    .global start64
+    .type start64, "function"
+start64:
+
+    //
+    // program the VBARs
+    //
+    ldr x1, =el1_vectors
+    msr VBAR_EL1, x1
+
+    ldr x1, =el2_vectors
+    msr VBAR_EL2, x1
+
+    ldr x1, =el3_vectors
+    msr VBAR_EL3, x1
+
+
+    // GIC-500 comes out of reset in GICv2 compatibility mode - first set
+    // system register enables for all relevant exception levels, and
+    // select GICv3 operating mode
+    //
+    msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL3, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
+
+    //
+    // set lower exception levels as non-secure, with no access
+    // back to EL2 or EL3, and are AArch64 capable
+    //
+    mov x3, #(SCR_EL3_RW  | \
+              SCR_EL3_SMD | \
+              SCR_EL3_NS)      // Set NS bit, to access Non-secure registers
+    msr SCR_EL3, x3
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL2, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
+
+
+    //
+    // no traps or VM modifications from the Hypervisor, EL1 is AArch64
+    //
+    mov x2, #HCR_EL2_RW
+    msr HCR_EL2, x2
+
+    //
+    // VMID is still significant, even when virtualisation is not
+    // being used, so ensure VTTBR_EL2 is properly initialised
+    //
+    msr VTTBR_EL2, xzr
+
+    //
+    // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
+    //  VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
+    // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
+    // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
+    // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
+    //
+    mrs x0, MPIDR_EL1
+    msr VMPIDR_EL2, x0
+    mrs x0, MIDR_EL1
+    msr VPIDR_EL2, x0
+
+    // extract the core number from MPIDR_EL1 and store it in
+    // x19 (defined by the AAPCS as callee-saved), so we can re-use
+    // the number later
+    //
+    bl GetCPUID
+    mov x19, x0
+
+    //
+    // neither EL3 nor EL2 trap floating point or accesses to CPACR
+    //
+    msr CPTR_EL3, xzr
+    msr CPTR_EL2, xzr
+
+    //
+    // SCTLR_ELx may come out of reset with UNKNOWN values so we will
+    // set the fields to 0 except, possibly, the endianess field(s).
+    // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
+    // is not strictly needed, since we're never in EL2 or EL0
+    //
+#ifdef __ARM_BIG_ENDIAN
+    mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
+#else
+    mov x0, #0
+#endif
+    msr SCTLR_EL3, x0
+    msr SCTLR_EL2, x0
+    msr SCTLR_EL1, x0
+
+#ifdef CORTEXA
+    //
+    // Configure ACTLR_EL[23]
+    // ----------------------
+    //
+    // These bits are IMPLEMENTATION DEFINED, so are different for
+    // different processors
+    //
+    // For Cortex-A57, the controls we set are:
+    //
+    //  Enable lower level access to CPUACTLR_EL1
+    //  Enable lower level access to CPUECTLR_EL1
+    //  Enable lower level access to L2CTLR_EL1
+    //  Enable lower level access to L2ECTLR_EL1
+    //  Enable lower level access to L2ACTLR_EL1
+    //
+    mov x0, #((1 << 0) | \
+              (1 << 1) | \
+              (1 << 4) | \
+              (1 << 5) | \
+              (1 << 6))
+
+    msr ACTLR_EL3, x0
+    msr ACTLR_EL2, x0
+
+    //
+    // configure CPUECTLR_EL1
+    //
+    // These bits are IMP DEF, so need to different for different
+    // processors
+    //
+    // SMPEN - bit 6 - Enables the processor to receive cache
+    //                 and TLB maintenance operations
+    //
+    // Note: For Cortex-A57/53 SMPEN should be set before enabling
+    //       the caches and MMU, or performing any cache and TLB
+    //       maintenance operations.
+    //
+    //       This register has a defined reset value, so we use a
+    //       read-modify-write sequence to set SMPEN
+    //
+    mrs x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
+    orr x0, x0, #(1 << 6)  // Set the SMPEN bit
+    msr S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
+
+    isb
+#endif
+
+    //
+    // That's the last of the control settings for now
+    //
+    // Note: no ISB after all these changes, as registers won't be
+    // accessed until after an exception return, which is itself a
+    // context synchronisation event
+    //
+
+    //
+    // Setup some EL3 stack space, ready for calling some subroutines, below.
+    //
+    // Stack space allocation is CPU-specific, so use CPU
+    // number already held in x19
+    //
+    // 2^12 bytes per CPU for the EL3 stacks
+    //
+    ldr x0, =__el3_stack
+    sub x0, x0, x19, lsl #12
+    mov sp, x0
+
+    //
+    // we need to configure the GIC while still in secure mode, specifically
+    // all PPIs and SPIs have to be programmed as Group1 interrupts
+    //
+
+    //
+    // Before the GIC can be reliably programmed, we need to
+    // enable Affinity Routing, as this affects where the configuration
+    // registers are (with Affinity Routing enabled, some registers are
+    // in the Redistributor, whereas those same registers are in the
+    // Distributor with Affinity Routing disabled (i.e. when in GICv2
+    // compatibility mode).
+    //
+    mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
+    mov x1, x19
+    bl  SyncAREinGICD
+
+    //
+    // The Redistributor comes out of reset assuming the processor is
+    // asleep - correct that assumption
+    //
+    mov w0, w19
+    bl  WakeupGICR
+
+    //
+    // Now we're ready to set security and other initialisations
+    //
+    // This is a per-CPU configuration for these interrupts
+    //
+    // for the first cluster, CPU number is the redistributor index
+    //
+    mov w0, w19
+    mov w1, #1    // gicigroupr_G1NS
+    bl  SetPrivateIntSecurityBlock
+
+    //
+    // While we're in the Secure World, set the priority mask low enough
+    // for it to be writable in the Non-Secure World
+    //
+    //mov x0, #16 << 3    // 5 bits of priority in the Secure world
+    mov x0, #0xFF  // for Non-Secure interrupts
+    msr ICC_PMR_EL1, x0
+
+    //
+    // there's more GIC setup to do, but only for the primary CPU
+    //
+    cbnz x19, drop_to_el1
+
+    //
+    // There's more to do to the GIC - call the utility routine to set
+    // all SPIs to Group1
+    //
+    mov w0, #1    // gicigroupr_G1NS
+    bl  SetSPISecurityAll
+
+    //
+    // Set up EL1 entry point and "dummy" exception return information,
+    // then perform exception return to enter EL1
+    //
+    .global drop_to_el1
+drop_to_el1:
+    adr x1, el1_entry_aarch64
+    msr ELR_EL3, x1
+    mov x1, #(AARCH64_SPSR_EL1h | \
+              AARCH64_SPSR_F  | \
+              AARCH64_SPSR_I  | \
+              AARCH64_SPSR_A)
+    msr SPSR_EL3, x1
+    eret
+
+
+
+// ------------------------------------------------------------
+// EL1 - Common start-up code
+// ------------------------------------------------------------
+
+    .global el1_entry_aarch64
+    .type el1_entry_aarch64, "function"
+el1_entry_aarch64:
+
+    //
+    // Now we're in EL1, setup the application stack
+    // the scatter file allocates 2^14 bytes per app stack
+    //
+    ldr x0, =handler_stack_limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+    MSR     SPSel, #0
+    ISB
+    ldr x0, =__stack
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+
+    //
+    // Enable floating point
+    //
+    mov x0, #CPACR_EL1_FPEN
+    msr CPACR_EL1, x0
+
+    //
+    // Invalidate caches and TLBs for all stage 1
+    // translations used at EL1
+    //
+    // Cortex-A processors automatically invalidate their caches on reset
+    // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
+    // It is therefore not necessary for software to invalidate the caches 
+    // on startup, however, this is done here in case of a warm reset.
+    bl  InvalidateUDCaches
+    tlbi VMALLE1
+
+
+    //
+    // Set TTBR0 Base address
+    //
+    // The CPUs share one set of translation tables that are
+    // generated by CPU0 at run-time
+    //
+    // TTBR1_EL1 is not used in this example
+    //
+    ldr x1, =__ttb0_l1
+    msr TTBR0_EL1, x1
+
+
+    //
+    // Set up memory attributes
+    //
+    // These equate to:
+    //
+    // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
+    // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
+    // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
+    //
+    mov  x1, #0xff44
+    movk x1, #4, LSL #16    // equiv to: movk x1, #0x0000000000040000
+    msr MAIR_EL1, x1
+
+
+    //
+    // Set up TCR_EL1
+    //
+    // We're using only TTBR0 (EPD1 = 1), and the page table entries:
+    //  - are using an 8-bit ASID from TTBR0
+    //  - have a 4K granularity (TG0 = 0b00)
+    //  - are outer-shareable (SH0 = 0b10)
+    //  - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
+    //  - map
+    //      + 32 bits of VA space (T0SZ = 0x20)
+    //      + into a 32-bit PA space (IPS = 0b000)
+    //
+    //     36   32   28   24   20   16   12    8    4    0
+    //  -----+----+----+----+----+----+----+----+----+----+
+    //       |    |    |OOII|    |    |    |OOII|    |    |
+    //    TT |    |    |RRRR|E T |   T|    |RRRR|E T |   T|
+    //    BB | I I|TTSS|GGGG|P 1 |   1|TTSS|GGGG|P 0 |   0|
+    //    IIA| P P|GGHH|NNNN|DAS |   S|GGHH|NNNN|D S |   S|
+    //    10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
+    //
+    //    000 0000 0000 0000 1000 0000 0010 0101 0010 0000
+    //
+    //                    0x    8    0    2    5    2    0
+    //
+    // Note: the ISB is needed to ensure the changes to system
+    //       context are before the write of SCTLR_EL1.M to enable
+    //       the MMU. It is likely on a "real" implementation that
+    //       this setup would work without an ISB, due to the
+    //       amount of code that gets executed before enabling the
+    //       MMU, but that would not be architecturally correct.
+    //
+    ldr x1, =0x0000000000802520
+    msr TCR_EL1, x1
+    isb
+
+    //
+    // the primary CPU is going to use SGI 15 as a wakeup event
+    // to let us know when it is OK to proceed, so prepare for
+    // receiving that interrupt
+    //
+    // NS interrupt priorities run from 0 to 15, with 15 being
+    // too low a priority to ever raise an interrupt, so let's
+    // use 14
+    //
+    mov w0, w19
+    mov w1, #0
+    mov w2, #14 << 4    // we're in NS world, so 4 bits of priority,
+                        // 8-bit field, - 4 = 4-bit shift
+    bl SetPrivateIntPriority
+
+    mov w0, w19
+    mov w1, #0
+    bl  EnablePrivateInt
+
+    //
+    // set priority mask as low as possible; although,being in the
+    // NS World, we can't set bit[7] of the priority, we still
+    // write all 8-bits of priority to an ICC register
+    //
+    mov x0, #31 << 3
+    msr ICC_PMR_EL1, x0
+
+    //
+    // set global enable and wait for our interrupt to arrive
+    //
+    mov x0, #1
+    msr ICC_IGRPEN1_EL1, x0
+    isb
+
+    //
+    // x19 already contains the CPU number, so branch to secondary
+    // code if we're not on CPU0
+    //
+    cbnz x19, el1_secondary
+
+    //
+    // Fall through to primary code
+    //
+
+
+//
+// ------------------------------------------------------------
+//
+// EL1 - primary CPU init code
+//
+// This code is run on CPU0, while the other CPUs are in the
+// holding pen
+//
+
+    .global el1_primary
+    .type el1_primary, "function"
+el1_primary:
+
+    //
+    // Turn on the banked GIC distributor enable,
+    // ready for individual CPU enables later
+    //
+    mov w0, #(1 << 1)  // gicdctlr_EnableGrp1A
+    bl  EnableGICD
+
+    //
+    // Generate TTBR0 L1
+    //
+    // at 4KB granularity, 32-bit VA space, table lookup starts at
+    // L1, with 1GB regions
+    //
+    // we are going to create entries pointing to L2 tables for a
+    // couple of these 1GB regions, the first of which is the
+    // RAM on the VE board model - get the table addresses and
+    // start by emptying out the L1 page tables (4 entries at L1
+    // for a 4K granularity)
+    //
+    // x21 = address of L1 tables
+    //
+    ldr x21, =__ttb0_l1
+    mov x0, x21
+    mov x1, #(4 << 3)
+    bl  ZeroBlock
+
+    //
+    // time to start mapping the RAM regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // x22 = address of L2 tables, needs to be remembered in case
+    //       we want to re-use the tables for mapping peripherals
+    //
+    ldr x22, =__ttb0_l2_ram
+    mov x1, #(512 << 3)
+    mov x0, x22
+    bl  ZeroBlock
+
+    //
+    // Get the start address of RAM (the EXEC region) into x4
+    // and calculate the offset into the L1 table (1GB per region,
+    // max 4GB)
+    //
+    // x23 = L1 table offset, saved for later comparison against
+    //       peripheral offset
+    //
+    ldr x4, =__code_start
+    ubfx x23, x4, #30, #2
+
+    orr x1, x22, #TT_S1_ATTR_PAGE
+    str x1, [x21, x23, lsl #3]
+
+    //
+    // we've already used the RAM start address in x4 - we now need
+    // to get this in terms of an offset into the L2 page tables,
+    // where each entry covers 2MB
+    //
+    ubfx x2, x4, #21, #9
+
+    //
+    // TOP_OF_RAM in the scatter file marks the end of the
+    // Execute region in RAM: convert the end of this region to an
+    // offset too, being careful to round up, then calculate the
+    // number of entries to write
+    //
+    ldr x5, =__top_of_ram
+    sub  x3, x5, #1
+    ubfx x3, x3, #21, #9
+    add  x3, x3, #1
+    sub  x3, x3, x2
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as Shared, Normal WBWA (MAIR[1]) with a flat
+    // VA->PA translation
+    //
+    bic x4, x4, #((1 << 21) - 1)
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (1 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_SH_INNER | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // factor the offset into the page table address and then write
+    // the entries
+    //
+    add x0, x22, x2, lsl #3
+
+loop1:
+    subs x3, x3, #1
+    str x1, [x0], #8
+    add x1, x1, #0x200, LSL #12    // equiv to add x1, x1, #(1 << 21)  // 2MB per entry
+    bne loop1
+
+
+    //
+    // now mapping the Peripheral regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // The assumption here is that all peripherals live within
+    // a common 1GB region (i.e. that there's a single set of
+    // L2 pages for all the peripherals). We only use a UART
+    // and the GIC in this example, so the assumption is sound
+    //
+    // x24 = address of L2 peripheral tables
+    //
+    ldr x24, =__ttb0_l2_periph
+
+    //
+    // get the GICD address into x4 and calculate
+    // the offset into the L1 table
+    //
+    // x25 = L1 table offset
+    //
+    ldr x4, =gicd
+    ubfx x25, x4, #30, #2
+
+    //
+    // here's the tricky bit: it's possible that the peripherals are
+    // in the same 1GB region as the RAM, in which case we don't need
+    // to prime a separate set of L2 page tables, nor add them to the
+    // L1 tables
+    //
+    // if we're going to re-use the TTB0_L2_RAM tables, get their
+    // address into x24, which is used later on to write the PTEs
+    //
+    cmp x25, x23
+    csel x24, x22, x24, EQ
+    b.eq nol2setup
+
+    //
+    // Peripherals are in a separate 1GB region, and so have their own
+    // set of L2 tables - clean out the tables and add them to the L1
+    // table
+    //
+    mov x0, x24
+    mov x1, #512 << 3
+    bl  ZeroBlock
+
+    orr x1, x24, #TT_S1_ATTR_PAGE
+    str x1, [x21, x25, lsl #3]
+
+    //
+    // there's only going to be a single 2MB region for GICD (in
+    // x4) - get this in terms of an offset into the L2 page tables
+    //
+    // with larger systems, it is possible that the GIC redistributor
+    // registers require extra 2MB pages, in which case extra code
+    // would be required here
+    //
+nol2setup:
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry for this, so no loop as we have for RAM, above
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // we have CS3_PERIPHERALS that include the UART controller
+    //
+    // Again, the code is making assumptions - this time that the CS3_PERIPHERALS
+    // region uses the same 1GB portion of the address space as the GICD,
+    // and thus shares the same set of L2 page tables
+    //
+    // Get CS3_PERIPHERALS address into x4 and calculate the offset into the
+    // L2 tables
+    //
+    ldr x4, =__cs3_peripherals
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry again - write it
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // issue a barrier to ensure all table entry writes are complete
+    //
+    dsb ish
+
+    ldr x1, =is_mmu_ready
+    mov x2, #1
+    str x2, [x1]
+
+    //
+    // Enable the MMU.  Caches will be enabled later, after scatterloading.
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+    
+    //
+    // The Arm Architecture Reference Manual for Armv8-A states:
+    //
+    //     Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
+    //     Correspondingly, the sequence for ensuring that modifications to instructions are available
+    //     for execution must include invalidation of the modified locations from the instruction cache,
+    //     even if the instructions are held in Normal Non-cacheable memory.
+    //     This includes cases where the instruction cache is disabled.
+    //
+
+    dsb ish     // ensure all previous stores have completed before invalidating
+    ic  ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
+    dsb ish     // ensure completion on inner shareable domain   (which includes secondary cores)
+    isb
+
+    // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    msr SCTLR_EL1, x1
+    isb
+
+    // Zero the bss
+    ldr x0, =__bss_start__ // Start of block
+    mov x1, #0             // Fill value
+    ldr x2, =__bss_end__   // End of block
+    sub x2, x2, x0         // Length of block
+    bl  memset
+
+    // Set up the standard file handles
+    bl  initialise_monitor_handles
+
+    // Set up _fini and fini_array to be called at exit
+    ldr x0, =__libc_fini_array
+    bl  atexit
+
+    // Call preinit_array, _init and init_array
+    bl  __libc_init_array
+
+    // Set argc = 1, argv[0] = "" and then call main
+    .pushsection .data
+    .align 3
+argv:
+    .dword arg0
+    .dword 0
+arg0:
+    .byte 0
+    .popsection
+
+    mov x0, #1
+    ldr x1, =argv
+    bl main
+
+    b exit // Will not return
+    
+// ------------------------------------------------------------
+// EL1 - secondary CPU init code
+//
+// This code is run on CPUs 1, 2, 3 etc....
+// ------------------------------------------------------------
+
+    .global el1_secondary
+    .type el1_secondary, "function"
+el1_secondary:
+
+wait_for_mmu_ready:
+    ldr x1, =is_mmu_ready
+    ldr x1, [x1]
+    cmp x1, #1
+    b.ne wait_for_mmu_ready
+
+    //
+    // Enable the MMU and caches
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    /* EL: Secondary core entrance.  */
+    B       _tx_thread_smp_initialize_wait
+
+loop_wfi:
+    dsb SY      // Clear all pending data accesses
+    wfi         // Go to sleep
+
+    //
+    // something woke us from our wait, was it the required interrupt?
+    //
+    mov w0, w19
+    mov w1, #15
+    bl  GetPrivateIntPending
+    cbz w0, loop_wfi
+
+    //
+    // it was - there's no need to actually take the interrupt,
+    // so just clear it
+    //
+    mov w0, w19
+    mov w1, #15
+    bl  ClearPrivateIntPending
+
+    //
+    // Branch to thread start
+    //
+    //B  MainApp
+    
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/timer_interrupts.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/timer_interrupts.c
new file mode 100644
index 00000000..7b0996ef
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/timer_interrupts.c
@@ -0,0 +1,152 @@
+/* Bare-metal example for Armv8-A FVP Base model */
+
+/* Timer and interrupts */
+
+/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */
+/* Use, modification and redistribution of this file is subject to your      */
+/* possession of a valid DS-5 end user licence agreement and your compliance */
+/* with all applicable terms and conditions of such licence agreement.       */
+
+#include <stdio.h>
+
+#include "GICv3.h"
+#include "GICv3_gicc.h"
+#include "sp804_timer.h"
+
+void   _tx_timer_interrupt(void);
+
+// LED Base address
+#define LED_BASE (volatile unsigned int *)0x1C010008
+
+
+void nudge_leds(void) // Move LEDs along
+{
+    static int state = 1;
+    static int value = 1;
+
+    if (state)
+    {
+        int max = (1 << 7);
+        value <<= 1;
+        if (value == max)
+            state = 0;
+    }
+    else
+    {
+        value >>= 1;
+        if (value == 1)
+            state = 1;
+    }
+
+    *LED_BASE = value;  // Update LEDs hardware
+}
+
+
+// Initialize Timer 0 and Interrupt Controller
+void init_timer(void)
+{
+    // Enable interrupts
+    __asm("MSR DAIFClr, #0xF");
+    setICC_IGRPEN1_EL1(igrpEnable);
+
+    // Configure the SP804 timer to generate an interrupt
+    setTimerBaseAddress(0x1C110000);
+    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
+    startTimer();
+
+    // The SP804 timer generates SPI INTID 34.  Enable
+    // this ID, and route it to core 0.0.0.0 (this one!)
+    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
+    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
+    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
+    EnableSPI(34);                                   // Enable INTID 34
+}
+
+
+// --------------------------------------------------------
+
+void irqHandler(void)
+{
+  unsigned int ID;
+
+  ID = getICC_IAR1(); // readIntAck();
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+      //printf("irqHandler() - Reserved INTID %d\n\n", ID);
+      return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("irqHandler() - External timer interrupt\n\n");
+      nudge_leds();
+      clearTimerIrq();
+
+      /* Call ThreadX timer interrupt processing.  */
+      _tx_timer_interrupt();
+
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("irqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
+
+// --------------------------------------------------------
+
+// Not actually used in this example, but provided for completeness
+
+void fiqHandler(void)
+{
+  unsigned int ID;
+  unsigned int aliased = 0;
+
+  ID = getICC_IAR0(); // readIntAck();
+  printf("fiqHandler() - Read %d from IAR0\n", ID);
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+    printf("fiqHandler() - Reserved INTID %d\n\n", ID);
+    ID = getICC_IAR1(); // readAliasedIntAck();
+    printf("fiqHandler() - Read %d from AIAR\n", ID);
+    aliased = 1;
+
+    // If still spurious then simply return
+    if ((1020 <= ID) && (ID <= 1023))
+        return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      printf("fiqHandler() - External timer interrupt\n\n");
+      clearTimerIrq();
+      break;
+
+    default:
+      // Unexpected ID value
+      printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  // NOTE: If the ID was read from the Aliased IAR, then
+  // the aliased EOI register must be used
+  if (aliased == 0)
+    setICC_EOIR0(ID); // writeEOI(ID);
+  else
+    setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/use_model_semihosting.ds b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/use_model_semihosting.ds
new file mode 100644
index 00000000..6fde52b2
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/use_model_semihosting.ds
@@ -0,0 +1 @@
+set semihosting enabled off
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S
new file mode 100644
index 00000000..d86fecb6
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S
@@ -0,0 +1,163 @@
+// ------------------------------------------------------------
+// Armv8-A AArch64 - Common helper functions
+//
+// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global EnableCachesEL1
+    .global DisableCachesEL1
+    .global InvalidateUDCaches
+    .global GetMIDR
+    .global GetMPIDR
+    .global GetCPUID
+
+// ------------------------------------------------------------
+
+//
+// void EnableCachesEL1(void)
+//
+//    enable Instruction and Data caches
+//
+    .type EnableCachesEL1, "function"
+    .cfi_startproc
+EnableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    orr x0, x0, #SCTLR_ELx_I
+    orr x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+    .type DisableCachesEL1, "function"
+    .cfi_startproc
+DisableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    bic x0, x0, #SCTLR_ELx_I
+    bic x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// void InvalidateUDCaches(void)
+//
+//    Invalidate data and unified caches
+//
+    .type InvalidateUDCaches, "function"
+    .cfi_startproc
+InvalidateUDCaches:
+    // From the Armv8-A Architecture Reference Manual
+
+    dmb  ish                   // ensure all prior inner-shareable accesses have been observed
+
+    mrs  x0, CLIDR_EL1
+    and  w3, w0, #0x07000000   // get 2 x level of coherence
+    lsr  w3, w3, #23
+    cbz  w3, finished
+    mov  w10, #0               // w10 = 2 x cache level
+    mov  w8, #1                // w8 = constant 0b1
+loop_level:
+    add  w2, w10, w10, lsr #1  // calculate 3 x cache level
+    lsr  w1, w0, w2            // extract 3-bit cache type for this level
+    and  w1, w1, #0x7
+    cmp  w1, #2
+    b.lt next_level            // no data or unified cache at this level
+    msr  CSSELR_EL1, x10       // select this cache level
+    isb                        // synchronize change of csselr
+    mrs  x1, CCSIDR_EL1        // read ccsidr
+    and  w2, w1, #7            // w2 = log2(linelen)-4
+    add  w2, w2, #4            // w2 = log2(linelen)
+    ubfx w4, w1, #3, #10       // w4 = max way number, right aligned
+    clz  w5, w4                // w5 = 32-log2(ways), bit position of way in dc operand
+    lsl  w9, w4, w5            // w9 = max way number, aligned to position in dc operand
+    lsl  w16, w8, w5           // w16 = amount to decrement way number per iteration
+loop_way:
+    ubfx w7, w1, #13, #15      // w7 = max set number, right aligned
+    lsl  w7, w7, w2            // w7 = max set number, aligned to position in dc operand
+    lsl  w17, w8, w2           // w17 = amount to decrement set number per iteration
+loop_set:
+    orr  w11, w10, w9          // w11 = combine way number and cache number ...
+    orr  w11, w11, w7          // ... and set number for dc operand
+    dc   isw, x11              // do data cache invalidate by set and way
+    subs w7, w7, w17           // decrement set number
+    b.ge loop_set
+    subs x9, x9, x16           // decrement way number
+    b.ge loop_way
+next_level:
+    add  w10, w10, #2          // increment 2 x cache level
+    cmp  w3, w10
+    b.gt loop_level
+    dsb  sy                    // ensure completion of previous cache maintenance operation
+    isb
+finished:
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// ID Register functions
+//
+
+    .type GetMIDR, "function"
+    .cfi_startproc
+GetMIDR:
+
+    mrs x0, MIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetMPIDR, "function"
+    .cfi_startproc
+GetMPIDR:
+
+    mrs x0, MPIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetCPUID, "function"
+    .cfi_startproc
+GetCPUID:
+
+    mrs x0, MIDR_EL1
+    ubfx    x0, x0, #4, #12 // extract PartNum
+    cmp x0, #0xD0B          // Cortex-A76
+    b.eq DynamIQ
+    cmp x0, #0xD0A          // Cortex-A75
+    b.eq DynamIQ
+    cmp x0, #0xD05          // Cortex-A55
+    b.eq DynamIQ
+    b Others
+DynamIQ:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+
+Others:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h
new file mode 100644
index 00000000..0185feba
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h
@@ -0,0 +1,118 @@
+//
+// Defines for v8 Memory Model
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_MMU_H
+#define V8_MMU_H
+
+//
+// Translation Control Register fields
+//
+// RGN field encodings
+//
+#define TCR_RGN_NC   0b00
+#define TCR_RGN_WBWA 0b01
+#define TCR_RGN_WT   0b10
+#define TCR_RGN_WBRA 0b11
+
+//
+// Shareability encodings
+//
+#define TCR_SHARE_NONE  0b00
+#define TCR_SHARE_OUTER 0b10
+#define TCR_SHARE_INNER 0b11
+
+//
+// Granule size encodings
+//
+#define TCR_GRANULE_4K  0b00
+#define TCR_GRANULE_64K 0b01
+#define TCR_GRANULE_16K 0b10
+
+//
+// Physical Address sizes
+//
+#define TCR_SIZE_4G   0b000
+#define TCR_SIZE_64G  0b001
+#define TCR_SIZE_1T   0b010
+#define TCR_SIZE_4T   0b011
+#define TCR_SIZE_16T  0b100
+#define TCR_SIZE_256T 0b101
+
+//
+// Translation Control Register fields
+//
+#define TCR_EL1_T0SZ_SHIFT   0
+#define TCR_EL1_EPD0  (1 << 7)
+#define TCR_EL1_IRGN0_SHIFT  8
+#define TCR_EL1_ORGN0_SHIFT 10
+#define TCR_EL1_SH0_SHIFT   12
+#define TCR_EL1_TG0_SHIFT   14
+
+#define TCR_EL1_T1SZ_SHIFT  16
+#define TCR_EL1_A1   (1 << 22)
+#define TCR_EL1_EPD1 (1 << 23)
+#define TCR_EL1_IRGN1_SHIFT 24
+#define TCR_EL1_ORGN1_SHIFT 26
+#define TCR_EL1_SH1_SHIFT   28
+#define TCR_EL1_TG1_SHIFT   30
+#define TCR_EL1_IPS_SHIFT   32
+#define TCR_EL1_AS   (1 << 36)
+#define TCR_EL1_TBI0 (1 << 37)
+#define TCR_EL1_TBI1 (1 << 38)
+
+//
+// Stage 1 Translation Table descriptor fields
+//
+#define TT_S1_ATTR_FAULT (0b00 << 0)
+#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
+#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
+#define TT_S1_ATTR_PAGE  (0b11 << 0) // Level 3
+
+#define TT_S1_ATTR_MATTR_LSB 2
+
+#define TT_S1_ATTR_NS (1 << 5)
+
+#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
+#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
+#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
+#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
+
+#define TT_S1_ATTR_SH_NONE   (0b00 << 8)
+#define TT_S1_ATTR_SH_OUTER  (0b10 << 8)
+#define TT_S1_ATTR_SH_INNER  (0b11 << 8)
+
+#define TT_S1_ATTR_AF (1 << 10)
+#define TT_S1_ATTR_nG (1 << 11)
+
+#define TT_S1_ATTR_CONTIG (1 << 52)
+#define TT_S1_ATTR_PXN    (1 << 53)
+#define TT_S1_ATTR_UXN    (1 << 54)
+
+#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
+#define TT_S1_MAIR_DEV_nGnRE  0b00000100
+#define TT_S1_MAIR_DEV_nGRE   0b00001000
+#define TT_S1_MAIR_DEV_GRE    0b00001100
+
+//
+// Inner and Outer Normal memory attributes use the same bit patterns
+// Outer attributes just need to be shifted up
+//
+#define TT_S1_MAIR_OUTER_SHIFT 4
+
+#define TT_S1_MAIR_WT_TRANS_RA  0b0010
+
+#define TT_S1_MAIR_WB_TRANS_RA  0b0110
+#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
+
+#define TT_S1_MAIR_WT_RA  0b1010
+
+#define TT_S1_MAIR_WB_RA  0b1110
+#define TT_S1_MAIR_WB_RWA 0b1111
+
+#endif // V8_MMU_H
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h
new file mode 100644
index 00000000..ff96deff
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h
@@ -0,0 +1,115 @@
+//
+// Defines for v8 System Registers
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_SYSTEM_H
+#define V8_SYSTEM_H
+
+//
+// AArch64 SPSR
+//
+#define AARCH64_SPSR_EL3h 0b1101
+#define AARCH64_SPSR_EL3t 0b1100
+#define AARCH64_SPSR_EL2h 0b1001
+#define AARCH64_SPSR_EL2t 0b1000
+#define AARCH64_SPSR_EL1h 0b0101
+#define AARCH64_SPSR_EL1t 0b0100
+#define AARCH64_SPSR_EL0t 0b0000
+#define AARCH64_SPSR_RW (1 << 4)
+#define AARCH64_SPSR_F  (1 << 6)
+#define AARCH64_SPSR_I  (1 << 7)
+#define AARCH64_SPSR_A  (1 << 8)
+#define AARCH64_SPSR_D  (1 << 9)
+#define AARCH64_SPSR_IL (1 << 20)
+#define AARCH64_SPSR_SS (1 << 21)
+#define AARCH64_SPSR_V  (1 << 28)
+#define AARCH64_SPSR_C  (1 << 29)
+#define AARCH64_SPSR_Z  (1 << 30)
+#define AARCH64_SPSR_N  (1 << 31)
+
+//
+// Multiprocessor Affinity Register
+//
+#define MPIDR_EL1_AFF3_LSB 32
+#define MPIDR_EL1_U  (1 << 30)
+#define MPIDR_EL1_MT (1 << 24)
+#define MPIDR_EL1_AFF2_LSB 16
+#define MPIDR_EL1_AFF1_LSB  8
+#define MPIDR_EL1_AFF0_LSB  0
+#define MPIDR_EL1_AFF_WIDTH 8
+
+//
+// Data Cache Zero ID Register
+//
+#define DCZID_EL0_BS_LSB   0
+#define DCZID_EL0_BS_WIDTH 4
+#define DCZID_EL0_DZP_LSB  5
+#define DCZID_EL0_DZP (1 << 5)
+
+//
+// System Control Register
+//
+#define SCTLR_EL1_UCI     (1 << 26)
+#define SCTLR_ELx_EE      (1 << 25)
+#define SCTLR_EL1_E0E     (1 << 24)
+#define SCTLR_ELx_WXN     (1 << 19)
+#define SCTLR_EL1_nTWE    (1 << 18)
+#define SCTLR_EL1_nTWI    (1 << 16)
+#define SCTLR_EL1_UCT     (1 << 15)
+#define SCTLR_EL1_DZE     (1 << 14)
+#define SCTLR_ELx_I       (1 << 12)
+#define SCTLR_EL1_UMA     (1 << 9)
+#define SCTLR_EL1_SED     (1 << 8)
+#define SCTLR_EL1_ITD     (1 << 7)
+#define SCTLR_EL1_THEE    (1 << 6)
+#define SCTLR_EL1_CP15BEN (1 << 5)
+#define SCTLR_EL1_SA0     (1 << 4)
+#define SCTLR_ELx_SA      (1 << 3)
+#define SCTLR_ELx_C       (1 << 2)
+#define SCTLR_ELx_A       (1 << 1)
+#define SCTLR_ELx_M       (1 << 0)
+
+//
+// Architectural Feature Access Control Register
+//
+#define CPACR_EL1_TTA     (1 << 28)
+#define CPACR_EL1_FPEN    (3 << 20)
+
+//
+// Architectural Feature Trap Register
+//
+#define CPTR_ELx_TCPAC (1 << 31)
+#define CPTR_ELx_TTA   (1 << 20)
+#define CPTR_ELx_TFP   (1 << 10)
+
+//
+// Secure Configuration Register
+//
+#define SCR_EL3_TWE  (1 << 13)
+#define SCR_EL3_TWI  (1 << 12)
+#define SCR_EL3_ST   (1 << 11)
+#define SCR_EL3_RW   (1 << 10)
+#define SCR_EL3_SIF  (1 << 9)
+#define SCR_EL3_HCE  (1 << 8)
+#define SCR_EL3_SMD  (1 << 7)
+#define SCR_EL3_EA   (1 << 3)
+#define SCR_EL3_FIQ  (1 << 2)
+#define SCR_EL3_IRQ  (1 << 1)
+#define SCR_EL3_NS   (1 << 0)
+
+//
+// Hypervisor Configuration Register
+//
+#define HCR_EL2_ID   (1 << 33)
+#define HCR_EL2_CD   (1 << 32)
+#define HCR_EL2_RW   (1 << 31)
+#define HCR_EL2_TRVM (1 << 30)
+#define HCR_EL2_HVC  (1 << 29)
+#define HCR_EL2_TDZ  (1 << 28)
+
+#endif // V8_SYSTEM_H
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S
new file mode 100644
index 00000000..f0fcef26
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S
@@ -0,0 +1,69 @@
+//
+// Simple utility routines for baremetal v8 code
+//
+// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//
+// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
+//
+// Zero fill a block of memory
+//   Fill memory pages or similar structures with zeros.
+//   The byte count must be a multiple of the block fill size (16 bytes)
+//
+//  Inputs:
+//    blockPtr - base address of block to fill
+//    nBytes - block size, in bytes
+//
+//  Returns:
+//    pointer to just filled block, NULL if nBytes is
+//  incompatible with block fill size
+//
+    .global ZeroBlock
+    .type ZeroBlock, "function"
+    .cfi_startproc
+ZeroBlock:
+
+    //
+    // we fill data by steam, 16 bytes at a time: check that
+    // blocksize is a multiple of that
+    //
+    ubfx x2, x1, #0, #4
+    cbnz x2, incompatible
+
+    //
+    // we already have one register full of zeros, get another
+    //
+    mov x3, x2
+
+    //
+    // OK, set temporary pointer and away we go
+    //
+    add x0, x0, x1
+
+loop0:
+    subs x1, x1, #16
+    stp  x2, x3, [x0, #-16]!
+    b.ne loop0
+
+    //
+    // that's all - x0 will be back to its start value
+    //
+    ret
+
+    //
+    // parameters are incompatible with block size - return
+    // an indication that this is so
+    //
+incompatible:
+    mov x0,#0
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S
new file mode 100644
index 00000000..9e60e001
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S
@@ -0,0 +1,252 @@
+// ------------------------------------------------------------
+// Armv8-A Vector tables
+//
+// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+    .global c0sync1
+    .global irqHandler
+    .global fiqHandler
+    .global irqFirstLevelHandler
+    .global fiqFirstLevelHandler
+
+    .section  EL1VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el1_vectors:
+c0sync1: B c0sync1
+
+    .balign 0x80
+c0irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr1: B c0serr1
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync1: B cxsync1
+
+    .balign 0x80
+cxirq1: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr1: B cxserr1
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync1: B l64sync1
+
+    .balign 0x80
+l64irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr1: B l64serr1
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync1: B l32sync1
+
+    .balign 0x80
+l32irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr1: B l32serr1
+
+//----------------------------------------------------------------
+
+    .section  EL2VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el2_vectors:
+c0sync2: B c0sync2
+
+    .balign 0x80
+c0irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr2: B c0serr2
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync2: B cxsync2
+
+    .balign 0x80
+cxirq2: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr2: B cxserr2
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync2: B l64sync2
+
+    .balign 0x80
+l64irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr2: B l64serr2
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync2: B l32sync2
+
+    .balign 0x80
+l32irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr2: B l32serr2
+
+//----------------------------------------------------------------
+
+    .section  EL3VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el3_vectors:
+c0sync3: B c0sync3
+
+    .balign 0x80
+c0irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr3: B c0serr3
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync3: B cxsync3
+
+    .balign 0x80
+cxirq3: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr3: B cxserr3
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync3: B l64sync3
+
+    .balign 0x80
+l64irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr3: B l64serr3
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync3: B l32sync3
+
+    .balign 0x80
+l32irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr3: B l32serr3
+
+
+    .section InterruptHandlers, "ax"
+    .balign 4
+
+    .type irqFirstLevelHandler, "function"
+irqFirstLevelHandler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+  BL       irqHandler
+  B        _tx_thread_context_restore
+
+    .type fiqFirstLevelHandler, "function"
+fiqFirstLevelHandler:
+  STP      x29, x30, [sp, #-16]!
+  STP      x18, x19, [sp, #-16]!
+  STP      x16, x17, [sp, #-16]!
+  STP      x14, x15, [sp, #-16]!
+  STP      x12, x13, [sp, #-16]!
+  STP      x10, x11, [sp, #-16]!
+  STP      x8, x9, [sp, #-16]!
+  STP      x6, x7, [sp, #-16]!
+  STP      x4, x5, [sp, #-16]!
+  STP      x2, x3, [sp, #-16]!
+  STP      x0, x1, [sp, #-16]!
+
+  BL       fiqHandler
+
+  LDP      x0, x1, [sp], #16
+  LDP      x2, x3, [sp], #16
+  LDP      x4, x5, [sp], #16
+  LDP      x6, x7, [sp], #16
+  LDP      x8, x9, [sp], #16
+  LDP      x10, x11, [sp], #16
+  LDP      x12, x13, [sp], #16
+  LDP      x14, x15, [sp], #16
+  LDP      x16, x17, [sp], #16
+  LDP      x18, x19, [sp], #16
+  LDP      x29, x30, [sp], #16
+  ERET
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject
new file mode 100644
index 00000000..296685a7
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject
@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1413182734" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1413182734.1169749362" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/sample_threadx_module}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.848667697" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.2024653550" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.1939971857" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1613679555" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.261941817" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.1053841009" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
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+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
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+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.1741634605" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1189207744" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.62845631" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.208858280" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.267102905" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" valueType="boolean"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.1148824792" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
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+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.1591133511" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libs.1533546658" name="Libraries (-l)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libs" useByScannerDiscovery="false" valueType="libs">
+                                    									
+                                    <listOptionValue builtIn="false" value="txm"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.1940339274" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="--specs=nosys.specs -nostartfiles -e _txm_module_thread_shell_entry" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.script.124204299" name="Linker script" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.script" useByScannerDiscovery="false" value="..\sample_threadx_module.ld" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch.1660266056" name="Library search path (-L)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch" useByScannerDiscovery="false" valueType="libPaths">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;..\..\txm\Debug&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.extras.896111217" name="Other options (-Xlinker [option])" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.extras" useByScannerDiscovery="false" valueType="stringList">
+                                    									
+                                    <listOptionValue builtIn="false" value="-Map=sample_threadx_module.map"/>
+                                    								
+                                </option>
+                                								
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+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.413208540" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.2066918847" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.project b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.project
new file mode 100644
index 00000000..17f6aba3
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx_module</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.arm.debug.ds.nature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/gcc_setup.s b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/gcc_setup.s
new file mode 100644
index 00000000..7c454996
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/gcc_setup.s
@@ -0,0 +1,129 @@
+
+    .text
+    .align 4
+
+    .global _gcc_setup
+_gcc_setup:
+
+	sub 	sp, sp, 16		// Store other preserved registers here
+	str 	x30, [sp]
+
+    ldr     x3, =__FLASH_segment_start__
+    ldr     x4, =__RAM_segment_start__
+    mov     x5,x0
+
+// This is for modules linked to absolute addresses
+// On PIC modules x9 (or r9) will hold the data base address
+    ldr     x9, =__RAM_segment_start__
+
+    /* Copy GOT table. */
+  
+    ldr     x0, =__got_load_start__
+    sub     x0 ,x0, x3
+    add     x0, x0, x5
+    ldr     x1, =__new_got_start__
+    sub     x1, x1, x4
+    add     x1, x1, x9
+    ldr     x2, =__new_got_end__
+    sub     x2, x2, x4
+    add     x2, x2, x9
+
+new_got_setup:
+    cmp     x1, x2          // See if there are more GOT entries
+    beq     got_setup_done  // No, done with GOT setup
+    ldr     x6, [x0]        // Pickup current GOT entry
+    cmp     x6, #0          // Is it 0?
+    beq     address_built   // Yes, just skip the adjustment
+    cmp     x6, x4          // Is it in the code or data area?
+    blt     flash_area      // If less than, it is a code address
+    sub     x6, x6, x4      // Compute offset of data area
+    add     x6, x6, x9      // Build address based on the loaded data address
+    b       address_built   // Finished building address
+flash_area:
+    sub     x6, x6, x3      // Compute offset of code area
+    add     x6, x6, x5      // Build address based on the loaded code address
+address_built:
+    str     x6, [x1]        // Store in new GOT table
+    add     x0, x0, #4      // Move to next entry
+    add     x1, x1, #4      //
+    b       new_got_setup   // Continue at the top of the loop
+got_setup_done:
+
+
+    /* Copy initialised sections into RAM if required. */
+  
+    ldr     x0, =__data_load_start__
+    sub     x0, x0, x3
+    add     x0, x0, x5
+    ldr     x1, =__data_start__
+    sub     x1, x1, x4
+    add     x1, x1, x9
+    ldr     x2, =__data_end__
+    sub     x2, x2, x4
+    add     x2, x2, x9
+    bl      crt0_memory_copy
+  
+    /* Zero bss. */
+    
+    ldr     x0, =__bss_start__
+    sub     x0, x0, x4
+    add     x0, x0, x9
+    ldr     x1, =__bss_end__
+    sub     x1, x1, x4
+    add     x1, x1, x9
+    mov     x2, #0
+    bl      crt0_memory_set
+
+
+    /* Setup heap - not recommended for Threadx but here for compatibility reasons */
+
+    ldr     x0, =__heap_start__
+    sub     x0, x0, x4
+    add     x0, x0, x9
+    ldr     x1, =__heap_end__
+    sub     x1, x1, x4
+    add     x1, x1, x9
+    sub     x1, x1, x0
+    mov     x2, #0
+    str     x2, [x0]
+    add     x0, x0, #4
+    str     x1, [x0]
+    
+	ldr 	x30, [sp]		// Restore other preserved registers
+	add 	sp, sp, 16
+
+    ret	                    // Return to caller
+  
+
+  /* Startup helper functions. */
+
+    .align 4
+crt0_memory_copy:
+    cmp     x0, x1
+    beq     memory_copy_done
+    cmp     x2, x1
+    beq     memory_copy_done
+    sub     x2, x2, x1
+memory_copy_loop:
+    ldrb    w3, [x0]
+    add     x0, x0, #1
+    strb    w3, [x1]
+    add     x1, x1, #1
+    sub     x2, x2, #1
+    cmp     x2, #0
+    bne     memory_copy_loop
+memory_copy_done:
+    ret
+
+crt0_memory_set:
+    cmp     x0, x1
+    beq     memory_set_done
+    str     w2, [x0]
+    add     x0, x0, #1
+    b       crt0_memory_set
+memory_set_done:
+    ret
+
+    /* Setup attibutes of heap section so it doesn't take up room in the elf file */
+    .section .heap, "wa", %nobits
+  
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c
new file mode 100644
index 00000000..a974cdf1
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c
@@ -0,0 +1,467 @@
+/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes 
+   examples of eight threads of different priorities, using a message queue, semaphore, mutex, 
+   event flags group, byte pool, and block pool.  */
+
+/* Specify that this is a module!  */
+
+#define TXM_MODULE
+
+
+/* Include the ThreadX module definitions.  */
+
+#include "txm_module.h"
+
+
+/* Define constants.  */
+
+#define DEMO_BYTE_POOL_SIZE     (1024 * 48)
+#define DEMO_STACK_SIZE         (1024 * 4)
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the pool space in the bss section of the module. ULONG is used to 
+   get the word alignment.  */
+
+ULONG                   demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)];
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               *thread_0;
+TX_THREAD               *thread_1;
+TX_THREAD               *thread_2;
+TX_THREAD               *thread_3;
+TX_THREAD               *thread_4;
+TX_THREAD               *thread_5;
+TX_THREAD               *thread_6;
+TX_THREAD               *thread_7;
+TX_QUEUE                *queue_0;
+TX_SEMAPHORE            *semaphore_0;
+TX_MUTEX                *mutex_0;
+TX_EVENT_FLAGS_GROUP    *event_flags_0;
+TX_BYTE_POOL            *byte_pool_0;
+TX_BLOCK_POOL           *block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter = 0;
+ULONG           thread_1_counter = 0;
+ULONG           thread_1_messages_sent = 0;
+ULONG           thread_2_counter = 0;
+ULONG           thread_2_messages_received = 0;
+ULONG           thread_3_counter = 0;
+ULONG           thread_4_counter = 0;
+ULONG           thread_5_counter = 0;
+ULONG           thread_6_counter = 0;
+ULONG           thread_7_counter = 0;
+ULONG           semaphore_0_puts = 0;
+ULONG           event_0_sets = 0;
+ULONG           queue_0_sends = 0;
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+void  semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
+{
+
+    if (semaphore_ptr == semaphore_0)
+        semaphore_0_puts++;
+}
+
+
+void  event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
+{
+
+    if (event_flag_group_ptr == event_flags_0)
+        event_0_sets++;
+}
+
+
+void  queue_0_notify(TX_QUEUE *queue_ptr)
+{
+
+    if (queue_ptr == queue_0)
+        queue_0_sends++;
+}
+
+
+/* Define the module start function.  */
+
+void    demo_module_start(ULONG id)
+{
+
+UINT    status;
+CHAR    *pointer;
+
+
+    /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within
+       their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting 
+       the control block(s).  */
+    status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
+    while (status != TX_SUCCESS);
+    status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
+    while (status != TX_SUCCESS);
+                               
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
+    while (status != TX_SUCCESS);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the message queue.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    status = tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+    while (status != TX_SUCCESS);
+
+    status = tx_queue_send_notify(queue_0, queue_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    status = tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
+    while (status != TX_SUCCESS);
+
+    status = tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    status = tx_event_flags_create(event_flags_0, "module event flags 0");
+    while (status != TX_SUCCESS);
+
+    status = tx_event_flags_set_notify(event_flags_0, event_0_notify);
+    while (status != TX_SUCCESS);
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    status = tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the memory for a small block pool.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    status = tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+    while (status != TX_SUCCESS);
+
+    /* Allocate a block and release the block memory.  */
+    status = tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Release the block back to the pool.  */
+    status = tx_block_release(pointer);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 0.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create the main thread.  */
+    status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 1.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 2.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 3.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 4.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 5.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 6.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+
+    /* Allocate the stack for thread 7.  */
+    status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+    while (status != TX_SUCCESS);
+
+    status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+    while (status != TX_SUCCESS);
+}
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+    
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+       
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld
new file mode 100644
index 00000000..042b59bf
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld
@@ -0,0 +1,195 @@
+SECTIONS
+{
+  __FLASH_segment_start__ = 0x80180000;
+  __RAM_segment_start__   = 0x801A0000;
+
+  __HEAPSIZE__ = 1024;
+
+  __text_load_start__ =  ALIGN(__FLASH_segment_start__ , 4);
+  .text ALIGN(__text_load_start__ , 4) : AT(ALIGN(__text_load_start__, 4))
+  {
+    __preamble_start__ = .;
+    * (.txm_module_preamble)
+    __text_start__ = .;
+    *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table  )
+  }
+  __text_end__ = __text_start__ + SIZEOF(.text);
+
+  __dynsym_load_start__ =  ALIGN(__text_end__ , 4);
+  .dynsym ALIGN(__dynsym_load_start__ , 4) : AT(ALIGN(__dynsym_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.dynsym))
+    KEEP (*(.dynsym*))
+    . = ALIGN(4);
+  }
+  __dynsym_end__ = __dynsym_load_start__ + SIZEOF(.dynsym);
+
+  __dynstr_load_start__ =  ALIGN(__dynsym_end__ , 4);
+  .dynstr ALIGN(__dynstr_load_start__ , 4) : AT(ALIGN(__dynstr_load_start__, 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.dynstr))
+    KEEP (*(.dynstr*))
+    . = ALIGN(4);
+  }
+  __dynstr_end__ = __dynstr_load_start__ + SIZEOF(.dynstr);
+
+  __reldyn_load_start__ =  ALIGN(__dynstr_end__ , 4);
+  .rel.dyn ALIGN(__reldyn_load_start__ , 4) : AT(ALIGN(__reldyn_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.rel.dyn))
+    KEEP (*(.rel.dyn*))
+    . = ALIGN(4);
+  }
+  __reldyn_end__ = __reldyn_load_start__ + SIZEOF(.rel.dyn);
+
+  __relplt_load_start__ =  ALIGN(__reldyn_end__ , 4);
+  .rel.plt ALIGN(__relplt_load_start__ , 4) : AT(ALIGN(__relplt_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.rel.plt))
+    KEEP (*(.rel.plt*))
+    . = ALIGN(4);
+  }
+  __relplt_end__ = __relplt_load_start__ + SIZEOF(.rel.plt);
+
+  __plt_load_start__ =  ALIGN(__relplt_end__ , 4);
+  .plt ALIGN(__plt_load_start__ , 4) : AT(ALIGN(__plt_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.plt))
+    KEEP (*(.plt*))
+    . = ALIGN(4);
+  }
+  __plt_end__ = __plt_load_start__ + SIZEOF(.plt);
+
+  __interp_load_start__ =  ALIGN(__plt_end__ , 4);
+  .interp ALIGN(__interp_load_start__ , 4) : AT(ALIGN(__interp_load_start__ , 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.interp))
+    KEEP (*(.interp*))
+    . = ALIGN(4);
+  }
+  __interp_end__ = __interp_load_start__ + SIZEOF(.interp);
+
+  __hash_load_start__ =  ALIGN(__interp_end__ , 4);
+  .hash ALIGN(__hash_load_start__ , 4) : AT(ALIGN(__hash_load_start__, 4))
+  {
+    . = ALIGN(4);
+    KEEP (*(.hash))
+    KEEP (*(.hash*))
+    . = ALIGN(4);
+  }
+  __hash_end__ = __hash_load_start__ + SIZEOF(.hash);
+
+  __dtors_load_start__ = ALIGN(__hash_end__ , 4);
+  .dtors ALIGN(__hash_end__ , 4) : AT(ALIGN(__hash_end__ , 4))
+  {
+    __dtors_start__ = .;
+    KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))
+  }
+  __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
+
+  __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
+  .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
+  {
+    __ctors_start__ = .;
+    KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))
+  }
+  __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
+
+  __got_load_start__ = ALIGN(__ctors_end__ , 4);
+  .got ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
+  {
+    . = ALIGN(4);
+    _sgot = .;
+    KEEP (*(.got))
+    KEEP (*(.got*))
+    . = ALIGN(4);
+    _egot = .;
+  } 
+  __got_end__ =  __got_load_start__ + SIZEOF(.got);
+
+  __rodata_load_start__ = ALIGN(__got_end__ , 4);
+  .rodata ALIGN(__got_end__ , 4) : AT(ALIGN(__got_end__ , 4))
+  {
+    __rodata_start__ = .;
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+  }
+  __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
+ 
+  __code_size__ =  __rodata_end__ - __FLASH_segment_start__;
+
+  __fast_load_start__ = ALIGN(__rodata_end__ , 4);
+
+  __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
+
+  __new_got_start__ = ALIGN(__RAM_segment_start__ , 4);
+
+  __new_got_end__ =  __new_got_start__ + SIZEOF(.got);
+
+  .fast ALIGN(__new_got_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
+  {
+    __fast_start__ = .;
+    *(.fast .fast.*)
+  }
+  __fast_end__ = __fast_start__ + SIZEOF(.fast);
+
+  .fast_run ALIGN(__fast_end__ , 4) (NOLOAD) :
+  {
+    __fast_run_start__ = .;
+    . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
+  }
+  __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
+
+  __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
+  .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
+  {
+    __data_start__ = .;
+    *(.data .data.* .gnu.linkonce.d.*)
+  }
+  __data_end__ = __data_start__ + SIZEOF(.data);
+
+  __data_load_end__ = __data_load_start__ + SIZEOF(.data);
+
+  __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data);
+
+  .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
+  {
+    __data_run_start__ = .;
+    . = MAX(__data_run_start__ + SIZEOF(.data), .);
+  }
+  __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
+
+  __bss_load_start__ = ALIGN(__data_run_end__ , 4);
+  .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
+  {
+    __bss_start__ = .;
+    *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+  }
+  __bss_end__ = __bss_start__ + SIZEOF(.bss);
+
+  __non_init_load_start__ = ALIGN(__bss_end__ , 4);
+  .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
+  {
+    __non_init_start__ = .;
+    *(.non_init .non_init.*)
+  }
+  __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
+
+  __heap_load_start__ = ALIGN(__non_init_end__ , 4);
+  .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
+  {
+    __heap_start__ = .;
+    *(.heap)
+    . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
+  }
+  __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+  __data_size__ =  __heap_end__ - __RAM_segment_start__;
+
+}
+
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S
new file mode 100644
index 00000000..cce29ef8
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S
@@ -0,0 +1,53 @@
+    .section .txm_module_preamble
+    .align 4
+    
+    // External references
+    .global  _txm_module_thread_shell_entry
+    .global  _txm_module_callback_request_thread_entry
+    .global  demo_module_start
+
+    .global __txm_module_preamble
+__txm_module_preamble:
+    .dc.l   0x4D4F4455                                          // Module ID
+    .dc.l   0x6                                                 // Module Major Version
+    .dc.l   0x1                                                 // Module Minor Version
+    .dc.l   32                                                  // Module Preamble Size in 32-bit words
+    .dc.l   0x12345678                                          // Module ID (application defined)
+    .dc.l   0x02000000                                          // Module Properties where:
+                                                                //   Bits 31-24: Compiler ID
+                                                                //           0 -> IAR
+                                                                //           1 -> ARM
+                                                                //           2 -> GNU
+                                                                //   Bit 0:  0 -> Privileged mode execution
+                                                                //           1 -> User mode execution
+                                                                //   Bit 1:  0 -> No MPU protection
+                                                                //           1 -> MPU protection (must have user mode selected)
+                                                                //   Bit 2:  0 -> Disable shared/external memory access
+                                                                //           1 -> Enable shared/external memory access
+    .dc.l   _txm_module_thread_shell_entry                      // Module Shell Entry Point
+    .dc.l   demo_module_start                                   // Module Start Thread Entry Point
+    .dc.l   0                                                   // Module Stop Thread Entry Point
+    .dc.l   1                                                   // Module Start/Stop Thread Priority
+    .dc.l   4096                                                // Module Start/Stop Thread Stack Size
+    .dc.l   _txm_module_callback_request_thread_entry           // Module Callback Thread Entry
+    .dc.l   1                                                   // Module Callback Thread Priority
+    .dc.l   4096                                                // Module Callback Thread Stack Size
+    .dc.l   __code_size__                                       // Module Code Size
+    .dc.l   __data_size__                                       // Module Data Size
+    .dc.l   0                                                   // Reserved 0
+    .dc.l   0                                                   // Reserved 1
+    .dc.l   0                                                   // Reserved 2
+    .dc.l   0                                                   // Reserved 3
+    .dc.l   0                                                   // Reserved 4
+    .dc.l   0                                                   // Reserved 5
+    .dc.l   0                                                   // Reserved 6
+    .dc.l   0                                                   // Reserved 7
+    .dc.l   0                                                   // Reserved 8
+    .dc.l   0                                                   // Reserved 9
+    .dc.l   0                                                   // Reserved 10
+    .dc.l   0                                                   // Reserved 11
+    .dc.l   0                                                   // Reserved 12
+    .dc.l   0                                                   // Reserved 13
+    .dc.l   0                                                   // Reserved 14
+    .dc.l   0                                                   // Reserved 15
+
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject
new file mode 100644
index 00000000..572198b3
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject
@@ -0,0 +1,268 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.33749088" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.33749088.1343346543" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/sample_threadx_module_manager}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.910370896" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1331565505" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.831465095" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/sample_threadx_module_manager/inc_common_module_manager}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym.1613866201" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1769854265" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.268949876" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.1607040325" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.warnings.all.559759568" name="All warnings (-Wall)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.warnings.all" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.301538030" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.64294854" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1835980884" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.788212214" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                							
+                            </tool>
+                            							
+                            <tool command="aarch64-elf-gcc.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.1804365799" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.490655419" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" valueType="boolean"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.694327385" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym.1950316412" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.883450564" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.891273559" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
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+                                    									
+                                    <listOptionValue builtIn="false" value="tx"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch.764636049" name="Library search path (-L)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.libsearch" useByScannerDiscovery="false" valueType="libPaths">
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+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.2107716357" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.1675872554" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.exe.release.base.262471578">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" name="Release" parent="com.arm.eclipse.build.config.v6.exe.release.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.exe.release.base.262471578." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6.2039978271" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6">
+                            							
+                            <targetPlatform id="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6.2039978271.1401365679" name=""/>
+                            							
+                            <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx_module_manager}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.152908166" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/>
+                            							
+                            <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2113724202" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.1064912621" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
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+                                <inputType id="com.arm.tool.c.compiler.v6.base.input.274442412" superClass="com.arm.tool.c.compiler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.857388488" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
+                                								
+                                <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.703057645" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
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+                                								
+                                <inputType id="com.arm.tool.assembler.v6.base.input.2016749997" superClass="com.arm.tool.assembler.v6.base.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1332640632" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
+                            							
+                            <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1069857726" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="sample_threadx_module_manager.com.arm.eclipse.build.project.v6.exe.1027551600" name="Executable"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        		
+        <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.exe.debug.base.515451048;com.arm.eclipse.build.config.v6.exe.debug.base.515451048.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1331565505;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.301538030">
+            			
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
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+</cproject>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.project b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.project
new file mode 100644
index 00000000..310289aa
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.project
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>sample_threadx_module_manager</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_common_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
+		</link>
+		<link>
+			<name>src_common_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3.h
new file mode 100644
index 00000000..23bc7fd8
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3.h
@@ -0,0 +1,561 @@
+/*
+ * GICv3.h - data types and function prototypes for GICv3 utility routines
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_h
+#define GICV3_h
+
+#include <stdint.h>
+
+/*
+ * extra flags for GICD enable
+ */
+typedef enum
+{
+    gicdctlr_EnableGrp0 = (1 << 0),
+    gicdctlr_EnableGrp1NS = (1 << 1),
+    gicdctlr_EnableGrp1A = (1 << 1),
+    gicdctlr_EnableGrp1S = (1 << 2),
+    gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0),
+    gicdctlr_ARE_S = (1 << 4),	/* Enable Secure state affinity routing */
+    gicdctlr_ARE_NS = (1 << 5),	/* Enable Non-Secure state affinity routing */
+    gicdctlr_DS = (1 << 6),	/* Disable Security support */
+    gicdctlr_E1NWF = (1 << 7)	/* Enable "1-of-N" wakeup model */
+} GICDCTLRFlags_t;
+
+/*
+ * modes for SPI routing
+ */
+typedef enum
+{
+    gicdirouter_ModeSpecific = 0,
+    gicdirouter_ModeAny = (1 << 31)
+} GICDIROUTERBits_t;
+
+typedef enum
+{
+    gicdicfgr_Level = 0,
+    gicdicfgr_Edge = (1 << 1)
+} GICDICFGRBits_t;
+
+typedef enum
+{
+    gicigroupr_G0S = 0,
+    gicigroupr_G1NS = (1 << 0),
+    gicigroupr_G1S = (1 << 2)
+} GICIGROUPRBits_t;
+
+typedef enum
+{
+    gicrwaker_ProcessorSleep = (1 << 1),
+    gicrwaker_ChildrenAsleep = (1 << 2)
+} GICRWAKERBits_t;
+
+/**********************************************************************/
+
+/*
+ * Utility macros & functions
+ */
+#define RANGE_LIMIT(x)		((sizeof(x) / sizeof((x)[0])) - 1)
+
+static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2,
+					 uint32_t aff1, uint32_t aff0)
+{
+    /*
+     * only need to cast aff3 to get type promotion for all affinities
+     */
+    return ((((uint64_t)aff3 & 0xff) << 32) |
+	    ((aff2 & 0xff) << 16) |
+	    ((aff1 & 0xff) << 8) | aff0);
+}
+
+/**********************************************************************/
+
+/*
+ * GIC Distributor Function Prototypes
+ */
+
+/*
+ * ConfigGICD - configure GIC Distributor prior to enabling it
+ *
+ * Inputs:
+ *
+ *  control - control flags
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void ConfigGICD(GICDCTLRFlags_t flags);
+
+/*
+ * EnableGICD - top-level enable for GIC Distributor
+ *
+ * Inputs:
+ *
+ *  flags - new control flags to set
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void EnableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * DisableGICD - top-level disable for GIC Distributor
+ *
+ * Inputs
+ *
+ *  flags - control flags to clear
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ *  ConfigGICD() will set an absolute flags value, whereas
+ *  {En,Dis}ableGICD() will only {set,clear} the flag bits
+ *  passed as a parameter
+ */
+void DisableGICD(GICDCTLRFlags_t flags);
+
+/*
+ * SyncAREinGICD - synchronise GICD Address Routing Enable bits
+ *
+ * Inputs
+ *
+ *  flags - absolute flag bits to set in GIC Distributor
+ *
+ *  dosync - flag whether to wait for ARE bits to match passed
+ *      flag field (dosync = true), or whether to set absolute
+ *      flag bits (dosync = false)
+ *
+ * Returns
+ *
+ *  <nothing>
+ *
+ * NOTE:
+ *
+ * This function is used to resolve a race in an MP system whereby secondary
+ * CPUs cannot reliably program all Redistributor registers until the
+ * primary CPU has enabled Address Routing. The primary CPU will call this
+ * function with dosync = false, while the secondaries will call it with
+ * dosync = true.
+ */
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync);
+
+/*
+ * EnableSPI - enable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnableSPI(uint32_t id);
+
+/*
+ * DisableSPI - disable a specific shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisableSPI(uint32_t id);
+
+/*
+ * SetSPIPriority - configure the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetSPIPriority(uint32_t id, uint32_t priority);
+
+/*
+ * GetSPIPriority - determine the priority for a shared peripheral interrupt
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  interrupt priority in the range 0 - 0xff
+ */
+uint32_t GetSPIPriority(uint32_t id);
+
+/*
+ * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ *  affinity - prepacked "dotted quad" affinity routing. NOTE: use the
+ *      gicv3PackAffinity() helper routine to generate this input
+ *
+ *  mode - select routing mode (specific affinity, or any recipient)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode);
+
+/*
+ * GetSPIRoute - read ARE-enabled interrupt routing information
+ *
+ * Inputs:
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *  routing configuration
+ */
+uint64_t GetSPIRoute(uint32_t id);
+
+/*
+ * SetSPITarget - configure the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ *  target - 8-bit target bitmap
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPITarget(uint32_t id, uint32_t target);
+
+/*
+ * GetSPITarget - read the set of processor targets for an interrupt
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *  8-bit target bitmap
+ */
+uint32_t GetSPITarget(uint32_t id);
+
+/*
+ * ConfigureSPI - setup an interrupt as edge- or level-triggered
+ *
+ * Inputs
+ *
+ *   id - interrupt identifier
+ *
+ *   config - desired configuration
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config);
+
+/*
+ * SetSPIPending - mark an interrupt as pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetSPIPending(uint32_t id);
+
+/*
+ * ClearSPIPending - mark an interrupt as not pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearSPIPending(uint32_t id);
+
+/*
+ * GetSPIPending - query whether an interrupt is pending
+ *
+ * Inputs
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetSPIPending(uint32_t id);
+
+/*
+ * SetSPISecurity - mark a shared peripheral interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityBlock - mark a block of 32 shared peripheral
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  block - which block to mark (e.g. 1 = Ints 32-63)
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group);
+
+/*
+ * SetSPISecurityAll - mark all shared peripheral interrupts
+ *     as security <group>
+ *
+ * Inputs:
+ *
+ *  group - the group for the interrupts
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetSPISecurityAll(GICIGROUPRBits_t group);
+
+/**********************************************************************/
+
+/*
+ * GIC Re-Distributor Function Prototypes
+ *
+ * The model for calling Redistributor functions is that, rather than
+ * identifying the target redistributor with every function call, the
+ * SelectRedistributor() function is used to identify which redistributor
+ * is to be used for all functions until a different redistributor is
+ * explicitly selected
+ */
+
+/*
+ * WakeupGICR - wake up a Redistributor
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to wakeup
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void WakeupGICR(uint32_t gicr);
+
+/*
+ * EnablePrivateInt - enable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to enable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void EnablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * DisablePrivateInt - disable a private (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to disable
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void DisablePrivateInt(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ *  priority - 8-bit priority to program (see note below)
+ *
+ * Returns:
+ *
+ *  <nothing>
+ *
+ * Note:
+ *
+ *  The GICv3 architecture makes this function sensitive to the Security
+ *  context in terms of what effect it has on the programmed priority: no
+ *  attempt is made to adjust for the reduced priority range available
+ *  when making Non-Secure accesses to the GIC
+ */
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority);
+
+/*
+ * GetPrivateIntPriority - configure the priority for a private
+ *     (SGI/PPI) interrupt
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns:
+ *
+ *   Int priority
+ */
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void SetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   <nothing>
+ */
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - interrupt identifier
+ *
+ * Returns
+ *
+ *   pending status
+ */
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id);
+
+/*
+ * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as
+ *     security <group>
+ *
+ * Inputs
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  id - which interrupt to mark
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group);
+
+/*
+ * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI)
+ *     interrupts as security <group>
+ *
+ * Inputs:
+ *
+ *  gicr - which Redistributor to program
+ *
+ *  group - the group for the interrupt
+ *
+ * Returns:
+ *
+ *  <nothing>
+ */
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group);
+
+#endif /* ndef GICV3_h */
+
+/* EOF GICv3.h */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h
new file mode 100644
index 00000000..0928d14c
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h
@@ -0,0 +1,113 @@
+//
+// Aliases for GICv3 registers
+//
+// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef GICV3_ALIASES_H
+#define GICV3_ALIASES_H
+
+#ifndef __clang__
+
+/*
+ * Mapping of MSR and MRS to physical and virtual CPU interface registers
+ *
+ * Arm Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3.0 and version 4.0
+ * Table 8-5
+ */
+#define ICC_AP0R0_EL1       S3_0_C12_C8_4
+#define ICC_AP0R1_EL1       S3_0_C12_C8_5
+#define ICC_AP0R2_EL1       S3_0_C12_C8_6
+#define ICC_AP0R3_EL1       S3_0_C12_C8_7
+
+#define ICC_AP1R0_EL1       S3_0_C12_C9_0
+#define ICC_AP1R1_EL1       S3_0_C12_C9_1
+#define ICC_AP1R2_EL1       S3_0_C12_C9_2
+#define ICC_AP1R3_EL1       S3_0_C12_C9_3
+
+#define ICC_ASGI1R_EL1      S3_0_C12_C11_6
+
+#define ICC_BPR0_EL1        S3_0_C12_C8_3
+#define ICC_BPR1_EL1        S3_0_C12_C12_3
+
+#define ICC_CTLR_EL1        S3_0_C12_C12_4
+#define ICC_CTLR_EL3        S3_6_C12_C12_4
+
+#define ICC_DIR_EL1         S3_0_C12_C11_1
+
+#define ICC_EOIR0_EL1       S3_0_C12_C8_1
+#define ICC_EOIR1_EL1       S3_0_C12_C12_1
+
+#define ICC_HPPIR0_EL1      S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1      S3_0_C12_C12_2
+
+#define ICC_IAR0_EL1        S3_0_C12_C8_0
+#define ICC_IAR1_EL1        S3_0_C12_C12_0
+
+#define ICC_IGRPEN0_EL1     S3_0_C12_C12_6
+#define ICC_IGRPEN1_EL1     S3_0_C12_C12_7
+#define ICC_IGRPEN1_EL3     S3_6_C12_C12_7
+
+#define ICC_PMR_EL1         S3_0_C4_C6_0
+#define ICC_RPR_EL1         S3_0_C12_C11_3
+
+#define ICC_SGI0R_EL1       S3_0_C12_C11_7
+#define ICC_SGI1R_EL1       S3_0_C12_C11_5
+
+#define ICC_SRE_EL1         S3_0_C12_C12_5
+#define ICC_SRE_EL2         S3_4_C12_C9_5
+#define ICC_SRE_EL3         S3_6_C12_C12_5
+
+/*
+ * Mapping of MSR and MRS to virtual interface control registers
+ *
+ * Arm Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3.0 and version 4.0
+ * Table 8-6
+ */
+#define ICH_AP0R0_EL2       S3_4_C12_C8_0
+#define ICH_AP0R1_EL2       S3_4_C12_C8_1
+#define ICH_AP0R2_EL2       S3_4_C12_C8_2
+#define ICH_AP0R3_EL2       S3_4_C12_C8_3
+
+#define ICH_AP1R0_EL2       S3_4_C12_C9_0
+#define ICH_AP1R1_EL2       S3_4_C12_C9_1
+#define ICH_AP1R2_EL2       S3_4_C12_C9_2
+#define ICH_AP1R3_EL2       S3_4_C12_C9_3
+
+#define ICH_HCR_EL2         S3_4_C12_C11_0
+
+#define ICH_VTR_EL2         S3_4_C12_C11_1
+
+#define ICH_MISR_EL2        S3_4_C12_C11_2
+
+#define ICH_EISR_EL2        S3_4_C12_C11_3
+
+#define ICH_ELRSR_EL2       S3_4_C12_C11_5
+
+#define ICH_VMCR_EL2        S3_4_C12_C11_7
+
+#define ICH_LR0_EL2         S3_4_C12_C12_0
+#define ICH_LR1_EL2         S3_4_C12_C12_1
+#define ICH_LR2_EL2         S3_4_C12_C12_2
+#define ICH_LR3_EL2         S3_4_C12_C12_3
+#define ICH_LR4_EL2         S3_4_C12_C12_4
+#define ICH_LR5_EL2         S3_4_C12_C12_5
+#define ICH_LR6_EL2         S3_4_C12_C12_6
+#define ICH_LR7_EL2         S3_4_C12_C12_7
+#define ICH_LR8_EL2         S3_4_C12_C13_0
+#define ICH_LR9_EL2         S3_4_C12_C13_1
+#define ICH_LR10_EL2        S3_4_C12_C13_2
+#define ICH_LR11_EL2        S3_4_C12_C13_3
+#define ICH_LR12_EL2        S3_4_C12_C13_4
+#define ICH_LR13_EL2        S3_4_C12_C13_5
+#define ICH_LR14_EL2        S3_4_C12_C13_6
+#define ICH_LR15_EL2        S3_4_C12_C13_7
+
+#endif /* not __clang__ */
+
+#endif /* GICV3_ALIASES */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h
new file mode 100644
index 00000000..2b8a2d3e
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h
@@ -0,0 +1,254 @@
+/*
+ * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#ifndef GICV3_gicc_h
+#define GICV3_gicc_h
+
+#include "GICv3_aliases.h"
+
+#define stringify_no_expansion(x) #x
+#define stringify(x) stringify_no_expansion(x)
+
+/**********************************************************************/
+
+typedef enum
+{
+    sreSRE = (1 << 0),
+    sreDFB = (1 << 1),
+    sreDIB = (1 << 2),
+    sreEnable = (1 << 3)
+} ICC_SREBits_t;
+
+static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL2(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
+{
+    asm("msr  "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_SRE_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    igrpEnable = (1 << 0),
+    igrpEnableGrp1NS = (1 << 0),
+    igrpEnableGrp1S = (1 << 2)
+} ICC_IGRPBits_t;
+
+static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
+{
+    asm("msr  "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    ctlrCBPR = (1 << 0),
+    ctlrCBPR_EL1S = (1 << 0),
+    ctlrEOImode = (1 << 1),
+    ctlrCBPR_EL1NS = (1 << 1),
+    ctlrEOImode_EL3 = (1 << 2),
+    ctlrEOImode_EL1S = (1 << 3),
+    ctlrEOImode_EL1NS = (1 << 4),
+    ctlrRM = (1 << 5),
+    ctlrPMHE = (1 << 6)
+} ICC_CTLRBits_t;
+
+static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
+{
+    asm("msr  "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
+{
+    asm("msr  "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
+}
+
+static inline uint64_t getICC_CTLR_EL3(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+static inline uint64_t getICC_IAR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_IAR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline void setICC_EOIR0(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_EOIR1(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_DIR(uint32_t interrupt)
+{
+    asm("msr  "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
+}
+
+static inline void setICC_PMR(uint32_t priority)
+{
+    asm("msr  "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority));
+}
+
+static inline void setICC_BPR0(uint32_t binarypoint)
+{
+    asm("msr  "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline void setICC_BPR1(uint32_t binarypoint)
+{
+    asm("msr  "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
+}
+
+static inline uint64_t getICC_BPR0(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_BPR1(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+static inline uint64_t getICC_RPR(void)
+{
+    uint64_t retc;
+
+    asm("mrs  %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc));
+
+    return retc;
+}
+
+/**********************************************************************/
+
+typedef enum
+{
+    sgirIRMTarget = 0,
+    sgirIRMAll = (1ull << 40)
+} ICC_SGIRBits_t;
+
+static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
+                uint8_t aff1, ICC_SGIRBits_t irm,
+                uint16_t targetlist, uint8_t intid)
+{
+    uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \
+               ((uint64_t)aff1 << 16) | irm | targetlist | \
+               ((uint64_t)(intid & 0x0f) << 24));
+
+    asm("msr  "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
+}
+
+#endif /* ndef GICV3_gicc_h */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c
new file mode 100644
index 00000000..2cf9e843
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c
@@ -0,0 +1,339 @@
+/*
+ * GICv3_gicd.c - generic driver code for GICv3 distributor
+ *
+ * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include <stdint.h>
+
+#include "GICv3.h"
+
+typedef struct
+{
+        volatile uint32_t GICD_CTLR;              // +0x0000
+  const volatile uint32_t GICD_TYPER;             // +0x0004
+  const volatile uint32_t GICD_IIDR;              // +0x0008
+
+  const volatile uint32_t padding0;               // +0x000c
+
+        volatile uint32_t GICD_STATUSR;           // +0x0010
+
+  const volatile uint32_t padding1[3];            // +0x0014
+
+        volatile uint32_t IMP_DEF[8];             // +0x0020
+
+        volatile uint32_t GICD_SETSPI_NSR;        // +0x0040
+  const volatile uint32_t padding2;               // +0x0044
+        volatile uint32_t GICD_CLRSPI_NSR;        // +0x0048
+  const volatile uint32_t padding3;               // +0x004c
+        volatile uint32_t GICD_SETSPI_SR;         // +0x0050
+  const volatile uint32_t padding4;               // +0x0054
+        volatile uint32_t GICD_CLRSPI_SR;         // +0x0058
+
+  const volatile uint32_t padding5[3];            // +0x005c
+
+        volatile uint32_t GICD_SEIR;              // +0x0068
+
+  const volatile uint32_t padding6[5];            // +0x006c
+
+        volatile uint32_t GICD_IGROUPR[32];       // +0x0080
+
+        volatile uint32_t GICD_ISENABLER[32];     // +0x0100
+        volatile uint32_t GICD_ICENABLER[32];     // +0x0180
+        volatile uint32_t GICD_ISPENDR[32];       // +0x0200
+        volatile uint32_t GICD_ICPENDR[32];       // +0x0280
+        volatile uint32_t GICD_ISACTIVER[32];     // +0x0300
+        volatile uint32_t GICD_ICACTIVER[32];     // +0x0380
+
+        volatile uint8_t  GICD_IPRIORITYR[1024];  // +0x0400
+        volatile uint8_t  GICD_ITARGETSR[1024];   // +0x0800
+        volatile uint32_t GICD_ICFGR[64];         // +0x0c00
+        volatile uint32_t GICD_IGRPMODR[32];      // +0x0d00
+  const volatile uint32_t padding7[32];           // +0x0d80
+        volatile uint32_t GICD_NSACR[64];         // +0x0e00
+
+        volatile uint32_t GICD_SGIR;              // +0x0f00
+
+  const volatile uint32_t padding8[3];            // +0x0f04
+
+        volatile uint32_t GICD_CPENDSGIR[4];      // +0x0f10
+        volatile uint32_t GICD_SPENDSGIR[4];      // +0x0f20
+
+  const volatile uint32_t padding9[52];           // +0x0f30
+  const volatile uint32_t padding10[5120];        // +0x1000
+
+        volatile uint64_t GICD_IROUTER[1024];     // +0x6000
+} GICv3_distributor;
+
+/*
+ * use the scatter file to place GICD
+ */
+GICv3_distributor __attribute__((section(".gicd"))) gicd;
+
+void ConfigGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR = flags;
+}
+
+void EnableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR |= flags;
+}
+
+void DisableGICD(GICDCTLRFlags_t flags)
+{
+    gicd.GICD_CTLR &= ~flags;
+}
+
+void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync)
+{
+    if (dosync)
+    {
+	const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS;
+	const uint32_t tval = flags & tmask;
+
+	while ((gicd.GICD_CTLR & tmask) != tval)
+	    continue;
+    }
+    else
+	gicd.GICD_CTLR = flags;
+}
+
+void EnableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ISENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void DisableSPI(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISENABLER has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER);
+    id &= 32 - 1;
+
+    gicd.GICD_ICENABLER[bank] = 1 << id;
+
+    return;
+}
+
+void SetSPIPriority(uint32_t id, uint32_t priority)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    gicd.GICD_IPRIORITYR[bank] = priority;
+}
+
+uint32_t GetSPIPriority(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR);
+
+    return (uint32_t)(gicd.GICD_IPRIORITYR[bank]);
+}
+
+void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode;
+}
+
+uint64_t GetSPIRoute(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_IROUTER has one doubleword-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_IROUTER);
+
+    return gicd.GICD_IROUTER[bank];
+}
+
+void SetSPITarget(uint32_t id, uint32_t target)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    gicd.GICD_ITARGETSR[bank] = target;
+}
+
+uint32_t GetSPITarget(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ITARGETSR has one byte-wide entry per interrupt
+     */
+    /*
+     * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of
+     * target bitmap per register
+     */
+    bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR);
+
+    return (uint32_t)(gicd.GICD_ITARGETSR[bank]);
+}
+
+void ConfigureSPI(uint32_t id, GICDICFGRBits_t config)
+{
+    uint32_t bank, tmp;
+
+    /*
+     * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of
+     * configuration per register
+     */
+    bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR);
+    config &= 3;
+
+    id = (id & 0xf) << 1;
+
+    tmp = gicd.GICD_ICFGR[bank];
+    tmp &= ~(3 << id);
+    tmp |= config << id;
+    gicd.GICD_ICFGR[bank] = tmp;
+}
+
+void SetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ISPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ISPENDR[bank] = 1 << id;
+}
+
+void ClearSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    gicd.GICD_ICPENDR[bank] = 1 << id;
+}
+
+uint32_t GetSPIPending(uint32_t id)
+{
+    uint32_t bank;
+
+    /*
+     * GICD_ICPENDR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR);
+    id &= 0x1f;
+
+    return (gicd.GICD_ICPENDR[bank] >> id) & 1;
+}
+
+void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group)
+{
+    uint32_t bank, groupmod;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR);
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+	gicd.GICD_IGROUPR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGROUPR[bank] &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+	gicd.GICD_IGRPMODR[bank] |= 1 << id;
+    else
+	gicd.GICD_IGRPMODR[bank] &= ~(1 << id);
+}
+
+void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group)
+{
+    uint32_t groupmod;
+    const uint32_t nbits = (sizeof group * 8) - 1;
+
+    /*
+     * GICD_IGROUPR has 32 interrupts per register
+     */
+    block &= RANGE_LIMIT(gicd.GICD_IGROUPR);
+
+    /*
+     * get each bit of group config duplicated over all 32-bits in a word
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicd.GICD_IGROUPR[block] = group;
+    gicd.GICD_IGRPMODR[block] = groupmod;
+}
+
+void SetSPISecurityAll(GICIGROUPRBits_t group)
+{
+    uint32_t block;
+
+    /*
+     * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we
+     * want to iterate over all blocks excluding 0 (which are the
+     * SGI/PPI interrupts, and not relevant here)
+     */
+    for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block)
+	SetSPISecurityBlock(block, group);
+}
+
+/* EOF GICv3_gicd.c */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c
new file mode 100644
index 00000000..ef5c8925
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c
@@ -0,0 +1,289 @@
+/*
+ * GICv3_gicr.c - generic driver code for GICv3 redistributor
+ *
+ * Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved.
+ * Use, modification and redistribution of this file is subject to your possession of a
+ * valid End User License Agreement for the Arm Product of which these examples are part of 
+ * and your compliance with all applicable terms and conditions of such licence agreement.
+ */
+#include "GICv3.h"
+
+/*
+ * physical LPI Redistributor register map
+ */
+typedef struct
+{
+        volatile uint32_t GICR_CTLR;             // +0x0000 - RW - Redistributor Control Register
+  const volatile uint32_t GICR_IIDR;             // +0x0004 - RO - Implementer Identification Register
+  const volatile uint32_t GICR_TYPER[2];         // +0x0008 - RO - Redistributor Type Register
+        volatile uint32_t GICR_STATUSR;          // +0x0010 - RW - Error Reporting Status Register, optional
+        volatile uint32_t GICR_WAKER;            // +0x0014 - RW - Redistributor Wake Register
+  const volatile uint32_t padding1[2];           // +0x0018 - RESERVED
+#ifndef USE_GIC600
+        volatile uint32_t IMPDEF1[8];            // +0x0020 - ?? - IMPLEMENTATION DEFINED
+#else
+        volatile uint32_t GICR_FCTLR;            // +0x0020 - RW - Function Control Register
+        volatile uint32_t GICR_PWRR;             // +0x0024 - RW - Power Management Control Register
+        volatile uint32_t GICR_CLASS;            // +0x0028 - RW - Class Register
+  const volatile uint32_t padding2[5];           // +0x002C - RESERVED
+#endif
+        volatile uint64_t GICR_SETLPIR;          // +0x0040 - WO - Set LPI Pending Register
+        volatile uint64_t GICR_CLRLPIR;          // +0x0048 - WO - Clear LPI Pending Register
+  const volatile uint32_t padding3[8];           // +0x0050 - RESERVED
+        volatile uint64_t GICR_PROPBASER;        // +0x0070 - RW - Redistributor Properties Base Address Register
+        volatile uint64_t GICR_PENDBASER;        // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register
+  const volatile uint32_t padding4[8];           // +0x0080 - RESERVED
+        volatile uint64_t GICR_INVLPIR;          // +0x00A0 - WO - Redistributor Invalidate LPI Register
+  const volatile uint32_t padding5[2];           // +0x00A8 - RESERVED
+        volatile uint64_t GICR_INVALLR;          // +0x00B0 - WO - Redistributor Invalidate All Register
+  const volatile uint32_t padding6[2];           // +0x00B8 - RESERVED
+        volatile uint64_t GICR_SYNCR;            // +0x00C0 - RO - Redistributor Synchronize Register
+  const volatile uint32_t padding7[2];           // +0x00C8 - RESERVED
+  const volatile uint32_t padding8[12];          // +0x00D0 - RESERVED
+        volatile uint64_t IMPDEF2;               // +0x0100 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding9[2];           // +0x0108 - RESERVED
+        volatile uint64_t IMPDEF3;               // +0x0110 - WO - IMPLEMENTATION DEFINED
+  const volatile uint32_t padding10[2];          // +0x0118 - RESERVED
+} GICv3_redistributor_RD;
+
+/*
+ * SGI and PPI Redistributor register map
+ */
+typedef struct
+{
+  const volatile uint32_t padding1[32];          // +0x0000 - RESERVED
+        volatile uint32_t GICR_IGROUPR0;         // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
+  const volatile uint32_t padding2[31];          // +0x0084 - RESERVED
+        volatile uint32_t GICR_ISENABLER;        // +0x0100 - RW - Interrupt Set-Enable Registers
+  const volatile uint32_t padding3[31];          // +0x0104 - RESERVED
+        volatile uint32_t GICR_ICENABLER;        // +0x0180 - RW - Interrupt Clear-Enable Registers
+  const volatile uint32_t padding4[31];          // +0x0184 - RESERVED
+        volatile uint32_t GICR_ISPENDR;          // +0x0200 - RW - Interrupt Set-Pending Registers
+  const volatile uint32_t padding5[31];          // +0x0204 - RESERVED
+        volatile uint32_t GICR_ICPENDR;          // +0x0280 - RW - Interrupt Clear-Pending Registers
+  const volatile uint32_t padding6[31];          // +0x0284 - RESERVED
+        volatile uint32_t GICR_ISACTIVER;        // +0x0300 - RW - Interrupt Set-Active Register
+  const volatile uint32_t padding7[31];          // +0x0304 - RESERVED
+        volatile uint32_t GICR_ICACTIVER;        // +0x0380 - RW - Interrupt Clear-Active Register
+  const volatile uint32_t padding8[31];          // +0x0184 - RESERVED
+        volatile uint8_t  GICR_IPRIORITYR[32];   // +0x0400 - RW - Interrupt Priority Registers
+  const volatile uint32_t padding9[504];         // +0x0420 - RESERVED
+        volatile uint32_t GICR_ICnoFGR[2];       // +0x0C00 - RW - Interrupt Configuration Registers
+  const volatile uint32_t padding10[62];         // +0x0C08 - RESERVED
+        volatile uint32_t GICR_IGRPMODR0;        // +0x0D00 - RW - ????
+  const volatile uint32_t padding11[63];         // +0x0D04 - RESERVED
+        volatile uint32_t GICR_NSACR;            // +0x0E00 - RW - Non-Secure Access Control Register
+} GICv3_redistributor_SGI;
+
+/*
+ * We have a multiplicity of GIC Redistributors; on the GIC-AEM and
+ * GIC-500 they are arranged as one 128KB region per redistributor: one
+ * 64KB page of GICR LPI registers, and one 64KB page of GICR Private
+ * Int registers
+ */
+typedef struct
+{
+    union
+    {
+        GICv3_redistributor_RD RD_base;
+        uint8_t padding[64 * 1024];
+    } RDblock;
+
+    union
+    {
+        GICv3_redistributor_SGI SGI_base;
+        uint8_t padding[64 * 1024];
+    } SGIblock;
+} GICv3_GICR;
+
+/*
+ * use the scatter file to place GIC Redistributor base address
+ *
+ * although this code doesn't know how many Redistributor banks
+ * a particular system will have, we declare gicrbase as an array
+ * to avoid unwanted compiler optimisations when calculating the
+ * base of a particular Redistributor bank
+ */
+static const GICv3_GICR gicrbase[2] __attribute__((section (".gicr")));
+
+/**********************************************************************/
+
+/*
+ * utility functions to calculate base of a particular
+ * Redistributor bank
+ */
+
+static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr)
+{
+    GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase;
+
+    return &((arraybase + gicr)->RDblock.RD_base);
+}
+
+static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
+{
+    GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase);
+
+    return &(arraybase[gicr].SGIblock.SGI_base);
+}
+
+/**********************************************************************/
+
+void WakeupGICR(uint32_t gicr)
+{
+    GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
+#ifdef USE_GIC600
+    //Power up Re-distributor for GIC-600
+    gicrRD->GICR_PWRR = 0x2;
+#endif
+
+    /*
+     * step 1 - ensure GICR_WAKER.ProcessorSleep is off
+     */
+    gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep;
+
+    /*
+     * step 2 - wait for children asleep to be cleared
+     */
+    while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
+        continue;
+
+    /*
+     * OK, GICR is go
+     */
+    return;
+}
+
+void EnablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISENABLER = 1 << id;
+}
+
+void DisablePrivateInt(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICENABLER = 1 << id;
+}
+
+void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    gicrSGI->GICR_IPRIORITYR[id] = priority;
+}
+
+uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICD_IPRIORITYR has one byte-wide entry per interrupt
+     */
+    id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR);
+
+    return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]);
+}
+
+void SetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ISPENDR = 1 << id;
+}
+
+void ClearPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ICPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    gicrSGI->GICR_ICPENDR = 1 << id;
+}
+
+uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+
+    /*
+     * GICR_ISPENDR is one 32-bit register
+     */
+    id &= 0x1f;
+
+    return (gicrSGI->GICR_ISPENDR >> id) & 0x01;
+}
+
+void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    uint32_t groupmod;
+
+    /*
+     * GICR_IGROUPR0 is one 32-bit register
+     */
+    id &= 0x1f;
+
+    /*
+     * the single group argument is split into two separate
+     * registers, so filter out and remove the (new to gicv3)
+     * group modifier bit
+     */
+    groupmod = (group >> 1) & 1;
+    group &= 1;
+
+    /*
+     * either set or clear the Group bit for the interrupt as appropriate
+     */
+    if (group)
+        gicrSGI->GICR_IGROUPR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
+
+    /*
+     * now deal with groupmod
+     */
+    if (groupmod)
+        gicrSGI->GICR_IGRPMODR0 |= 1 << id;
+    else
+        gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
+}
+
+void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
+{
+    GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr);
+    const uint32_t nbits = (sizeof group * 8) - 1;
+    uint32_t groupmod;
+
+    /*
+     * get each bit of group config duplicated over all 32 bits
+     */
+    groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
+    group = (uint32_t)(((int32_t)group << nbits) >> 31);
+
+    /*
+     * set the security state for this block of SPIs
+     */
+    gicrSGI->GICR_IGROUPR0 = group;
+    gicrSGI->GICR_IGRPMODR0 = groupmod;
+}
+
+/* EOF GICv3_gicr.c */
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S
new file mode 100644
index 00000000..77fa0a0f
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S
@@ -0,0 +1,86 @@
+//
+// Armv8-A AArch64 - Basic Mutex Example
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+
+    .global _mutex_initialize
+    .global _mutex_acquire
+    .global _mutex_release
+
+//
+// These routines implement the mutex management functions required for running
+// the Arm C library in a multi-threaded environment.
+//
+// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex
+//
+// **********************************************************************
+//
+
+    .type _mutex_initialize, "function"
+    .cfi_startproc
+_mutex_initialize:
+
+    //
+    // mark the mutex as unlocked
+    //
+    mov     w1, #0
+    str     w1, [x0]
+
+    //
+    // we are running multi-threaded, so set a non-zero return
+    // value (function prototype says use 1)
+    //
+    mov     w0, #1
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_acquire, "function"
+    .cfi_startproc
+_mutex_acquire:
+
+    //
+    // send ourselves an event, so we don't stick on the wfe at the
+    // top of the loop
+    //
+    sevl
+
+    //
+    // wait until the mutex is available
+    //
+loop:
+    wfe
+    ldaxr   w1, [x0]
+    cbnz    w1, loop
+
+    //
+    // mutex is (at least, it was) available - try to claim it
+    //
+    mov     w1, #1
+    stxr    w2, w1, [x0]
+    cbnz    w2, loop
+
+    //
+    // OK, we have the mutex, our work is done here
+    //
+    ret
+    .cfi_endproc
+
+
+    .type _mutex_release, "function"
+    .cfi_startproc
+_mutex_release:
+
+    mov     w1, #0
+    stlr    w1, [x0]
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h
new file mode 100644
index 00000000..52c9a0fe
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h
@@ -0,0 +1,66 @@
+//
+// Private Peripheral Map for the v8 Architecture Envelope Model
+//
+// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef PPM_AEM_H
+#define PPM_AEM_H
+
+//
+// Distributor layout
+//
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+//
+// CPU Interface layout
+//
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+
+#endif // PPM_AEM_H
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
new file mode 100644
index 00000000..c7296646
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c
@@ -0,0 +1,149 @@
+/* Small demonstration of the ThreadX module manager.  */
+
+#include "tx_api.h"
+#include "txm_module.h"
+#include <stddef.h>
+
+
+/* Define the ThreadX module manager thread and stack...  */
+
+TX_THREAD               module_manager;
+#define MODULE_MANAGER_STACK_SIZE (1024 * 4)
+ALIGN_TYPE              module_manager_stack[MODULE_MANAGER_STACK_SIZE / sizeof(ALIGN_TYPE)];
+
+
+/* Define the module instance object  */
+
+TXM_MODULE_INSTANCE     my_module;
+
+
+/* The module code should be loaded here.  */
+
+#define MODULE_CODE (0x80180000)
+
+
+/* Define the object pool area.  */
+
+UCHAR                   object_memory[1024 * 16];
+
+
+/* Define the module data pool area.  */
+
+#define MODULE_DATA_SIZE (1024 * 32)
+ALIGN_TYPE MODULE_DATA [MODULE_DATA_SIZE / sizeof(ALIGN_TYPE)];
+
+
+/* Define the count of memory faults.  */
+
+ULONG                   memory_faults = 0;
+
+
+/* Define thread prototypes.  */
+
+void    module_manager_entry(ULONG thread_input);
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+UCHAR   event_buffer[65536];
+
+#endif
+
+
+/* Define main entry point.  */
+
+int main(void)
+{
+
+    /* Initialize timer for ThreadX.  */
+    extern void init_timer(void);    /* in timer_interrupts.c  */
+    init_timer();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+
+    /* The functions doesn't really return*/
+    return 0;
+}
+
+ULONG simple_thread_counter = 0;
+TX_THREAD simple_thread;
+#define SIMPLE_THREAD_STACK_SIZE (1024 * 4)
+ALIGN_TYPE simple_thread_stack[SIMPLE_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)];
+void simple_thread_entry(ULONG thread_input)
+{
+    while(1)
+    {
+        simple_thread_counter++;
+        tx_thread_sleep(2);
+    }
+}
+
+/* Define what the initial system looks like.  */
+
+void tx_application_define(void *first_unused_memory)
+{
+    tx_thread_create(
+            &module_manager,
+            "Module Manager Thread",
+            module_manager_entry, 0,
+            module_manager_stack, MODULE_MANAGER_STACK_SIZE,
+            1, 1,
+            TX_NO_TIME_SLICE,
+            TX_AUTO_START);
+
+    tx_thread_create(
+            &simple_thread,
+            "Simple Thread",
+            simple_thread_entry, 0,
+            simple_thread_stack, SIMPLE_THREAD_STACK_SIZE,
+            1, 1,
+            TX_NO_TIME_SLICE,
+            TX_AUTO_START);
+}
+
+
+/* Define the test threads.  */
+
+void module_manager_entry(ULONG thread_input)
+{
+
+    /* Initialize the module manager.   */
+    txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE);
+
+    txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
+
+    /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download.  */
+    txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
+    
+    /* Start the module.  */
+    txm_module_manager_start(&my_module);
+
+    /* Sleep for a while....  */
+    {
+        int i;
+        for (i = 0; i < 10; i++)
+        {
+            tx_thread_sleep(10);
+        }
+    }
+    
+    /* Stop the module.  */
+    txm_module_manager_stop(&my_module);
+    
+    /* Unload the module.  */
+    txm_module_manager_unload(&my_module);
+
+    /* Load the module again.  */
+    txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE);
+
+    /* Start the module again.  */
+    txm_module_manager_start(&my_module);
+    
+    /* Now just spin...  */
+    while(1)
+    {
+    
+        tx_thread_sleep(10);
+    }
+}
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
new file mode 100644
index 00000000..6152beab
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch
@@ -0,0 +1,451 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+    <listAttribute key="1685211613816507265.viewid=2">
+        <listEntry value="thread_info"/>
+        <listEntry value="thread_ptr"/>
+        <listEntry value="shell_function"/>
+        <listEntry value="thread_entry_info"/>
+        <listEntry value="module_instance"/>
+        <listEntry value="module_preamble"/>
+        <listEntry value="return_value"/>
+        <listEntry value="status"/>
+        <listEntry value="_entry_param_thread_ptr"/>
+        <listEntry value="data_allocation_size"/>
+        <listEntry value="_txm_module_manager_byte_pool"/>
+        <listEntry value="pool_ptr"/>
+        <listEntry value="&amp;_txm_module_manager_byte_pool"/>
+        <listEntry value="(void*)(_txm_module_manager_byte_pool.tx_byte_pool_start)"/>
+        <listEntry value="(void*)(_txm_module_manager_byte_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size)"/>
+        <listEntry value="_tx_timer_thread"/>
+        <listEntry value="byte_pool_ptr"/>
+        <listEntry value="object_ptr"/>
+        <listEntry value="module_instance -&gt; txm_module_instance_data_start"/>
+        <listEntry value="module_instance -&gt; txm_module_instance_data_end"/>
+        <listEntry value="code_alignment"/>
+    </listAttribute>
+    <mapAttribute key="1685211613816507265.viewid=2.ExpressionsData">
+        <mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,1;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,8;NODE_TYPE,VALUE;FORMATTER,Hexadecimal"/>
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+    </mapAttribute>
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+    <listAttribute key="2016305617678564833.viewid=3">
+        <listEntry value="thread_0"/>
+        <listEntry value="thread_1"/>
+        <listEntry value="thread_2"/>
+        <listEntry value="byte_pool_0"/>
+        <listEntry value="block_pool_0"/>
+        <listEntry value="queue_0_sends"/>
+        <listEntry value="semaphore_0_puts"/>
+        <listEntry value="thread_ptr"/>
+        <listEntry value="module_instance"/>
+        <listEntry value="thread_info -&gt; txm_module_thread_entry_info_start_thread"/>
+        <listEntry value="_txm_module_manager_object_pool"/>
+        <listEntry value="code_size"/>
+    </listAttribute>
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+    <stringAttribute key="dtsl_options_file" value="default"/>
+    <stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
+    <stringAttribute key="launch_configuration_version" value="2020.0"/>
+    <booleanAttribute key="linuxOS" value="false"/>
+    <stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
+    <stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
+    <booleanAttribute key="runAfterConnect" value="false"/>
+    <mapAttribute key="scripts_view_script_links">
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager.ds" value=""/>
+        <mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_module\cortex_a35\ac6\example_build\sample_threadx_module_manager\sample_threadx_module_manager_debug.ds" value=""/>
+    </mapAttribute>
+    <listAttribute key="setup">
+        <listEntry value="CDB://Scripts/rtsm_launcher.py"/>
+        <listEntry value="FVP_Base_Cortex-A35x4"/>
+    </listAttribute>
+    <stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
+    <stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
+</launchConfiguration>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld
new file mode 100644
index 00000000..e9b12a82
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld
@@ -0,0 +1,245 @@
+/* Linker script to place sections and symbol values.
+ * It references following symbols, which must be defined in code:
+ *   start64 : Entry point
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __cs3_peripherals
+ *   __code_start
+ *   __exidx_start
+ *   __exidx_end
+ *   __data_start
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   __stack
+ *   __el3_stack
+ *   __ttb0_l1
+ *   __ttb0_l2_ram
+ *   __ttb0_l2_private
+ *   __ttb0_l2_periph
+ *   __top_of_ram
+ */
+
+ENTRY(start64)
+
+SECTIONS
+{
+    /*
+     * CS3 Peripherals is a 64MB region from 0x1c000000
+     * that includes the following:
+     * System Registers             at 0x1C010000
+     * UART0 (PL011)                at 0x1C090000
+     * Color LCD Controller (PL111) at 0x1C1F0000
+     * plus a number of others.
+     * CS3_PERIPHERALS is used by the startup code for page-table generation
+     * This region is not truly empty, but we have no
+     * predefined objects that live within it
+     */
+    __cs3_peripherals  = 0x1c000000;
+
+    /*
+     * GICv3 distributor
+     */
+    .gicd 0x2f000000 (NOLOAD):
+    {
+        *(.gicd)
+    }
+
+    /*
+     * GICv3 redistributors
+     * 128KB for each redistributor in the system
+     */
+    .gicr 0x2f100000 (NOLOAD):
+    {
+        *(.gicr)
+    }
+
+    .vectors 0x80000000:
+    {
+        __code_start = .;
+        KEEP(*(StartUp))
+        KEEP(*(EL1VECTORS EL2VECTORS EL3VECTORS))
+    }
+
+    .init :
+    {
+        KEEP (*(SORT_NONE(.init)))
+    }
+
+    .text :
+    {
+        *(.text*)
+    }
+
+    .fini :
+    {
+        KEEP (*(SORT_NONE(.fini)))
+    }
+
+    .rodata :
+    {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+    }
+
+    .eh_frame :
+    {
+        KEEP (*(.eh_frame))
+    }
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    }
+
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    }
+
+    .preinit_array :
+    {
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+    }
+
+    .init_array :
+    {
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array ))
+        PROVIDE_HIDDEN (__init_array_end = .);
+    }
+
+    .fini_array :
+    {
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP (*(SORT(.fini_array.*)))
+        KEEP (*(.fini_array ))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+    }
+
+    .ctors :
+    {
+        /* gcc uses crtbegin.o to find the start of
+           the constructors, so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtbegin.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtbegin.o
+           is in.  */
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*crtbegin?.o(.ctors))
+        /* We don't want to include the .ctor section from
+           the crtend.o file until after the sorted ctors.
+           The .ctor section from the crtend file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+    }
+
+    .dtors :
+    {
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*crtbegin?.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+    }
+
+    .jcr :
+    {
+        KEEP (*(.jcr))
+    }
+
+    .data :
+    {
+        __data_start = . ;
+        *(.data .data.* .gnu.linkonce.d.*)
+        SORT(CONSTRUCTORS)
+    }
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    }
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(64);
+        __end__ = .;
+        PROVIDE(end = .);
+        . = . + 0x1000;
+    }
+
+    .stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 4 * 0x8000;
+        __stack = .;
+    }
+    
+    .handler_stack_limit (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 4 * 0x4000;
+        handler_stack_limit = .;
+    }
+
+    .el3_stack (NOLOAD):
+    {
+        . = ALIGN(64);
+        . = . + 4 * 0x1000;
+        __el3_stack = .;
+    }
+
+    .ttb0_l1 (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l1 = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_ram (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_ram = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_private (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_private = .;
+        . = . + 0x1000;
+    }
+
+    .ttb0_l2_periph (NOLOAD):
+    {
+        . = ALIGN(4096);
+        __ttb0_l2_periph = .;
+        . = . + 0x1000;
+    }
+
+    /*
+     * The startup code uses the end of this region to calculate
+     * the top of memory - don't place any RAM regions after it
+     */
+    __top_of_ram = .;
+}
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.c
new file mode 100644
index 00000000..4dc009b2
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.c
@@ -0,0 +1,122 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "sp804_timer.h"
+
+#define TIMER_SP804_CTRL_TIMEREN     (1 << 7)
+#define TIMER_SP804_CTRL_TIMERMODE   (1 << 6)        // Bit 6:
+#define TIMER_SP804_CTRL_INTENABLE   (1 << 5)
+#define TIMER_SP804_CTRL_TIMERSIZE   (1 << 1)        // Bit 1: 0=16-bit, 1=32-bit
+#define TIMER_SP804_CTRL_ONESHOT     (1 << 0)        // Bit 0: 0=wrapping, 1=one-shot
+
+#define TIMER_SP804_CTRL_PRESCALE_1  (0 << 2)        // clk/1
+#define TIMER_SP804_CTRL_PRESCALE_4  (1 << 2)        // clk/4
+#define TIMER_SP804_CTRL_PRESCALE_8  (2 << 2)        // clk/8
+
+struct sp804_timer
+{
+        volatile uint32_t Time1Load;     // +0x00
+  const volatile uint32_t Time1Value;    // +0x04 - RO
+        volatile uint32_t Timer1Control; // +0x08
+        volatile uint32_t Timer1IntClr;  // +0x0C - WO
+  const volatile uint32_t Timer1RIS;     // +0x10 - RO
+  const volatile uint32_t Timer1MIS;     // +0x14 - RO
+        volatile uint32_t Timer1BGLoad;  // +0x18
+
+        volatile uint32_t Time2Load;     // +0x20
+        volatile uint32_t Time2Value;    // +0x24
+        volatile uint8_t  Timer2Control; // +0x28
+        volatile uint32_t Timer2IntClr;  // +0x2C - WO
+  const volatile uint32_t Timer2RIS;     // +0x30 - RO
+  const volatile uint32_t Timer2MIS;     // +0x34 - RO
+        volatile uint32_t Timer2BGLoad;  // +0x38
+
+  // Not including ID registers
+
+};
+
+// Instance of the dual timer, will be placed using the scatter file
+struct sp804_timer* dual_timer;
+
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address)
+{
+  dual_timer = (struct sp804_timer*)address;
+  return;
+}
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt)
+{
+  uint32_t tmp = 0;
+
+  dual_timer->Time1Load = load_value;
+
+  // Fixed setting: 32-bit, no prescaling
+  tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE;
+
+  // Settings from parameters: interrupt generation & reload
+  tmp = tmp | interrupt | auto_reload;
+
+  // Write control register
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Starts the timer
+void startTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp | TIMER_SP804_CTRL_TIMEREN;      // Set TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Stops the timer
+void stopTimer(void)
+{
+  uint32_t tmp;
+
+  tmp = dual_timer->Timer1Control;
+  tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN;     // Clear TimerEn (bit 7)
+  dual_timer->Timer1Control = tmp;
+
+  return;
+}
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void)
+{
+  return dual_timer->Time1Value;
+}
+
+
+void clearTimerIrq(void)
+{
+  // A write to this register, of any value, clears the interrupt
+  dual_timer->Timer1IntClr = 1;
+}
+
+
+// ------------------------------------------------------------
+// End of sp804_timer.c
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.h
new file mode 100644
index 00000000..777062cc
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.h
@@ -0,0 +1,53 @@
+// ------------------------------------------------------------
+// SP804 Dual Timer
+// Header Filer
+//
+// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#ifndef _SP804_TIMER_
+#define _SP804_TIMER_
+
+#include <stdint.h>
+
+// Set base address of timer
+// address - virtual address of SP804 timer
+void setTimerBaseAddress(uint64_t address);
+
+
+// Sets up the private timer
+// load_value  - Initial value of timer
+// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT)
+// interrupt   - Whether to generate an interrupt
+
+#define SP804_AUTORELOAD   (0)
+#define SP804_SINGLESHOT   (1)
+#define SP804_GENERATE_IRQ (1 << 5)
+#define SP804_NO_IRQ       (0)
+
+void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt);
+
+
+// Starts the timer
+void startTimer(void);
+
+
+// Stops the timer
+void stopTimer(void);
+
+
+// Returns the current timer count
+uint32_t getTimerCount(void);
+
+
+// Clears the timer interrupt
+void clearTimerIrq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of sp804_timer.h
+// ------------------------------------------------------------
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/startup.S
new file mode 100644
index 00000000..53f02e37
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/startup.S
@@ -0,0 +1,798 @@
+// ------------------------------------------------------------
+// Armv8-A MPCore EL3 AArch64 Startup Code
+//
+// Basic Vectors, MMU, caches and GICv3 initialization
+//
+// Exits in EL1 AArch64
+//
+// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_mmu.h"
+#include "v8_system.h"
+#include "GICv3_aliases.h"
+
+    .section StartUp, "ax"
+    .balign 4
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+
+    .global InvalidateUDCaches
+    .global ZeroBlock
+
+    .global SetPrivateIntSecurityBlock
+    .global SetSPISecurityAll
+    .global SetPrivateIntPriority
+
+    .global WakeupGICR
+    .global SyncAREinGICD
+    .global EnableGICD
+    .global EnablePrivateInt
+    .global GetPrivateIntPending
+    .global ClearPrivateIntPending
+
+    .global _start
+    .global MainApp
+
+    .global __code_start
+    .global __ttb0_l1
+    .global __ttb0_l2_ram
+    .global __ttb0_l2_periph
+    .global __top_of_ram
+    .global gicd
+    .global __stack
+    .global __el3_stack
+    .global __cs3_peripherals
+
+is_mmu_ready:
+.word 0
+
+
+// ------------------------------------------------------------
+
+    .global start64
+    .type start64, "function"
+start64:
+
+    //
+    // program the VBARs
+    //
+    ldr x1, =el1_vectors
+    msr VBAR_EL1, x1
+
+    ldr x1, =el2_vectors
+    msr VBAR_EL2, x1
+
+    ldr x1, =el3_vectors
+    msr VBAR_EL3, x1
+
+
+    // GIC-500 comes out of reset in GICv2 compatibility mode - first set
+    // system register enables for all relevant exception levels, and
+    // select GICv3 operating mode
+    //
+    msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL3, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1
+
+    //
+    // set lower exception levels as non-secure, with no access
+    // back to EL2 or EL3, and are AArch64 capable
+    //
+    mov x3, #(SCR_EL3_RW  | \
+              SCR_EL3_SMD | \
+              SCR_EL3_NS)      // Set NS bit, to access Non-secure registers
+    msr SCR_EL3, x3
+    isb
+
+    mov x0, #15
+    msr ICC_SRE_EL2, x0
+    isb
+    msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1
+
+
+    //
+    // no traps or VM modifications from the Hypervisor, EL1 is AArch64
+    //
+    mov x2, #HCR_EL2_RW
+    msr HCR_EL2, x2
+
+    //
+    // VMID is still significant, even when virtualisation is not
+    // being used, so ensure VTTBR_EL2 is properly initialised
+    //
+    msr VTTBR_EL2, xzr
+
+    //
+    // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
+    //  VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1.
+    // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value
+    // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values.
+    // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value.
+    //
+    mrs x0, MPIDR_EL1
+    msr VMPIDR_EL2, x0
+    mrs x0, MIDR_EL1
+    msr VPIDR_EL2, x0
+
+    // extract the core number from MPIDR_EL1 and store it in
+    // x19 (defined by the AAPCS as callee-saved), so we can re-use
+    // the number later
+    //
+    bl GetCPUID
+    mov x19, x0
+
+    //
+    // neither EL3 nor EL2 trap floating point or accesses to CPACR
+    //
+    msr CPTR_EL3, xzr
+    msr CPTR_EL2, xzr
+
+    //
+    // SCTLR_ELx may come out of reset with UNKNOWN values so we will
+    // set the fields to 0 except, possibly, the endianess field(s).
+    // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1
+    // is not strictly needed, since we're never in EL2 or EL0
+    //
+#ifdef __ARM_BIG_ENDIAN
+    mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E)
+#else
+    mov x0, #0
+#endif
+    msr SCTLR_EL3, x0
+    msr SCTLR_EL2, x0
+    msr SCTLR_EL1, x0
+
+#ifdef CORTEXA
+    //
+    // Configure ACTLR_EL[23]
+    // ----------------------
+    //
+    // These bits are IMPLEMENTATION DEFINED, so are different for
+    // different processors
+    //
+    // For Cortex-A57, the controls we set are:
+    //
+    //  Enable lower level access to CPUACTLR_EL1
+    //  Enable lower level access to CPUECTLR_EL1
+    //  Enable lower level access to L2CTLR_EL1
+    //  Enable lower level access to L2ECTLR_EL1
+    //  Enable lower level access to L2ACTLR_EL1
+    //
+    mov x0, #((1 << 0) | \
+              (1 << 1) | \
+              (1 << 4) | \
+              (1 << 5) | \
+              (1 << 6))
+
+    msr ACTLR_EL3, x0
+    msr ACTLR_EL2, x0
+
+    //
+    // configure CPUECTLR_EL1
+    //
+    // These bits are IMP DEF, so need to different for different
+    // processors
+    //
+    // SMPEN - bit 6 - Enables the processor to receive cache
+    //                 and TLB maintenance operations
+    //
+    // Note: For Cortex-A57/53 SMPEN should be set before enabling
+    //       the caches and MMU, or performing any cache and TLB
+    //       maintenance operations.
+    //
+    //       This register has a defined reset value, so we use a
+    //       read-modify-write sequence to set SMPEN
+    //
+    mrs x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
+    orr x0, x0, #(1 << 6)  // Set the SMPEN bit
+    msr S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
+
+    isb
+#endif
+
+    //
+    // That's the last of the control settings for now
+    //
+    // Note: no ISB after all these changes, as registers won't be
+    // accessed until after an exception return, which is itself a
+    // context synchronisation event
+    //
+
+    //
+    // Setup some EL3 stack space, ready for calling some subroutines, below.
+    //
+    // Stack space allocation is CPU-specific, so use CPU
+    // number already held in x19
+    //
+    // 2^12 bytes per CPU for the EL3 stacks
+    //
+    ldr x0, =__el3_stack
+    sub x0, x0, x19, lsl #12
+    mov sp, x0
+
+    //
+    // we need to configure the GIC while still in secure mode, specifically
+    // all PPIs and SPIs have to be programmed as Group1 interrupts
+    //
+
+    //
+    // Before the GIC can be reliably programmed, we need to
+    // enable Affinity Routing, as this affects where the configuration
+    // registers are (with Affinity Routing enabled, some registers are
+    // in the Redistributor, whereas those same registers are in the
+    // Distributor with Affinity Routing disabled (i.e. when in GICv2
+    // compatibility mode).
+    //
+    mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS
+    mov x1, x19
+    bl  SyncAREinGICD
+
+    //
+    // The Redistributor comes out of reset assuming the processor is
+    // asleep - correct that assumption
+    //
+    mov w0, w19
+    bl  WakeupGICR
+
+    //
+    // Now we're ready to set security and other initialisations
+    //
+    // This is a per-CPU configuration for these interrupts
+    //
+    // for the first cluster, CPU number is the redistributor index
+    //
+    mov w0, w19
+    mov w1, #1    // gicigroupr_G1NS
+    bl  SetPrivateIntSecurityBlock
+
+    //
+    // While we're in the Secure World, set the priority mask low enough
+    // for it to be writable in the Non-Secure World
+    //
+    //mov x0, #16 << 3    // 5 bits of priority in the Secure world
+    mov x0, #0xFF  // for Non-Secure interrupts
+    msr ICC_PMR_EL1, x0
+
+    //
+    // there's more GIC setup to do, but only for the primary CPU
+    //
+    cbnz x19, drop_to_el1
+
+    //
+    // There's more to do to the GIC - call the utility routine to set
+    // all SPIs to Group1
+    //
+    mov w0, #1    // gicigroupr_G1NS
+    bl  SetSPISecurityAll
+
+    //
+    // Set up EL1 entry point and "dummy" exception return information,
+    // then perform exception return to enter EL1
+    //
+    .global drop_to_el1
+drop_to_el1:
+    adr x1, el1_entry_aarch64
+    msr ELR_EL3, x1
+    mov x1, #(AARCH64_SPSR_EL1h | \
+              AARCH64_SPSR_F  | \
+              AARCH64_SPSR_I  | \
+              AARCH64_SPSR_A)
+    msr SPSR_EL3, x1
+    eret
+
+
+
+// ------------------------------------------------------------
+// EL1 - Common start-up code
+// ------------------------------------------------------------
+
+    .global el1_entry_aarch64
+    .type el1_entry_aarch64, "function"
+el1_entry_aarch64:
+
+    //
+    // Now we're in EL1, setup the application stack
+    // the scatter file allocates 2^14 bytes per app stack
+    //
+    ldr x0, =handler_stack_limit
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+    MSR     SPSel, #0
+    ISB
+    ldr x0, =__stack
+    sub x0, x0, x19, lsl #14
+    mov sp, x0
+
+    //
+    // Enable floating point
+    //
+    mov x0, #CPACR_EL1_FPEN
+    msr CPACR_EL1, x0
+
+    //
+    // Invalidate caches and TLBs for all stage 1
+    // translations used at EL1
+    //
+    // Cortex-A processors automatically invalidate their caches on reset
+    // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
+    // It is therefore not necessary for software to invalidate the caches 
+    // on startup, however, this is done here in case of a warm reset.
+    bl  InvalidateUDCaches
+    tlbi VMALLE1
+
+
+    //
+    // Set TTBR0 Base address
+    //
+    // The CPUs share one set of translation tables that are
+    // generated by CPU0 at run-time
+    //
+    // TTBR1_EL1 is not used in this example
+    //
+    ldr x1, =__ttb0_l1
+    msr TTBR0_EL1, x1
+
+
+    //
+    // Set up memory attributes
+    //
+    // These equate to:
+    //
+    // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable
+    // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate
+    // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE
+    //
+    mov  x1, #0xff44
+    movk x1, #4, LSL #16    // equiv to: movk x1, #0x0000000000040000
+    msr MAIR_EL1, x1
+
+
+    //
+    // Set up TCR_EL1
+    //
+    // We're using only TTBR0 (EPD1 = 1), and the page table entries:
+    //  - are using an 8-bit ASID from TTBR0
+    //  - have a 4K granularity (TG0 = 0b00)
+    //  - are outer-shareable (SH0 = 0b10)
+    //  - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01)
+    //  - map
+    //      + 32 bits of VA space (T0SZ = 0x20)
+    //      + into a 32-bit PA space (IPS = 0b000)
+    //
+    //     36   32   28   24   20   16   12    8    4    0
+    //  -----+----+----+----+----+----+----+----+----+----+
+    //       |    |    |OOII|    |    |    |OOII|    |    |
+    //    TT |    |    |RRRR|E T |   T|    |RRRR|E T |   T|
+    //    BB | I I|TTSS|GGGG|P 1 |   1|TTSS|GGGG|P 0 |   0|
+    //    IIA| P P|GGHH|NNNN|DAS |   S|GGHH|NNNN|D S |   S|
+    //    10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z|
+    //
+    //    000 0000 0000 0000 1000 0000 0010 0101 0010 0000
+    //
+    //                    0x    8    0    2    5    2    0
+    //
+    // Note: the ISB is needed to ensure the changes to system
+    //       context are before the write of SCTLR_EL1.M to enable
+    //       the MMU. It is likely on a "real" implementation that
+    //       this setup would work without an ISB, due to the
+    //       amount of code that gets executed before enabling the
+    //       MMU, but that would not be architecturally correct.
+    //
+    ldr x1, =0x0000000000802520
+    msr TCR_EL1, x1
+    isb
+
+    //
+    // the primary CPU is going to use SGI 15 as a wakeup event
+    // to let us know when it is OK to proceed, so prepare for
+    // receiving that interrupt
+    //
+    // NS interrupt priorities run from 0 to 15, with 15 being
+    // too low a priority to ever raise an interrupt, so let's
+    // use 14
+    //
+    mov w0, w19
+    mov w1, #0
+    mov w2, #14 << 4    // we're in NS world, so 4 bits of priority,
+                        // 8-bit field, - 4 = 4-bit shift
+    bl SetPrivateIntPriority
+
+    mov w0, w19
+    mov w1, #0
+    bl  EnablePrivateInt
+
+    //
+    // set priority mask as low as possible; although,being in the
+    // NS World, we can't set bit[7] of the priority, we still
+    // write all 8-bits of priority to an ICC register
+    //
+    mov x0, #31 << 3
+    msr ICC_PMR_EL1, x0
+
+    //
+    // set global enable and wait for our interrupt to arrive
+    //
+    mov x0, #1
+    msr ICC_IGRPEN1_EL1, x0
+    isb
+
+    //
+    // x19 already contains the CPU number, so branch to secondary
+    // code if we're not on CPU0
+    //
+    cbnz x19, el1_secondary
+
+    //
+    // Fall through to primary code
+    //
+
+
+//
+// ------------------------------------------------------------
+//
+// EL1 - primary CPU init code
+//
+// This code is run on CPU0, while the other CPUs are in the
+// holding pen
+//
+
+    .global el1_primary
+    .type el1_primary, "function"
+el1_primary:
+
+    //
+    // Turn on the banked GIC distributor enable,
+    // ready for individual CPU enables later
+    //
+    mov w0, #(1 << 1)  // gicdctlr_EnableGrp1A
+    bl  EnableGICD
+
+    //
+    // Generate TTBR0 L1
+    //
+    // at 4KB granularity, 32-bit VA space, table lookup starts at
+    // L1, with 1GB regions
+    //
+    // we are going to create entries pointing to L2 tables for a
+    // couple of these 1GB regions, the first of which is the
+    // RAM on the VE board model - get the table addresses and
+    // start by emptying out the L1 page tables (4 entries at L1
+    // for a 4K granularity)
+    //
+    // x21 = address of L1 tables
+    //
+    ldr x21, =__ttb0_l1
+    mov x0, x21
+    mov x1, #(4 << 3)
+    bl  ZeroBlock
+
+    //
+    // time to start mapping the RAM regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // x22 = address of L2 tables, needs to be remembered in case
+    //       we want to re-use the tables for mapping peripherals
+    //
+    ldr x22, =__ttb0_l2_ram
+    mov x1, #(512 << 3)
+    mov x0, x22
+    bl  ZeroBlock
+
+    //
+    // Get the start address of RAM (the EXEC region) into x4
+    // and calculate the offset into the L1 table (1GB per region,
+    // max 4GB)
+    //
+    // x23 = L1 table offset, saved for later comparison against
+    //       peripheral offset
+    //
+    ldr x4, =__code_start
+    ubfx x23, x4, #30, #2
+
+    orr x1, x22, #TT_S1_ATTR_PAGE
+    str x1, [x21, x23, lsl #3]
+
+    //
+    // we've already used the RAM start address in x4 - we now need
+    // to get this in terms of an offset into the L2 page tables,
+    // where each entry covers 2MB
+    //
+    ubfx x2, x4, #21, #9
+
+    //
+    // TOP_OF_RAM in the scatter file marks the end of the
+    // Execute region in RAM: convert the end of this region to an
+    // offset too, being careful to round up, then calculate the
+    // number of entries to write
+    //
+    ldr x5, =__top_of_ram
+    sub  x3, x5, #1
+    ubfx x3, x3, #21, #9
+    add  x3, x3, #1
+    sub  x3, x3, x2
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as Shared, Normal WBWA (MAIR[1]) with a flat
+    // VA->PA translation
+    //
+    bic x4, x4, #((1 << 21) - 1)
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (1 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_SH_INNER | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // factor the offset into the page table address and then write
+    // the entries
+    //
+    add x0, x22, x2, lsl #3
+
+loop1:
+    subs x3, x3, #1
+    str x1, [x0], #8
+    add x1, x1, #0x200, LSL #12    // equiv to add x1, x1, #(1 << 21)  // 2MB per entry
+    bne loop1
+
+
+    //
+    // now mapping the Peripheral regions - clear out the
+    // L2 tables and point to them from the L1 tables
+    //
+    // The assumption here is that all peripherals live within
+    // a common 1GB region (i.e. that there's a single set of
+    // L2 pages for all the peripherals). We only use a UART
+    // and the GIC in this example, so the assumption is sound
+    //
+    // x24 = address of L2 peripheral tables
+    //
+    ldr x24, =__ttb0_l2_periph
+
+    //
+    // get the GICD address into x4 and calculate
+    // the offset into the L1 table
+    //
+    // x25 = L1 table offset
+    //
+    ldr x4, =gicd
+    ubfx x25, x4, #30, #2
+
+    //
+    // here's the tricky bit: it's possible that the peripherals are
+    // in the same 1GB region as the RAM, in which case we don't need
+    // to prime a separate set of L2 page tables, nor add them to the
+    // L1 tables
+    //
+    // if we're going to re-use the TTB0_L2_RAM tables, get their
+    // address into x24, which is used later on to write the PTEs
+    //
+    cmp x25, x23
+    csel x24, x22, x24, EQ
+    b.eq nol2setup
+
+    //
+    // Peripherals are in a separate 1GB region, and so have their own
+    // set of L2 tables - clean out the tables and add them to the L1
+    // table
+    //
+    mov x0, x24
+    mov x1, #512 << 3
+    bl  ZeroBlock
+
+    orr x1, x24, #TT_S1_ATTR_PAGE
+    str x1, [x21, x25, lsl #3]
+
+    //
+    // there's only going to be a single 2MB region for GICD (in
+    // x4) - get this in terms of an offset into the L2 page tables
+    //
+    // with larger systems, it is possible that the GIC redistributor
+    // registers require extra 2MB pages, in which case extra code
+    // would be required here
+    //
+nol2setup:
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry for this, so no loop as we have for RAM, above
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // we have CS3_PERIPHERALS that include the UART controller
+    //
+    // Again, the code is making assumptions - this time that the CS3_PERIPHERALS
+    // region uses the same 1GB portion of the address space as the GICD,
+    // and thus shares the same set of L2 page tables
+    //
+    // Get CS3_PERIPHERALS address into x4 and calculate the offset into the
+    // L2 tables
+    //
+    ldr x4, =__cs3_peripherals
+    ubfx x2, x4, #21, #9
+
+    //
+    // set x1 to the required page table attributes, then orr
+    // in the start address (modulo 2MB)
+    //
+    // L2 tables in our configuration cover 2MB per entry - map
+    // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA
+    // translation
+    //
+    bic x4, x4, #((1 << 21) - 1)  // start address mod 2MB
+    mov x1, #(TT_S1_ATTR_BLOCK | \
+             (2 << TT_S1_ATTR_MATTR_LSB) | \
+              TT_S1_ATTR_NS | \
+              TT_S1_ATTR_AP_RW_PL1 | \
+              TT_S1_ATTR_AF | \
+              TT_S1_ATTR_nG)
+    orr x1, x1, x4
+
+    //
+    // only a single L2 entry again - write it
+    //
+    str x1, [x24, x2, lsl #3]
+
+    //
+    // issue a barrier to ensure all table entry writes are complete
+    //
+    dsb ish
+
+    ldr x1, =is_mmu_ready
+    mov x2, #1
+    str x2, [x1]
+
+    //
+    // Enable the MMU.  Caches will be enabled later, after scatterloading.
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+    
+    //
+    // The Arm Architecture Reference Manual for Armv8-A states:
+    //
+    //     Instruction accesses to Non-cacheable Normal memory can be held in instruction caches.
+    //     Correspondingly, the sequence for ensuring that modifications to instructions are available
+    //     for execution must include invalidation of the modified locations from the instruction cache,
+    //     even if the instructions are held in Normal Non-cacheable memory.
+    //     This includes cases where the instruction cache is disabled.
+    //
+
+    dsb ish     // ensure all previous stores have completed before invalidating
+    ic  ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores)
+    dsb ish     // ensure completion on inner shareable domain   (which includes secondary cores)
+    isb
+
+    // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    msr SCTLR_EL1, x1
+    isb
+
+    // Zero the bss
+    ldr x0, =__bss_start__ // Start of block
+    mov x1, #0             // Fill value
+    ldr x2, =__bss_end__   // End of block
+    sub x2, x2, x0         // Length of block
+    bl  memset
+
+    // Set up the standard file handles
+    bl  initialise_monitor_handles
+
+    // Set up _fini and fini_array to be called at exit
+    ldr x0, =__libc_fini_array
+    bl  atexit
+
+    // Call preinit_array, _init and init_array
+    bl  __libc_init_array
+
+    // Set argc = 1, argv[0] = "" and then call main
+    .pushsection .data
+    .align 3
+argv:
+    .dword arg0
+    .dword 0
+arg0:
+    .byte 0
+    .popsection
+
+    mov x0, #1
+    ldr x1, =argv
+    bl main
+
+    b exit // Will not return
+    
+// ------------------------------------------------------------
+// EL1 - secondary CPU init code
+//
+// This code is run on CPUs 1, 2, 3 etc....
+// ------------------------------------------------------------
+
+    .global el1_secondary
+    .type el1_secondary, "function"
+el1_secondary:
+
+wait_for_mmu_ready:
+    ldr x1, =is_mmu_ready
+    ldr x1, [x1]
+    cmp x1, #1
+    b.ne wait_for_mmu_ready
+
+    //
+    // Enable the MMU and caches
+    //
+    mrs x1, SCTLR_EL1
+    orr x1, x1, #SCTLR_ELx_M
+    orr x1, x1, #SCTLR_ELx_C
+    orr x1, x1, #SCTLR_ELx_I
+    bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking.  To enable, change bic to orr
+    msr SCTLR_EL1, x1
+    isb
+
+    /* EL: Secondary core entrance.  */
+    B       _tx_thread_smp_initialize_wait
+
+loop_wfi:
+    dsb SY      // Clear all pending data accesses
+    wfi         // Go to sleep
+
+    //
+    // something woke us from our wait, was it the required interrupt?
+    //
+    mov w0, w19
+    mov w1, #15
+    bl  GetPrivateIntPending
+    cbz w0, loop_wfi
+
+    //
+    // it was - there's no need to actually take the interrupt,
+    // so just clear it
+    //
+    mov w0, w19
+    mov w1, #15
+    bl  ClearPrivateIntPending
+
+    //
+    // Branch to thread start
+    //
+    //B  MainApp
+    
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/timer_interrupts.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/timer_interrupts.c
new file mode 100644
index 00000000..7b0996ef
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/timer_interrupts.c
@@ -0,0 +1,152 @@
+/* Bare-metal example for Armv8-A FVP Base model */
+
+/* Timer and interrupts */
+
+/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */
+/* Use, modification and redistribution of this file is subject to your      */
+/* possession of a valid DS-5 end user licence agreement and your compliance */
+/* with all applicable terms and conditions of such licence agreement.       */
+
+#include <stdio.h>
+
+#include "GICv3.h"
+#include "GICv3_gicc.h"
+#include "sp804_timer.h"
+
+void   _tx_timer_interrupt(void);
+
+// LED Base address
+#define LED_BASE (volatile unsigned int *)0x1C010008
+
+
+void nudge_leds(void) // Move LEDs along
+{
+    static int state = 1;
+    static int value = 1;
+
+    if (state)
+    {
+        int max = (1 << 7);
+        value <<= 1;
+        if (value == max)
+            state = 0;
+    }
+    else
+    {
+        value >>= 1;
+        if (value == 1)
+            state = 1;
+    }
+
+    *LED_BASE = value;  // Update LEDs hardware
+}
+
+
+// Initialize Timer 0 and Interrupt Controller
+void init_timer(void)
+{
+    // Enable interrupts
+    __asm("MSR DAIFClr, #0xF");
+    setICC_IGRPEN1_EL1(igrpEnable);
+
+    // Configure the SP804 timer to generate an interrupt
+    setTimerBaseAddress(0x1C110000);
+    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
+    startTimer();
+
+    // The SP804 timer generates SPI INTID 34.  Enable
+    // this ID, and route it to core 0.0.0.0 (this one!)
+    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
+    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
+    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
+    EnableSPI(34);                                   // Enable INTID 34
+}
+
+
+// --------------------------------------------------------
+
+void irqHandler(void)
+{
+  unsigned int ID;
+
+  ID = getICC_IAR1(); // readIntAck();
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+      //printf("irqHandler() - Reserved INTID %d\n\n", ID);
+      return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      //printf("irqHandler() - External timer interrupt\n\n");
+      nudge_leds();
+      clearTimerIrq();
+
+      /* Call ThreadX timer interrupt processing.  */
+      _tx_timer_interrupt();
+
+      break;
+
+    default:
+      // Unexpected ID value
+      //printf("irqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
+
+// --------------------------------------------------------
+
+// Not actually used in this example, but provided for completeness
+
+void fiqHandler(void)
+{
+  unsigned int ID;
+  unsigned int aliased = 0;
+
+  ID = getICC_IAR0(); // readIntAck();
+  printf("fiqHandler() - Read %d from IAR0\n", ID);
+
+  // Check for reserved IDs
+  if ((1020 <= ID) && (ID <= 1023))
+  {
+    printf("fiqHandler() - Reserved INTID %d\n\n", ID);
+    ID = getICC_IAR1(); // readAliasedIntAck();
+    printf("fiqHandler() - Read %d from AIAR\n", ID);
+    aliased = 1;
+
+    // If still spurious then simply return
+    if ((1020 <= ID) && (ID <= 1023))
+        return;
+  }
+
+  switch(ID)
+  {
+    case 34:
+      // Dual-Timer 0 (SP804)
+      printf("fiqHandler() - External timer interrupt\n\n");
+      clearTimerIrq();
+      break;
+
+    default:
+      // Unexpected ID value
+      printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
+      break;
+  }
+
+  // Write the End of Interrupt register to tell the GIC
+  // we've finished handling the interrupt
+  // NOTE: If the ID was read from the Aliased IAR, then
+  // the aliased EOI register must be used
+  if (aliased == 0)
+    setICC_EOIR0(ID); // writeEOI(ID);
+  else
+    setICC_EOIR1(ID); // writeAliasedEOI(ID);
+}
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S
new file mode 100644
index 00000000..d86fecb6
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S
@@ -0,0 +1,163 @@
+// ------------------------------------------------------------
+// Armv8-A AArch64 - Common helper functions
+//
+// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+    .global EnableCachesEL1
+    .global DisableCachesEL1
+    .global InvalidateUDCaches
+    .global GetMIDR
+    .global GetMPIDR
+    .global GetCPUID
+
+// ------------------------------------------------------------
+
+//
+// void EnableCachesEL1(void)
+//
+//    enable Instruction and Data caches
+//
+    .type EnableCachesEL1, "function"
+    .cfi_startproc
+EnableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    orr x0, x0, #SCTLR_ELx_I
+    orr x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+    .type DisableCachesEL1, "function"
+    .cfi_startproc
+DisableCachesEL1:
+
+    mrs x0, SCTLR_EL1
+    bic x0, x0, #SCTLR_ELx_I
+    bic x0, x0, #SCTLR_ELx_C
+    msr SCTLR_EL1, x0
+
+    isb
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// void InvalidateUDCaches(void)
+//
+//    Invalidate data and unified caches
+//
+    .type InvalidateUDCaches, "function"
+    .cfi_startproc
+InvalidateUDCaches:
+    // From the Armv8-A Architecture Reference Manual
+
+    dmb  ish                   // ensure all prior inner-shareable accesses have been observed
+
+    mrs  x0, CLIDR_EL1
+    and  w3, w0, #0x07000000   // get 2 x level of coherence
+    lsr  w3, w3, #23
+    cbz  w3, finished
+    mov  w10, #0               // w10 = 2 x cache level
+    mov  w8, #1                // w8 = constant 0b1
+loop_level:
+    add  w2, w10, w10, lsr #1  // calculate 3 x cache level
+    lsr  w1, w0, w2            // extract 3-bit cache type for this level
+    and  w1, w1, #0x7
+    cmp  w1, #2
+    b.lt next_level            // no data or unified cache at this level
+    msr  CSSELR_EL1, x10       // select this cache level
+    isb                        // synchronize change of csselr
+    mrs  x1, CCSIDR_EL1        // read ccsidr
+    and  w2, w1, #7            // w2 = log2(linelen)-4
+    add  w2, w2, #4            // w2 = log2(linelen)
+    ubfx w4, w1, #3, #10       // w4 = max way number, right aligned
+    clz  w5, w4                // w5 = 32-log2(ways), bit position of way in dc operand
+    lsl  w9, w4, w5            // w9 = max way number, aligned to position in dc operand
+    lsl  w16, w8, w5           // w16 = amount to decrement way number per iteration
+loop_way:
+    ubfx w7, w1, #13, #15      // w7 = max set number, right aligned
+    lsl  w7, w7, w2            // w7 = max set number, aligned to position in dc operand
+    lsl  w17, w8, w2           // w17 = amount to decrement set number per iteration
+loop_set:
+    orr  w11, w10, w9          // w11 = combine way number and cache number ...
+    orr  w11, w11, w7          // ... and set number for dc operand
+    dc   isw, x11              // do data cache invalidate by set and way
+    subs w7, w7, w17           // decrement set number
+    b.ge loop_set
+    subs x9, x9, x16           // decrement way number
+    b.ge loop_way
+next_level:
+    add  w10, w10, #2          // increment 2 x cache level
+    cmp  w3, w10
+    b.gt loop_level
+    dsb  sy                    // ensure completion of previous cache maintenance operation
+    isb
+finished:
+    ret
+    .cfi_endproc
+
+
+// ------------------------------------------------------------
+
+//
+// ID Register functions
+//
+
+    .type GetMIDR, "function"
+    .cfi_startproc
+GetMIDR:
+
+    mrs x0, MIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetMPIDR, "function"
+    .cfi_startproc
+GetMPIDR:
+
+    mrs x0, MPIDR_EL1
+    ret
+    .cfi_endproc
+
+
+    .type GetCPUID, "function"
+    .cfi_startproc
+GetCPUID:
+
+    mrs x0, MIDR_EL1
+    ubfx    x0, x0, #4, #12 // extract PartNum
+    cmp x0, #0xD0B          // Cortex-A76
+    b.eq DynamIQ
+    cmp x0, #0xD0A          // Cortex-A75
+    b.eq DynamIQ
+    cmp x0, #0xD05          // Cortex-A55
+    b.eq DynamIQ
+    b Others
+DynamIQ:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+
+Others:
+    mrs x0, MPIDR_EL1
+    ubfx    x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_mmu.h
new file mode 100644
index 00000000..0185feba
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_mmu.h
@@ -0,0 +1,118 @@
+//
+// Defines for v8 Memory Model
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_MMU_H
+#define V8_MMU_H
+
+//
+// Translation Control Register fields
+//
+// RGN field encodings
+//
+#define TCR_RGN_NC   0b00
+#define TCR_RGN_WBWA 0b01
+#define TCR_RGN_WT   0b10
+#define TCR_RGN_WBRA 0b11
+
+//
+// Shareability encodings
+//
+#define TCR_SHARE_NONE  0b00
+#define TCR_SHARE_OUTER 0b10
+#define TCR_SHARE_INNER 0b11
+
+//
+// Granule size encodings
+//
+#define TCR_GRANULE_4K  0b00
+#define TCR_GRANULE_64K 0b01
+#define TCR_GRANULE_16K 0b10
+
+//
+// Physical Address sizes
+//
+#define TCR_SIZE_4G   0b000
+#define TCR_SIZE_64G  0b001
+#define TCR_SIZE_1T   0b010
+#define TCR_SIZE_4T   0b011
+#define TCR_SIZE_16T  0b100
+#define TCR_SIZE_256T 0b101
+
+//
+// Translation Control Register fields
+//
+#define TCR_EL1_T0SZ_SHIFT   0
+#define TCR_EL1_EPD0  (1 << 7)
+#define TCR_EL1_IRGN0_SHIFT  8
+#define TCR_EL1_ORGN0_SHIFT 10
+#define TCR_EL1_SH0_SHIFT   12
+#define TCR_EL1_TG0_SHIFT   14
+
+#define TCR_EL1_T1SZ_SHIFT  16
+#define TCR_EL1_A1   (1 << 22)
+#define TCR_EL1_EPD1 (1 << 23)
+#define TCR_EL1_IRGN1_SHIFT 24
+#define TCR_EL1_ORGN1_SHIFT 26
+#define TCR_EL1_SH1_SHIFT   28
+#define TCR_EL1_TG1_SHIFT   30
+#define TCR_EL1_IPS_SHIFT   32
+#define TCR_EL1_AS   (1 << 36)
+#define TCR_EL1_TBI0 (1 << 37)
+#define TCR_EL1_TBI1 (1 << 38)
+
+//
+// Stage 1 Translation Table descriptor fields
+//
+#define TT_S1_ATTR_FAULT (0b00 << 0)
+#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2
+#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2
+#define TT_S1_ATTR_PAGE  (0b11 << 0) // Level 3
+
+#define TT_S1_ATTR_MATTR_LSB 2
+
+#define TT_S1_ATTR_NS (1 << 5)
+
+#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6)
+#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6)
+#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6)
+#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6)
+
+#define TT_S1_ATTR_SH_NONE   (0b00 << 8)
+#define TT_S1_ATTR_SH_OUTER  (0b10 << 8)
+#define TT_S1_ATTR_SH_INNER  (0b11 << 8)
+
+#define TT_S1_ATTR_AF (1 << 10)
+#define TT_S1_ATTR_nG (1 << 11)
+
+#define TT_S1_ATTR_CONTIG (1 << 52)
+#define TT_S1_ATTR_PXN    (1 << 53)
+#define TT_S1_ATTR_UXN    (1 << 54)
+
+#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
+#define TT_S1_MAIR_DEV_nGnRE  0b00000100
+#define TT_S1_MAIR_DEV_nGRE   0b00001000
+#define TT_S1_MAIR_DEV_GRE    0b00001100
+
+//
+// Inner and Outer Normal memory attributes use the same bit patterns
+// Outer attributes just need to be shifted up
+//
+#define TT_S1_MAIR_OUTER_SHIFT 4
+
+#define TT_S1_MAIR_WT_TRANS_RA  0b0010
+
+#define TT_S1_MAIR_WB_TRANS_RA  0b0110
+#define TT_S1_MAIR_WB_TRANS_RWA 0b0111
+
+#define TT_S1_MAIR_WT_RA  0b1010
+
+#define TT_S1_MAIR_WB_RA  0b1110
+#define TT_S1_MAIR_WB_RWA 0b1111
+
+#endif // V8_MMU_H
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_system.h
new file mode 100644
index 00000000..ff96deff
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_system.h
@@ -0,0 +1,115 @@
+//
+// Defines for v8 System Registers
+//
+// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#ifndef V8_SYSTEM_H
+#define V8_SYSTEM_H
+
+//
+// AArch64 SPSR
+//
+#define AARCH64_SPSR_EL3h 0b1101
+#define AARCH64_SPSR_EL3t 0b1100
+#define AARCH64_SPSR_EL2h 0b1001
+#define AARCH64_SPSR_EL2t 0b1000
+#define AARCH64_SPSR_EL1h 0b0101
+#define AARCH64_SPSR_EL1t 0b0100
+#define AARCH64_SPSR_EL0t 0b0000
+#define AARCH64_SPSR_RW (1 << 4)
+#define AARCH64_SPSR_F  (1 << 6)
+#define AARCH64_SPSR_I  (1 << 7)
+#define AARCH64_SPSR_A  (1 << 8)
+#define AARCH64_SPSR_D  (1 << 9)
+#define AARCH64_SPSR_IL (1 << 20)
+#define AARCH64_SPSR_SS (1 << 21)
+#define AARCH64_SPSR_V  (1 << 28)
+#define AARCH64_SPSR_C  (1 << 29)
+#define AARCH64_SPSR_Z  (1 << 30)
+#define AARCH64_SPSR_N  (1 << 31)
+
+//
+// Multiprocessor Affinity Register
+//
+#define MPIDR_EL1_AFF3_LSB 32
+#define MPIDR_EL1_U  (1 << 30)
+#define MPIDR_EL1_MT (1 << 24)
+#define MPIDR_EL1_AFF2_LSB 16
+#define MPIDR_EL1_AFF1_LSB  8
+#define MPIDR_EL1_AFF0_LSB  0
+#define MPIDR_EL1_AFF_WIDTH 8
+
+//
+// Data Cache Zero ID Register
+//
+#define DCZID_EL0_BS_LSB   0
+#define DCZID_EL0_BS_WIDTH 4
+#define DCZID_EL0_DZP_LSB  5
+#define DCZID_EL0_DZP (1 << 5)
+
+//
+// System Control Register
+//
+#define SCTLR_EL1_UCI     (1 << 26)
+#define SCTLR_ELx_EE      (1 << 25)
+#define SCTLR_EL1_E0E     (1 << 24)
+#define SCTLR_ELx_WXN     (1 << 19)
+#define SCTLR_EL1_nTWE    (1 << 18)
+#define SCTLR_EL1_nTWI    (1 << 16)
+#define SCTLR_EL1_UCT     (1 << 15)
+#define SCTLR_EL1_DZE     (1 << 14)
+#define SCTLR_ELx_I       (1 << 12)
+#define SCTLR_EL1_UMA     (1 << 9)
+#define SCTLR_EL1_SED     (1 << 8)
+#define SCTLR_EL1_ITD     (1 << 7)
+#define SCTLR_EL1_THEE    (1 << 6)
+#define SCTLR_EL1_CP15BEN (1 << 5)
+#define SCTLR_EL1_SA0     (1 << 4)
+#define SCTLR_ELx_SA      (1 << 3)
+#define SCTLR_ELx_C       (1 << 2)
+#define SCTLR_ELx_A       (1 << 1)
+#define SCTLR_ELx_M       (1 << 0)
+
+//
+// Architectural Feature Access Control Register
+//
+#define CPACR_EL1_TTA     (1 << 28)
+#define CPACR_EL1_FPEN    (3 << 20)
+
+//
+// Architectural Feature Trap Register
+//
+#define CPTR_ELx_TCPAC (1 << 31)
+#define CPTR_ELx_TTA   (1 << 20)
+#define CPTR_ELx_TFP   (1 << 10)
+
+//
+// Secure Configuration Register
+//
+#define SCR_EL3_TWE  (1 << 13)
+#define SCR_EL3_TWI  (1 << 12)
+#define SCR_EL3_ST   (1 << 11)
+#define SCR_EL3_RW   (1 << 10)
+#define SCR_EL3_SIF  (1 << 9)
+#define SCR_EL3_HCE  (1 << 8)
+#define SCR_EL3_SMD  (1 << 7)
+#define SCR_EL3_EA   (1 << 3)
+#define SCR_EL3_FIQ  (1 << 2)
+#define SCR_EL3_IRQ  (1 << 1)
+#define SCR_EL3_NS   (1 << 0)
+
+//
+// Hypervisor Configuration Register
+//
+#define HCR_EL2_ID   (1 << 33)
+#define HCR_EL2_CD   (1 << 32)
+#define HCR_EL2_RW   (1 << 31)
+#define HCR_EL2_TRVM (1 << 30)
+#define HCR_EL2_HVC  (1 << 29)
+#define HCR_EL2_TDZ  (1 << 28)
+
+#endif // V8_SYSTEM_H
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_utils.S
new file mode 100644
index 00000000..f0fcef26
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_utils.S
@@ -0,0 +1,69 @@
+//
+// Simple utility routines for baremetal v8 code
+//
+// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//
+
+#include "v8_system.h"
+
+    .text
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//
+// void *ZeroBlock(void *blockPtr, unsigned int nBytes)
+//
+// Zero fill a block of memory
+//   Fill memory pages or similar structures with zeros.
+//   The byte count must be a multiple of the block fill size (16 bytes)
+//
+//  Inputs:
+//    blockPtr - base address of block to fill
+//    nBytes - block size, in bytes
+//
+//  Returns:
+//    pointer to just filled block, NULL if nBytes is
+//  incompatible with block fill size
+//
+    .global ZeroBlock
+    .type ZeroBlock, "function"
+    .cfi_startproc
+ZeroBlock:
+
+    //
+    // we fill data by steam, 16 bytes at a time: check that
+    // blocksize is a multiple of that
+    //
+    ubfx x2, x1, #0, #4
+    cbnz x2, incompatible
+
+    //
+    // we already have one register full of zeros, get another
+    //
+    mov x3, x2
+
+    //
+    // OK, set temporary pointer and away we go
+    //
+    add x0, x0, x1
+
+loop0:
+    subs x1, x1, #16
+    stp  x2, x3, [x0, #-16]!
+    b.ne loop0
+
+    //
+    // that's all - x0 will be back to its start value
+    //
+    ret
+
+    //
+    // parameters are incompatible with block size - return
+    // an indication that this is so
+    //
+incompatible:
+    mov x0,#0
+    ret
+    .cfi_endproc
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/vectors.S
new file mode 100644
index 00000000..9e60e001
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/vectors.S
@@ -0,0 +1,252 @@
+// ------------------------------------------------------------
+// Armv8-A Vector tables
+//
+// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+// ------------------------------------------------------------
+
+
+    .global el1_vectors
+    .global el2_vectors
+    .global el3_vectors
+    .global c0sync1
+    .global irqHandler
+    .global fiqHandler
+    .global irqFirstLevelHandler
+    .global fiqFirstLevelHandler
+
+    .section  EL1VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el1_vectors:
+c0sync1: B c0sync1
+
+    .balign 0x80
+c0irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr1: B c0serr1
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync1: B cxsync1
+
+    .balign 0x80
+cxirq1: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr1: B cxserr1
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync1: B l64sync1
+
+    .balign 0x80
+l64irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr1: B l64serr1
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync1: B l32sync1
+
+    .balign 0x80
+l32irq1: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq1: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr1: B l32serr1
+
+//----------------------------------------------------------------
+
+    .section  EL2VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el2_vectors:
+c0sync2: B c0sync2
+
+    .balign 0x80
+c0irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr2: B c0serr2
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync2: B cxsync2
+
+    .balign 0x80
+cxirq2: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr2: B cxserr2
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync2: B l64sync2
+
+    .balign 0x80
+l64irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr2: B l64serr2
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync2: B l32sync2
+
+    .balign 0x80
+l32irq2: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq2: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr2: B l32serr2
+
+//----------------------------------------------------------------
+
+    .section  EL3VECTORS, "ax"
+    .align 11
+
+//
+// Current EL with SP0
+//
+el3_vectors:
+c0sync3: B c0sync3
+
+    .balign 0x80
+c0irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+c0fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+c0serr3: B c0serr3
+
+//
+// Current EL with SPx
+//
+    .balign 0x80
+cxsync3: B cxsync3
+
+    .balign 0x80
+cxirq3: B irqFirstLevelHandler
+
+    .balign 0x80
+cxfiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+cxserr3: B cxserr3
+
+//
+// Lower EL using AArch64
+//
+    .balign 0x80
+l64sync3: B l64sync3
+
+    .balign 0x80
+l64irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l64fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l64serr3: B l64serr3
+
+//
+// Lower EL using AArch32
+//
+    .balign 0x80
+l32sync3: B l32sync3
+
+    .balign 0x80
+l32irq3: B irqFirstLevelHandler
+
+    .balign 0x80
+l32fiq3: B fiqFirstLevelHandler
+
+    .balign 0x80
+l32serr3: B l32serr3
+
+
+    .section InterruptHandlers, "ax"
+    .balign 4
+
+    .type irqFirstLevelHandler, "function"
+irqFirstLevelHandler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+  BL       irqHandler
+  B        _tx_thread_context_restore
+
+    .type fiqFirstLevelHandler, "function"
+fiqFirstLevelHandler:
+  STP      x29, x30, [sp, #-16]!
+  STP      x18, x19, [sp, #-16]!
+  STP      x16, x17, [sp, #-16]!
+  STP      x14, x15, [sp, #-16]!
+  STP      x12, x13, [sp, #-16]!
+  STP      x10, x11, [sp, #-16]!
+  STP      x8, x9, [sp, #-16]!
+  STP      x6, x7, [sp, #-16]!
+  STP      x4, x5, [sp, #-16]!
+  STP      x2, x3, [sp, #-16]!
+  STP      x0, x1, [sp, #-16]!
+
+  BL       fiqHandler
+
+  LDP      x0, x1, [sp], #16
+  LDP      x2, x3, [sp], #16
+  LDP      x4, x5, [sp], #16
+  LDP      x6, x7, [sp], #16
+  LDP      x8, x9, [sp], #16
+  LDP      x10, x11, [sp], #16
+  LDP      x12, x13, [sp], #16
+  LDP      x14, x15, [sp], #16
+  LDP      x16, x17, [sp], #16
+  LDP      x18, x19, [sp], #16
+  LDP      x29, x30, [sp], #16
+  ERET
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject
new file mode 100644
index 00000000..a38608a6
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject
@@ -0,0 +1,288 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings>
+                    					
+                    <externalSetting>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
+                        					
+                    </externalSetting>
+                    				
+                </externalSettings>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674" name="Debug" parent="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf">
+                    					
+                    <folderInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.debug.var.gcc-8.3.0-aarch64-elf.1044400792" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.debug.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674..1923732242" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/tx}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.192205232" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1514058704" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1047964694" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.1734103792" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_modules}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym.829608210" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.other.349843643" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.other" useByScannerDiscovery="false" value="-Wno-unused-function" valueType="string"/>
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+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1073576394" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.1215160681" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1361727446" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.777741249" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                							
+                            </tool>
+                            							
+                            <tool command="aarch64-elf-gcc.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.3581408" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.1479915574" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" valueType="boolean"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym.247736544" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.598225750" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool command="aarch64-elf-ar.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.1915339168" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.1026192913" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="-r" valueType="string"/>
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+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                								
+                                <outputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.output.800978390" outputPrefix="lib" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.output"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.1585841955" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.545644886" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="src_generic/tx_misra.c|src_generic/tx_thread_timeout.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        		
+        <cconfiguration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976" name="Release" parent="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf">
+                    					
+                    <folderInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.release.var.gcc-8.3.0-aarch64-elf.34718044" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.release.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976..1773498793" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/tx}/Release" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.1193489338" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1738885767" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
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+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.377151475" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
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+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.1245584605" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
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+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.803848059" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
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+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.869473566" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
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+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
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+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.1435138732" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.1360800770" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
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+                    					
+                    <sourceEntries>
+                        						
+                        <entry excluding="src_generic/tx_misra.c|src_generic/tx_thread_timeout.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                        					
+                    </sourceEntries>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="tx.com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.exe.var.gcc-8.3.0-aarch64-elf.1102801152" name="Executable" projectType="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.exe.var.gcc-8.3.0-aarch64-elf"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        		
+        <scannerConfigBuildInfo instanceId="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1738885767;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1019453589">
+            			
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+            		
+        </scannerConfigBuildInfo>
+        		
+        <scannerConfigBuildInfo instanceId="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1073576394">
+            			
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+            		
+        </scannerConfigBuildInfo>
+        	
+    </storageModule>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/tx/.project b/ports_module/cortex_a35_smp/gnu/example_build/tx/.project
new file mode 100644
index 00000000..7e68cb5c
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/tx/.project
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>tx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_modules</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
+		</link>
+		<link>
+			<name>src_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/src</locationURI>
+		</link>
+		<link>
+			<name>src_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/module_manager/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/txm/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/txm/.cproject
new file mode 100644
index 00000000..267cf889
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/txm/.cproject
@@ -0,0 +1,198 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                				
+                <externalSettings>
+                    					
+                    <externalSetting>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
+                        						
+                        <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
+                        						
+                        <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/>
+                        					
+                    </externalSetting>
+                    				
+                </externalSettings>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    					
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    				
+                </extensions>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                				
+                <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
+                    					
+                    <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1940578560" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf">
+                            							
+                            <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-8.3.0-aarch64-elf.1940578560.1206339987" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/txm}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.577302939" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.948279352" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.808254157" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath">
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_port}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic_modules}&quot;"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc_generic_module_manager}&quot;"/>
+                                    								
+                                </option>
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1147593988" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.581062876" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.269490798" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch.168537148" name="Architecture (-march)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym.841907083" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.846815502" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.1779346429" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.730893571" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1685004753" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.933436547" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option defaultValue="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.2021469141" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" useByScannerDiscovery="false" valueType="boolean"/>
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+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.arch.1802198374" name="Architecture (-march)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.arch" useByScannerDiscovery="false" value="" valueType="string"/>
+                                								
+                                <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym.477939538" name="Defined symbols (-D)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.defsym" useByScannerDiscovery="false" valueType="definedSymbols">
+                                    									
+                                    <listOptionValue builtIn="false" value="STANDALONE"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="ENABLE_ARM_FP"/>
+                                    									
+                                    <listOptionValue builtIn="false" value="EL1"/>
+                                    								
+                                </option>
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu.1013171365" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/>
+                                								
+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.1844101184" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
+                                							
+                            </tool>
+                            							
+                            <tool command="aarch64-elf-ar.exe" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.1278004178" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
+                                								
+                                <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.1900478654" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="-r" valueType="string"/>
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+                                <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input.824702411" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input">
+                                    									
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                    									
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    								
+                                </inputType>
+                                								
+                                <outputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.output.478843545" outputPrefix="lib" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.output"/>
+                                							
+                            </tool>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.494963401" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
+                            							
+                            <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.276907065" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="refreshScope" versionNumber="2">
+        		
+        <configuration configurationName="Debug">
+            			
+            <resource resourceType="PROJECT" workspacePath="/txm"/>
+            		
+        </configuration>
+        		
+        <configuration configurationName="Release">
+            			
+            <resource resourceType="PROJECT" workspacePath="/tx"/>
+            		
+        </configuration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
+    	
+    <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        		
+        <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551;com.arm.eclipse.build.config.v6.lib.debug.base.1507005551.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.948279352;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.846815502">
+            			
+            <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+            		
+        </scannerConfigBuildInfo>
+        	
+    </storageModule>
+    
+</cproject>
diff --git a/ports_module/cortex_a35_smp/gnu/example_build/txm/.project b/ports_module/cortex_a35_smp/gnu/example_build/txm/.project
new file mode 100644
index 00000000..8b510516
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/example_build/txm/.project
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>txm</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>inc_generic</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_generic_module_manager</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_generic_modules</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
+		</link>
+		<link>
+			<name>inc_port</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
+		</link>
+		<link>
+			<name>src_generic_module_lib</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_lib/src</locationURI>
+		</link>
+		<link>
+			<name>src_port_module_lib</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/module_lib/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h
new file mode 100644
index 00000000..cf8ec0b1
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h
@@ -0,0 +1,450 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                        Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/************* Define ThreadX SMP constants.  *************/
+
+#define TX_THREAD_SMP                           1
+
+
+/* Define the ThreadX SMP maximum number of cores.  */
+
+#ifndef TX_THREAD_SMP_MAX_CORES
+#define TX_THREAD_SMP_MAX_CORES                 4
+#endif
+
+
+/* Define the ThreadX SMP core mask. */
+
+#ifndef TX_THREAD_SMP_CORE_MASK
+#define TX_THREAD_SMP_CORE_MASK                 0xF            /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc.  */
+#endif
+
+
+/* Define INLINE_DECLARE to whitespace for ARM compiler.  */
+
+#define INLINE_DECLARE
+
+
+/* Define ThreadX SMP initialization macro.  */
+
+#define TX_PORT_SPECIFIC_PRE_INITIALIZATION                 
+
+
+/* Define ThreadX SMP pre-scheduler initialization.  */
+
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION       
+
+
+/* Enable the inter-core interrupt logic.  */
+
+#define TX_THREAD_SMP_INTER_CORE_INTERRUPT
+
+
+/* Determine if there is customer-specific wakeup logic needed.  */
+
+#ifdef TX_THREAD_SMP_WAKEUP_LOGIC
+
+/* Include customer-specific wakeup code.  */
+
+#include "tx_thread_smp_core_wakeup.h"
+#else
+
+#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC
+
+/* Default wakeup code.  */
+#define TX_THREAD_SMP_WAKEUP_LOGIC
+#define TX_THREAD_SMP_WAKEUP(i)                _tx_thread_smp_core_preempt(i)
+#endif
+#endif
+
+
+/* Ensure that the in-line resume/suspend define is not allowed.  */
+
+#ifdef TX_INLINE_THREAD_RESUME_SUSPEND
+#undef TX_INLINE_THREAD_RESUME_SUSPEND
+#endif
+
+
+/************* End ThreadX SMP constants.  *************/
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include <stdlib.h>
+#include <string.h>
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef int                                     LONG;
+typedef unsigned int                            ULONG;
+typedef unsigned long long                      ULONG64;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Override the alignment type to use 64-bit alignment and storage for pointers.  */
+
+#define ALIGN_TYPE_DEFINED
+typedef unsigned long long                      ALIGN_TYPE;
+
+
+/* Override the free block marker for byte pools to be a 64-bit constant.   */
+
+#define TX_BYTE_BLOCK_FREE                      ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE)
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              4096        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex ARMv8 port.  */ 
+
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ & FIQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    _tx_thread_smp_time_get()
+#endif
+#else
+#ifndef TX_TRACE_TIME_SOURCE
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0
+#define TX_THREAD_EXTENSION_1
+#define TX_THREAD_EXTENSION_2               ULONG   tx_thread_fp_enable;
+#define TX_THREAD_EXTENSION_3               VOID    *tx_thread_extension_ptr;               \
+                                            VOID    *tx_thread_module_instance_ptr;         \
+                                            VOID    *tx_thread_module_entry_info_ptr;       \
+                                            ULONG   tx_thread_module_current_user_mode;     \
+                                            ULONG   tx_thread_module_user_mode;             \
+                                            ULONG   tx_thread_module_saved_lr;              \
+                                            VOID    *tx_thread_module_kernel_stack_start;   \
+                                            VOID    *tx_thread_module_kernel_stack_end;     \
+                                            ULONG   tx_thread_module_kernel_stack_size;     \
+                                            VOID    *tx_thread_module_stack_ptr;            \
+                                            VOID    *tx_thread_module_stack_start;          \
+                                            VOID    *tx_thread_module_stack_end;            \
+                                            ULONG   tx_thread_module_stack_size;            \
+                                            VOID    *tx_thread_module_reserved;
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       b =  (UINT) __builtin_ctz((unsigned int) m);
+
+#endif
+
+
+/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout
+   can figure out what thread timeout to process.  */
+   
+#define TX_TIMER_INTERNAL_EXTENSION             VOID    *tx_timer_internal_thread_timeout_ptr;
+
+
+/* Define the thread timeout setup logic in _tx_thread_create.  */
+
+#define TX_THREAD_CREATE_TIMEOUT_SETUP(t)    (t) -> tx_thread_timer.tx_timer_internal_timeout_function =    &(_tx_thread_timeout);            \
+                                             (t) -> tx_thread_timer.tx_timer_internal_timeout_param =       0;                                \
+                                             (t) -> tx_thread_timer.tx_timer_internal_thread_timeout_ptr =  (VOID *) (t);
+
+
+/* Define the thread timeout pointer setup in _tx_thread_timeout.  */
+
+#define TX_THREAD_TIMEOUT_POINTER_SETUP(t)   (t) =  (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr;
+
+
+/************* Define ThreadX SMP data types and function prototypes.  *************/
+
+struct TX_THREAD_STRUCT;
+
+
+/* Define the ThreadX SMP protection structure.   */
+
+typedef struct TX_THREAD_SMP_PROTECT_STRUCT
+{
+    ULONG           tx_thread_smp_protect_in_force;
+    ULONG           tx_thread_smp_protect_core;
+    ULONG           tx_thread_smp_protect_count;
+    ULONG           tx_thread_smp_protect_pad_0;
+    ULONG           tx_thread_smp_protect_pad_1;
+    ULONG           tx_thread_smp_protect_pad_2;    
+    ULONG           tx_thread_smp_protect_pad_3;    
+} TX_THREAD_SMP_PROTECT;
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_smp_protect();
+#define TX_RESTORE                              _tx_thread_smp_unprotect(interrupt_save);
+
+/************* End ThreadX SMP data type and function prototype definitions.  *************/
+
+
+/* Define FP extension for the Cortex-A35.  Each is assumed to be called in the context of the executing
+   thread.  */
+
+#ifndef TX_SOURCE_CODE
+#define tx_thread_fp_enable                     _tx_thread_fp_enable
+#define tx_thread_fp_disable                    _tx_thread_fp_disable
+#endif
+
+VOID    tx_thread_fp_enable(VOID);
+VOID    tx_thread_fp_disable(VOID);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Modules Cortex-A35-SMP/GNU Version 6.1.3 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
diff --git a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h
new file mode 100644
index 00000000..604b801a
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h
@@ -0,0 +1,279 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
+/*                                                                        */
+/*    txm_module_port.h                                 Cortex-A35/GNU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file defines the basic module constants, interface structures, */
+/*    and function prototypes.                                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TXM_MODULE_PORT_H
+#define TXM_MODULE_PORT_H
+
+/* Determine if the optional Modules user define file should be used.  */
+
+#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in txm_module_user.h. The defines in this file may
+   alternately be defined on the command line.  */
+
+#include "txm_module_user.h"
+#endif
+
+/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
+  following extensions to the ThreadX thread control block (this code should replace
+  the corresponding macro define in tx_port.h):
+
+#define TX_THREAD_EXTENSION_2               VOID    *tx_thread_module_instance_ptr;         \
+                                            VOID    *tx_thread_module_entry_info_ptr;       \
+                                            ULONG   tx_thread_module_current_user_mode;     \
+                                            ULONG   tx_thread_module_user_mode;             \
+                                            ULONG   tx_thread_module_saved_lr;              \
+                                            VOID    *tx_thread_module_kernel_stack_start;   \
+                                            VOID    *tx_thread_module_kernel_stack_end;     \
+                                            ULONG   tx_thread_module_kernel_stack_size;     \
+                                            VOID    *tx_thread_module_stack_ptr;            \
+                                            VOID    *tx_thread_module_stack_start;          \
+                                            VOID    *tx_thread_module_stack_end;            \
+                                            ULONG   tx_thread_module_stack_size;            \
+                                            VOID    *tx_thread_module_reserved;
+
+The following extensions must also be defined in tx_port.h:
+
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+*/
+
+/* Define the kernel stack size for a module thread.  */
+#ifndef TXM_MODULE_KERNEL_STACK_SIZE
+#define TXM_MODULE_KERNEL_STACK_SIZE            768
+#endif
+
+/* Define constants specific to the tools the module can be built with for this particular modules port.  */
+
+#define TXM_MODULE_IAR_COMPILER                 0x00000000
+#define TXM_MODULE_RVDS_COMPILER                0x01000000
+#define TXM_MODULE_GNU_COMPILER                 0x02000000
+#define TXM_MODULE_COMPILER_MASK                0xFF000000
+#define TXM_MODULE_OPTIONS_MASK                 0x000000FF
+
+
+/* Define the properties for this particular module port.  */
+
+#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
+
+#ifdef  TXM_MODULE_MEMORY_PROTECTION_ENABLED
+#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
+#else
+#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
+#endif
+
+#define TXM_MODULE_USER_MODE                        0x00000001
+#define TXM_MODULE_MEMORY_PROTECTION                0x00000002
+#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS    0x00000004
+
+
+/* Define the supported options for this module.   */
+
+#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS    (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
+#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS     0
+
+
+/* Define offset adjustments according to the compiler used to build the module.  */
+
+#define TXM_MODULE_IAR_SHELL_ADJUST             24
+#define TXM_MODULE_IAR_START_ADJUST             28
+#define TXM_MODULE_IAR_STOP_ADJUST              32
+#define TXM_MODULE_IAR_CALLBACK_ADJUST          44
+
+#define TXM_MODULE_RVDS_SHELL_ADJUST            0
+#define TXM_MODULE_RVDS_START_ADJUST            0
+#define TXM_MODULE_RVDS_STOP_ADJUST             0
+#define TXM_MODULE_RVDS_CALLBACK_ADJUST         0
+
+#define TXM_MODULE_GNU_SHELL_ADJUST             24
+#define TXM_MODULE_GNU_START_ADJUST             28
+#define TXM_MODULE_GNU_STOP_ADJUST              32
+#define TXM_MODULE_GNU_CALLBACK_ADJUST          44
+
+
+/* Define other module port-specific constants.  */
+
+/* Define the port-extensions to the module manager instance structure.  */
+
+#define TXM_MODULE_MANAGER_PORT_EXTENSION
+
+
+/* Define the memory fault information structure that is populated when a memory fault occurs.  */
+
+typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
+{
+    TX_THREAD           *txm_module_manager_memory_fault_info_thread_ptr;
+    VOID                *txm_module_manager_memory_fault_info_code_location;
+    ULONG               txm_module_manager_memory_fault_info_shcsr;
+    ULONG               txm_module_manager_memory_fault_info_cfsr;
+    ULONG               txm_module_manager_memory_fault_info_mmfar;
+    ULONG               txm_module_manager_memory_fault_info_bfar;
+    ULONG               txm_module_manager_memory_fault_info_control;
+    ULONG               txm_module_manager_memory_fault_info_sp;
+    ULONG               txm_module_manager_memory_fault_info_r0;
+    ULONG               txm_module_manager_memory_fault_info_r1;
+    ULONG               txm_module_manager_memory_fault_info_r2;
+    ULONG               txm_module_manager_memory_fault_info_r3;
+    ULONG               txm_module_manager_memory_fault_info_r4;
+    ULONG               txm_module_manager_memory_fault_info_r5;
+    ULONG               txm_module_manager_memory_fault_info_r6;
+    ULONG               txm_module_manager_memory_fault_info_r7;
+    ULONG               txm_module_manager_memory_fault_info_r8;
+    ULONG               txm_module_manager_memory_fault_info_r9;
+    ULONG               txm_module_manager_memory_fault_info_r10;
+    ULONG               txm_module_manager_memory_fault_info_r11;
+    ULONG               txm_module_manager_memory_fault_info_r12;
+    ULONG               txm_module_manager_memory_fault_info_lr;
+    ULONG               txm_module_manager_memory_fault_info_xpsr;
+} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
+
+
+#define TXM_MODULE_MANAGER_FAULT_INFO                                               \
+    TXM_MODULE_MANAGER_MEMORY_FAULT_INFO    _txm_module_manager_memory_fault_info;
+
+/* Define the macro to check the code alignment.  */
+
+#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment)    \
+    {                                                                               \
+        ALIGN_TYPE   temp;                                                          \
+        temp =  (ALIGN_TYPE) module_location;                                       \
+        temp =  temp & (code_alignment - 1);                                        \
+        if (temp)                                                                   \
+        {                                                                           \
+            _tx_mutex_put(&_txm_module_manager_mutex);                              \
+            return(TXM_MODULE_ALIGNMENT_ERROR);                                     \
+        }                                                                           \
+    }
+
+
+/* Define the macro to adjust the alignment and size for code/data areas.  */
+
+#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) \
+    {                                                                                                              \
+        code_size = (code_size % 32) ? ((code_size + 32) & ~32) : (code_size);                                     \
+        code_alignment = 32;                                                                                       \
+        data_size = (data_size % 32) ? ((data_size + 32) & ~32) : (data_size);                                     \
+        data_alignment = 32;                                                                                       \
+    }
+
+
+/* Define the macro to adjust the symbols in the module preamble.  */
+
+#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
+    if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER)         \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_IAR_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_IAR_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_IAR_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_IAR_CALLBACK_ADJUST;                 \
+    }                                                                               \
+    else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER)   \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_RVDS_SHELL_ADJUST;                   \
+        start_function_adjust =     TXM_MODULE_RVDS_START_ADJUST;                   \
+        stop_function_adjust =      TXM_MODULE_RVDS_STOP_ADJUST;                    \
+        callback_function_adjust =  TXM_MODULE_RVDS_CALLBACK_ADJUST;                \
+    }                                                                               \
+    else                                                                            \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_GNU_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_GNU_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_GNU_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_GNU_CALLBACK_ADJUST;                 \
+    }
+
+
+/* Define the macro to populate the thread control block with module port-specific information.
+   Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
+*/
+
+#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance)                                                                    \
+    thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher =   _txm_module_manager_kernel_dispatch;
+
+
+/* Define the macro to populate the module control block with module port-specific information.
+*/
+#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance)
+
+
+/* Define the macro to perform port-specific functions when unloading the module.  */
+/* Nothing needs to be done for this port.  */
+#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
+
+
+/* Define the macros to perform port-specific checks when passing pointers to the kernel.  */
+
+/* Define macro to make sure object is inside the module's data.  */
+#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) (TX_SUCCESS)
+
+/* Define some internal prototypes to this module port.  */
+
+#ifndef TX_SOURCE_CODE
+#define txm_module_manager_memory_fault_notify              _txm_module_manager_memory_fault_notify
+#endif
+
+
+#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES                                                                                                                      \
+VOID  _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment);   \
+ULONG _txm_module_manager_region_size_get(ULONG block_size);                                                                                                          \
+UINT  _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);                                                 \
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2);
+
+#define TXM_MODULE_MANAGER_VERSION_ID   \
+CHAR                            _txm_module_manager_version_id[] =  \
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Module Cortex-A35/GNU Version 6.1.3 *";
+
+#endif
diff --git a/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c
new file mode 100644
index 00000000..1427d7fd
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c
@@ -0,0 +1,172 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#ifndef TXM_MODULE
+#define TXM_MODULE
+#endif
+
+#ifndef TX_SOURCE_CODE
+#define TX_SOURCE_CODE
+#endif
+
+
+/* Include necessary system files.  */
+
+#include "txm_module.h"
+#include "tx_thread.h"
+
+/* Define the global module entry pointer from the start thread of the module.  */
+
+TXM_MODULE_THREAD_ENTRY_INFO    *_txm_module_entry_info;
+
+
+/* Define the dispatch function pointer used in the module implementation.  */
+
+ALIGN_TYPE                      (*_txm_module_kernel_call_dispatcher)(ULONG type, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param3);
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_thread_shell_entry                   Cortex-A35/GNU     */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function calls the specified entry function of the thread.  It */
+/*    also provides a place for the thread's entry function to return.    */
+/*    If the thread returns, this function places the thread in a         */
+/*    "COMPLETED" state.                                                  */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                        Pointer to current thread         */
+/*    thread_info                       Pointer to thread entry info      */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_initialize            cstartup initialization           */
+/*    thread_entry                      Thread's entry function           */
+/*    tx_thread_resume                  Resume the module callback thread */
+/*    _txm_module_thread_system_suspend Module thread suspension routine  */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Initial thread stack frame                                          */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
+{
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+VOID            (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type);
+#endif
+
+
+    /* Perform any additional activities for tool or user purpose.  */
+    TX_THREAD_STARTED_EXTENSION(thread_ptr)
+
+    /* Determine if this is the start thread.  If so, we must prepare the module for
+       execution.  If not, simply skip the C startup code.  */
+    if (thread_info -> txm_module_thread_entry_info_start_thread)
+    {
+        /* Initialize the C library */
+        extern VOID _gcc_setup(TXM_MODULE_INSTANCE *);
+        _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address);
+
+        /* Save the entry info pointer, for later use.  */
+        _txm_module_entry_info =  thread_info;
+
+        /* Save the kernel function dispatch address. This is used to make all resident calls from
+           the module.  */
+        _txm_module_kernel_call_dispatcher =  thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
+
+        /* Ensure that we have a valid pointer.  */
+        while (!_txm_module_kernel_call_dispatcher)
+        {
+            /* Loop here, if an error is present getting the dispatch function pointer!
+               An error here typically indicates the resident portion of _tx_thread_schedule
+               is not supporting the trap to obtain the function pointer.   */
+        }
+        
+        /* Resume the module's callback thread, already created in the manager.  */
+        _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
+    }
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Pickup the entry/exit application callback routine.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has been entered!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
+    }
+#endif
+
+    /* Call current thread's entry function.  */
+    (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
+
+    /* Suspend thread with a "completed" state.  */
+
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Pickup the entry/exit application callback routine again.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has exited!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
+    }
+#endif
+
+    /* Call actual thread suspension routine.  */
+    _txm_module_thread_system_suspend(thread_ptr);
+
+#ifdef TX_SAFETY_CRITICAL
+
+    /* If we ever get here, raise safety critical exception.  */
+    TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
+#endif
+}
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S
new file mode 100644
index 00000000..787ae572
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S
@@ -0,0 +1,100 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_initialize_low_level                         Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for any low-level processor            */
+/*    initialization, including setting up interrupt vectors, setting     */
+/*    up a periodic timer interrupt source, saving the system stack       */
+/*    pointer for use in ISR processing later, and finding the first      */
+/*    available RAM memory address for tx_application_define.             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_initialize_low_level(VOID)
+// {
+    .global  _tx_initialize_low_level
+    .type    _tx_initialize_low_level, @function
+_tx_initialize_low_level:
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+
+    /* Save the system stack pointer.  */
+    // _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
+
+    LDR     x0, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    MOV     x1, sp                              // Pickup SP
+    SUB     x1, x1, #15                         //
+    BIC     x1, x1, #0xF                        // Get 16-bit alignment
+    STR     x1, [x0]                            // Store system stack
+
+    /* Save the first available memory address.  */
+    // _tx_initialize_unused_memory =  (VOID_PTR) __top_of_ram;
+
+    LDR     x0, =_tx_initialize_unused_memory   // Pickup address of unused memory ptr
+    LDR     x1, =__top_of_ram                   // Pickup unused memory address - A free
+                                                //   memory section must be setup after the
+                                                //   heap section.
+    STR     x1, [x0]                            // Store unused memory address
+
+    /* Done, return to caller.  */
+
+    RET                                         // Return to caller
+// }
+
+    .align 3
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..886df701
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S
@@ -0,0 +1,380 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* Include macros for modifying the wait list.  */
+#include "tx_thread_smp_protection_wait_list_macros.h"
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_restore                       Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function restores the interrupt context if it is processing a  */
+/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+/*    if no thread was running, the function returns to the scheduler.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling routine     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                  Interrupt Service Routines    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_restore(VOID)
+// {
+    .global _tx_thread_context_restore
+    .type   _tx_thread_context_restore, @function
+_tx_thread_context_restore:
+
+    /* Lockout interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR exit function to indicate an ISR is complete.  */
+
+    BL      _tx_execution_isr_exit              // Call the ISR exit function
+#endif
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x8, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x2, x8, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x8, x8, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x8, x8, x2, LSL #2                  // Calculate CPU ID
+#endif
+
+    /* Determine if interrupts are nested.  */
+    // if (--_tx_thread_system_state)
+    // {
+
+    LDR     x3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     w2, [x3, x8, LSL #2]                // Pickup system state
+    SUB     w2, w2, #1                          // Decrement the counter
+    STR     w2, [x3, x8, LSL #2]                // Store the counter 
+    CMP     w2, #0                              // Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      // If so, not a nested restore
+
+    /* Interrupts are nested.  */
+
+    /* Just recover the saved registers and return to the point of 
+       interrupt.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+    // }
+__tx_thread_not_nested_restore:
+
+    /* Determine if a thread was interrupted and no preemption is required.  */
+    // else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
+    //           || (_tx_thread_preempt_disable))
+    // {
+
+    LDR     x1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     x0, [x1, x8, LSL #3]                // Pickup actual current thread pointer
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     // Yes, idle system was interrupted
+    LDR     x3, =_tx_thread_execute_ptr         // Pickup address of execute thread ptr
+    LDR     x2, [x3, x8, LSL #3]                // Pickup actual execute thread pointer
+    CMP     x0, x2                              // Is the same thread highest priority?
+    BEQ     __tx_thread_no_preempt_restore      // Same thread in the execute list, 
+                                                //   no preemption needs to happen
+    LDR     x3, =_tx_thread_smp_protection      // Build address to protection structure
+    LDR     w3, [x3, #4]                        // Pickup the owning core
+    CMP     w3, w8                              // Is it this core?
+    BNE     __tx_thread_preempt_restore         // No, proceed to preempt thread
+
+    LDR     x3, =_tx_thread_preempt_disable     // Pickup preempt disable address
+    LDR     w2, [x3, #0]                        // Pickup actual preempt disable flag
+    CMP     w2, #0                              // Is it set?
+    BEQ     __tx_thread_preempt_restore         // No, okay to preempt this thread
+
+__tx_thread_no_preempt_restore:
+
+    /* Restore interrupted thread or ISR.  */
+
+    /* Pickup the saved stack pointer.  */
+    // sp =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+
+    LDR     x4, [x0, #8]                        // Switch to thread stack pointer
+    MOV     sp, x4                              //
+
+   /* Recover the saved context and return to the point of interrupt.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+    // }
+    // else
+    // {
+__tx_thread_preempt_restore:
+
+    /* Was the thread being preempted waiting for the lock?  */
+    // if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
+    // {
+
+    LDR     x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
+    LDR     w3, [x2, x8, LSL #2]                // Load waiting value for this core
+    CMP     w3, #0
+    BEQ     _nobody_waiting_for_lock            // Is the core waiting for the lock?
+
+    /* Do we not have the lock? This means the ISR never got the inter-core lock.  */
+    // if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
+    // {
+
+    LDR     x2, =_tx_thread_smp_protection      // Load address of protection structure
+    LDR     w3, [x2, #4]                        // Pickup the owning core
+    CMP     w8, w3                              // Compare our core to the owning core
+    BEQ     _this_core_has_lock                 // Do we have the lock?
+
+    /* We don't have the lock. This core should be in the list. Remove it.  */
+    // _tx_thread_smp_protect_wait_list_remove(this_core);
+
+    _tx_thread_smp_protect_wait_list_remove     // Call macro to remove core from the list
+    B       _nobody_waiting_for_lock            // Leave
+
+    // }
+    // else
+    // {
+    /* We have the lock. This means the ISR got the inter-core lock, but
+       never released it because it saw that there was someone waiting.
+       Note this core is not in the list.  */
+
+_this_core_has_lock:
+
+    /* We're no longer waiting. Note that this should be zero since this happens during thread preemption.  */
+    // _tx_thread_smp_protect_wait_counts[core]--;
+
+    LDR     x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
+    LDR     w3, [x2, x8, LSL #2]                // Load waiting value for this core
+    SUB     w3, w3, #1                          // Decrement waiting value. Should be zero now
+    STR     w3, [x2, x8, LSL #2]                // Store new waiting value
+
+    /* Now release the inter-core lock.  */
+
+    /* Set protected core as invalid.  */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
+
+    LDR     x2, =_tx_thread_smp_protection      // Load address of protection structure
+    MOV     w3, #0xFFFFFFFF                     // Build invalid value
+    STR     w3, [x2, #4]                        // Mark the protected core as invalid
+    DMB     ISH                                 // Ensure that accesses to shared resource have completed
+
+    /* Release protection.  */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
+
+    MOV     w3, #0                              // Build release protection value
+    STR     w3, [x2, #0]                        // Release the protection
+    DSB     ISH                                 // To ensure update of the protection occurs before other CPUs awake
+
+    /* Wake up waiting processors. Note interrupts are already enabled.  */
+
+#ifdef TX_ENABLE_WFE
+    SEV                                         // Send event to other CPUs
+#endif
+
+      // }
+    // }
+
+_nobody_waiting_for_lock:
+
+    LDR     x4, [x0, #8]                        // Switch to thread stack pointer
+    MOV     sp, x4                              //
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+    STP     x20, x21, [sp, #-16]!               // Save x20, x21
+    STP     x22, x23, [sp, #-16]!               // Save x22, x23
+    STP     x24, x25, [sp, #-16]!               // Save x24, x25
+    STP     x26, x27, [sp, #-16]!               // Save x26, x27
+    STP     x28, x29, [sp, #-16]!               // Save x28, x29
+#ifdef ENABLE_ARM_FP
+    LDR     w3, [x0, #268]                      // Pickup FP enable flag
+    CMP     w3, #0                              // Is FP enabled?
+    BEQ     _skip_fp_save                       // No, skip FP save
+    STP     q0,  q1,  [sp, #-32]!               // Save q0, q1
+    STP     q2,  q3,  [sp, #-32]!               // Save q2, q3
+    STP     q4,  q5,  [sp, #-32]!               // Save q4, q5
+    STP     q6,  q7,  [sp, #-32]!               // Save q6, q7
+    STP     q8,  q9,  [sp, #-32]!               // Save q8, q9
+    STP     q10, q11, [sp, #-32]!               // Save q10, q11
+    STP     q12, q13, [sp, #-32]!               // Save q12, q13
+    STP     q14, q15, [sp, #-32]!               // Save q14, q15
+    STP     q16, q17, [sp, #-32]!               // Save q16, q17
+    STP     q18, q19, [sp, #-32]!               // Save q18, q19
+    STP     q20, q21, [sp, #-32]!               // Save q20, q21
+    STP     q22, q23, [sp, #-32]!               // Save q22, q23
+    STP     q24, q25, [sp, #-32]!               // Save q24, q25
+    STP     q26, q27, [sp, #-32]!               // Save q26, q27
+    STP     q28, q29, [sp, #-32]!               // Save q28, q29
+    STP     q30, q31, [sp, #-32]!               // Save q30, q31
+    MRS     x2, FPSR                            // Pickup FPSR
+    MRS     x3, FPCR                            // Pickup FPCR
+    STP     x2, x3, [sp, #-16]!                 // Save FPSR, FPCR
+_skip_fp_save:
+#endif
+    STP     x4, x5, [sp, #-16]!                 // Save x4 (SPSR_EL3), x5 (ELR_E3)
+
+    MOV     x3, sp                              // Move sp into x3
+    STR     x3, [x0, #8]                        // Save stack pointer in thread control
+                                                //   block
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, x8, LSL #3]                // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+
+    /* Save the remaining time-slice and disable it.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    LDR     x3, =_tx_timer_time_slice           // Pickup time-slice variable address
+    LDR     w2, [x3, x8, LSL #2]                // Pickup time-slice
+    CMP     w2, #0                              // Is it active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save it
+
+        /* _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+        _tx_timer_time_slice =  0;  */
+
+    STR     w2, [x0, #36]                       // Save thread's time-slice
+    MOV     w2, #0                              // Clear value
+    STR     w2, [x3, x8, LSL #2]                // Disable global time-slice flag
+
+    // }
+__tx_thread_dont_save_ts:
+
+
+    /* Clear the current task pointer.  */
+    // _tx_thread_current_ptr =  TX_NULL;
+
+    MOV     x2, #0                              // NULL value
+    STR     x2, [x1, x8, LSL #3]                // Clear current thread pointer
+
+    /* Set bit indicating this thread is ready for execution.  */
+
+    MOV     x2, #1                              // Build ready flag
+    STR     w2, [x0, #260]                      // Set thread's ready flag
+    DMB     ISH                                 // Ensure that accesses to shared resource have completed
+
+    /* Return to the scheduler.  */
+    // _tx_thread_schedule();
+
+    // }
+
+__tx_thread_idle_system_restore:
+
+    /* Just return back to the scheduler!  */
+
+    LDR    x1, =_tx_thread_schedule             // Build address for _tx_thread_schedule
+#ifdef EL1
+    MSR    ELR_EL1, x1                          // Setup point of interrupt
+//    MOV    x1, #0x4                             // Setup EL1 return
+//    MSR    spsr_el1, x1                         // Move into SPSR
+#else
+#ifdef EL2
+    MSR    ELR_EL2, x1                          // Setup point of interrupt
+//    MOV    x1, #0x8                             // Setup EL2 return
+//    MSR    spsr_el2, x1                         // Move into SPSR
+#else
+    MSR    ELR_EL3, x1                          // Setup point of interrupt
+//    MOV    x1, #0xC                             // Setup EL3 return
+//    MSR    spsr_el3, x1                         // Move into SPSR
+#endif
+#endif
+    ERET                                        // Return to scheduler
+// }
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S
new file mode 100644
index 00000000..b0840bf4
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S
@@ -0,0 +1,238 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_save                          Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves the context of an executing thread in the       */
+/*    beginning of interrupt processing.  The function also ensures that  */
+/*    the system stack is used upon return to the calling ISR.            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_save(VOID)
+// {
+    .global _tx_thread_context_save
+    .type   _tx_thread_context_save, @function
+_tx_thread_context_save:
+
+    /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked
+       out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, 
+       and all other registers are intact.  */
+
+    /* Check for a nested interrupt condition.  */
+    // if (_tx_thread_system_state++)
+    // {
+
+    STP     x0, x1, [sp, #-16]!                 // Save x0, x1
+    STP     x2, x3, [sp, #-16]!                 // Save x2, x3
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x2, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x2, LSL #2                  // Calculate CPU ID
+#endif
+
+    LDR     x3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     w2, [x3, x1, LSL #2]                // Pickup system state
+    CMP     w2, #0                              // Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         // Yes, not a nested context save
+
+    /* Nested interrupt condition.  */
+
+    ADD     w2, w2, #1                          // Increment the nested interrupt counter
+    STR     w2, [x3, x1, LSL #2]                // Store it back in the variable
+
+   /* Save the rest of the scratch registers on the stack and return to the
+      calling ISR.  */
+
+    STP     x4, x5, [sp, #-16]!                 // Save x4, x5
+    STP     x6, x7, [sp, #-16]!                 // Save x6, x7
+    STP     x8, x9, [sp, #-16]!                 // Save x8, x9
+    STP     x10, x11, [sp, #-16]!               // Save x10, x11
+    STP     x12, x13, [sp, #-16]!               // Save x12, x13
+    STP     x14, x15, [sp, #-16]!               // Save x14, x15
+    STP     x16, x17, [sp, #-16]!               // Save x16, x17
+    STP     x18, x19, [sp, #-16]!               // Save x18, x19
+#ifdef EL1
+    MRS     x0, SPSR_EL1                        // Pickup SPSR
+    MRS     x1, ELR_EL1                         // Pickup ELR (point of interrupt)
+#else
+#ifdef EL2
+    MRS     x0, SPSR_EL2                        // Pickup SPSR
+    MRS     x1, ELR_EL2                         // Pickup ELR (point of interrupt)
+#else
+    MRS     x0, SPSR_EL3                        // Pickup SPSR
+    MRS     x1, ELR_EL3                         // Pickup ELR (point of interrupt)
+#endif
+#endif
+    STP     x0, x1, [sp, #-16]!                 // Save SPSR, ELR
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    /* Return to the ISR.  */
+
+    RET                                         // Return to ISR
+
+__tx_thread_not_nested_save:
+    // }
+
+    /* Otherwise, not nested, check to see if a thread was running.  */
+    // else if (_tx_thread_current_ptr)
+    // {
+
+    ADD     w2, w2, #1                          // Increment the interrupt counter
+    STR     w2, [x3, x1, LSL #2]                // Store it back in the variable
+    LDR     x2, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     x0, [x2, x1, LSL #3]                // Pickup current thread pointer
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_save        // If so, interrupt occurred in 
+                                                //   scheduling loop - nothing needs saving!
+
+    /* Save minimal context of interrupted thread.  */
+
+    STP     x4, x5, [sp, #-16]!                 // Save x4, x5
+    STP     x6, x7, [sp, #-16]!                 // Save x6, x7
+    STP     x8, x9, [sp, #-16]!                 // Save x8, x9
+    STP     x10, x11, [sp, #-16]!               // Save x10, x11
+    STP     x12, x13, [sp, #-16]!               // Save x12, x13
+    STP     x14, x15, [sp, #-16]!               // Save x14, x15
+    STP     x16, x17, [sp, #-16]!               // Save x16, x17
+    STP     x18, x19, [sp, #-16]!               // Save x18, x19
+#ifdef EL1
+    MRS     x4, SPSR_EL1                        // Pickup SPSR
+    MRS     x5, ELR_EL1                         // Pickup ELR (point of interrupt)
+#else
+#ifdef EL2
+    MRS     x4, SPSR_EL2                        // Pickup SPSR
+    MRS     x5, ELR_EL2                         // Pickup ELR (point of interrupt)
+#else
+    MRS     x4, SPSR_EL3                        // Pickup SPSR
+    MRS     x5, ELR_EL3                         // Pickup ELR (point of interrupt)
+#endif
+#endif
+    STP     x4, x5, [sp, #-16]!                 // Save SPSR, ELR
+
+    /* Save the current stack pointer in the thread's control block.  */
+    // _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+
+    MOV     x4, sp                              //
+    STR     x4, [x0, #8]                        // Save thread stack pointer
+
+    /* Switch to the system stack.  */
+    // sp =  _tx_thread_system_stack_ptr
+
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x2, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x2, LSL #2                  // Calculate CPU ID
+#endif
+
+    LDR     x4, [x3, x1, LSL #3]                // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    RET                                         // Return to caller
+
+    // }
+    // else
+    // {
+
+__tx_thread_idle_system_save:
+
+    /* Interrupt occurred in the scheduling loop.  */
+
+    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+       processing.  */
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    STP     x29, x30, [sp, #-16]!               // Save x29, x30
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+#endif
+
+    ADD     sp, sp, #48                         // Recover saved registers
+    RET                                         // Continue IRQ processing  
+
+    // }
+// } 
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c
new file mode 100644
index 00000000..df31e862
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c
@@ -0,0 +1,94 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fp_disable                            Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function disables the FP for the currently executing thread.   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_fp_disable(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+ULONG       system_state;
+
+
+    /* Pickup the current thread pointer.  */
+    TX_THREAD_GET_CURRENT(thread_ptr);
+
+    /* Get the system state.  */
+    system_state =  TX_THREAD_GET_SYSTEM_STATE();
+
+    /* Make sure it is not NULL. */
+    if (thread_ptr != TX_NULL)
+    {
+        
+        /* Thread is running... make sure the call is from the thread context.  */
+        if (system_state == 0)
+        {
+        
+            /* Yes, now set the FP enable flag to false in the TX_THREAD structure.  */
+            thread_ptr -> tx_thread_fp_enable =  TX_FALSE;
+        }
+    }
+}
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c
new file mode 100644
index 00000000..e556104d
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c
@@ -0,0 +1,94 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fp_enable                             Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function enabled the FP for the currently executing thread.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_fp_enable(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+ULONG       system_state;
+
+
+    /* Pickup the current thread pointer.  */
+    TX_THREAD_GET_CURRENT(thread_ptr);
+
+    /* Get the system state.  */
+    system_state =  TX_THREAD_GET_SYSTEM_STATE();
+
+    /* Make sure it is not NULL. */
+    if (thread_ptr != TX_NULL)
+    {
+        
+        /* Thread is running... make sure the call is from the thread context.  */
+        if (system_state == 0)
+        {
+        
+            /* Yes, now setup the FP enable flag in the TX_THREAD structure.  */
+            thread_ptr -> tx_thread_fp_enable =  TX_TRUE;
+        }
+    }
+}
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..65daf40e
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S
@@ -0,0 +1,80 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_control                     Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for changing the interrupt lockout     */
+/*    posture of the system.                                              */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    new_posture                           New interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_control(UINT new_posture)
+// {
+    .global  _tx_thread_interrupt_control
+    .type    _tx_thread_interrupt_control, @function
+_tx_thread_interrupt_control:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     x1, DAIF                            // Pickup current interrupt posture
+
+    /* Apply the new interrupt posture.  */
+
+    MSR     DAIF, x0                            // Set new interrupt posture
+    MOV     x0, x1                              // Setup return value
+    RET                                         // Return to caller
+// }
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S
new file mode 100644
index 00000000..f924f7e7
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S
@@ -0,0 +1,78 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_disable                     Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for disabling interrupts               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_disable(void)
+// {
+    .global _tx_thread_interrupt_disable
+    .type   _tx_thread_interrupt_disable, @function
+_tx_thread_interrupt_disable:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     x0, DAIF                            // Pickup current interrupt lockout posture
+
+    /* Mask interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    RET                                         // Return to caller
+// }
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S
new file mode 100644
index 00000000..789e7238
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S
@@ -0,0 +1,75 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_restore                     Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for restoring interrupts to the state  */
+/*    returned by a previous _tx_thread_interrupt_disable call.           */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_restore(UINT old_posture)
+// {
+    .global _tx_thread_interrupt_restore
+    .type   _tx_thread_interrupt_restore, @function
+_tx_thread_interrupt_restore:
+
+    /* Restore the old interrupt posture.  */
+
+    MSR     DAIF, x0                            // Setup the old posture
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S
new file mode 100644
index 00000000..3fbcc856
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S
@@ -0,0 +1,294 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_schedule                              Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function waits for a thread control block pointer to appear in */
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+/*    in the variable, the corresponding thread is resumed.               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+/*    _tx_thread_system_return             Return to system from thread   */
+/*    _tx_thread_context_restore           Restore thread's context       */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_schedule(VOID)
+// {
+    .global _tx_thread_schedule
+    .type   _tx_thread_schedule, @function
+_tx_thread_schedule:
+
+    /* Enable interrupts.  */
+
+    MSR     DAIFClr, 0x3                        // Enable interrupts
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x20, MPIDR_EL1                      // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x1, x20, #8, #8                     // Isolate cluster ID
+#endif
+    UBFX    x20, x20, #0, #8                    // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x20, x20, x1, LSL #2                // Calculate CPU ID
+#endif
+
+    /* Wait for a thread to execute.  */
+    // do
+    // {
+
+    LDR     x1, =_tx_thread_execute_ptr         // Address of thread execute ptr
+
+#ifdef TX_ENABLE_WFI
+__tx_thread_schedule_loop:
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    LDR     x0, [x1, x20, LSL #3]               // Pickup next thread to execute
+    CMP     x0, #0                              // Is it NULL?
+    BNE     _tx_thread_schedule_thread          //
+    MSR     DAIFClr, 0x3                        // Enable interrupts
+    WFI                                         //
+    B       __tx_thread_schedule_loop           // Keep looking for a thread
+_tx_thread_schedule_thread:
+#else
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    LDR     x0, [x1, x20, LSL #3]               // Pickup next thread to execute
+    CMP     x0, #0                              // Is it NULL?
+    BEQ     _tx_thread_schedule                 // Keep looking for a thread
+#endif
+
+    // }
+    // while(_tx_thread_execute_ptr == TX_NULL);
+
+    /* Get the lock for accessing the thread's ready bit.  */
+
+    MOV     w2, #280                            // Build offset to the lock
+    ADD     x2, x0, x2                          // Get the address to the lock
+    LDAXR   w3, [x2]                            // Pickup the lock value
+    CMP     w3, #0                              // Check if it's available
+    BNE     _tx_thread_schedule                 // No, lock not available
+    MOV     w3, #1                              // Build the lock set value
+    STXR    w4, w3, [x2]                        // Try to get the lock
+    CMP     w4, #0                              // Check if we got the lock
+    BNE     _tx_thread_schedule                 // No, another core got it first
+    DMB     ISH                                 // Ensure write to lock completes
+
+    /* Now make sure the thread's ready bit is set.  */
+
+    LDR     w3, [x0, #260]                      // Pickup the thread ready bit
+    CMP     w3, #0                              // Is it set?
+    BNE     _tx_thread_ready_for_execution      // Yes, schedule the thread
+
+    /* The ready bit isn't set. Release the lock and jump back to the scheduler.  */
+
+    MOV     w3, #0                              // Build clear value
+    STR     w3, [x2]                            // Release the lock
+    DMB     ISH                                 // Ensure write to lock completes
+    B       _tx_thread_schedule                 // Jump back to the scheduler
+
+_tx_thread_ready_for_execution:
+
+    /* We have a thread to execute. */
+
+    /* Clear the ready bit and release the lock.  */
+
+    MOV     w3, #0                              // Build clear value
+    STR     w3, [x0, #260]                      // Store it back in the thread control block
+    DMB     ISH
+    MOV     w3, #0                              // Build clear value for the lock
+    STR     w3, [x2]                            // Release the lock
+    DMB     ISH
+
+    /* Setup the current thread pointer.  */
+    // _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+
+    LDR     x2, =_tx_thread_current_ptr         // Pickup address of current thread
+    STR     x0, [x2, x20, LSL #3]               // Setup current thread pointer
+
+    LDR     x1, [x1, x20, LSL #3]               // Reload the execute pointer
+    CMP     w0, w1                              // Did it change?
+    BEQ     _execute_pointer_did_not_change     // If not, skip handling
+
+    /* In the time between reading the execute pointer and assigning
+       it to the current pointer, the execute pointer was changed by
+       some external code.  If the current pointer was still null when
+       the external code checked if a core preempt was necessary, then
+       it wouldn't have done it and a preemption will be missed.  To
+       handle this, undo some things and jump back to the scheduler so
+       it can schedule the new thread.  */
+
+    MOV     w1, #0                              // Build clear value
+    STR     x1, [x2, x20, LSL #3]               // Clear current thread pointer
+
+    MOV     w1, #1                              // Build set value
+    STR     w1, [x0, #260]                      // Re-set the ready bit
+    DMB     ISH                                 //
+
+    B       _tx_thread_schedule                 // Jump back to the scheduler to schedule the new thread
+
+_execute_pointer_did_not_change:
+    /* Increment the run count for this thread.  */
+    // _tx_thread_current_ptr -> tx_thread_run_count++;
+
+    LDR     w2, [x0, #4]                        // Pickup run counter
+    LDR     w3, [x0, #36]                       // Pickup time-slice for this thread
+    ADD     w2, w2, #1                          // Increment thread run-counter
+    STR     w2, [x0, #4]                        // Store the new run counter
+
+    /* Setup time-slice, if present.  */
+    // _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+
+    LDR     x2, =_tx_timer_time_slice           // Pickup address of time slice
+                                                //   variable
+    LDR     x4, [x0, #8]                        // Switch stack pointers
+    MOV     sp, x4                              //
+    STR     w3, [x2, x20, LSL #2]               // Setup time-slice
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread entry function to indicate the thread is executing.  */
+
+    MOV     x19, x0                             // Save x0
+    BL      _tx_execution_thread_enter          // Call the thread execution enter function
+    MOV     x0, x19                             // Restore x0
+#endif
+
+    /* Switch to the thread's stack.  */
+    // sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+
+    /* Determine if an interrupt frame or a synchronous task suspension frame
+       is present.  */
+
+    LDP     x4, x5, [sp], #16                   // Pickup saved SPSR/DAIF and ELR_EL1
+    CMP     x5, #0                              // Check for synchronous context switch (ELR_EL1 = NULL)
+    BEQ     _tx_solicited_return
+#ifdef EL1
+    MSR     SPSR_EL1, x4                        // Setup SPSR for return
+    MSR     ELR_EL1, x5                         // Setup point of interrupt
+#else
+#ifdef EL2
+    MSR     SPSR_EL2, x4                        // Setup SPSR for return
+    MSR     ELR_EL2, x5                         // Setup point of interrupt
+#else
+    MSR     SPSR_EL3, x4                        // Setup SPSR for return
+    MSR     ELR_EL3, x5                         // Setup point of interrupt
+#endif
+#endif
+#ifdef ENABLE_ARM_FP
+    LDR     w1, [x0, #268]                      // Pickup FP enable flag
+    CMP     w1, #0                              // Is FP enabled?
+    BEQ     _skip_interrupt_fp_restore          // No, skip FP restore
+    LDP     x0, x1,   [sp], #16                 // Pickup FPSR, FPCR
+    MSR     FPSR, x0                            // Recover FPSR
+    MSR     FPCR, x1                            // Recover FPCR
+    LDP     q30, q31, [sp], #32                 // Recover q30, q31
+    LDP     q28, q29, [sp], #32                 // Recover q28, q29
+    LDP     q26, q27, [sp], #32                 // Recover q26, q27
+    LDP     q24, q25, [sp], #32                 // Recover q24, q25
+    LDP     q22, q23, [sp], #32                 // Recover q22, q23
+    LDP     q20, q21, [sp], #32                 // Recover q20, q21
+    LDP     q18, q19, [sp], #32                 // Recover q18, q19
+    LDP     q16, q17, [sp], #32                 // Recover q16, q17
+    LDP     q14, q15, [sp], #32                 // Recover q14, q15
+    LDP     q12, q13, [sp], #32                 // Recover q12, q13
+    LDP     q10, q11, [sp], #32                 // Recover q10, q11
+    LDP     q8,  q9,  [sp], #32                 // Recover q8, q9
+    LDP     q6,  q7,  [sp], #32                 // Recover q6, q7
+    LDP     q4,  q5,  [sp], #32                 // Recover q4, q5
+    LDP     q2,  q3,  [sp], #32                 // Recover q2, q3
+    LDP     q0,  q1,  [sp], #32                 // Recover q0, q1
+_skip_interrupt_fp_restore:
+#endif
+    LDP     x28, x29, [sp], #16                 // Recover x28
+    LDP     x26, x27, [sp], #16                 // Recover x26, x27
+    LDP     x24, x25, [sp], #16                 // Recover x24, x25
+    LDP     x22, x23, [sp], #16                 // Recover x22, x23
+    LDP     x20, x21, [sp], #16                 // Recover x20, x21
+    LDP     x18, x19, [sp], #16                 // Recover x18, x19
+    LDP     x16, x17, [sp], #16                 // Recover x16, x17
+    LDP     x14, x15, [sp], #16                 // Recover x14, x15
+    LDP     x12, x13, [sp], #16                 // Recover x12, x13
+    LDP     x10, x11, [sp], #16                 // Recover x10, x11
+    LDP     x8,  x9,  [sp], #16                 // Recover x8, x9
+    LDP     x6,  x7,  [sp], #16                 // Recover x6, x7
+    LDP     x4,  x5,  [sp], #16                 // Recover x4, x5
+    LDP     x2,  x3,  [sp], #16                 // Recover x2, x3
+    LDP     x0,  x1,  [sp], #16                 // Recover x0, x1
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    ERET                                        // Return to point of interrupt
+
+_tx_solicited_return:
+
+#ifdef ENABLE_ARM_FP
+    LDR     w1, [x0, #268]                      // Pickup FP enable flag
+    CMP     w1, #0                              // Is FP enabled?
+    BEQ     _skip_solicited_fp_restore          // No, skip FP restore
+    LDP     x0, x1,   [sp], #16                 // Pickup FPSR, FPCR
+    MSR     FPSR, x0                            // Recover FPSR
+    MSR     FPCR, x1                            // Recover FPCR
+    LDP     q14, q15, [sp], #32                 // Recover q14, q15
+    LDP     q12, q13, [sp], #32                 // Recover q12, q13
+    LDP     q10, q11, [sp], #32                 // Recover q10, q11
+    LDP     q8,  q9,  [sp], #32                 // Recover q8, q9
+_skip_solicited_fp_restore:
+#endif
+    LDP     x27, x28, [sp], #16                 // Recover x27, x28
+    LDP     x25, x26, [sp], #16                 // Recover x25, x26
+    LDP     x23, x24, [sp], #16                 // Recover x23, x24
+    LDP     x21, x22, [sp], #16                 // Recover x21, x22
+    LDP     x19, x20, [sp], #16                 // Recover x19, x20
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    MSR     DAIF, x4                            // Recover DAIF
+    RET                                         // Return to caller
+// }
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S
new file mode 100644
index 00000000..a2dfb913
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S
@@ -0,0 +1,74 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_core_get                          Cortex-A35-SMP/GNU */
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function gets the currently running core number and returns it.*/
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    Core ID                                                             */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_core_get
+    .type    _tx_thread_smp_core_get, @function
+_tx_thread_smp_core_get:
+    MRS     x0, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x1, x0, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x0, x0, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x0, x0, x1, LSL #2                  // Calculate CPU ID
+#endif
+    RET
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S
new file mode 100644
index 00000000..27c25e9d
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S
@@ -0,0 +1,77 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define ICC_SGI1R_EL1 S3_0_C12_C11_5
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_core_preempt                      Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function preempts the specified core in situations where the   */
+/*    thread corresponding to this core is no longer ready or when the    */
+/*    core must be used for a higher-priority thread. If the specified is */
+/*    the current core, this processing is skipped since the will give up */
+/*    control subsequently on its own.                                    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    core                                  The core to preempt           */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_core_preempt
+    .type    _tx_thread_smp_core_preempt, @function
+_tx_thread_smp_core_preempt:
+    DSB ISH
+    MOV x2, #0x1                                //
+    LSL x2, x2, x0                              // Shift by the core ID
+    MSR ICC_SGI1R_EL1, x2                       // Issue inter-core interrupt
+    RET
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S
new file mode 100644
index 00000000..e88dd96e
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S
@@ -0,0 +1,80 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_current_state_get                 Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is gets the current state of the calling core.        */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_current_state_get
+    .type    _tx_thread_smp_current_state_get, @function
+_tx_thread_smp_current_state_get:
+
+    MRS     x1, DAIF                            // Pickup current interrupt posture
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    MRS     x2, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x2, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x2, x2, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x2, x2, x3, LSL #2                  // Calculate CPU ID
+#endif
+    LDR     x3, =_tx_thread_system_state        // Pickup the base of the current system state array
+    LDR     w0, [x3, x2, LSL #2]                // Pickup the current system state for this core
+    MSR     DAIF, x1                            // Restore interrupt posture
+    RET
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S
new file mode 100644
index 00000000..5db0890d
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S
@@ -0,0 +1,80 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_current_thread_get                Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is gets the current thread of the calling core.       */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_current_thread_get
+    .type    _tx_thread_smp_current_thread_get, @function
+_tx_thread_smp_current_thread_get:
+
+    MRS     x1, DAIF                            // Pickup current interrupt posture
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    MRS     x2, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x2, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x2, x2, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x2, x2, x3, LSL #2                  // Calculate CPU ID
+#endif
+    LDR     x3, =_tx_thread_current_ptr         // Pickup the base of the current thread pointer array
+    LDR     x0, [x3, x2, LSL #3]                // Pickup the current thread pointer for this core
+    MSR     DAIF, x1                            // Restore interrupt posture
+    RET
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S
new file mode 100644
index 00000000..51dbb214
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S
@@ -0,0 +1,130 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_initialize_wait                   Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is the place where additional cores wait until        */
+/*    initialization is complete before they enter the thread scheduling  */
+/*    loop.                                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling loop        */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Hardware                                                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_initialize_wait
+    .type    _tx_thread_smp_initialize_wait, @function
+_tx_thread_smp_initialize_wait:
+
+    /* Lockout interrupts.  */
+
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    /* Pickup the Core ID.   */
+
+    MRS     x2, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x2, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x2, x2, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x2, x2, x3, LSL #2                  // Calculate CPU ID
+#endif
+
+    /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release 
+       flag.  */
+
+    LDR     w1, =0xF0F0F0F0                     // Build TX_INITIALIZE_IN_PROGRESS flag
+    LDR     x3, =_tx_thread_system_state        // Pickup the base of the current system state array
+wait_for_initialize:
+    LDR     w0, [x3, x2, LSL #2]                // Pickup the current system state for this core
+    CMP     w0, w1                              // Make sure the TX_INITIALIZE_IN_PROGRESS flag is set
+    BNE     wait_for_initialize                 // Not equal, just spin here
+
+    /* Save the system stack pointer for this core.  */
+    
+    LDR     x0, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    MOV     x1, sp                              // Pickup SP
+    SUB     x1, x1, #15                         //
+    BIC     x1, x1, #0xF                        // Get 16-bit alignment
+    STR     x1, [x0, x2, LSL #3]                // Store system stack pointer
+
+
+    /* Pickup the release cores flag.  */
+    
+    LDR     x4, =_tx_thread_smp_release_cores_flag  // Build address of release cores flag
+wait_for_release:    
+    LDR     w0, [x4, #0]                        // Pickup the flag
+    CMP     w0, #0                              // Is it set?
+    BEQ     wait_for_release                    // Wait for the flag to be set
+    
+    /* Core 0 has released this core.  */
+    
+    /* Clear this core's system state variable.  */
+    
+    MOV     x0, #0                              // Build clear value
+    STR     w0, [x3, x2, LSL #2]                // Set the current system state for this core to zero
+    
+    /* Now wait for core 0 to finish it's initialization.  */
+    
+core_0_wait_loop:
+    LDR     w0, [x3, #0]                        // Pickup the current system state for core 0
+    CMP     w0, #0                              // Is it 0?
+    BNE     core_0_wait_loop                    // No, keep waiting for core 0 to finish its initialization
+    
+    /* Initialization is complete, enter the scheduling loop!  */
+    
+    B       _tx_thread_schedule                 // Enter the scheduling loop for this core    
+
+    RET
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S
new file mode 100644
index 00000000..b96b448e
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S
@@ -0,0 +1,68 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_low_level_initialize              Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function performs low-level initialization of the booting      */
+/*    core.                                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    number_of_cores                       Number of cores               */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_high_level            ThreadX high-level init        */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_low_level_initialize
+    .type    _tx_thread_smp_low_level_initialize, @function
+_tx_thread_smp_low_level_initialize:
+
+    RET
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S
new file mode 100644
index 00000000..cdb23c0b
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S
@@ -0,0 +1,352 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* Include macros for modifying the wait list.  */
+#include "tx_thread_smp_protection_wait_list_macros.h"
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_protect                           Cortex-A35-SMP/GNU */
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function gets protection for running inside the ThreadX        */
+/*    source. This is acomplished by a combination of a test-and-set      */
+/*    flag and periodically disabling interrupts.                         */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    Previous Status Register                                            */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_protect
+    .type    _tx_thread_smp_protect, @function
+_tx_thread_smp_protect:
+
+    /* Disable interrupts so we don't get preempted.  */
+
+    MRS     x0, DAIF                            // Pickup current interrupt posture
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x7, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x7, LSL #2                  // Calculate CPU ID
+#endif
+
+    /* Do we already have protection?  */
+    // if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
+    // {
+
+    LDR     x2, =_tx_thread_smp_protection      // Build address to protection structure
+    LDR     w3, [x2, #4]                        // Pickup the owning core
+    CMP     w1, w3                              // Is it not this core?
+    BNE     _protection_not_owned               // No, the protection is not already owned
+
+    /* We already have protection. */
+
+    /* Increment the protection count. */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_count++;
+
+    LDR     w3, [x2, #8]                        // Pickup ownership count
+    ADD     w3, w3, #1                          // Increment ownership count
+    STR     w3, [x2, #8]                        // Store ownership count
+    DMB     ISH
+
+    B       _return
+
+_protection_not_owned:
+
+    /* Is the lock available?  */
+    // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
+    // {
+
+    LDAXR   w3, [x2, #0]                        // Pickup the protection flag
+    CMP     w3, #0
+    BNE     _start_waiting                      // No, protection not available
+
+    /* Is the list empty?  */
+    // if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail)
+    // {
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_head
+    LDR     w3, [x3]
+    LDR     x4, =_tx_thread_smp_protect_wait_list_tail
+    LDR     w4, [x4]
+    CMP     w3, w4
+    BNE     _list_not_empty
+
+    /* Try to get the lock.  */
+    // if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS)
+    // {
+
+    MOV     w3, #1                              // Build lock value
+    STXR    w4, w3, [x2, #0]                    // Attempt to get the protection
+    CMP     w4, #0
+    BNE     _start_waiting                      // Did it fail?
+
+    /* We got the lock! */
+    // _tx_thread_smp_protect_lock_got();
+
+    DMB     ISH                                 // Ensure write to protection finishes
+    _tx_thread_smp_protect_lock_got             // Call the lock got function
+
+    B       _return
+
+_list_not_empty:
+
+    /* Are we at the front of the list?  */
+    // if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
+    // {
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
+    LDR     w3, [x3]                            // Get the value of the head
+    LDR     x4, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    LDR     w4, [x4, x3, LSL #2]                // Get the value at the head index
+
+    CMP     w1, w4
+    BNE     _start_waiting
+
+    /* Is the lock still available?  */
+    // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
+    // {
+
+    LDR     w3, [x2, #0]                        // Pickup the protection flag
+    CMP     w3, #0
+    BNE     _start_waiting                      // No, protection not available
+
+    /* Get the lock.  */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
+
+    MOV     w3, #1                              // Build lock value
+    STR     w3, [x2, #0]                        // Store lock value
+    DMB     ISH                                 //
+
+    /* Got the lock.  */
+    // _tx_thread_smp_protect_lock_got();
+
+    _tx_thread_smp_protect_lock_got
+
+    /* Remove this core from the wait list.  */
+    // _tx_thread_smp_protect_remove_from_front_of_list();
+
+    _tx_thread_smp_protect_remove_from_front_of_list
+
+    B       _return
+
+_start_waiting:
+
+    /* For one reason or another, we didn't get the lock.  */
+
+    /* Increment wait count. */
+    // _tx_thread_smp_protect_wait_counts[this_core]++;
+
+    LDR     x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
+    LDR     w4, [x3, x1, LSL #2]                // Load waiting value for this core
+    ADD     w4, w4, #1                          // Increment wait value
+    STR     w4, [x3, x1, LSL #2]                // Store new wait value
+
+    /* Have we not added ourselves to the list yet? */
+    // if (_tx_thread_smp_protect_wait_counts[this_core] == 1)
+    // {
+
+    CMP     w4, #1
+    BNE     _already_in_list0                   // Is this core already waiting?
+
+    /* Add ourselves to the list.  */
+    // _tx_thread_smp_protect_wait_list_add(this_core);
+
+    _tx_thread_smp_protect_wait_list_add        // Call macro to add ourselves to the list
+
+    // }
+
+_already_in_list0:
+
+    /* Restore interrupts. */
+
+    MSR     DAIF, x0                            // Restore interrupts
+    ISB                                         // 
+#ifdef TX_ENABLE_WFE
+    WFE                                         // Go into standby
+#endif
+
+    /* We do this until we have the lock. */
+    // while (1)
+    // {
+
+_try_to_get_lock:
+
+    /* Disable interrupts so we don't get preempted.  */
+
+    MRS     x0, DAIF                            // Pickup current interrupt posture
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    /* Pickup the CPU ID.   */
+
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x7, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x7, LSL #2                  // Calculate CPU ID
+#endif
+
+    /* Do we already have protection?  */
+    // if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
+    // {
+
+    LDR     w3, [x2, #4]                        // Pickup the owning core
+    CMP     w3, w1                              // Is it this core?
+    BEQ     _got_lock_after_waiting             // Yes, the protection is already owned. This means
+                                                // an ISR preempted us and got protection
+
+    // }
+
+    /* Are we at the front of the list?  */
+    // if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
+    // {/
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
+    LDR     w3, [x3]                            // Get the value of the head
+    LDR     x4, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    LDR     w4, [x4, x3, LSL #2]                // Get the value at the head index
+
+    CMP     w1, w4
+    BNE     _did_not_get_lock
+
+    /* Is the lock still available? */
+    // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
+    // {
+
+    LDR     w3, [x2, #0]                        // Pickup the protection flag
+    CMP     w3, #0
+    BNE     _did_not_get_lock                   // No, protection not available
+
+    /* Get the lock.  */
+    // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
+
+    MOV     w3, #1                              // Build lock value
+    STR     w3, [x2, #0]                        // Store lock value
+    DMB     ISH                                 //
+
+    /* Got the lock.  */
+    // _tx_thread_smp_protect_lock_got();
+
+    _tx_thread_smp_protect_lock_got
+
+    /* Remove this core from the wait list.  */
+    // _tx_thread_smp_protect_remove_from_front_of_list();
+
+    _tx_thread_smp_protect_remove_from_front_of_list
+
+    B       _got_lock_after_waiting
+
+_did_not_get_lock:
+
+    /* For one reason or another, we didn't get the lock.  */
+
+    /* Were we removed from the list? This can happen if we're a thread
+       and we got preempted. */
+    // if (_tx_thread_smp_protect_wait_counts[this_core] == 0)
+    // {
+
+    LDR     x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
+    LDR     w4, [x3, x1, LSL #2]                // Load waiting value for this core
+    CMP     w4, #0
+    BNE     _already_in_list1                   // Is this core already in the list?
+
+    /* Add ourselves to the list.  */
+    // _tx_thread_smp_protect_wait_list_add(this_core);
+
+    _tx_thread_smp_protect_wait_list_add        // Call macro to add ourselves to the list
+
+    /* Our waiting count was also reset when we were preempted. Increment it again. */
+    // _tx_thread_smp_protect_wait_counts[this_core]++;
+
+    LDR     x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
+    LDR     w4, [x3, x1, LSL #2]                // Load waiting value for this core
+    ADD     w4, w4, #1                          // Increment wait value
+    STR     w4, [x3, x1, LSL #2]                // Store new wait value value
+
+    // }
+
+_already_in_list1:
+
+    /* Restore interrupts and try again.  */
+
+    MSR     DAIF, x0                            // Restore interrupts
+    ISB                                         // 
+#ifdef TX_ENABLE_WFE
+    WFE                                         // Go into standby
+#endif
+    B       _try_to_get_lock                    // On waking, restart the protection attempt
+
+_got_lock_after_waiting:
+
+    /* We're no longer waiting.  */
+    // _tx_thread_smp_protect_wait_counts[this_core]--;
+
+    LDR     x3, =_tx_thread_smp_protect_wait_counts // Load waiting list
+    LDR     w4, [x3, x1, LSL #2]                // Load current wait value
+    SUB     w4, w4, #1                          // Decrement wait value
+    STR     w4, [x3, x1, LSL #2]                // Store new wait value value
+
+    /* Restore registers and return.  */
+
+_return:
+
+    RET
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h
new file mode 100644
index 00000000..5c33d940
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h
@@ -0,0 +1,296 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+    .macro _tx_thread_smp_protect_lock_got
+
+    /* Set the currently owned core.  */
+    /* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */
+
+    STR     w1, [x2, #4]                        // Store this core
+
+    /* Increment the protection count. */
+    /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */
+
+    LDR     w3, [x2, #8]                        // Pickup ownership count
+    ADD     w3, w3, #1                          // Increment ownership count
+    STR     w3, [x2, #8]                        // Store ownership count
+    DMB     ISH
+
+    .endm
+
+    .macro _tx_thread_smp_protect_remove_from_front_of_list
+
+    /* Remove ourselves from the list.  */
+    /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] =  0xFFFFFFFF; */
+
+    MOV     w3, #0xFFFFFFFF                     // Build the invalid core value
+    LDR     x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
+    LDR     w5, [x4]                            // Get the value of the head
+    LDR     x6, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    STR     w3, [x6, x5, LSL #2]                // Store the invalid core value
+    ADD     w5, w5, #1                          // Increment the head
+
+    /* Did we wrap?  */
+    /* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
+    { */
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size
+    LDR     w3, [x3]                            // Load the max cores value
+    CMP     w5, w3                              // Compare the head to it
+    BNE     _store_new_head\@                   // Are we at the max?
+
+    /* _tx_thread_smp_protect_wait_list_head = 0; */
+
+    EOR     w5, w5, w5                          // We're at the max. Set it to zero
+
+    /* } */
+
+_store_new_head\@:
+
+    STR     w5, [x4]                            // Store the new head
+
+    /* We have the lock!  */
+    /* return; */
+
+    .endm
+
+
+    .macro _tx_thread_smp_protect_wait_list_lock_get
+/* VOID  _tx_thread_smp_protect_wait_list_lock_get()
+{ */
+    /* We do this until we have the lock.  */
+    /* while (1)
+    { */
+
+_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
+
+    /* Is the list lock available?  */
+    /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */
+
+    LDR     x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
+    LDAXR   w2, [x1]                            // Pickup the protection flag
+
+    /* if (protect_in_force == 0)
+    { */
+
+    CMP     w2, #0
+    BNE     _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available
+
+    /* Try to get the list.  */
+    /* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */
+
+    MOV     w2, #1                              // Build lock value
+    STXR    w3, w2, [x1]                        // Attempt to get the protection
+
+    /* if (status == SUCCESS) */
+
+    CMP     w3, #0
+    BNE     _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again.
+
+    /* We have the lock!  */
+    /* return; */
+
+    .endm
+
+
+    .macro _tx_thread_smp_protect_wait_list_add
+/* VOID  _tx_thread_smp_protect_wait_list_add(UINT new_core)
+{ */
+
+    /* We're about to modify the list, so get the list lock.  */
+    /* _tx_thread_smp_protect_wait_list_lock_get(); */
+
+    STP     x1, x2, [sp, #-16]!                 // Save registers we'll be using
+
+    _tx_thread_smp_protect_wait_list_lock_get
+
+    LDP     x1, x2, [sp], #16
+
+    /* Add this core.  */
+    /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail
+    LDR     w4, [x3]                            // Get the value of tail
+    LDR     x5, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    STR     w1, [x5, x4, LSL #2]                // Store the new core value
+    ADD     w4, w4, #1                          // Increment the tail
+
+    /* Did we wrap?  */
+    /* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
+    { */
+
+    LDR     x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address
+    LDR     w5, [x5]                            // Load max cores value
+    CMP     w4, w5                              // Compare max cores to tail
+    BNE     _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap?
+
+    /* _tx_thread_smp_protect_wait_list_tail = 0; */
+
+    MOV     w4, #0
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_add__no_wrap\@:
+
+    STR     w4, [x3]                            // Store the new tail value.
+
+    /* Release the list lock.  */
+    /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
+
+    MOV     w3, #0                              // Build lock value
+    LDR     x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
+    STR     w3, [x4]                            // Store the new value
+
+    .endm
+
+
+    .macro _tx_thread_smp_protect_wait_list_remove
+/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
+{ */
+
+    /* Get the core index.  */
+    /* UINT core_index;
+    for (core_index = 0;; core_index++) */
+
+    EOR     w4, w4, w4                          // Clear for 'core_index'
+    LDR     x2, =_tx_thread_smp_protect_wait_list // Get the address of the list
+
+    /* { */
+
+_tx_thread_smp_protect_wait_list_remove__check_cur_core\@:
+
+    /* Is this the core?  */
+    /* if (_tx_thread_smp_protect_wait_list[core_index] == core)
+    {
+        break; */
+
+    LDR     w3, [x2, x4, LSL #2]                // Get the value at the current index
+    CMP     w3, w8                              // Did we find the core?
+    BEQ     _tx_thread_smp_protect_wait_list_remove__found_core\@
+
+    /* } */
+
+    ADD     w4, w4, #1                          // Increment cur index
+    B       _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_remove__found_core\@:
+
+    /* We're about to modify the list. Get the lock. We need the lock because another
+       core could be simultaneously adding (a core is simultaneously trying to get
+       the inter-core lock) or removing (a core is simultaneously being preempted,
+       like what is currently happening).  */
+    /* _tx_thread_smp_protect_wait_list_lock_get(); */
+
+    MOV     x6, x1
+    _tx_thread_smp_protect_wait_list_lock_get
+    MOV     x1, x6
+
+    /* We remove by shifting.  */
+    /* while (core_index != _tx_thread_smp_protect_wait_list_tail)
+    { */
+
+_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
+
+    LDR     x2, =_tx_thread_smp_protect_wait_list_tail // Load tail address
+    LDR     w2, [x2]                            // Load tail value
+    CMP     w4, w2                              // Compare cur index and tail
+    BEQ     _tx_thread_smp_protect_wait_list_remove__removed\@
+
+    /* UINT next_index = core_index + 1; */
+
+    MOV     w2, w4                              // Move current index to next index register
+    ADD     w2, w2, #1                          // Add 1
+
+    /* if (next_index == _tx_thread_smp_protect_wait_list_size)
+    { */
+
+    LDR     x3, =_tx_thread_smp_protect_wait_list_size
+    LDR     w3, [x3]
+    CMP     w2, w3
+    BNE     _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@
+
+    /* next_index = 0; */
+
+    MOV     w2, #0
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@:
+
+    /* list_cores[core_index] = list_cores[next_index]; */
+
+    LDR     x5, =_tx_thread_smp_protect_wait_list // Get the address of the list
+    LDR     w3, [x5, x2, LSL #2]                // Get the value at the next index
+    STR     w3, [x5, x4, LSL #2]                // Store the value at the current index
+
+    /* core_index = next_index; */
+
+    MOV     w4, w2
+
+    B       _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_remove__removed\@:
+
+    /* Now update the tail.  */
+    /* if (_tx_thread_smp_protect_wait_list_tail == 0)
+    { */
+
+    LDR     x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address
+    LDR     w4, [x5]                            // Load tail value
+    CMP     w4, #0
+    BNE     _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@
+
+    /* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */
+
+    LDR     x2, =_tx_thread_smp_protect_wait_list_size
+    LDR     w4, [x2]
+
+    /* } */
+
+_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@:
+
+    /* _tx_thread_smp_protect_wait_list_tail--; */
+
+    SUB     w4, w4, #1
+    STR     w4, [x5]                            // Store new tail value
+
+    /* Release the list lock.  */
+    /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
+
+    MOV     w2, #0                              // Build lock value
+    LDR     x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address
+    STR     w2, [x4]                            // Store the new value
+
+    /* We're no longer waiting. Note that this should be zero since, again,
+       this function is only called when a thread preemption is occurring.  */
+    /* _tx_thread_smp_protect_wait_counts[core]--; */
+    LDR     x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts
+    LDR     w2, [x4, x8, LSL #2]                // Load waiting value
+    SUB     w2, w2, #1                          // Subtract 1
+    STR     w2, [x4, x8, LSL #2]                // Store new waiting value
+
+    .endm
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S
new file mode 100644
index 00000000..55f5f2fb
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S
@@ -0,0 +1,69 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_time_get                          Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function gets the global time value that is used for debug     */
+/*    information and event tracing.                                      */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    32-bit time stamp                                                   */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     William E. Lamie         Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_time_get
+    .type    _tx_thread_smp_time_get, @function
+_tx_thread_smp_time_get:
+    MOV     x0, #0          // FIXME: Get timer
+    RET
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S
new file mode 100644
index 00000000..dfd77db1
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S
@@ -0,0 +1,117 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread - Low Level SMP Support                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_smp_unprotect                         Cortex-A35-SMP/GNU */
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function releases previously obtained protection. The supplied */
+/*    previous SR is restored. If the value of _tx_thread_system_state    */
+/*    and _tx_thread_preempt_disable are both zero, then multithreading   */
+/*    is enabled as well.                                                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    Previous Status Register                                            */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX Source                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+    .global  _tx_thread_smp_unprotect
+    .type    _tx_thread_smp_unprotect, @function
+_tx_thread_smp_unprotect:
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+
+    MRS     x1, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x2, x1, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x1, x1, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x1, x1, x2, LSL #2                  // Calculate CPU ID
+#endif
+
+    LDR     x2,=_tx_thread_smp_protection       // Build address of protection structure
+    LDR     w3, [x2, #4]                        // Pickup the owning core
+    CMP     w1, w3                              // Is it this core?
+    BNE     _still_protected                    // If this is not the owning core, protection is in force elsewhere
+
+    LDR     w3, [x2, #8]                        // Pickup the protection count
+    CMP     w3, #0                              // Check to see if the protection is still active
+    BEQ     _still_protected                    // If the protection count is zero, protection has already been cleared
+
+    SUB     w3, w3, #1                          // Decrement the protection count
+    STR     w3, [x2, #8]                        // Store the new count back
+    CMP     w3, #0                              // Check to see if the protection is still active
+    BNE     _still_protected                    // If the protection count is non-zero, protection is still in force
+    LDR     x2,=_tx_thread_preempt_disable      // Build address of preempt disable flag
+    LDR     w3, [x2]                            // Pickup preempt disable flag
+    CMP     w3, #0                              // Is the preempt disable flag set?
+    BNE     _still_protected                    // Yes, skip the protection release
+
+    LDR     x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts
+    LDR     w3, [x2, x1, LSL #2]                // Pickup wait list value
+    CMP     w3, #0                              // Are any entities on this core waiting?
+    BNE     _still_protected                    // Yes, skip the protection release
+
+    LDR     x2,=_tx_thread_smp_protection       // Build address of protection structure
+    MOV     w3, #0xFFFFFFFF                     // Build invalid value
+    STR     w3, [x2, #4]                        // Mark the protected core as invalid
+    DMB     ISH                                 // Ensure that accesses to shared resource have completed
+    MOV     w3, #0                              // Build release protection value
+    STR     w3, [x2, #0]                        // Release the protection
+    DSB     ISH                                 // To ensure update of the protection occurs before other CPUs awake
+
+_still_protected:
+#ifdef TX_ENABLE_WFE
+    SEV                                         // Send event to other CPUs, wakes anyone waiting on the protection (using WFE)
+#endif
+    MSR     DAIF, x0                            // Restore interrupt posture
+    RET
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..5b62156a
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S
@@ -0,0 +1,159 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_stack_build                           Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread             */
+/*    function_ptr                          Pointer to entry function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+// {
+    .global _tx_thread_stack_build
+    .type   _tx_thread_stack_build, @function
+_tx_thread_stack_build:
+
+
+    /* Build an interrupt frame.  On Cortex-A35 it should look like this:
+
+       Stack Top:      SSPR        Initial SSPR
+                       ELR         Point of interrupt
+                       x28         Initial value for x28
+                       not used    Not used
+                       x26         Initial value for x26
+                       x27         Initial value for x27
+                       x24         Initial value for x24
+                       x25         Initial value for x25
+                       x22         Initial value for x22
+                       x23         Initial value for x23
+                       x20         Initial value for x20
+                       x21         Initial value for x21
+                       x18         Initial value for x18
+                       x19         Initial value for x19
+                       x16         Initial value for x16
+                       x17         Initial value for x17
+                       x14         Initial value for x14
+                       x15         Initial value for x15
+                       x12         Initial value for x12
+                       x13         Initial value for x13
+                       x10         Initial value for x10
+                       x11         Initial value for x11
+                       x8          Initial value for x8
+                       x9          Initial value for x9
+                       x6          Initial value for x6
+                       x7          Initial value for x7
+                       x4          Initial value for x4
+                       x5          Initial value for x5
+                       x2          Initial value for x2
+                       x3          Initial value for x3
+                       x0          Initial value for x0
+                       x1          Initial value for x1
+                       x29         Initial value for x29 (frame pointer)
+                       x30         Initial value for x30 (link register)
+                       0           For stack backtracing
+
+       Stack Bottom: (higher memory address)
+    */
+
+    LDR     x4, [x0, #24]                       // Pickup end of stack area
+    BIC     x4, x4, #0xF                        // Ensure 16-byte alignment
+
+    /* Actually build the stack frame.  */
+
+    MOV     x2, #0                              // Build clear value
+    MOV     x3, #0                              //
+
+    STP     x2, x3, [x4, #-16]!                 // Set backtrace to 0
+    STP     x2, x3, [x4, #-16]!                 // Set initial x29, x30
+    STP     x2, x3, [x4, #-16]!                 // Set initial x0, x1
+    STP     x2, x3, [x4, #-16]!                 // Set initial x2, x3
+    STP     x2, x3, [x4, #-16]!                 // Set initial x4, x5
+    STP     x2, x3, [x4, #-16]!                 // Set initial x6, x7
+    STP     x2, x3, [x4, #-16]!                 // Set initial x8, x9
+    STP     x2, x3, [x4, #-16]!                 // Set initial x10, x11
+    STP     x2, x3, [x4, #-16]!                 // Set initial x12, x13
+    STP     x2, x3, [x4, #-16]!                 // Set initial x14, x15
+    STP     x2, x3, [x4, #-16]!                 // Set initial x16, x17
+    STP     x2, x3, [x4, #-16]!                 // Set initial x18, x19
+    STP     x2, x3, [x4, #-16]!                 // Set initial x20, x21
+    STP     x2, x3, [x4, #-16]!                 // Set initial x22, x23
+    STP     x2, x3, [x4, #-16]!                 // Set initial x24, x25
+    STP     x2, x3, [x4, #-16]!                 // Set initial x26, x27
+    STP     x2, x3, [x4, #-16]!                 // Set initial x28
+#ifdef EL1
+    MOV     x2, #0x4                            // Build initial SPSR  (EL1)
+#else
+#ifdef EL2
+    MOV     x2, #0x8                            // Build initial SPSR  (EL2)
+#else
+    MOV     x2, #0xC                            // Build initial SPSR  (EL3)
+#endif
+#endif
+    MOV     x3, x1                              // Build initial ELR
+    STP     x2, x3, [x4, #-16]!                 // Set initial SPSR & ELR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  x2;  */
+
+    STR     x4, [x0, #8]                        // Save stack pointer in thread's
+    MOV     x3, #1                              // Build ready flag
+    STR     w3, [x0, #260]                      // Set ready flag
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S
new file mode 100644
index 00000000..7f7665c3
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S
@@ -0,0 +1,179 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_system_return                         Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is target processor specific.  It is used to transfer */
+/*    control from a thread back to the ThreadX system.  Only a           */
+/*    minimal context is saved since the compiler assumes temp registers  */
+/*    are going to get slicked by a function call anyway.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling loop        */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_system_return(VOID)
+// {
+    .global _tx_thread_system_return
+    .type   _tx_thread_system_return, @function
+_tx_thread_system_return:
+
+    /* Save minimal context on the stack.  */
+
+    MRS     x0, DAIF                            // Pickup DAIF
+    MSR     DAIFSet, 0x3                        // Lockout interrupts
+    STP     x29, x30, [sp, #-16]!               // Save x29 (frame pointer), x30 (link register)
+    STP     x19, x20, [sp, #-16]!               // Save x19, x20
+    STP     x21, x22, [sp, #-16]!               // Save x21, x22
+    STP     x23, x24, [sp, #-16]!               // Save x23, x24
+    STP     x25, x26, [sp, #-16]!               // Save x25, x26
+    STP     x27, x28, [sp, #-16]!               // Save x27, x28
+    MRS     x8, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x8, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x8, x8, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x8, x8, x3, LSL #2                  // Calculate CPU ID
+#endif
+    LDR     x5, =_tx_thread_current_ptr         // Pickup address of current ptr
+    LDR     x6, [x5, x8, LSL #3]                // Pickup current thread pointer
+
+#ifdef ENABLE_ARM_FP
+    LDR     w7, [x6, #268]                      // Pickup FP enable flag
+    CMP     w7, #0                              // Is FP enabled?
+    BEQ     _skip_fp_save                       // No, skip FP save
+    STP     q8,  q9,  [sp, #-32]!               // Save q8, q9
+    STP     q10, q11, [sp, #-32]!               // Save q10, q11
+    STP     q12, q13, [sp, #-32]!               // Save q12, q13
+    STP     q14, q15, [sp, #-32]!               // Save q14, q15
+    MRS     x2, FPSR                            // Pickup FPSR
+    MRS     x3, FPCR                            // Pickup FPCR
+    STP     x2, x3, [sp, #-16]!                 // Save FPSR, FPCR
+_skip_fp_save:
+#endif
+
+    MOV     x1, #0                              // Clear x1
+    STP     x0, x1, [sp, #-16]!                 // Save DAIF and clear value for ELR_EK1
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread exit function to indicate the thread is no longer executing.  */
+
+    MOV     x19, x5                             // Save x5
+    MOV     x20, x6                             // Save x6
+    MOV     x21, x8                             // Save x2
+    BL      _tx_execution_thread_exit           // Call the thread exit function
+    MOV     x8, x21                             // Restore x2
+    MOV     x5, x19                             // Restore x5
+    MOV     x6, x20                             // Restore x6
+#endif
+
+    LDR     x2, =_tx_timer_time_slice           // Pickup address of time slice
+    LDR     w1, [x2, x8, LSL #2]                // Pickup current time slice
+
+    /* Save current stack and switch to system stack.  */
+    // _tx_thread_current_ptr[core] -> tx_thread_stack_ptr =  sp;
+    // sp = _tx_thread_system_stack_ptr[core];
+
+    MOV     x4, sp                              //
+    STR     x4, [x6, #8]                        // Save thread stack pointer
+    LDR     x3, =_tx_thread_system_stack_ptr    // Pickup address of system stack
+    LDR     x4, [x3, x8, LSL #3]                // Pickup system stack pointer
+    MOV     sp, x4                              // Setup system stack pointer
+
+    /* Determine if the time-slice is active.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    MOV     x4, #0                              // Build clear value
+    CMP     w1, #0                              // Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save the time-slice
+
+       /* Save the current remaining time-slice.  */
+       // _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+       // _tx_timer_time_slice =  0;
+
+    STR     w4, [x2, x8, LSL #2]                // Clear time-slice
+    STR     w1, [x6, #36]                       // Store current time-slice
+
+    // }
+__tx_thread_dont_save_ts:
+
+    /* Clear the current thread pointer.  */
+    // _tx_thread_current_ptr =  TX_NULL;
+
+    STR     x4, [x5, x8, LSL #3]                // Clear current thread pointer
+
+    /* Set ready bit in thread control block.  */
+    
+    MOV     x3, #1                              // Build ready value
+    STR     w3, [x6, #260]                      // Make the thread ready 
+    DMB     ISH                                 // 
+    
+    /* Now clear protection. It is assumed that protection is in force whenever this routine is called.  */
+    
+    LDR     x3, =_tx_thread_smp_protection      // Pickup address of protection structure
+    LDR     x1, =_tx_thread_preempt_disable     // Build address to preempt disable flag
+    STR     w4, [x1, #0]                        // Clear preempt disable flag
+    STR     w4, [x3, #8]                        // Cear protection count
+    MOV     x1, #0xFFFFFFFF                     // Build invalid value
+    STR     w1, [x3, #4]                        // Set core to an invalid value
+    DMB     ISH                                 // Ensure that accesses to shared resource have completed
+    STR     w4, [x3, #0]                        // Clear protection
+    DSB     ISH                                 // To ensure update of the shared resource occurs before other CPUs awake
+    SEV                                         // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE)
+    B       _tx_thread_schedule                 // Jump to scheduler!
+
+// }
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_timeout.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_timeout.c
new file mode 100644
index 00000000..c8710f9d
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_timeout.c
@@ -0,0 +1,165 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_timeout                                Cortex-A35-SMP    */
+/*                                                           6.1          */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function handles thread timeout processing.  Timeouts occur in */
+/*    two flavors, namely the thread sleep timeout and all other service  */
+/*    call timeouts.  Thread sleep timeouts are processed locally, while  */
+/*    the others are processed by the appropriate suspension clean-up     */
+/*    service.                                                            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    timeout_input                         Contains the thread pointer   */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    Suspension Cleanup Functions                                        */
+/*    _tx_thread_system_resume          Resume thread                     */
+/*    _tx_thread_system_ni_resume       Non-interruptable resume thread   */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_timer_expiration_process          Timer expiration function     */
+/*    _tx_timer_thread_entry                Timer thread function         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_timeout(ULONG timeout_input)
+{
+
+TX_INTERRUPT_SAVE_AREA
+
+TX_THREAD       *thread_ptr;                
+VOID            (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence);
+ULONG           suspension_sequence;
+
+
+    /* Pickup the thread pointer.  */
+    TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr)
+
+    /* Disable interrupts.  */
+    TX_DISABLE
+
+    /* Determine how the thread is currently suspended.  */
+    if (thread_ptr -> tx_thread_state == TX_SLEEP)
+    {
+
+#ifdef TX_NOT_INTERRUPTABLE
+
+        /* Resume the thread!  */
+        _tx_thread_system_ni_resume(thread_ptr);
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#else
+
+        /* Increment the disable preemption flag.  */
+        _tx_thread_preempt_disable++;
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+
+        /* Lift the suspension on the sleeping thread.  */
+        _tx_thread_system_resume(thread_ptr);
+#endif
+    }
+    else
+    {
+
+        /* Process all other suspension timeouts.  */
+
+#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO
+
+        /* Increment the total number of thread timeouts.  */
+        _tx_thread_performance_timeout_count++;
+
+        /* Increment the number of timeouts for this thread.  */
+        thread_ptr -> tx_thread_performance_timeout_count++;
+#endif
+    
+        /* Pickup the cleanup routine address.  */
+        suspend_cleanup =  thread_ptr -> tx_thread_suspend_cleanup;
+
+#ifndef TX_NOT_INTERRUPTABLE
+
+        /* Pickup the suspension sequence number that is used later to verify that the
+           cleanup is still necessary.  */
+        suspension_sequence =  thread_ptr -> tx_thread_suspension_sequence;
+#else
+
+        /* When not interruptable is selected, the suspension sequence is not used - just set to 0.  */
+        suspension_sequence =  ((ULONG) 0);
+#endif
+
+#ifndef TX_NOT_INTERRUPTABLE
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#endif
+
+        /* Call any cleanup routines.  */
+        if (suspend_cleanup != TX_NULL)
+        {
+
+            /* Yes, there is a function to call.  */
+            (suspend_cleanup)(thread_ptr, suspension_sequence);
+        }
+
+#ifdef TX_NOT_INTERRUPTABLE
+
+        /* Restore interrupts.  */
+        TX_RESTORE
+#endif
+    }
+}
+
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..83ca567f
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S
@@ -0,0 +1,187 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_timer_interrupt                              Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function processes the hardware timer interrupt.  This         */
+/*    processing includes incrementing the system clock and checking for  */
+/*    time slice and/or timer expiration.  If either is found, the        */
+/*    interrupt context save/restore functions are called along with the  */
+/*    expiration functions.                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_timer_expiration_process          Timer expiration processing   */
+/*    _tx_thread_time_slice                 Time slice interrupted thread */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    interrupt vector                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_timer_interrupt(VOID)
+// {
+    .global _tx_timer_interrupt
+    .type   _tx_timer_interrupt, @function
+_tx_timer_interrupt:
+
+    MRS     x2, MPIDR_EL1                       // Pickup the core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    UBFX    x3, x2, #8, #8                      // Isolate cluster ID
+#endif
+    UBFX    x2, x2, #0, #8                      // Isolate core ID
+#if TX_THREAD_SMP_CLUSTERS > 1
+    ADDS    x2, x2, x3, LSL #2                  // Calculate CPU ID
+#endif
+    CMP     x2, #0                              // Is this core 0?
+    BEQ     __tx_process_timer                  // If desired core, continue processing
+    RET                                         // Simply return if different core
+__tx_process_timer:
+
+    /* Upon entry to this routine, it is assumed that context save has already
+       been called, and therefore the compiler scratch registers are available
+       for use.  */
+
+    STP     x27, x28, [sp, #-16]!               // Save x27, x28
+    STP     x29, x30, [sp, #-16]!               // Save x29 (frame pointer), x30 (link register)
+
+    /* Get inter-core protection.  */
+
+    BL      _tx_thread_smp_protect              // Get inter-core protection
+    MOV     x28, x0                             // Save the return value in preserved register
+
+    /* Increment the system clock.  */
+    // _tx_timer_system_clock++;
+
+    LDR     x1, =_tx_timer_system_clock         // Pickup address of system clock
+    LDR     w0, [x1, #0]                        // Pickup system clock
+    ADD     w0, w0, #1                          // Increment system clock
+    STR     w0, [x1, #0]                        // Store new system clock
+
+    /* Test for timer expiration.  */
+    // if (*_tx_timer_current_ptr)
+    // {
+
+    LDR     x1, =_tx_timer_current_ptr          // Pickup current timer pointer addr
+    LDR     x0, [x1, #0]                        // Pickup current timer
+    LDR     x2, [x0, #0]                        // Pickup timer list entry
+    CMP     x2, #0                              // Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 // No, just increment the timer
+
+        /* Set expiration flag.  */
+        // _tx_timer_expired =  TX_TRUE;
+
+    LDR     x3, =_tx_timer_expired              // Pickup expiration flag address
+    MOV     w2, #1                              // Build expired value
+    STR     w2, [x3, #0]                        // Set expired flag
+    B       __tx_timer_done                     // Finished timer processing
+
+    // }
+    // else
+    // {
+__tx_timer_no_timer:
+
+        /* No timer expired, increment the timer pointer.  */
+        // _tx_timer_current_ptr++;
+
+    ADD     x0, x0, #8                          // Move to next timer
+
+        /* Check for wrap-around.  */
+        // if (_tx_timer_current_ptr == _tx_timer_list_end)
+
+    LDR     x3, =_tx_timer_list_end             // Pickup addr of timer list end
+    LDR     x2, [x3, #0]                        // Pickup list end
+    CMP     x0, x2                              // Are we at list end?
+    BNE     __tx_timer_skip_wrap                // No, skip wrap-around logic
+
+            /* Wrap to beginning of list.  */
+            // _tx_timer_current_ptr =  _tx_timer_list_start;
+
+    LDR     x3, =_tx_timer_list_start           // Pickup addr of timer list start
+    LDR     x0, [x3, #0]                        // Set current pointer to list start
+
+__tx_timer_skip_wrap:
+
+    STR     x0, [x1, #0]                        // Store new current timer pointer
+    // }
+
+__tx_timer_done:
+
+    /* Did a timer expire?  */
+    // if (_tx_timer_expired)
+    // {
+
+    LDR     x1, =_tx_timer_expired              // Pickup addr of expired flag
+    LDR     w0, [x1, #0]                        // Pickup timer expired flag
+    CMP     w0, #0                              // Check for timer expiration
+    BEQ     __tx_timer_dont_activate            // If not set, skip timer activation
+
+        /* Process timer expiration.  */
+        // _tx_timer_expiration_process();
+
+    BL      _tx_timer_expiration_process        // Call the timer expiration handling routine
+
+    // }
+
+__tx_timer_dont_activate:
+
+    /* Call time-slice processing.  */
+    // _tx_thread_time_slice();
+    BL      _tx_thread_time_slice               // Call time-slice processing
+
+    /* Release inter-core protection.  */
+    
+    MOV     x0, x28                             // Pass the previous status register back 
+    BL      _tx_thread_smp_unprotect            // Release protection
+
+    LDP     x29, x30, [sp], #16                 // Recover x29, x30
+    LDP     x27, x28, [sp], #16                 // Recover x27, x28
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c
new file mode 100644
index 00000000..39dccb14
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c
@@ -0,0 +1,85 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "txm_module.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_port_dispatch                 Cortex-A35/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function dispatches the module's kernel request based upon the */
+/*    ID and parameters specified in the request.                         */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Module pointer                    */
+/*    kernel_request                    Module's kernel request           */
+/*    param_0                           First parameter                   */
+/*    param_1                           Second parameter                  */
+/*    param_2                           Third parameter                   */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    Port-specific ThreadX API Calls                                     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _txm_module_manager_kernel_dispatch                                 */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)
+{
+
+ALIGN_TYPE return_value = TX_NOT_AVAILABLE;
+
+    switch(kernel_request)
+    {
+        default:
+        {
+            /* Unhandled kernel request, return an error!  */
+            break;
+        }
+    }
+    
+    return(return_value);
+}
diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S
new file mode 100644
index 00000000..f1fe1926
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S
@@ -0,0 +1,165 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+    .text
+    .align 3
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_thread_stack_build           Cortex-A35-SMP/GNU */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Andres Mlinar, Microsoft Corporation                                */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread             */
+/*    function_ptr                          Pointer to entry function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Andres Mlinar            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
+// {
+    .global  _txm_module_manager_thread_stack_build
+    .type    _txm_module_manager_thread_stack_build, @function
+_txm_module_manager_thread_stack_build:
+
+
+    /* Build an interrupt frame.  On Cortex-A35 it should look like this:
+
+       Stack Top:      SSPR        Initial SSPR
+                       ELR         Point of interrupt
+                       x28         Initial value for x28
+                       not used    Not used
+                       x26         Initial value for x26
+                       x27         Initial value for x27
+                       x24         Initial value for x24
+                       x25         Initial value for x25
+                       x22         Initial value for x22
+                       x23         Initial value for x23
+                       x20         Initial value for x20
+                       x21         Initial value for x21
+                       x18         Initial value for x18
+                       x19         Initial value for x19
+                       x16         Initial value for x16
+                       x17         Initial value for x17
+                       x14         Initial value for x14
+                       x15         Initial value for x15
+                       x12         Initial value for x12
+                       x13         Initial value for x13
+                       x10         Initial value for x10
+                       x11         Initial value for x11
+                       x8          Initial value for x8
+                       x9          Initial value for x9
+                       x6          Initial value for x6
+                       x7          Initial value for x7
+                       x4          Initial value for x4
+                       x5          Initial value for x5
+                       x2          Initial value for x2
+                       x3          Initial value for x3
+                       x0          Initial value for x0
+                       x1          Initial value for x1
+                       x29         Initial value for x29 (frame pointer)
+                       x30         Initial value for x30 (link register)
+                       0           For stack backtracing
+
+       Stack Bottom: (higher memory address)
+    */
+
+    LDR     x4, [x0, #24]                       // Pickup end of stack area
+    BIC     x4, x4, #0xF                        // Ensure 16-byte alignment
+
+    LDR     x5, [x0, #8]                        // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
+                                                //   It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
+                                                //   function with the actual, initial stack pointer.
+
+    /* Actually build the stack frame.  */
+
+    MOV     x2, #0                              // Build clear value
+    MOV     x3, #0                              //
+
+    STP     x2, x3, [x4, #-16]!                 // Set backtrace to 0
+    STP     x2, x3, [x4, #-16]!                 // Set initial x29, x30
+    STP     x0, x5, [x4, #-16]!                 // Set initial x0, x1
+                                                //   x0->x0 is the thread control block pointer
+                                                //   x5->x1 is the thread entry info pointer
+    STP     x2, x3, [x4, #-16]!                 // Set initial x2, x3
+    STP     x2, x3, [x4, #-16]!                 // Set initial x4, x5
+    STP     x2, x3, [x4, #-16]!                 // Set initial x6, x7
+    STP     x2, x3, [x4, #-16]!                 // Set initial x8, x9
+    STP     x2, x3, [x4, #-16]!                 // Set initial x10, x11
+    STP     x2, x3, [x4, #-16]!                 // Set initial x12, x13
+    STP     x2, x3, [x4, #-16]!                 // Set initial x14, x15
+    STP     x2, x3, [x4, #-16]!                 // Set initial x16, x17
+    STP     x2, x3, [x4, #-16]!                 // Set initial x18, x19
+    STP     x2, x3, [x4, #-16]!                 // Set initial x20, x21
+    STP     x2, x3, [x4, #-16]!                 // Set initial x22, x23
+    STP     x2, x3, [x4, #-16]!                 // Set initial x24, x25
+    STP     x2, x3, [x4, #-16]!                 // Set initial x26, x27
+    STP     x2, x3, [x4, #-16]!                 // Set initial x28
+#ifdef EL1
+    MOV     x2, #0x4                            // Build initial SPSR  (EL1)
+#else
+#ifdef EL2
+    MOV     x2, #0x8                            // Build initial SPSR  (EL2)
+#else
+    MOV     x2, #0xC                            // Build initial SPSR  (EL3)
+#endif
+#endif
+    MOV     x3, x1                              // Build initial ELR
+    STP     x2, x3, [x4, #-16]!                 // Set initial SPSR & ELR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  x2;  */
+
+    STR     x4, [x0, #8]                        // Save stack pointer in thread's
+    MOV     x3, #1                              // Build ready flag
+    STR     w3, [x0, #260]                      // Set ready flag
+    RET                                         // Return to caller
+
+// }
diff --git a/ports_module/cortex_a35_smp/gnu/readme_threadx.txt b/ports_module/cortex_a35_smp/gnu/readme_threadx.txt
new file mode 100644
index 00000000..de17c068
--- /dev/null
+++ b/ports_module/cortex_a35_smp/gnu/readme_threadx.txt
@@ -0,0 +1,254 @@
+                   Microsoft's Azure RTOS ThreadX SMP for Cortex-A35
+
+                          Using the ARM GNU Compiler & DS
+
+1. Import the ThreadX Projects
+
+In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import 
+the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) 
+into your DS workspace.
+
+
+2.  Building the ThreadX SMP run-time Library
+
+Building the ThreadX SMP library is easy; simply select the Eclipse project file 
+"tx" and then select the build button. You should now observe the compilation 
+and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP 
+library file tx.a.
+
+
+3.  Demonstration System
+
+The ThreadX SMP demonstration is designed to execute under the DS debugger on the
+'Debug Cortex-A35x4 SMP' FVP which must be downloaded from the ARM website and
+requires a license.
+
+Building the demonstration is easy; simply select the sample_threadx project, and
+select the build button. Next, in the sample_threadx project, right-click on the
+sample_threadx.launch file and select 'Debug As -> sample_threadx'.  The debugger is
+setup for the Cortex-35x4 SMP FVP, so selecting "Debug" will launch the FVP, load
+the sample_threadx.axf ELF file and run to main. You are now ready to execute the
+ThreadX SMP demonstration.
+
+
+4.  System Initialization
+
+The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label 
+"start64". This is defined within the GCC compiler's startup code. In addition, 
+this is where all static and global pre-set C variable initialization processing 
+takes place.
+
+The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the 
+first available RAM address for use by the application, which is supplied as the 
+sole input parameter to your application definition function, tx_application_define.
+
+
+5.  Register Usage and Stack Frames
+
+The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers 
+for each function. All other registers used by a C function must be preserved 
+by the function. ThreadX SMP takes advantage of this in situations where a context 
+switch happens as a result of making a ThreadX SMP service call (which is itself a 
+C function). In such cases, the saved context of a thread is only the 
+non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+FP not enabled and TX_THREAD.tx_thread_fp_enable == 0:
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x000                  SPSR                        DAIF
+     0x008                  ELR                         0
+     0x010                  x28                         x27
+     0x018                  reserved                    x28
+     0x020                  x26                         x25
+     0x028                  x27                         x26
+     0x030                  x24                         x23
+     0x038                  x25                         x24
+     0x040                  x22                         x21
+     0x048                  x23                         x22
+     0x050                  x20                         x19
+     0x058                  x21                         x20
+     0x060                  x18                         x29
+     0x068                  x19                         x30
+     0x070                  x16
+     0x078                  x17
+     0x080                  x14
+     0x088                  x15
+     0x090                  x12
+     0x098                  x13
+     0x0A0                  x10
+     0x0A8                  x11
+     0x0B0                  x8
+     0x0B8                  x9
+     0x0C0                  x6
+     0x0C8                  x7
+     0x0D0                  x4
+     0x0D8                  x5
+     0x0E0                  x2
+     0x0E8                  x3
+     0x0F0                  x0
+     0x0F8                  x1
+     0x100                  x29
+     0x108                  x30
+
+
+FP enabled and TX_THREAD.tx_thread_fp_enable == 1:
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x000                  SPSR                        DAIF
+     0x008                  ELR                         0
+     0x010                  FPSR                        FPSR
+     0x018                  FPCR                        FPCR
+     0x020                  q30                         q14
+     0x030                  q31                         q15
+     0x040                  q28                         q12
+     0x050                  q29                         q13
+     0x060                  q26                         q10
+     0x070                  q27                         q11
+     0x080                  q24                         q8
+     0x090                  q25                         q9
+     0x0A0                  q22                         x27
+     0x0A8                                              x28
+     0x0B0                  q23                         x25
+     0x0B8                                              x26
+     0x0C0                  q20                         x23
+     0x0C8                                              x24
+     0x0D0                  q21                         x21
+     0x0D8                                              x22
+     0x0E0                  q18                         x19
+     0x0E8                                              x20
+     0x0F0                  q19                         x29
+     0x0F8                                              x30
+     0x100                  q16
+     0x110                  q17
+     0x120                  q14
+     0x130                  q15
+     0x140                  q12
+     0x150                  q13
+     0x160                  q10
+     0x170                  q11
+     0x180                  q8
+     0x190                  q9
+     0x1A0                  q6
+     0x1B0                  q7
+     0x1C0                  q4
+     0x1D0                  q5
+     0x1E0                  q2
+     0x1F0                  q3
+     0x200                  q0
+     0x210                  q1
+     0x220                  x28
+     0x228                  reserved
+     0x230                  x26
+     0x238                  x27
+     0x240                  x24
+     0x248                  x25
+     0x250                  x22
+     0x258                  x23
+     0x260                  x20
+     0x268                  x21
+     0x270                  x18
+     0x278                  x19
+     0x280                  x16
+     0x288                  x17
+     0x290                  x14
+     0x298                  x15
+     0x2A0                  x12
+     0x2A8                  x13
+     0x2B0                  x10
+     0x2B8                  x11
+     0x2C0                  x8
+     0x2C8                  x9
+     0x2D0                  x6
+     0x2D8                  x7
+     0x2E0                  x4
+     0x2E8                  x5
+     0x2F0                  x2
+     0x2F8                  x3
+     0x300                  x0
+     0x308                  x1
+     0x310                  x29
+     0x318                  x30
+
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX SMP is built without any compiler optimizations. 
+This makes it easy to debug because you can trace or set breakpoints inside of 
+ThreadX SMP itself. Of course, this costs some performance. To make it run faster, 
+you can change the project settings to the desired compiler optimization level.
+
+In addition, you can eliminate the ThreadX SMP basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX SMP provides complete and high-performance interrupt handling for Cortex-A35
+targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following
+format:
+
+        .global irq_handler
+irq_handler:
+  MSR      SPSel, 0
+  STP      x29, x30, [sp, #-16]!
+  BL       _tx_thread_context_save
+
+  /* Your ISR call goes here!  */
+  BL       application_isr_handler
+
+  B        _tx_thread_context_restore
+
+By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 
+and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined.
+
+
+8.  ThreadX SMP Timer Interrupt
+
+ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, 
+timeouts, and application timers. Without such a timer interrupt source, these services 
+are not functional. However, all other ThreadX services are operational without a 
+periodic timer source.
+
+
+9. ARM FP Support
+
+By default, FP support is disabled for each thread. If saving the context of the FP registers
+is needed, the following API call must be made from the context of the application thread - before 
+the FP usage:
+
+void    tx_thread_fp_enable(void);
+
+After this API is called in the application, FP registers will be saved/restored for this thread if it
+is preempted via an interrupt. All other suspension of the this thread will not require the FP registers
+to be saved/restored.
+
+To disable FP register context saving, simply call the following API:
+
+void    tx_thread_fp_disable(void);
+
+
+10.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX SMP:
+
+09-30-2020  Initial ThreadX 6.1 version for Cortex-A35 using ARM GCC and DS tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt b/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt
new file mode 100644
index 00000000..04e32d1f
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt
@@ -0,0 +1,24 @@
+# Parameters:
+# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]
+#----------------------------------------------------------------------------------------------
+cpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support
+cpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension
+cpu0.semihosting-enable=0                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
+cpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
+cpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
+cpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
+cpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]
+cpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode
+cpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
+cpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
+cpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]
+cpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset
+cpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
+idau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : 
+cpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write
+cpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write
+cpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write
+cpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included
+cpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included
+fvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic
+#----------------------------------------------------------------------------------------------
diff --git a/ports_module/cortex_m33/ac6/example_build/AzureRTOS.uvmpw b/ports_module/cortex_m33/ac6/example_build/AzureRTOS.uvmpw
new file mode 100644
index 00000000..8674f162
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/AzureRTOS.uvmpw
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <WorkspaceName>WorkSpace</WorkspaceName>
+
+  <project>
+    <PathAndName>.\demo_secure_zone\demo_secure_zone.uvprojx</PathAndName>
+    <NodeIsExpanded>1</NodeIsExpanded>
+  </project>
+
+  <project>
+    <PathAndName>.\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx</PathAndName>
+    <NodeIsExpanded>1</NodeIsExpanded>
+  </project>
+
+  <project>
+    <PathAndName>.\ThreadX_Library.uvprojx</PathAndName>
+    <NodeIsActive>1</NodeIsActive>
+    <NodeIsExpanded>1</NodeIsExpanded>
+  </project>
+
+  <project>
+    <PathAndName>.\sample_threadx_module\sample_threadx_module.uvprojx</PathAndName>
+    <NodeIsExpanded>1</NodeIsExpanded>
+  </project>
+
+  <project>
+    <PathAndName>.\txm\txm.uvprojx</PathAndName>
+    <NodeIsExpanded>1</NodeIsExpanded>
+  </project>
+
+</ProjectWorkspace>
diff --git a/ports_module/cortex_m33/ac6/example_build/Debug.ini b/ports_module/cortex_m33/ac6/example_build/Debug.ini
new file mode 100644
index 00000000..9f305fef
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/Debug.ini
@@ -0,0 +1,5 @@
+LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental
+LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental
+LOAD "..\\sample_threadx_module\\Objects\\sample_threadx_module.axf" incremental
+RESET
+g, \\demo_secure_zone\main_s\main
\ No newline at end of file
diff --git a/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h
new file mode 100644
index 00000000..1eb74752
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'ThreadX_Library' 
+ * Target:  'ThreadX_Library_Project' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/ports_module/cortex_m33/ac6/example_build/RTOS.uvmpw.uvgui b/ports_module/cortex_m33/ac6/example_build/RTOS.uvmpw.uvgui
new file mode 100644
index 00000000..5c23c31f
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/RTOS.uvmpw.uvgui
@@ -0,0 +1,1777 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_gui.xsd">
+
+  <SchemaVersion>-6.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <WinLayoutEx>
+    <sActiveDebugView></sActiveDebugView>
+    <WindowPosition>
+      <length>44</length>
+      <flags>2</flags>
+      <showCmd>3</showCmd>
+      <MinPosition>
+        <xPos>-1</xPos>
+        <yPos>-1</yPos>
+      </MinPosition>
+      <MaxPosition>
+        <xPos>-1</xPos>
+        <yPos>-1</yPos>
+      </MaxPosition>
+      <NormalPosition>
+        <Top>0</Top>
+        <Left>0</Left>
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+      </NormalPosition>
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+      </MDITabState>
+    </MDIClientArea>
+    <ViewEx>
+      <ViewType>0</ViewType>
+      <ViewName>Build</ViewName>
+      <Window>
+        <RegID>-1</RegID>
+        <PaneID>-1</PaneID>
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+        <PaneID>109</PaneID>
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new file mode 100644
index 00000000..f3a174c5
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvprojx
@@ -0,0 +1,1588 @@
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+            <File>
+              <FileName>txe_timer_info_get.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common\src\txe_timer_info_get.c</FilePath>
+            </File>
+            <File>
+              <FileName>tx_trace_buffer_full_notify.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common\src\tx_trace_buffer_full_notify.c</FilePath>
+            </File>
+            <File>
+              <FileName>tx_trace_event_filter.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common\src\tx_trace_event_filter.c</FilePath>
+            </File>
+            <File>
+              <FileName>tx_trace_event_unfilter.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common\src\tx_trace_event_unfilter.c</FilePath>
+            </File>
+            <File>
+              <FileName>txe_thread_secure_stack_allocate.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\txe_thread_secure_stack_allocate.c</FilePath>
+            </File>
+            <File>
+              <FileName>txe_thread_secure_stack_free.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\txe_thread_secure_stack_free.c</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_stack_error_handler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\tx_thread_stack_error_handler.c</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_stack_error_notify.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\tx_thread_stack_error_notify.c</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_context_restore.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_context_restore.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_context_save.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_context_save.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_interrupt_control.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_interrupt_control.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_interrupt_disable.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_interrupt_disable.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_interrupt_restore.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_interrupt_restore.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_schedule.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_schedule.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_secure_stack_allocate.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_secure_stack_allocate.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_secure_stack_free.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_secure_stack_free.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_stack_build.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_stack_build.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_system_return.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_thread_system_return.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_timer_interrupt.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\tx_timer_interrupt.S</FilePath>
+            </File>
+            <File>
+              <FileName>tx_initialize_low_level.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\tx_initialize_low_level.S</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_application_request.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_application_request.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_callback_request.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_callback_request.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_event_flags_notify_trampoline.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_event_flags_notify_trampoline.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_file_load.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_file_load.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_in_place_load.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_in_place_load.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_initialize.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_initialize.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_internal_load.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_internal_load.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_kernel_dispatch.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_kernel_dispatch.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_maximum_module_priority_set.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_maximum_module_priority_set.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_memory_load.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_memory_load.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_object_allocate.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_allocate.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_object_deallocate.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_deallocate.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_object_pointer_get.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_object_pointer_get_extended.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get_extended.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_object_pool_create.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pool_create.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_properties_get.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_properties_get.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_queue_notify_trampoline.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_queue_notify_trampoline.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_semaphore_notify_trampoline.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_semaphore_notify_trampoline.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_start.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_start.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_stop.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_stop.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_thread_create.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_create.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_thread_notify_trampoline.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_notify_trampoline.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_thread_reset.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_reset.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_timer_notify_trampoline.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_timer_notify_trampoline.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_unload.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_unload.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_util.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\common_modules\module_manager\src\txm_module_manager_util.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_alignment_adjust.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\txm_module_manager_alignment_adjust.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_external_memory_enable.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\txm_module_manager_external_memory_enable.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_memory_fault_handler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\txm_module_manager_memory_fault_handler.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_memory_fault_notify.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\txm_module_manager_memory_fault_notify.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_mm_register_setup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\txm_module_manager_mm_register_setup.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_thread_stack_build.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\module_manager\src\txm_module_manager_thread_stack_build.S</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_manager_port_dispatch.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\module_manager\src\txm_module_manager_port_dispatch.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <packages>
+      <filter>
+        <targetInfos/>
+      </filter>
+      <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1">
+        <targetInfos>
+          <targetInfo name="ThreadX_Library_Project" versionMatchMode="fixed"/>
+        </targetInfos>
+      </package>
+    </packages>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
+        <targetInfos>
+          <targetInfo name="ThreadX_Library_Project"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>&lt;Project Info&gt;</LayName>
+        <LayDesc></LayDesc>
+        <LayUrl></LayUrl>
+        <LayKeys></LayKeys>
+        <LayCat></LayCat>
+        <LayLic></LayLic>
+        <LayTarg>0</LayTarg>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/Objects/ExtDll.iex b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/Objects/ExtDll.iex
new file mode 100644
index 00000000..6c0896e1
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/Objects/ExtDll.iex
@@ -0,0 +1,2 @@
+[EXTDLL]
+Count=0
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct
new file mode 100644
index 00000000..0abba8a4
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct
@@ -0,0 +1,78 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE     0x00000000
+#define __ROM_SIZE     0x00100000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE     0x20000000
+#define __RAM_SIZE     0x00020000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE       0x00000400
+#define __HEAP_SIZE        0x00000C00
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP        (__RAM_BASE + __RAM_SIZE)      /* starts at end of RAM */
+#define __HEAP_BASE        (AlignExpr(+0, 8))             /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE         __ROM_BASE
+#define __RO_SIZE         __ROM_SIZE
+
+#define __RW_BASE        (__RAM_BASE        )
+#define __RW_SIZE        (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
+  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+;   *(Veneer$$CMSE)                                  ; uncomment for secure applications
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data
+   .ANY (+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+  SEAL +0
+  {
+    *.o(.seal+FIRST)
+  }
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
new file mode 100644
index 00000000..3b564881
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
@@ -0,0 +1,1260 @@
+/**************************************************************************//**
+ * @file     partition_ARMCM33.h
+ * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
+ * @version  V1.1.1
+ * @date     12. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM33_H
+#define PARTITION_ARMCM33_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   1
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x000FFFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x00100000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x001FFFFF
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20200000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x203FFFFF
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x40040000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x00200000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x002fffff      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  1
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  1
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  1
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x80-0xFF
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      1
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    0
+
+/*
+// Interrupts 64..95
+//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    0
+
+/*
+// Interrupts 96..127
+//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4    0
+
+/*
+// Interrupts 128..159
+//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5    0
+
+/*
+// Interrupts 160..191
+//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6    0
+
+/*
+// Interrupts 192..223
+//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7    0
+
+/*
+// Interrupts 224..255
+//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8    0
+
+/*
+// Interrupts 256..287
+//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9    0
+
+/*
+// Interrupts 288..319
+//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10   0
+
+/*
+// Interrupts 320..351
+//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11   0
+
+/*
+// Interrupts 352..383
+//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12   0
+
+/*
+// Interrupts 384..415
+//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13   0
+
+/*
+// Interrupts 416..447
+//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14   0
+
+/*
+// Interrupts 448..479
+//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15   0
+
+/*
+// Interrupts 480..511
+//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 128 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+  #endif
+
+  /* repeat this for all possible ITNS elements */
+
+}
+
+#endif  /* PARTITION_ARMCM33_H */
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c
new file mode 100644
index 00000000..4fcc5dbc
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+ * @file     startup_ARMCM33.c
+ * @brief    CMSIS Core Device Startup File for Cortex-M33 Device
+ * @version  V2.0.0
+ * @date     20. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+  #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+  #include "ARMCM33_TZ.h"
+#elif defined (ARMCM33_DSP_FP)
+  #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+  #include "ARMCM33_DSP_FP_TZ.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __NO_RETURN;
+void Reset_Handler  (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __VECTOR_TABLE[496];
+       const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+  (pFunc)(&__INITIAL_SP),                   /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  SecureFault_Handler,                      /*  -9 Secure Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 480 are left out */
+};
+
+/* The linker will place this value at the bottom of the stack to seal the secure main stack. */
+const int stack_seal __attribute__((section (".seal"))) = 0xFEF5EDA5;
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+
+  SystemInit();                             /* CMSIS System Initialization */
+  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+  while(1);
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
new file mode 100644
index 00000000..36cb0c63
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
@@ -0,0 +1,115 @@
+/**************************************************************************//**
+ * @file     system_ARMCM33.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+  #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+  #include "ARMCM33_TZ.h"
+
+  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+    #include "partition_ARMCM33.h"
+  #endif
+#elif defined (ARMCM33_DSP_FP)
+  #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+  #include "ARMCM33_DSP_FP_TZ.h"
+
+  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+    #include "partition_ARMCM33.h"
+  #endif
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (XTAL / 2U)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                 (3U << 11U*2U)  );         /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  TZ_SAU_Setup();
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+    
+    *(uint32_t *)0xE000ED24 = 0x000F0000;   /* S: enable secure, usage, bus, mem faults */
+    *(uint32_t *)0xE002ED24 = 0x000F0000;   /* NS: enable secure, usage, bus, mem faults */
+}
+
+#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
+void HardFault_Handler(void)
+{
+  while(1);
+
+}
+
+void UsageFault_Handler(void)
+{
+  while(1);
+}
+#endif
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h
new file mode 100644
index 00000000..65bfdcd7
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'demo_secure_zone' 
+ * Target:  'FVP Simulation Model' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx
new file mode 100644
index 00000000..8731d61f
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx
@@ -0,0 +1,440 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>FVP Simulation Model</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>15</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>..\Debug.ini</tIfile>
+        <pMon>BIN\DbgFMv8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(6010=1895,-444,2372,152,1)(6018=-1,-1,-1,-1,0)(6019=105,137,294,473,0)(6008=1877,-377,2171,-192,0)(6009=-1,-1,-1,-1,0)(6014=1819,316,2077,1047,1)(6015=2064,312,2322,934,1)(6003=1812,210,2394,746,1)(6000=1831,294,2284,626,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=2227,107,2993,421,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DbgFMv8M</Key>
+          <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -PF -MA</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint>
+        <Bp>
+          <Number>0</Number>
+          <Type>0</Type>
+          <LineNumber>137</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>2068</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename>&lt;1&gt;RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression>\\demo_secure_zone\RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c\137</Expression>
+        </Bp>
+        <Bp>
+          <Number>1</Number>
+          <Type>0</Type>
+          <LineNumber>113</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>1050838</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename>&lt;2&gt;.\sample_threadx_module_manager.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression>\\demo_threadx_non_secure_zone\sample_threadx_module_manager.c\113</Expression>
+        </Bp>
+        <Bp>
+          <Number>2</Number>
+          <Type>0</Type>
+          <LineNumber>128</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>1050886</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename>&lt;2&gt;.\sample_threadx_module_manager.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression>\\demo_threadx_non_secure_zone\sample_threadx_module_manager.c\128</Expression>
+        </Bp>
+        <Bp>
+          <Number>3</Number>
+          <Type>0</Type>
+          <LineNumber>0</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>1059030</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename></Filename>
+          <ExecCommand></ExecCommand>
+          <Expression>0x001028D6</Expression>
+        </Bp>
+        <Bp>
+          <Number>4</Number>
+          <Type>0</Type>
+          <LineNumber>81</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>1064656</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename>&lt;3&gt;..\module_manager\src\tx_thread_stack_error_handler.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression>\\demo_threadx_non_secure_zone\../module_manager/src/tx_thread_stack_error_handler.c\81</Expression>
+        </Bp>
+        <Bp>
+          <Number>5</Number>
+          <Type>0</Type>
+          <LineNumber>244</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>2101430</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename>&lt;4&gt;.\sample_threadx_module.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression>\\sample_threadx_module\sample_threadx_module.c\244</Expression>
+        </Bp>
+      </Breakpoint>
+      <WatchWindow1>
+        <Ww>
+          <count>0</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_0_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>1</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_1_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>2</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_2_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>3</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_3_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>4</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_4_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>5</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_5_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>6</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_6_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>7</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_7_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>8</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>_tx_thread_current_ptr</ItemText>
+        </Ww>
+        <Ww>
+          <count>9</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>_tx_thread_execute_ptr</ItemText>
+        </Ww>
+        <Ww>
+          <count>10</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>my_module</ItemText>
+        </Ww>
+        <Ww>
+          <count>11</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>_tx_timer_system_clock</ItemText>
+        </Ww>
+        <Ww>
+          <count>12</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>(TX_THREAD*)0x202116B8</ItemText>
+        </Ww>
+      </WatchWindow1>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>2</SubType>
+          <ItemText>0x20211090</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
+      <MemoryWindow2>
+        <Mm>
+          <WinNumber>2</WinNumber>
+          <SubType>2</SubType>
+          <ItemText>0xE000ED28</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow2>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Secure Code</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\main_s.c</PathWithFileName>
+      <FilenameWithoutPath>main_s.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\module_manager\src\tx_thread_secure_stack.c</PathWithFileName>
+      <FilenameWithoutPath>tx_thread_secure_stack.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Interface</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\interface.c</PathWithFileName>
+      <FilenameWithoutPath>interface.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::Device</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx
new file mode 100644
index 00000000..a92def51
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx
@@ -0,0 +1,497 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP Simulation Model</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM33_DSP_FP_TZ</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.7.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>demo_secure_zone</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>1</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>0</Capability>
+            <DriverSelection>-1</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>0</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M33"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>1</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x200000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20200000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>7</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\..\..\common\inc, ..\..\inc</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_AC6.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Secure Code</GroupName>
+          <Files>
+            <File>
+              <FileName>main_s.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main_s.c</FilePath>
+            </File>
+            <File>
+              <FileName>tx_thread_secure_stack.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\module_manager\src\tx_thread_secure_stack.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Interface</GroupName>
+          <Files>
+            <File>
+              <FileName>interface.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\interface.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.0" condition="ARMCM33 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.0.0">
+        <instance index="0" removed="1">RTE\CMSIS\RTX_Config.c</instance>
+        <component Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.0.0" condition="RTOS2 RTX5 NS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" condition="TZ Secure" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.1">
+        <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.0.0">
+        <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>&lt;Project Info&gt;</LayName>
+        <LayDesc></LayDesc>
+        <LayUrl></LayUrl>
+        <LayKeys></LayKeys>
+        <LayCat></LayCat>
+        <LayLic></LayLic>
+        <LayTarg>0</LayTarg>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c
new file mode 100644
index 00000000..4e6e8eee
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * interface.c      Secure/non-secure callable application code
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+
+
+#include <arm_cmse.h>     // CMSE definitions
+#include "interface.h"    // Header file with secure interface API
+
+/* typedef for non-secure callback functions */
+typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));
+
+/* Non-secure callable (entry) function */
+int func1(int x) __attribute__((cmse_nonsecure_entry)) { 
+  return x+3; 
+}
+
+/* Non-secure callable (entry) function, calling a non-secure callback function */
+int func2(funcptr callback, int x)  __attribute__((cmse_nonsecure_entry))	{
+	funcptr_NS callback_NS;               // non-secure callback function pointer
+	int y;
+	
+	/* return function pointer with cleared LSB */
+  callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);
+	
+	y = callback_NS (x+1);
+	
+	return (y+2);
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.h b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.h
new file mode 100644
index 00000000..8215d5a3
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * interface.h    API definition for the non-secure state
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+
+/* Function pointer declaration */
+typedef int (*funcptr)(int);
+
+/* Non-secure callable functions */
+extern int func1(int x);
+extern int func2(funcptr callback, int x);
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c
new file mode 100644
index 00000000..a65b6880
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * main_ns.c      Non-secure main function - RTOS demo
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+
+#include "..\demo_secure_zone\interface.h"        // Interface API
+//#include "cmsis_os2.h"                  // ARM::CMSIS:RTOS2:Keil RTX5
+
+//static osStatus_t Status;
+
+//static osThreadId_t ThreadA_Id;
+//static osThreadId_t ThreadB_Id;
+//static osThreadId_t ThreadC_Id;
+
+void ThreadA (void *argument);
+void ThreadB (void *argument);
+void ThreadC (void *argument);
+
+
+extern volatile int counterA;
+extern volatile int counterB;
+extern volatile int counterC;
+
+volatile int counterA;
+volatile int counterB;
+volatile int counterC;
+
+/*
+static int callbackA (int val)  {
+  return (val);
+}
+
+__attribute__((noreturn))
+void ThreadA (void *argument)  {
+  (void)argument;
+
+  for (;;) {
+    counterA = func1 (counterA);
+    counterA = func2 (callbackA, counterA);
+    osDelay(2U);
+  }
+}
+
+static int callbackB (int val)  {
+  uint32_t flags;
+  
+  flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever);
+  if (flags == 1U)  {
+    return (val+1);
+  }  else {
+    return (0);
+  }
+}
+
+
+__attribute__((noreturn))
+void ThreadB (void *argument)  {
+  (void)argument;
+
+  for (;;) {
+    counterB = func1 (counterB);
+    counterB = func2 (callbackB, counterB);
+  }
+}
+
+__attribute__((noreturn))
+void ThreadC (void *argument) {
+  (void)argument;
+
+  for (;;) {
+    counterC = counterC + 1;
+    if ((counterC % 0x10) == 0)  {
+      osThreadFlagsSet (ThreadB_Id, 1);
+    }
+    osDelay(1U);
+  }
+}
+
+static const osThreadAttr_t ThreadAttr = {
+  .tz_module = 1U,                  // indicate calls to secure mode
+};
+*/
+#if 1
+int main (void) {
+
+  //Status = osKernelInitialize();
+
+  //ThreadA_Id = osThreadNew(ThreadA, NULL, &ThreadAttr);
+  //ThreadB_Id = osThreadNew(ThreadB, NULL, &ThreadAttr);
+  //ThreadC_Id = osThreadNew(ThreadC, NULL, NULL);
+
+  //Status = osKernelStart();
+
+  for (;;);
+}
+#endif
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c
new file mode 100644
index 00000000..548b383a
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        15. October 2016
+ * $Revision:    1.1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Code template for secure main function
+ *
+ *---------------------------------------------------------------------------*/
+ 
+/* Use CMSE intrinsics */
+#include <arm_cmse.h>
+ #include <stdlib.h>
+#include "RTE_Components.h"
+#include CMSIS_device_header
+ 
+/* TZ_START_NS: Start address of non-secure application */
+#ifndef TZ_START_NS
+#define TZ_START_NS (0x100000U)
+#endif
+ 
+/* typedef for non-secure callback functions */
+typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
+ 
+/* Secure main() */
+int main(void) {
+  funcptr_void NonSecure_ResetHandler;
+ 
+  /* Add user setup code for secure part here*/
+    
+  /* Set non-secure main stack (MSP_NS) */
+  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+ 
+  /* Get non-secure reset handler */
+  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
+ 
+  /* Start non-secure state software application */
+  NonSecure_ResetHandler();
+ 
+  /* Non-secure software does not return, this code is not executed */
+  while (1) {
+    __NOP();
+  }
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/Objects/ExtDll.iex b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/Objects/ExtDll.iex
new file mode 100644
index 00000000..6c0896e1
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/Objects/ExtDll.iex
@@ -0,0 +1,2 @@
+[EXTDLL]
+Count=0
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c
new file mode 100644
index 00000000..e4871014
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.1.0
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+#include "cmsis_compiler.h"
+#include "rtx_os.h"
+ 
+// OS Idle Thread
+__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
+  (void)argument;
+
+  for (;;) {}
+}
+ 
+// OS Error Callback function
+__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
+  (void)object_id;
+
+  switch (code) {
+    case osRtxErrorStackUnderflow:
+      // Stack overflow detected for thread (thread_id=object_id)
+      break;
+    case osRtxErrorISRQueueOverflow:
+      // ISR Queue overflow detected when inserting object (object_id)
+      break;
+    case osRtxErrorTimerQueueOverflow:
+      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
+      break;
+    case osRtxErrorClibSpace:
+      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
+      break;
+    case osRtxErrorClibMutex:
+      // Standard C/C++ library mutex initialization failed
+      break;
+    default:
+      // Reserved
+      break;
+  }
+  for (;;) {}
+//return 0U;
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h
new file mode 100644
index 00000000..3021efbc
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h
@@ -0,0 +1,578 @@
+/*
+ * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.5.0
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+#ifndef RTX_CONFIG_H_
+#define RTX_CONFIG_H_
+ 
+#ifdef   _RTE_
+#include "RTE_Components.h"
+#ifdef    RTE_RTX_CONFIG_H
+#include  RTE_RTX_CONFIG_H
+#endif
+#endif
+ 
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+ 
+// <h>System Configuration
+// =======================
+ 
+//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
+//   <i> Defines the combined global dynamic memory size.
+//   <i> Default: 4096
+#ifndef OS_DYNAMIC_MEM_SIZE
+#define OS_DYNAMIC_MEM_SIZE         4096
+#endif
+ 
+//   <o>Kernel Tick Frequency [Hz] <1-1000000>
+//   <i> Defines base time unit for delays and timeouts.
+//   <i> Default: 1000 (1ms tick)
+#ifndef OS_TICK_FREQ
+#define OS_TICK_FREQ                1000
+#endif
+ 
+//   <e>Round-Robin Thread switching
+//   <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN_ENABLE
+#define OS_ROBIN_ENABLE             1
+#endif
+ 
+//     <o>Round-Robin Timeout <1-1000>
+//     <i> Defines how many ticks a thread will execute before a thread switch.
+//     <i> Default: 5
+#ifndef OS_ROBIN_TIMEOUT
+#define OS_ROBIN_TIMEOUT            5
+#endif
+ 
+//   </e>
+ 
+//   <o>ISR FIFO Queue 
+//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries
+//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries
+//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries
+//   <i> RTOS Functions called from ISR store requests to this buffer.
+//   <i> Default: 16 entries
+#ifndef OS_ISR_FIFO_QUEUE
+#define OS_ISR_FIFO_QUEUE           16
+#endif
+ 
+//   <q>Object Memory usage counters
+//   <i> Enables object memory usage counters (requires RTX source variant).
+#ifndef OS_OBJ_MEM_USAGE
+#define OS_OBJ_MEM_USAGE            0
+#endif
+ 
+// </h>
+ 
+// <h>Thread Configuration
+// =======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_THREAD_OBJ_MEM
+#define OS_THREAD_OBJ_MEM           0
+#endif
+ 
+//     <o>Number of user Threads <1-1000>
+//     <i> Defines maximum number of user threads that can be active at the same time.
+//     <i> Applies to user threads with system provided memory for control blocks.
+#ifndef OS_THREAD_NUM
+#define OS_THREAD_NUM               1
+#endif
+ 
+//     <o>Number of user Threads with default Stack size <0-1000>
+//     <i> Defines maximum number of user threads with default stack size.
+//     <i> Applies to user threads with zero stack size specified.
+#ifndef OS_THREAD_DEF_STACK_NUM
+#define OS_THREAD_DEF_STACK_NUM     0
+#endif
+ 
+//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
+//     <i> Defines the combined stack size for user threads with user-provided stack size.
+//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.
+//     <i> Default: 0
+#ifndef OS_THREAD_USER_STACK_SIZE
+#define OS_THREAD_USER_STACK_SIZE   0
+#endif
+ 
+//   </e>
+ 
+//   <o>Default Thread Stack size [bytes] <96-1073741824:8>
+//   <i> Defines stack size for threads with zero stack size specified.
+//   <i> Default: 256
+#ifndef OS_STACK_SIZE
+#define OS_STACK_SIZE               256
+#endif
+ 
+//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>
+//   <i> Defines stack size for Idle thread.
+//   <i> Default: 256
+#ifndef OS_IDLE_THREAD_STACK_SIZE
+#define OS_IDLE_THREAD_STACK_SIZE   256
+#endif
+ 
+//   <o>Idle Thread TrustZone Module Identifier
+//   <i> Defines TrustZone Thread Context Management Identifier.
+//   <i> Applies only to cores with TrustZone technology.
+//   <i> Default: 0 (not used)
+#ifndef OS_IDLE_THREAD_TZ_MOD_ID
+#define OS_IDLE_THREAD_TZ_MOD_ID    0
+#endif
+ 
+//   <q>Stack overrun checking
+//   <i> Enables stack overrun check at thread switch.
+//   <i> Enabling this option increases slightly the execution time of a thread switch.
+#ifndef OS_STACK_CHECK
+#define OS_STACK_CHECK              1
+#endif
+ 
+//   <q>Stack usage watermark
+//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.
+//   <i> Enabling this option increases significantly the execution time of thread creation.
+#ifndef OS_STACK_WATERMARK
+#define OS_STACK_WATERMARK          0
+#endif
+ 
+//   <o>Processor mode for Thread execution 
+//     <0=> Unprivileged mode 
+//     <1=> Privileged mode
+//   <i> Default: Privileged mode
+#ifndef OS_PRIVILEGE_MODE
+#define OS_PRIVILEGE_MODE           1
+#endif
+ 
+// </h>
+ 
+// <h>Timer Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_TIMER_OBJ_MEM
+#define OS_TIMER_OBJ_MEM            0
+#endif
+ 
+//     <o>Number of Timer objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_TIMER_NUM
+#define OS_TIMER_NUM                1
+#endif
+ 
+//   </e>
+ 
+//   <o>Timer Thread Priority
+//      <8=> Low
+//     <16=> Below Normal  <24=> Normal  <32=> Above Normal
+//     <40=> High
+//     <48=> Realtime
+//   <i> Defines priority for timer thread
+//   <i> Default: High
+#ifndef OS_TIMER_THREAD_PRIO
+#define OS_TIMER_THREAD_PRIO        40
+#endif
+ 
+//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>
+//   <i> Defines stack size for Timer thread.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 256
+#ifndef OS_TIMER_THREAD_STACK_SIZE
+#define OS_TIMER_THREAD_STACK_SIZE  256
+#endif
+ 
+//   <o>Timer Thread TrustZone Module Identifier
+//   <i> Defines TrustZone Thread Context Management Identifier.
+//   <i> Applies only to cores with TrustZone technology.
+//   <i> Default: 0 (not used)
+#ifndef OS_TIMER_THREAD_TZ_MOD_ID
+#define OS_TIMER_THREAD_TZ_MOD_ID   0
+#endif
+ 
+//   <o>Timer Callback Queue entries <0-256>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 4
+#ifndef OS_TIMER_CB_QUEUE
+#define OS_TIMER_CB_QUEUE           4
+#endif
+ 
+// </h>
+ 
+// <h>Event Flags Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_EVFLAGS_OBJ_MEM
+#define OS_EVFLAGS_OBJ_MEM          0
+#endif
+ 
+//     <o>Number of Event Flags objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_EVFLAGS_NUM
+#define OS_EVFLAGS_NUM              1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Mutex Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MUTEX_OBJ_MEM
+#define OS_MUTEX_OBJ_MEM            0
+#endif
+ 
+//     <o>Number of Mutex objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MUTEX_NUM
+#define OS_MUTEX_NUM                1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Semaphore Configuration
+// ==========================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_SEMAPHORE_OBJ_MEM
+#define OS_SEMAPHORE_OBJ_MEM        0
+#endif
+ 
+//     <o>Number of Semaphore objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_SEMAPHORE_NUM
+#define OS_SEMAPHORE_NUM            1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Memory Pool Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MEMPOOL_OBJ_MEM
+#define OS_MEMPOOL_OBJ_MEM          0
+#endif
+ 
+//     <o>Number of Memory Pool objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MEMPOOL_NUM
+#define OS_MEMPOOL_NUM              1
+#endif
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#ifndef OS_MEMPOOL_DATA_SIZE
+#define OS_MEMPOOL_DATA_SIZE        0
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Message Queue Configuration
+// ==============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MSGQUEUE_OBJ_MEM
+#define OS_MSGQUEUE_OBJ_MEM         0
+#endif
+ 
+//     <o>Number of Message Queue objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MSGQUEUE_NUM
+#define OS_MSGQUEUE_NUM             1
+#endif
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#ifndef OS_MSGQUEUE_DATA_SIZE
+#define OS_MSGQUEUE_DATA_SIZE       0
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Event Recorder Configuration
+// ===============================
+ 
+//   <e>Global Initialization
+//   <i> Initialize Event Recorder during 'osKernelInitialize'.
+#ifndef OS_EVR_INIT
+#define OS_EVR_INIT                 0
+#endif
+ 
+//     <q>Start recording
+//     <i> Start event recording after initialization.
+#ifndef OS_EVR_START
+#define OS_EVR_START                1
+#endif
+ 
+//     <h>Global Event Filter Setup
+//     <i> Initial recording level applied to all components.
+//       <o.0>Error events
+//       <o.1>API function call events
+//       <o.2>Operation events
+//       <o.3>Detailed operation events
+//     </h>
+#ifndef OS_EVR_LEVEL
+#define OS_EVR_LEVEL                0x00U
+#endif
+ 
+//     <h>RTOS Event Filter Setup
+//     <i> Recording levels for RTX components.
+//     <i> Only applicable if events for the respective component are generated.
+ 
+//       <h>Memory Management
+//       <i> Recording level for Memory Management events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_MEMORY_LEVEL 
+#define OS_EVR_MEMORY_LEVEL         0x01U
+#endif
+ 
+//       <h>Kernel
+//       <i> Recording level for Kernel events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_KERNEL_LEVEL 
+#define OS_EVR_KERNEL_LEVEL         0x01U
+#endif
+ 
+//       <h>Thread
+//       <i> Recording level for Thread events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_THREAD_LEVEL 
+#define OS_EVR_THREAD_LEVEL         0x05U
+#endif
+ 
+//       <h>Generic Wait
+//       <i> Recording level for Generic Wait events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_WAIT_LEVEL 
+#define OS_EVR_WAIT_LEVEL           0x01U
+#endif
+ 
+//       <h>Thread Flags
+//       <i> Recording level for Thread Flags events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_THFLAGS_LEVEL 
+#define OS_EVR_THFLAGS_LEVEL        0x01U
+#endif
+ 
+//       <h>Event Flags
+//       <i> Recording level for Event Flags events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_EVFLAGS_LEVEL 
+#define OS_EVR_EVFLAGS_LEVEL        0x01U
+#endif
+ 
+//       <h>Timer
+//       <i> Recording level for Timer events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_TIMER_LEVEL 
+#define OS_EVR_TIMER_LEVEL          0x01U
+#endif
+ 
+//       <h>Mutex
+//       <i> Recording level for Mutex events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_MUTEX_LEVEL 
+#define OS_EVR_MUTEX_LEVEL          0x01U
+#endif
+ 
+//       <h>Semaphore
+//       <i> Recording level for Semaphore events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_SEMAPHORE_LEVEL 
+#define OS_EVR_SEMAPHORE_LEVEL      0x01U
+#endif
+ 
+//       <h>Memory Pool
+//       <i> Recording level for Memory Pool events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_MEMPOOL_LEVEL 
+#define OS_EVR_MEMPOOL_LEVEL        0x01U
+#endif
+ 
+//       <h>Message Queue
+//       <i> Recording level for Message Queue events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </h>
+#ifndef OS_EVR_MSGQUEUE_LEVEL 
+#define OS_EVR_MSGQUEUE_LEVEL       0x01U
+#endif
+ 
+//     </h>
+ 
+//   </e>
+ 
+//   <h>RTOS Event Generation
+//   <i> Enables event generation for RTX components (requires RTX source variant).
+ 
+//     <q>Memory Management
+//     <i> Enables Memory Management event generation.
+#ifndef OS_EVR_MEMORY
+#define OS_EVR_MEMORY               1
+#endif
+ 
+//     <q>Kernel
+//     <i> Enables Kernel event generation.
+#ifndef OS_EVR_KERNEL
+#define OS_EVR_KERNEL               1
+#endif
+ 
+//     <q>Thread
+//     <i> Enables Thread event generation.
+#ifndef OS_EVR_THREAD
+#define OS_EVR_THREAD               1
+#endif
+ 
+//     <q>Generic Wait
+//     <i> Enables Generic Wait event generation.
+#ifndef OS_EVR_WAIT
+#define OS_EVR_WAIT                 1
+#endif
+ 
+//     <q>Thread Flags
+//     <i> Enables Thread Flags event generation.
+#ifndef OS_EVR_THFLAGS
+#define OS_EVR_THFLAGS              1
+#endif
+ 
+//     <q>Event Flags
+//     <i> Enables Event Flags event generation.
+#ifndef OS_EVR_EVFLAGS
+#define OS_EVR_EVFLAGS              1
+#endif
+ 
+//     <q>Timer
+//     <i> Enables Timer event generation.
+#ifndef OS_EVR_TIMER
+#define OS_EVR_TIMER                1
+#endif
+ 
+//     <q>Mutex
+//     <i> Enables Mutex event generation.
+#ifndef OS_EVR_MUTEX
+#define OS_EVR_MUTEX                1
+#endif
+ 
+//     <q>Semaphore
+//     <i> Enables Semaphore event generation.
+#ifndef OS_EVR_SEMAPHORE
+#define OS_EVR_SEMAPHORE            1
+#endif
+ 
+//     <q>Memory Pool
+//     <i> Enables Memory Pool event generation.
+#ifndef OS_EVR_MEMPOOL
+#define OS_EVR_MEMPOOL              1
+#endif
+ 
+//     <q>Message Queue
+//     <i> Enables Message Queue event generation.
+#ifndef OS_EVR_MSGQUEUE
+#define OS_EVR_MSGQUEUE             1
+#endif
+ 
+//   </h>
+ 
+// </h>
+ 
+// Number of Threads which use standard C/C++ library libspace
+// (when thread specific memory allocation is not used).
+#if (OS_THREAD_OBJ_MEM == 0)
+#define OS_THREAD_LIBSPACE_NUM      4
+#else
+#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM
+#endif
+ 
+//------------- <<< end of configuration section >>> ---------------------------
+ 
+#endif  // RTX_CONFIG_H_
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct
new file mode 100644
index 00000000..5ca53575
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct
@@ -0,0 +1,74 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE     0x00100000
+#define __ROM_SIZE     0x00100000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE     0x20200000
+#define __RAM_SIZE     0x00020000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE       0x00000400
+#define __HEAP_SIZE        0x00000C00
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP        (__RAM_BASE + __RAM_SIZE)      /* starts at end of RAM */
+#define __HEAP_BASE        (AlignExpr(+0, 8))             /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE         __ROM_BASE
+#define __RO_SIZE         __ROM_SIZE
+
+#define __RW_BASE        (__RAM_BASE        )
+#define __RW_SIZE        (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
+  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+;   *(Veneer$$CMSE)                                  ; uncomment for secure applications
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data
+   .ANY (+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
new file mode 100644
index 00000000..a7cb0d73
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
@@ -0,0 +1,1260 @@
+/**************************************************************************//**
+ * @file     partition_ARMCM33.h
+ * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
+ * @version  V1.1.1
+ * @date     12. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM33_H
+#define PARTITION_ARMCM33_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   1
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x00200000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x003FFFFF
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20200000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x203FFFFF
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x40040000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  1
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  1
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  1
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x80-0xFF
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      1
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    0
+
+/*
+// Interrupts 64..95
+//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    0
+
+/*
+// Interrupts 96..127
+//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4    0
+
+/*
+// Interrupts 128..159
+//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5    0
+
+/*
+// Interrupts 160..191
+//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6    0
+
+/*
+// Interrupts 192..223
+//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7    0
+
+/*
+// Interrupts 224..255
+//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8    0
+
+/*
+// Interrupts 256..287
+//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9    0
+
+/*
+// Interrupts 288..319
+//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10   0
+
+/*
+// Interrupts 320..351
+//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11   0
+
+/*
+// Interrupts 352..383
+//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12   0
+
+/*
+// Interrupts 384..415
+//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13   0
+
+/*
+// Interrupts 416..447
+//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14   0
+
+/*
+// Interrupts 448..479
+//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15   0
+
+/*
+// Interrupts 480..511
+//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 128 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+  #endif
+
+  /* repeat this for all possible ITNS elements */
+
+}
+
+#endif  /* PARTITION_ARMCM33_H */
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c
new file mode 100644
index 00000000..5ee4322c
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     startup_ARMCM33.c
+ * @brief    CMSIS Core Device Startup File for Cortex-M33 Device
+ * @version  V2.0.0
+ * @date     20. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+  #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+  #include "ARMCM33_TZ.h"
+#elif defined (ARMCM33_DSP_FP)
+  #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+  #include "ARMCM33_DSP_FP_TZ.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __NO_RETURN;
+void Reset_Handler  (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __VECTOR_TABLE[496];
+       const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+  (pFunc)(&__INITIAL_SP),                   /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  SecureFault_Handler,                      /*  -9 Secure Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 480 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+
+  SystemInit();                             /* CMSIS System Initialization */
+  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+  while(1);
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
new file mode 100644
index 00000000..17679234
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
@@ -0,0 +1,99 @@
+/**************************************************************************//**
+ * @file     system_ARMCM33.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+  #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+  #include "ARMCM33_TZ.h"
+
+  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+    #include "partition_ARMCM33.h"
+  #endif
+#elif defined (ARMCM33_DSP_FP)
+  #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+  #include "ARMCM33_DSP_FP_TZ.h"
+
+  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+    #include "partition_ARMCM33.h"
+  #endif
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (XTAL / 2U)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                 (3U << 11U*2U)  );         /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  TZ_SAU_Setup();
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h
new file mode 100644
index 00000000..78d1b429
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'demo_threadx_non-secure_zone' 
+ * Target:  'FVP Simulation Model' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h
new file mode 100644
index 00000000..1eb74752
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'ThreadX_Library' 
+ * Target:  'ThreadX_Library_Project' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt
new file mode 100644
index 00000000..7ec4b36b
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt
@@ -0,0 +1,305 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ThreadX_Demo</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>-1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon></pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMRTXEVENTFLAGS</Key>
+          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGDARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name>-T5F</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <WatchWindow1>
+        <Ww>
+          <count>0</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_0_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>1</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_1_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>2</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_2_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>3</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_3_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>4</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_4_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>5</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_5_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>6</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>_tx_thread_current_ptr</ItemText>
+        </Ww>
+      </WatchWindow1>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Group</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\tx_initialize_low_level.s</PathWithFileName>
+      <FilenameWithoutPath>tx_initialize_low_level.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>1</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\demo_threadx.c</PathWithFileName>
+      <FilenameWithoutPath>demo_threadx.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+      <WindowPosition>
+        <length>44</length>
+        <flags>0</flags>
+        <showCmd>1</showCmd>
+        <MinPosition>
+          <xPos>-1</xPos>
+          <yPos>-1</yPos>
+        </MinPosition>
+        <MaxPosition>
+          <xPos>-1</xPos>
+          <yPos>-1</yPos>
+        </MaxPosition>
+        <NormalPosition>
+          <Top>56</Top>
+          <Left>12</Left>
+          <Right>1633</Right>
+          <Bottom>671</Bottom>
+        </NormalPosition>
+      </WindowPosition>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Library_Group</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>4</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\ThreadX_Library.lib</PathWithFileName>
+      <FilenameWithoutPath>ThreadX_Library.lib</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj
new file mode 100644
index 00000000..5f5dcbdb
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj
@@ -0,0 +1,556 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ThreadX_Demo</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M4 FPU</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId>5237</DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Luminary\</RegisterFilePath>
+          <DBRegisterFilePath>Luminary\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\</OutputDirectory>
+          <OutputName>threadx_demo</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4F</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4F</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>1</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>0</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>-1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver></Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>0</hadIROM>
+            <hadIRAM>0</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>0</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>0</RoSelD>
+            <RwSelD>0</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>0</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--first __tx_vectors --entry=__main</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Group</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>1</RVCTCodeConst>
+              <RVCTZI>1</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>2</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>0</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>0</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <uGnu>2</uGnu>
+                <useXO>2</useXO>
+                <v6Lang>0</v6Lang>
+                <v6LangP>0</v6LangP>
+                <vShortEn>2</vShortEn>
+                <vShortWch>2</vShortWch>
+                <v6Lto>2</v6Lto>
+                <v6WtE>2</v6WtE>
+                <v6Rtti>2</v6Rtti>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <uClangAs>2</uClangAs>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>tx_initialize_low_level.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\tx_initialize_low_level.s</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>2</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Aads>
+                    <interw>2</interw>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <thumb>1</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
+                    <uSurpInc>2</uSurpInc>
+                    <useXO>2</useXO>
+                    <uClangAs>2</uClangAs>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Aads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>demo_threadx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\demo_threadx.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Library_Group</GroupName>
+          <Files>
+            <File>
+              <FileName>ThreadX_Library.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>.\ThreadX_Library.lib</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx
new file mode 100644
index 00000000..bc65c4e5
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx
@@ -0,0 +1,342 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>FVP Simulation Model</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>15</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>..\Debug.ini</tIfile>
+        <pMon>BIN\DbgFMv8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>PWSTATINFO</Key>
+          <Name>200,50,700</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(6010=1243,118,1720,714,0)(6018=1284,352,1473,701,0)(6019=1328,34,1517,370,0)(6008=-1,-1,-1,-1,0)(6009=969,18,1263,203,0)(6014=1111,129,1369,860,0)(6015=872,146,1130,768,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=511,345,1277,660,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DbgFMv8M</Key>
+          <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -PF -MA</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <WatchWindow1>
+        <Ww>
+          <count>0</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_0_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>1</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_1_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>2</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_2_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>3</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_3_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>4</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_4_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>5</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_5_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>6</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_6_counter</ItemText>
+        </Ww>
+        <Ww>
+          <count>7</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>thread_7_counter</ItemText>
+        </Ww>
+      </WatchWindow1>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>2</SubType>
+          <ItemText>0x20200a10</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
+      <MemoryWindow2>
+        <Mm>
+          <WinNumber>2</WinNumber>
+          <SubType>2</SubType>
+          <ItemText>0xE000ED28</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow2>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>1</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Non-secure Code</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>4</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\ThreadX_Library.lib</PathWithFileName>
+      <FilenameWithoutPath>ThreadX_Library.lib</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\sample_threadx_module_manager.c</PathWithFileName>
+      <FilenameWithoutPath>sample_threadx_module_manager.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>CMSE Library</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\demo_secure_zone\interface.h</PathWithFileName>
+      <FilenameWithoutPath>interface.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>3</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</PathWithFileName>
+      <FilenameWithoutPath>demo_secure_zone_CMSE_Lib.o</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::Device</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx
new file mode 100644
index 00000000..a9797aec
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx
@@ -0,0 +1,585 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP Simulation Model</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM33_DSP_FP_TZ</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.7.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>demo_threadx_non-secure_zone</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
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+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
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+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
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+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
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+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
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+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>0</Capability>
+            <DriverSelection>-1</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
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+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M33"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
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+            <hadIROM2>1</hadIROM2>
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+            <useUlib>1</useUlib>
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+            <RoSelD>4</RoSelD>
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+              </OCR_RVCT10>
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+              <MiscControls>-Wno-unused-function -Wno-visibility -Wno-missing-noreturn -Wno-unused-parameter</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\..\..\common\inc, ..\..\inc, ..\..\..\..\..\common_modules\inc</IncludePath>
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+              <Define></Define>
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+            <ScatterFile>.\RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_AC6.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Non-secure Code</GroupName>
+          <Files>
+            <File>
+              <FileName>ThreadX_Library.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>..\ThreadX_Library.lib</FilePath>
+            </File>
+            <File>
+              <FileName>sample_threadx_module_manager.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\sample_threadx_module_manager.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSE Library</GroupName>
+          <Files>
+            <File>
+              <FileName>interface.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\demo_secure_zone\interface.h</FilePath>
+            </File>
+            <File>
+              <FileName>demo_secure_zone_CMSE_Lib.o</FileName>
+              <FileType>3</FileType>
+              <FilePath>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis>
+      <api Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </api>
+    </apis>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.0" condition="ARMCM33 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
+        <instance index="0" removed="1">RTE\CMSIS\RTX_Config.c</instance>
+        <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 NS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
+        <instance index="0" removed="1">RTE\CMSIS\RTX_Config.h</instance>
+        <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 NS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.1">
+        <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.0" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.0.0">
+        <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM33_TZ\partition_ARMCM33.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM33_TZ\startup_ARMCM33.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM33_TZ\system_ARMCM33.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="Device\ARM\ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMv8MBL\partition_ARMv8MBL.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMv8MBL\Source\ARM\startup_ARMv8MBL.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMv8MBL\startup_ARMv8MBL.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMv8MBL\Source\system_ARMv8MBL.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMv8MBL\system_ARMv8MBL.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="CMSIS\Config\RTE_Device.h" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+        <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="Device\CMSDK_ARMv8MBL\Include\Template\partition_CMSDK_ARMv8MBL.h" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+        <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" condition="ARMCC" name="Device\CMSDK_ARMv8MBL\Source\ARM\startup_CMSDK_ARMv8MBL.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+        <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Device\CMSDK_ARMv8MBL\Source\system_CMSDK_ARMv8MBL.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+        <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>&lt;Project Info&gt;</LayName>
+        <LayDesc></LayDesc>
+        <LayUrl></LayUrl>
+        <LayKeys></LayKeys>
+        <LayCat></LayCat>
+        <LayLic></LayLic>
+        <LayTarg>0</LayTarg>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>
diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c
new file mode 100644
index 00000000..93dd8379
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c
@@ -0,0 +1,130 @@
+/* Small demonstration of the ThreadX module manager.  */
+
+#include "tx_api.h"
+#include "txm_module.h"
+
+
+#define DEMO_STACK_SIZE         1024
+
+/* Define the ThreadX object control blocks...  */
+
+static TX_THREAD                module_manager;
+static TXM_MODULE_INSTANCE      my_module;
+
+
+/* Define the object pool area.  */
+
+static UCHAR                    object_memory[16384];
+
+
+/* Define the module data pool area.  */
+
+#define MODULE_DATA_SIZE (64 * 1024)
+static UCHAR                    module_data_area[MODULE_DATA_SIZE];
+
+
+/* The module code should be loaded here.  */
+
+#define MODULE_CODE (0x00200000)
+
+
+/* Define the shared memory area.  */
+
+#define SHARED_MEMORY_SIZE      (256)
+static UCHAR                    shared_memory[SHARED_MEMORY_SIZE] __attribute__((aligned (32)));
+
+
+/* Define the count of memory faults.  */
+
+static ULONG                    memory_faults;
+
+
+/* Define thread prototypes.  */
+
+void    module_manager_entry(ULONG thread_input);
+
+
+/* Define fault handler.  */
+
+static VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module)
+{
+
+    /* Just increment the fault counter.   */
+    memory_faults++;
+}
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = (CHAR*)first_unused_memory;
+
+
+    tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0,  
+                     pointer, DEMO_STACK_SIZE, 
+                     1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+    pointer =  pointer + DEMO_STACK_SIZE;
+}
+
+
+
+
+/* Define the test threads.  */
+
+void    module_manager_entry(ULONG thread_input)
+{
+
+    (void)thread_input;
+    
+    tx_thread_secure_stack_allocate(&module_manager, 256);
+    
+    /* Initialize the module manager.   */
+    txm_module_manager_initialize((void *) module_data_area, MODULE_DATA_SIZE);
+
+    txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
+
+    /* Register a fault handler.  */
+    txm_module_manager_memory_fault_notify(module_fault_handler);
+    
+    /* Load the module that is already there, in this example it is placed there by the multiple image download.  */
+    txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE);
+    
+    /* Enable a read/write shared memory region.  */
+    txm_module_manager_external_memory_enable(&my_module, (void *) shared_memory, SHARED_MEMORY_SIZE, TXM_MODULE_ATTRIBUTE_READ_WRITE);
+    
+    /* Start the module.  */
+    txm_module_manager_start(&my_module);
+
+    /* Sleep for a while....  */
+    tx_thread_sleep(1000);
+    
+    /* Stop the module.  */
+    txm_module_manager_stop(&my_module);
+    
+    /* Unload the module.  */
+    txm_module_manager_unload(&my_module);
+
+    /* Load the module that is already there.  */
+    txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE);
+
+    /* Start the module again.  */
+    txm_module_manager_start(&my_module);
+    
+    /* Now just spin...  */
+    while(1)
+    {
+    
+        tx_thread_sleep(100);
+    }
+}
diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h
new file mode 100644
index 00000000..c930572b
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'sample_threadx_module' 
+ * Target:  'FVP Simulation Model' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c
new file mode 100644
index 00000000..e32c4ec6
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c
@@ -0,0 +1,438 @@
+/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes 
+   examples of eight threads of different priorities, using a message queue, semaphore, mutex, 
+   event flags group, byte pool, and block pool.  */
+
+/* Specify that this is a module!  */
+
+#define TXM_MODULE
+
+
+/* Include the ThreadX module definitions.  */
+
+#include "txm_module.h"
+
+
+#include "interface.h"
+
+/* Define constants.  */
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the external memory area.  */
+
+#define EXTERNAL_MEMORY_SIZE (64 * 1024)
+#define EXTERNAL_MEMORY (0x00200100)
+
+
+/* Define the pool space in the bss section of the module. ULONG is used to 
+   get the word alignment.  */
+
+ULONG                   demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4];
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               *thread_0;
+TX_THREAD               *thread_1;
+TX_THREAD               *thread_2;
+TX_THREAD               *thread_3;
+TX_THREAD               *thread_4;
+TX_THREAD               *thread_5;
+TX_THREAD               *thread_6;
+TX_THREAD               *thread_7;
+TX_QUEUE                *queue_0;
+TX_SEMAPHORE            *semaphore_0;
+TX_MUTEX                *mutex_0;
+TX_EVENT_FLAGS_GROUP    *event_flags_0;
+TX_BYTE_POOL            *byte_pool_0;
+TX_BLOCK_POOL           *block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter;
+ULONG           thread_1_counter;
+ULONG           thread_1_messages_sent;
+ULONG           thread_2_counter;
+ULONG           thread_2_messages_received;
+ULONG           thread_3_counter;
+ULONG           thread_4_counter;
+ULONG           thread_5_counter;
+ULONG           thread_6_counter;
+ULONG           thread_7_counter;
+ULONG           semaphore_0_puts;
+ULONG           event_0_sets;
+ULONG           queue_0_sends;
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+void  semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
+{
+
+    if (semaphore_ptr == semaphore_0)
+        semaphore_0_puts++;
+}
+
+
+void  event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
+{
+
+    if (event_flag_group_ptr == event_flags_0)
+        event_0_sets++;
+}
+
+
+void  queue_0_notify(TX_QUEUE *queue_ptr)
+{
+
+    if (queue_ptr == queue_0)
+        queue_0_sends++;
+}
+
+
+/* Define the module start function.  */
+
+void    demo_module_start(ULONG id)
+{
+
+CHAR    *pointer;
+
+    /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within
+       their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting 
+       the control block(s).  */
+    txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
+    txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
+    txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
+    txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
+    txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
+    txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
+    txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
+    txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
+    txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
+    txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
+    txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
+    txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
+    txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
+    txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
+                               
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    tx_queue_send_notify(queue_0, queue_0_notify);
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
+
+    tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(event_flags_0, "module event flags 0");
+
+    tx_event_flags_set_notify(event_flags_0, event_0_notify);
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+    
+    tx_thread_secure_stack_allocate(thread_0, 256);
+    thread_0_counter = func1(thread_0_counter);
+    tx_thread_secure_stack_free(thread_0);
+    
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+        
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+       
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+        /* Test external memory sharing.  */
+        // *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB;
+        
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.uvoptx b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.uvoptx
new file mode 100644
index 00000000..cef6b11f
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.uvoptx
@@ -0,0 +1,236 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>FVP Simulation Model</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
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+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
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+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>13</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2V8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
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+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Module Code</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\sample_threadx_module.c</PathWithFileName>
+      <FilenameWithoutPath>sample_threadx_module.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\txm_module_preamble.S</PathWithFileName>
+      <FilenameWithoutPath>txm_module_preamble.S</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>4</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\txm\Objects\txm.lib</PathWithFileName>
+      <FilenameWithoutPath>txm.lib</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>3</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</PathWithFileName>
+      <FilenameWithoutPath>demo_secure_zone_CMSE_Lib.o</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
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+    <cbSel>0</cbSel>
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+</ProjectOpt>
diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.uvprojx b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.uvprojx
new file mode 100644
index 00000000..282eca3f
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.uvprojx
@@ -0,0 +1,453 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP Simulation Model</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM33_DSP_FP_TZ</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.5.1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>sample_threadx_module</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4101</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M33"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>4</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x200000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20200000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>2</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>1</Ropi>
+            <Rwpi>1</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\..\..\common_modules\inc, ..\..\..\..\..\common\inc, ..\..\..\..\..\ports_module\cortex_m33\ac6\inc, ..\demo_secure_zone</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>1</Ropi>
+            <Rwpi>1</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>1</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>1</Ropi>
+            <Rwpi>1</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00200000</TextAddressRange>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry demo_module_start --first __txm_module_preamble</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Module Code</GroupName>
+          <Files>
+            <File>
+              <FileName>sample_threadx_module.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\sample_threadx_module.c</FilePath>
+            </File>
+            <File>
+              <FileName>txm_module_preamble.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\txm_module_preamble.S</FilePath>
+            </File>
+            <File>
+              <FileName>txm.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>..\txm\Objects\txm.lib</FilePath>
+            </File>
+            <File>
+              <FileName>demo_secure_zone_CMSE_Lib.o</FileName>
+              <FileType>3</FileType>
+              <FilePath>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <packages>
+      <filter>
+        <targetInfos/>
+      </filter>
+      <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1">
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model" versionMatchMode="fixed"/>
+        </targetInfos>
+      </package>
+    </packages>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
+        <targetInfos>
+          <targetInfo name="FVP Simulation Model"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>&lt;Project Info&gt;</LayName>
+        <LayDesc></LayDesc>
+        <LayUrl></LayUrl>
+        <LayKeys></LayKeys>
+        <LayCat></LayCat>
+        <LayLic></LayLic>
+        <LayTarg>0</LayTarg>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>
diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S
new file mode 100644
index 00000000..f6530c9f
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S
@@ -0,0 +1,66 @@
+    .text
+    .align 4
+    .syntax unified
+    .section RESET
+    
+    // Define public symbols
+    .global __txm_module_preamble
+
+    // Define application-specific start/stop entry points for the module
+    .global demo_module_start
+
+    // Define common external references
+    .global  _txm_module_thread_shell_entry
+    .global  _txm_module_callback_request_thread_entry
+
+    .eabi_attribute Tag_ABI_PCS_RO_data, 1
+    .eabi_attribute Tag_ABI_PCS_R9_use,  1
+    .eabi_attribute Tag_ABI_PCS_RW_data, 2
+
+__txm_module_preamble:
+    .dc.l   0x4D4F4455                                          // Module ID
+    .dc.l   0x6                                                 // Module Major Version
+    .dc.l   0x1                                                 // Module Minor Version
+    .dc.l   32                                                  // Module Preamble Size in 32-bit words
+    .dc.l   0x12345678                                          // Module ID (application defined)
+    .dc.l   0x01000007                                          // Module Properties where:
+                                                                //   Bits 31-24: Compiler ID
+                                                                //           0 -> IAR
+                                                                //           1 -> ARM
+                                                                //           2 -> GNU
+                                                                //   Bit 0:  0 -> Privileged mode execution
+                                                                //           1 -> User mode execution
+                                                                //   Bit 1:  0 -> No MPU protection
+                                                                //           1 -> MPU protection (must have user mode selected)
+                                                                //   Bit 2:  0 -> Disable shared/external memory access
+                                                                //           1 -> Enable shared/external memory access
+    .dc.l   _txm_module_thread_shell_entry - __txm_module_preamble // Module Shell Entry Point
+    .dc.l   demo_module_start - __txm_module_preamble           // Module Start Thread Entry Point
+    .dc.l   0                                                   // Module Stop Thread Entry Point
+    .dc.l   1                                                   // Module Start/Stop Thread Priority
+    .dc.l   1024                                                // Module Start/Stop Thread Stack Size
+    .dc.l   _txm_module_callback_request_thread_entry - __txm_module_preamble // Module Callback Thread Entry
+    .dc.l   1                                                   // Module Callback Thread Priority
+    .dc.l   1024                                                // Module Callback Thread Stack Size
+    //the tools can't add two symbols together, but it should look like this:
+    //.dc.l   Image$$ER_RO$$Length + Image$$ER_RW$$Length         // Module Code Size
+    //.dc.l   Image$$ER_RW$$Length + Image$$ER_ZI$$ZI$$Length     // Module Data Size
+    //so instead we'll define hard values:
+    .dc.l   0x4000                                              // Module Code Size
+    .dc.l   0x4000                                              // Module Data Size
+    .dc.l   0                                                   // Reserved 0
+    .dc.l   0                                                   // Reserved 1
+    .dc.l   0                                                   // Reserved 2
+    .dc.l   0                                                   // Reserved 3
+    .dc.l   0                                                   // Reserved 4
+    .dc.l   0                                                   // Reserved 5
+    .dc.l   0                                                   // Reserved 6
+    .dc.l   0                                                   // Reserved 7
+    .dc.l   0                                                   // Reserved 8
+    .dc.l   0                                                   // Reserved 9
+    .dc.l   0                                                   // Reserved 10
+    .dc.l   0                                                   // Reserved 11
+    .dc.l   0                                                   // Reserved 12
+    .dc.l   0                                                   // Reserved 13
+    .dc.l   0                                                   // Reserved 14
+    .dc.l   0                                                   // Reserved 15
diff --git a/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S
new file mode 100644
index 00000000..feb9e0ed
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S
@@ -0,0 +1,268 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+SYSTEM_CLOCK        =     6000000
+SYSTICK_CYCLES      =     ((SYSTEM_CLOCK / 100) -1)
+
+/* Setup the stack and heap areas.  */
+
+STACK_SIZE          =     0x00000400
+HEAP_SIZE           =     0x00000000
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_initialize_low_level                          Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for any low-level processor            */
+/*    initialization, including setting up interrupt vectors, setting     */
+/*    up a periodic timer interrupt source, saving the system stack       */
+/*    pointer for use in ISR processing later, and finding the first      */
+/*    available RAM memory address for tx_application_define.             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_initialize_low_level(VOID)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_initialize_low_level
+    .thumb_func
+.type _tx_initialize_low_level, function
+_tx_initialize_low_level:
+
+    /* Disable interrupts during ThreadX initialization.  */
+    CPSID   i
+
+    /* Set base of available memory to end of non-initialised RAM area.  */
+    LDR     r0, =_tx_initialize_unused_memory       // Build address of unused memory pointer
+    LDR     r1, =Image$$ARM_LIB_STACK$$ZI$$Limit    // Build first free address
+    ADD     r1, r1, #4                              //
+    STR     r1, [r0]                                // Setup first unused memory pointer
+
+    /* Setup Vector Table Offset Register.  */
+    MOV     r0, #0xE000E000                         // Build address of NVIC registers
+    LDR     r1, =__Vectors                          // Pickup address of vector table
+    STR     r1, [r0, #0xD08]                        // Set vector table address
+
+    /* Enable the cycle count register.  */
+    LDR     r0, =0xE0001000                         // Build address of DWT register
+    LDR     r1, [r0]                                // Pickup the current value
+    ORR     r1, r1, #1                              // Set the CYCCNTENA bit
+    STR     r1, [r0]                                // Enable the cycle count register
+
+    /* Set system stack pointer from vector value.  */
+    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
+    LDR     r1, =__Vectors                          // Pickup address of vector table
+    LDR     r1, [r1]                                // Pickup reset stack pointer
+    STR     r1, [r0]                                // Save system stack pointer
+
+    /* Configure SysTick.  */
+    MOV     r0, #0xE000E000                         // Build address of NVIC registers
+    LDR     r1, =SYSTICK_CYCLES
+    STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
+    MOV     r1, #0x7                                // Build SysTick Control Enable Value
+    STR     r1, [r0, #0x10]                         // Setup SysTick Control
+
+    /* Configure handler priorities.  */
+    LDR     r1, =0x00000000                         // Rsrv, UsgF, BusF, MemM
+    STR     r1, [r0, #0xD18]                        // Setup System Handlers 4-7 Priority Registers
+
+    LDR     r1, =0xFF000000                         // SVCl, Rsrv, Rsrv, Rsrv
+    STR     r1, [r0, #0xD1C]                        // Setup System Handlers 8-11 Priority Registers
+                                                    // Note: SVC must be lowest priority, which is 0xFF
+
+    LDR     r1, =0x40FF0000                         // SysT, PnSV, Rsrv, DbgM
+    STR     r1, [r0, #0xD20]                        // Setup System Handlers 12-15 Priority Registers
+                                                    // Note: PnSV must be lowest priority, which is 0xFF
+
+    /* Return to caller.  */
+    BX      lr
+// }
+
+
+/* Define shells for each of the unused vectors.  */
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  __tx_BadHandler
+    .thumb_func
+.type __tx_BadHandler, function
+__tx_BadHandler:
+    B       __tx_BadHandler
+
+
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  __tx_IntHandler
+    .thumb_func
+.type __tx_IntHandler, function
+__tx_IntHandler:
+// VOID InterruptHandler (VOID)
+// {
+    PUSH    {r0,lr}     // Save LR (and dummy r0 to maintain stack alignment)
+
+    /* Do interrupt handler work here */
+    /* .... */
+
+    POP     {r0,lr}
+    BX      LR
+// }
+
+
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  SysTick_Handler
+    .thumb_func
+.type SysTick_Handler, function
+SysTick_Handler:
+// VOID TimerInterruptHandler (VOID)
+// {
+    PUSH    {r0,lr}     // Save LR (and dummy r0 to maintain stack alignment)
+    BL      _tx_timer_interrupt
+    POP     {r0,lr}
+    BX      LR
+// }
+
+
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  HardFault_Handler
+    .thumb_func
+.type HardFault_Handler, function
+HardFault_Handler:
+    B       HardFault_Handler
+
+
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  UsageFault_Handler
+    .thumb_func
+.type UsageFault_Handler, function
+UsageFault_Handler:
+    CPSID   i                                       // Disable interrupts
+    // Check for stack limit fault
+    LDR     r0, =0xE000ED28                         // CFSR address
+    LDR     r1,[r0]                                 // Pick up CFSR
+    TST     r1, #0x00100000                         // Check for Stack Overflow
+_unhandled_usage_loop:
+    BEQ     _unhandled_usage_loop                   // If not stack overflow then loop
+
+    // Handle stack overflow
+    STR     r1, [r0]                                // Clear CFSR flag(s)
+
+#ifdef __ARM_PCS_VFP
+    LDR     r0, =0xE000EF34                         // Cleanup FPU context: Load FPCCR address
+    LDR     r1, [r0]                                // Load FPCCR
+    BIC     r1, r1, #1                              // Clear the lazy preservation active bit
+    STR     r1, [r0]                                // Store the value
+#endif
+
+    LDR     r0, =_tx_thread_current_ptr             // Build current thread pointer address
+    LDR     r0,[r0]                                 // Pick up current thread pointer
+    PUSH    {r0,lr}                                 // Save LR (and r0 to maintain stack alignment)
+    BL      _tx_thread_stack_error_handler          // Call ThreadX/user handler
+    POP     {r0,lr}                                 // Restore LR and dummy reg
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    // Call the thread exit function to indicate the thread is no longer executing.
+    PUSH    {r0, lr}                                // Save LR (and r0 just for alignment)
+    BL      _tx_execution_thread_exit               // Call the thread exit function
+    POP     {r0, lr}                                // Recover LR
+#endif
+
+    MOV     r1, #0                                  // Build NULL value
+    LDR     r0, =_tx_thread_current_ptr             // Pickup address of current thread pointer
+    STR     r1, [r0]                                // Clear current thread pointer
+
+    // Return from UsageFault_Handler exception
+    LDR     r0, =0xE000ED04                         // Load ICSR
+    LDR     r1, =0x10000000                         // Set PENDSVSET bit
+    STR     r1, [r0]                                // Store ICSR
+    DSB                                             // Wait for memory access to complete
+    CPSIE   i                                       // Enable interrupts
+    BX      lr                                      // Return from exception
+
+
+
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  __tx_NMIHandler
+    .thumb_func
+.type __tx_NMIHandler, function
+__tx_NMIHandler:
+    B       __tx_NMIHandler
+
+
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  __tx_DBGHandler
+    .thumb_func
+.type __tx_DBGHandler, function
+__tx_DBGHandler:
+    B       __tx_DBGHandler
+
+    .end
diff --git a/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h
new file mode 100644
index 00000000..014a2a2b
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'txm' 
+ * Target:  'ThreadX Module Library' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/ports_module/cortex_m33/ac6/example_build/txm/txm.uvoptx b/ports_module/cortex_m33/ac6/example_build/txm/txm.uvoptx
new file mode 100644
index 00000000..dab51218
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/txm/txm.uvoptx
@@ -0,0 +1,1412 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ThreadX Module Library</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>13</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2V8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Group</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c</PathWithFileName>
+      <FilenameWithoutPath>txm_block_allocate.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c</PathWithFileName>
+      <FilenameWithoutPath>txm_block_pool_create.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c</PathWithFileName>
+      <FilenameWithoutPath>txm_block_pool_delete.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c</PathWithFileName>
+      <FilenameWithoutPath>txm_block_pool_info_get.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>5</FileNumber>
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+      <tvExpOptDlg>0</tvExpOptDlg>
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+      <FilenameWithoutPath>txm_block_pool_performance_info_get.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
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+      <FileNumber>6</FileNumber>
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+      <FilenameWithoutPath>txm_block_release.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
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+    </File>
+    <File>
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+    </File>
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+      <FilenameWithoutPath>txm_byte_pool_delete.c</FilenameWithoutPath>
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+    </File>
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+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
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+      <GroupNumber>1</GroupNumber>
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+    </File>
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+      <FilenameWithoutPath>txm_byte_release.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>17</FileNumber>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c</PathWithFileName>
+      <FilenameWithoutPath>txm_event_flags_create.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
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new file mode 100644
index 00000000..29432101
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/example_build/txm/txm.uvprojx
@@ -0,0 +1,943 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ThreadX Module Library</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM33_DSP_FP_TZ</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.5.1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>txm</OutputName>
+          <CreateExecutable>0</CreateExecutable>
+          <CreateLib>1</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
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+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
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+            <UserProg1Name></UserProg1Name>
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+            <nStopA1X>0</nStopA1X>
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+          </AfterMake>
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+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
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+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
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+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
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+          <TargetDllArguments> -MPU</TargetDllArguments>
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+          <OPTHX>
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+        </DebugOption>
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+            <RunIndependent>0</RunIndependent>
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+          <Flash3></Flash3>
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+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
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+        <TargetArmAds>
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+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
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+            <RvctDeviceName></RvctDeviceName>
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+            <hadIRAM>1</hadIRAM>
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+      <Groups>
+        <Group>
+          <GroupName>Source Group</GroupName>
+          <Files>
+            <File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_block_release.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c</FilePath>
+            </File>
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+            </File>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_byte_release.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c</FilePath>
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+            <File>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c</FilePath>
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+              <FileName>txm_mutex_create.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c</FilePath>
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+              <FileName>txm_mutex_delete.c</FileName>
+              <FileType>1</FileType>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c</FilePath>
+            </File>
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+              <FileName>txm_mutex_performance_system_info_get.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c</FilePath>
+            </File>
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+              <FileName>txm_mutex_put.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_create.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_send.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c</FilePath>
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+              <FileType>1</FileType>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c</FilePath>
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+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c</FilePath>
+            </File>
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+              <FileName>txm_semaphore_put.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c</FilePath>
+            </File>
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+              <FileName>txm_semaphore_put_notify.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c</FilePath>
+            </File>
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+              <FileName>txm_thread_create.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_create.c</FilePath>
+            </File>
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+              <FileName>txm_thread_delete.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c</FilePath>
+            </File>
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+              <FileName>txm_thread_entry_exit_notify.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c</FilePath>
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+              <FileName>txm_thread_terminate.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c</FilePath>
+            </File>
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+              <FileName>txm_thread_wait_abort.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c</FilePath>
+            </File>
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+              <FileName>txm_time_get.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_time_get.c</FilePath>
+            </File>
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+              <FileName>txm_time_set.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_time_set.c</FilePath>
+            </File>
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+              <FileName>txm_timer_activate.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c</FilePath>
+            </File>
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+              <FileName>txm_timer_change.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_change.c</FilePath>
+            </File>
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+              <FileName>txm_timer_create.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_create.c</FilePath>
+            </File>
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+              <FileName>txm_timer_deactivate.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c</FilePath>
+            </File>
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+              <FileName>txm_timer_delete.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c</FilePath>
+            </File>
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+              <FileName>txm_timer_info_get.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c</FilePath>
+            </File>
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+              <FileName>txm_timer_performance_info_get.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c</FilePath>
+            </File>
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+              <FileName>txm_timer_performance_system_info_get.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c</FilePath>
+            </File>
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+              <FileName>txm_trace_buffer_full_notify.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c</FilePath>
+            </File>
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+              <FileName>txm_trace_disable.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c</FilePath>
+            </File>
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+              <FileName>txm_trace_enable.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c</FilePath>
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+              <FileName>txm_trace_event_filter.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c</FilePath>
+            </File>
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+              <FileName>txm_trace_event_unfilter.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c</FilePath>
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+              <FileName>txm_trace_interrupt_control.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_interrupt_control.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c</FilePath>
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diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h
new file mode 100644
index 00000000..c0b14d97
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/inc/tx_port.h
@@ -0,0 +1,583 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-M33/AC6    */
+/*                                                            6.1.3       */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+/* Determine if the optional ThreadX user define file should be used.  */
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+/* Define compiler library include files.  */
+
+#include <stdlib.h>
+#include <string.h>
+#include <arm_compat.h>
+#include "ARMCM33_DSP_FP_TZ.h"          /* For intrinsic functions. */
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef unsigned long long                      ULONG64;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+/* Function prototypes for this port. */
+struct  TX_THREAD_STRUCT;
+UINT    _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size);
+UINT    _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
+UINT    _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
+UINT    _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
+
+/* This hardware has stack checking that we take advantage of - do NOT define. */
+#ifdef TX_ENABLE_STACK_CHECKING
+    #error "Do not define TX_ENABLE_STACK_CHECKING"
+#endif
+
+/* If user does not want to terminate thread on stack overflow, 
+   #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol.
+   The thread will be rescheduled and continue to cause the exception.
+   It is suggested user code handle this by registering a notification with the
+   tx_thread_stack_error_notify function. */
+/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */
+
+/* Define the system API mappings based on the error checking 
+   selected by the user.  Note: this section is only applicable to 
+   application source code, hence the conditional that turns off this
+   stuff when the include file is processed by the ThreadX source. */
+
+#ifndef TX_SOURCE_CODE
+
+
+/* Determine if error checking is desired.  If so, map API functions 
+   to the appropriate error checking front-ends.  Otherwise, map API
+   functions to the core functions that actually perform the work. 
+   Note: error checking is enabled by default.  */
+
+#ifdef TX_DISABLE_ERROR_CHECKING
+
+/* Services without error checking.  */
+
+#define tx_thread_secure_stack_allocate   _tx_thread_secure_stack_allocate
+#define tx_thread_secure_stack_free       _tx_thread_secure_stack_free
+
+#else
+
+/* Services with error checking.  */
+
+#define tx_thread_secure_stack_allocate   _txe_thread_secure_stack_allocate
+#define tx_thread_secure_stack_free       _txe_thread_secure_stack_free
+
+#endif
+#endif
+
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex-M33 port.  */
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0xE0001004)
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (0)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0
+#define TX_THREAD_EXTENSION_1
+#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
+#define TX_THREAD_EXTENSION_2                   VOID    *tx_thread_module_instance_ptr;         \
+                                                VOID    *tx_thread_module_entry_info_ptr;       \
+                                                ULONG   tx_thread_module_current_user_mode;     \
+                                                ULONG   tx_thread_module_user_mode;             \
+                                                ULONG   tx_thread_module_saved_lr;              \
+                                                VOID    *tx_thread_module_kernel_stack_start;   \
+                                                VOID    *tx_thread_module_kernel_stack_end;     \
+                                                ULONG   tx_thread_module_kernel_stack_size;     \
+                                                VOID    *tx_thread_module_stack_ptr;            \
+                                                VOID    *tx_thread_module_stack_start;          \
+                                                VOID    *tx_thread_module_stack_end;            \
+                                                ULONG   tx_thread_module_stack_size;            \
+                                                VOID    *tx_thread_module_reserved;             \
+                                                VOID   *tx_thread_secure_stack_context;
+#else
+#define TX_THREAD_EXTENSION_2                   VOID    *tx_thread_module_instance_ptr;         \
+                                                VOID    *tx_thread_module_entry_info_ptr;       \
+                                                ULONG   tx_thread_module_current_user_mode;     \
+                                                ULONG   tx_thread_module_user_mode;             \
+                                                ULONG   tx_thread_module_saved_lr;              \
+                                                VOID    *tx_thread_module_kernel_stack_start;   \
+                                                VOID    *tx_thread_module_kernel_stack_end;     \
+                                                ULONG   tx_thread_module_kernel_stack_size;     \
+                                                VOID    *tx_thread_module_stack_ptr;            \
+                                                VOID    *tx_thread_module_stack_start;          \
+                                                VOID    *tx_thread_module_stack_end;            \
+                                                ULONG   tx_thread_module_stack_size;            \
+                                                VOID    *tx_thread_module_reserved;
+#endif
+#define TX_THREAD_EXTENSION_3
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
+
+#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)  if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);}
+#else
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
+#endif
+
+#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
+/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */
+#define TX_TIMER_THREAD_SECURE_STACK_SIZE   256
+#define TX_TIMER_INITIALIZE_EXTENSION(status)   _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE);
+#endif
+
+
+#ifndef TX_MISRA_ENABLE
+
+//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
+inline static unsigned int _get_ipsr(void);
+inline static unsigned int _get_ipsr(void)
+{
+    unsigned int _ipsr;
+    __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
+    return _ipsr;
+}
+
+#endif
+
+
+#ifdef __ARM_PCS_VFP
+
+#ifdef TX_MISRA_ENABLE
+
+ULONG  _tx_misra_control_get(void);
+void   _tx_misra_control_set(ULONG value);
+ULONG  _tx_misra_fpccr_get(void);
+void   _tx_misra_vfp_touch(void);
+
+#else
+
+#ifdef TX_SOURCE_CODE
+
+static unsigned int _get_control(void);
+static unsigned int _get_control(void)
+{
+    unsigned int _control;
+    __asm("MRS %[result], control" : [result] "=r" (_control) : );
+    return _control;
+}
+
+static void _set_control(unsigned int _control);
+static void _set_control(unsigned int _control)
+{
+    __asm("MSR control, %[input]" : : [input] "r" (_control));
+}
+
+#endif
+#endif
+
+/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
+   in order to ensure no lazy stacking will occur. */
+
+#ifndef TX_MISRA_ENABLE
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _get_control();                                                                \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _set_control(_tx_vfp_state);;                                                           \
+                                                                    }
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _tx_misra_control_get();                                                 \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _tx_misra_control_set(_tx_vfp_state);                                                     \
+                                                                    }
+                                                                    
+#endif
+
+/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
+   If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
+   this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush 
+   the lazy FPU save, then restore the CONTROL.FPCA state. */
+
+#ifndef TX_MISRA_ENABLE
+
+void _tx_vfp_access(void);
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _get_control();                                                            \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _set_control(_tx_vfp_state);                                                       \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  *((ULONG *) 0xE000EF34);                                                 \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state =  _get_control();                                                        \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_vfp_access();                                                                 \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _get_control();                                                    \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _set_control(_tx_vfp_state);                                               \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#else
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _tx_misra_control_get();                                             \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _tx_misra_control_set(_tx_vfp_state);                                                 \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  _tx_misra_fpccr_get();                                                   \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state = _tx_misra_control_get();                                          \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_misra_vfp_touch();                                                            \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _tx_misra_control_get();                                     \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _tx_misra_control_set(_tx_vfp_state);                                         \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#endif
+
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+#endif
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Define the get system state macro.   */
+   
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+#ifndef TX_MISRA_ENABLE
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _get_ipsr())
+#else
+ULONG   _tx_misra_ipsr_get(VOID);
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _tx_misra_ipsr_get())
+#endif
+#endif
+
+
+/* Define the check for whether or not to call the _tx_thread_system_return function.  A non-zero value
+   indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
+   for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
+   zero after initialization for Cortex-M ports. */
+
+#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
+#define TX_THREAD_SYSTEM_RETURN_CHECK(c)    (c) = ((ULONG) _tx_thread_preempt_disable);
+#endif
+
+#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
+/* Initialize secure stacks for threads calling secure functions. */
+extern void    _tx_thread_secure_stack_initialize(void);
+#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION            _tx_thread_secure_stack_initialize();
+#endif
+
+/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to 
+   prevent early scheduling on Cortex-M parts.  */
+   
+#define TX_PORT_SPECIFIC_POST_INITIALIZATION    _tx_thread_preempt_disable++;
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) = (UINT)__clz(__rbit((m)));
+
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int  was_masked;
+#define TX_DISABLE                              was_masked = __disable_irq();
+#define TX_RESTORE                              if (was_masked == 0) __enable_irq();
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+
+static void _tx_thread_system_return_inline(void)
+{
+unsigned int          was_masked;
+
+
+    /* Set PendSV to invoke ThreadX scheduler.  */
+    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    if (_get_ipsr() == 0)
+    {
+        was_masked = __disable_irq();
+        __enable_irq();
+        if (was_masked != 0)
+            __disable_irq();
+    }
+}
+#endif
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-M33/AC6 Version 6.1 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
diff --git a/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h
new file mode 100644
index 00000000..5493af01
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h
@@ -0,0 +1,60 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  COMPONENT DEFINITION                                   RELEASE        */
+/*                                                                        */
+/*    tx_secure_interface.h                               PORTABLE C      */
+/*                                                            6.1.3       */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file defines the ThreadX secure thread stack components,       */
+/*    including data types and external references.                       */
+/*    It is assumed that tx_api.h and tx_port.h have already been         */
+/*    included.                                                           */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_SECURE_INTERFACE_H
+#define TX_SECURE_INTERFACE_H
+
+/* Define internal secure thread stack function prototypes.  */
+
+extern void    _tx_thread_secure_stack_initialize(void);
+extern UINT    _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size);
+extern UINT    _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr);
+extern void    _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr);
+extern void    _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr);
+
+#endif
diff --git a/ports_module/cortex_m33/ac6/inc/txm_module_port.h b/ports_module/cortex_m33/ac6/inc/txm_module_port.h
new file mode 100644
index 00000000..6b846e72
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/inc/txm_module_port.h
@@ -0,0 +1,354 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
+/*                                                                        */
+/*    txm_module_port.h                               Cortex-M33/MPU/AC6  */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file defines the basic module constants, interface structures, */
+/*    and function prototypes.                                            */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TXM_MODULE_PORT_H
+#define TXM_MODULE_PORT_H
+
+/* Determine if the optional Modules user define file should be used.  */
+
+#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
+
+/* Yes, include the user defines in txm_module_user.h. The defines in this file may
+   alternately be defined on the command line.  */
+
+#include "txm_module_user.h"
+#endif
+
+/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
+  following extensions to the ThreadX thread control block (this code should replace
+  the corresponding macro define in tx_port.h):
+
+#define TX_THREAD_EXTENSION_2                   VOID    *tx_thread_module_instance_ptr;         \
+                                                VOID    *tx_thread_module_entry_info_ptr;       \
+                                                ULONG   tx_thread_module_current_user_mode;     \
+                                                ULONG   tx_thread_module_user_mode;             \
+                                                ULONG   tx_thread_module_saved_lr;              \
+                                                VOID    *tx_thread_module_kernel_stack_start;   \
+                                                VOID    *tx_thread_module_kernel_stack_end;     \
+                                                ULONG   tx_thread_module_kernel_stack_size;     \
+                                                VOID    *tx_thread_module_stack_ptr;            \
+                                                VOID    *tx_thread_module_stack_start;          \
+                                                VOID    *tx_thread_module_stack_end;            \
+                                                ULONG   tx_thread_module_stack_size;            \
+                                                VOID    *tx_thread_module_reserved;
+
+The following extensions must also be defined in tx_port.h:
+
+#define TX_EVENT_FLAGS_GROUP_EXTENSION          VOID    *tx_event_flags_group_module_instance; \
+                                                VOID   (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
+
+#define TX_QUEUE_EXTENSION                      VOID    *tx_queue_module_instance; \
+                                                VOID   (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
+
+#define TX_SEMAPHORE_EXTENSION                  VOID    *tx_semaphore_module_instance; \
+                                                VOID   (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
+
+#define TX_TIMER_EXTENSION                      VOID    *tx_timer_module_instance; \
+                                                VOID   (*tx_timer_module_expiration_function)(ULONG id);
+*/
+
+/* Define the kernel stack size for a module thread.  */
+#ifndef TXM_MODULE_KERNEL_STACK_SIZE
+#define TXM_MODULE_KERNEL_STACK_SIZE            768
+#endif
+
+/* Define constants specific to the tools the module can be built with for this particular modules port.  */
+
+#define TXM_MODULE_IAR_COMPILER                 0x00000000
+#define TXM_MODULE_RVDS_COMPILER                0x01000000
+#define TXM_MODULE_GNU_COMPILER                 0x02000000
+#define TXM_MODULE_COMPILER_MASK                0xFF000000
+#define TXM_MODULE_OPTIONS_MASK                 0x000000FF
+
+
+/* Define the properties for this particular module port.  */
+
+#define TXM_MODULE_PORT_DISPATCH
+
+#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
+
+#ifdef  TXM_MODULE_MEMORY_PROTECTION_ENABLED
+#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
+#else
+#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
+#endif
+
+#define TXM_MODULE_USER_MODE                        0x00000001
+#define TXM_MODULE_MEMORY_PROTECTION                0x00000002
+#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS    0x00000004
+
+
+/* Define the supported options for this module.   */
+
+#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS    (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
+#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS     0
+
+
+/* Define offset adjustments according to the compiler used to build the module.  */
+
+#define TXM_MODULE_IAR_SHELL_ADJUST             24
+#define TXM_MODULE_IAR_START_ADJUST             28
+#define TXM_MODULE_IAR_STOP_ADJUST              32
+#define TXM_MODULE_IAR_CALLBACK_ADJUST          44
+
+#define TXM_MODULE_RVDS_SHELL_ADJUST            0
+#define TXM_MODULE_RVDS_START_ADJUST            0
+#define TXM_MODULE_RVDS_STOP_ADJUST             0
+#define TXM_MODULE_RVDS_CALLBACK_ADJUST         0
+
+#define TXM_MODULE_GNU_SHELL_ADJUST             24
+#define TXM_MODULE_GNU_START_ADJUST             28
+#define TXM_MODULE_GNU_STOP_ADJUST              32
+#define TXM_MODULE_GNU_CALLBACK_ADJUST          44
+
+
+/* Define other module port-specific constants.  */
+
+/* Define INLINE_DECLARE to inline for ARM compiler.  */
+
+#define INLINE_DECLARE inline
+
+/* Define the number of MPU entries assigned to the code and data sections.
+   On Cortex-M33 devices, there are 8 total entries. ThreadX uses one for access
+   to the kernel entry function, one for module code protection, one for module data protection,
+   leaving five regions available for shared memory.  */
+#define TXM_MODULE_MPU_TOTAL_ENTRIES            8
+#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX       0
+#define TXM_MODULE_MPU_CODE_INDEX               1
+#define TXM_MODULE_MPU_DATA_INDEX               2
+
+#define TXM_MODULE_MPU_SHARED_INDEX             3
+#define TXM_MODULE_MPU_SHARED_ENTRIES           5
+
+#define TXM_MODULE_ATTRIBUTE_NON_SHAREABLE      0x00
+#define TXM_MODULE_ATTRIBUTE_OUTER_SHAREABLE    0x10
+#define TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE    0x18
+#define TXM_MODULE_ATTRIBUTE_READ_WRITE         0x02
+#define TXM_MODULE_ATTRIBUTE_READ_ONLY          0x06
+#define TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER      0x01
+#define TXM_MODULE_ATTRIBUTE_REGION_ENABLE      0x01
+#define TXM_MODULE_ATTRIBUTE_MASK               0x1E
+#define TXM_MODULE_ATTRIBUTE_INDEX              0x00
+
+/* MAIR_ATTR settings
+Device-nGnRE : 0b [Outer]0000 [Inner]0100
+Code WT   RA : 0b [Outer]1010 [Inner]1010
+DATA WBWA RA : 0b [Outer]1111 [Inner]1111
+*/
+
+/* Data aligned to 8 bytes (stacks must be 8-byte aligned).  */
+#define TXM_MODULE_DATA_ALIGNMENT               8
+
+/* MPU regions must be 32-byte aligned.  */
+#define TXM_MODULE_MPU_ALIGNMENT                32
+
+#define TXM_THREAD_SECURE_STACK_ALLOCATE_CALL   TXM_MODULE_PORT_EXTENSION_API_ID_START
+#define TXM_THREAD_SECURE_STACK_FREE_CALL       (TXM_MODULE_PORT_EXTENSION_API_ID_START+1)
+
+/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RLAR.  */
+typedef struct TXM_MODULE_MPU_INFO_STRUCT
+{
+    ULONG   txm_module_mpu_region_base_address;
+    ULONG   txm_module_mpu_region_limit_address;
+} TXM_MODULE_MPU_INFO;
+
+/* Define the port-extensions to the module manager instance structure.  */
+#define TXM_MODULE_MANAGER_PORT_EXTENSION                                                               \
+    TXM_MODULE_MPU_INFO     txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES];            \
+    ULONG                   txm_module_instance_shared_memory_count;                                    \
+    ULONG                   txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES];   \
+    ULONG                   txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
+
+
+/* Define the memory fault information structure that is populated when a memory fault occurs.  */
+
+typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
+{
+    TX_THREAD           *txm_module_manager_memory_fault_info_thread_ptr;
+    VOID                *txm_module_manager_memory_fault_info_code_location;
+    ULONG               txm_module_manager_memory_fault_info_shcsr;
+    ULONG               txm_module_manager_memory_fault_info_cfsr;
+    ULONG               txm_module_manager_memory_fault_info_mmfar;
+    ULONG               txm_module_manager_memory_fault_info_bfar;
+    ULONG               txm_module_manager_memory_fault_info_control;
+    ULONG               txm_module_manager_memory_fault_info_sp;
+    ULONG               txm_module_manager_memory_fault_info_r0;
+    ULONG               txm_module_manager_memory_fault_info_r1;
+    ULONG               txm_module_manager_memory_fault_info_r2;
+    ULONG               txm_module_manager_memory_fault_info_r3;
+    ULONG               txm_module_manager_memory_fault_info_r4;
+    ULONG               txm_module_manager_memory_fault_info_r5;
+    ULONG               txm_module_manager_memory_fault_info_r6;
+    ULONG               txm_module_manager_memory_fault_info_r7;
+    ULONG               txm_module_manager_memory_fault_info_r8;
+    ULONG               txm_module_manager_memory_fault_info_r9;
+    ULONG               txm_module_manager_memory_fault_info_r10;
+    ULONG               txm_module_manager_memory_fault_info_r11;
+    ULONG               txm_module_manager_memory_fault_info_r12;
+    ULONG               txm_module_manager_memory_fault_info_lr;
+    ULONG               txm_module_manager_memory_fault_info_xpsr;
+} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
+
+
+#define TXM_MODULE_MANAGER_FAULT_INFO                                               \
+    TXM_MODULE_MANAGER_MEMORY_FAULT_INFO    _txm_module_manager_memory_fault_info;
+
+
+/* Define the macro to check the code alignment.  */
+
+#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment)    \
+    {                                                                               \
+        ULONG   temp;                                                               \
+        temp =  (ULONG) module_location;                                            \
+        temp =  temp & (code_alignment - 1);                                        \
+        if (temp)                                                                   \
+        {                                                                           \
+            _tx_mutex_put(&_txm_module_manager_mutex);                              \
+            return(TXM_MODULE_ALIGNMENT_ERROR);                                     \
+        }                                                                           \
+    }
+
+
+/* Define the macro to adjust the alignment and size for code/data areas.  */
+
+#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment)   _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment);
+
+
+/* Define the macro to adjust the symbols in the module preamble.  */
+
+#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
+    if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER)         \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_IAR_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_IAR_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_IAR_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_IAR_CALLBACK_ADJUST;                 \
+    }                                                                               \
+    else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER)   \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_RVDS_SHELL_ADJUST;                   \
+        start_function_adjust =     TXM_MODULE_RVDS_START_ADJUST;                   \
+        stop_function_adjust =      TXM_MODULE_RVDS_STOP_ADJUST;                    \
+        callback_function_adjust =  TXM_MODULE_RVDS_CALLBACK_ADJUST;                \
+    }                                                                               \
+    else                                                                            \
+    {                                                                               \
+        shell_function_adjust =     TXM_MODULE_GNU_SHELL_ADJUST;                    \
+        start_function_adjust =     TXM_MODULE_GNU_START_ADJUST;                    \
+        stop_function_adjust =      TXM_MODULE_GNU_STOP_ADJUST;                     \
+        callback_function_adjust =  TXM_MODULE_GNU_CALLBACK_ADJUST;                 \
+    }
+
+
+/* Define the macro to populate the thread control block with module port-specific information.
+   Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
+*/
+
+#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance)                                                                    \
+    thread_ptr -> tx_thread_module_current_user_mode =  module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE;   \
+    thread_ptr -> tx_thread_module_user_mode =          module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE;   \
+    if (thread_ptr -> tx_thread_module_user_mode)                                                                                       \
+    {                                                                                                                                   \
+        thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher =   _txm_module_manager_user_mode_entry;               \
+    }                                                                                                                                   \
+    else                                                                                                                                \
+    {                                                                                                                                   \
+        thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher =   _txm_module_manager_kernel_dispatch;               \
+    }
+
+
+/* Define the macro to populate the module control block with module port-specific information.
+   If memory protection is enabled, set up the MPU registers.
+*/
+#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance)                                            \
+    if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE)               \
+    {                                                                                               \
+        if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)   \
+        {                                                                                           \
+            _txm_module_manager_mm_register_setup(module_instance);                                 \
+        }                                                                                           \
+    }                                                                                               \
+    else                                                                                            \
+    {                                                                                               \
+        /* Do nothing.  */                                                                          \
+    }
+
+/* Define the macro to perform port-specific functions when unloading the module.  */
+/* Nothing needs to be done for this port.  */
+#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
+
+
+/* Define the macros to perform port-specific checks when passing pointers to the kernel.  */
+
+/* Define macro to make sure object is inside the module's data.  */
+#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
+    _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
+
+/* Define some internal prototypes to this module port.  */
+
+#ifndef TX_SOURCE_CODE
+#define txm_module_manager_memory_fault_notify              _txm_module_manager_memory_fault_notify
+#endif
+
+
+#ifdef TX_SOURCE_CODE
+
+#endif
+
+#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES                                                                                \
+VOID  _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment);   \
+VOID  _txm_module_manager_memory_fault_handler(VOID);                                                                           \
+UINT  _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *));                     \
+VOID  _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance);                                              \
+UINT  _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size);           \
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2);
+
+
+#define TXM_MODULE_MANAGER_VERSION_ID   \
+CHAR                            _txm_module_manager_version_id[] =  \
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Module Cortex-M33/MPU/AC6 Version 6.1.3 *";
+
+#endif
diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S
new file mode 100644
index 00000000..a18327b2
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S
@@ -0,0 +1,103 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+    .global     __use_two_region_memory
+    .global     __scatterload
+
+    .eabi_attribute Tag_ABI_PCS_RO_data, 1
+    .eabi_attribute Tag_ABI_PCS_R9_use,  1
+    .eabi_attribute Tag_ABI_PCS_RW_data, 2
+
+    .text
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_initialize                          Cortex-M33/MPU/AC6  */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function initializes the module c runtime.                     */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    __scatterload                         Initialize C runtime          */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _txm_module_thread_shell_entry        Start module thread           */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _txm_module_initialize(VOID)
+    .global  _txm_module_initialize
+    .thumb_func
+_txm_module_initialize:
+    PUSH    {r4-r12,lr}                         // Save dregs and LR
+    //B       __scatterload                       // Call ARM func to initialize variables
+
+// Override the __rt_exit function.
+    .global  __rt_exit
+    .thumb_func
+__rt_exit:
+    POP     {r4-r12,lr}                         // Restore dregs and LR
+    BX      lr                                  // Return to caller
+
+#define TXM_MODULE_HEAP_SIZE 512
+
+// returns heap start address in  R0
+// returns heap end address in    R2
+// does not touch SP, it is already set up before the module runs
+    .global __user_setup_stackheap
+    .thumb_func
+__user_setup_stackheap:
+    LDR     r1, _txm_heap                       // load heap offset
+    MOV     r2, TXM_MODULE_HEAP_SIZE            // load heap size
+    ADD     r2, r2, r0                          // calculate heap end address
+    BX      lr
+
+// dummy main function
+    .global main
+    .thumb_func
+main:
+    BX      lr
+
+    .align 8
+_txm_heap:
+    .zero   TXM_MODULE_HEAP_SIZE
diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c
new file mode 100644
index 00000000..55bb7e7d
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c
@@ -0,0 +1,172 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#ifndef TXM_MODULE
+#define TXM_MODULE
+#endif
+
+#ifndef TX_SOURCE_CODE
+#define TX_SOURCE_CODE
+#endif
+
+
+/* Include necessary system files.  */
+
+#include "txm_module.h"
+#include "tx_thread.h"
+
+/* Define the global module entry pointer from the start thread of the module.  */
+
+TXM_MODULE_THREAD_ENTRY_INFO    *_txm_module_entry_info;
+
+
+/* Define the dispatch function pointer used in the module implementation.  */
+
+ULONG                           (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
+
+
+/* Define the ARM cstartup code.  */
+extern VOID _txm_module_initialize(VOID);
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_thread_shell_entry                   Cortex-M33/MPU/AC6 */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function calls the specified entry function of the thread.  It */
+/*    also provides a place for the thread's entry function to return.    */
+/*    If the thread returns, this function places the thread in a         */
+/*    "COMPLETED" state.                                                  */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                        Pointer to current thread         */
+/*    thread_info                       Pointer to thread entry info      */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_initialize            cstartup initialization           */
+/*    thread_entry                      Thread's entry function           */
+/*    tx_thread_resume                  Resume the module callback thread */
+/*    _txm_module_thread_system_suspend Module thread suspension routine  */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Initial thread stack frame                                          */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
+{
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+    VOID            (*entry_exit_notify)(TX_THREAD *, UINT);
+#endif
+
+
+    /* Determine if this is the start thread.  If so, we must prepare the module for
+       execution.  If not, simply skip the C startup code.  */
+    if (thread_info -> txm_module_thread_entry_info_start_thread)
+    {
+        /* Initialize the ARM C environment.  */
+        _txm_module_initialize();
+
+        /* Save the entry info pointer, for later use.  */
+        _txm_module_entry_info =  thread_info;
+
+        /* Save the kernel function dispatch address. This is used to make all resident calls from
+           the module.  */
+        _txm_module_kernel_call_dispatcher =  thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
+
+        /* Ensure that we have a valid pointer.  */
+        while (!_txm_module_kernel_call_dispatcher)
+        {
+            /* Loop here, if an error is present getting the dispatch function pointer!
+               An error here typically indicates the resident portion of _tx_thread_schedule
+               is not supporting the trap to obtain the function pointer.   */
+        }
+        
+        /* Resume the module's callback thread, already created in the manager.  */
+        _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
+    }
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Pickup the entry/exit application callback routine.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has been entered!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
+    }
+#endif
+
+    /* Call current thread's entry function.  */
+    (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
+
+    /* Suspend thread with a "completed" state.  */
+
+
+#ifndef TX_DISABLE_NOTIFY_CALLBACKS
+
+    /* Pickup the entry/exit application callback routine again.  */
+    entry_exit_notify =  thread_info -> txm_module_thread_entry_info_exit_notify;
+
+    /* Determine if an application callback routine is specified.  */
+    if (entry_exit_notify != TX_NULL)
+    {
+
+        /* Yes, notify application that this thread has exited!  */
+        (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
+    }
+#endif
+
+    /* Call actual thread suspension routine.  */
+    _txm_module_thread_system_suspend(thread_ptr);
+
+#ifdef TX_SAFETY_CRITICAL
+
+    /* If we ever get here, raise safety critical exception.  */
+    TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
+#endif
+}
+
diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c
new file mode 100644
index 00000000..4d1e786b
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c
@@ -0,0 +1,77 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TXM_MODULE
+#include "txm_module.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txe_thread_secure_stack_allocate                   PORTABLE C      */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function allocate a secure stack for the thread.               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*    stack_size                            Size of secure stack to       */
+/*                                            allocate                    */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    TX_THREAD_ERROR                   Invalid thread pointer            */
+/*    TX_CALLER_ERROR                   Invalid caller of this function   */
+/*    status                            Actual completion status          */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_kernel_call_dispatcher                                  */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Module application code                                             */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
+{
+
+UINT return_value;
+
+    /* Call module manager dispatcher.  */
+    return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_ALLOCATE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) stack_size, 0);
+
+    /* Return value to the caller.  */
+    return(return_value);
+}
diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c
new file mode 100644
index 00000000..47594acd
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c
@@ -0,0 +1,75 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TXM_MODULE
+#include "txm_module.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txe_thread_secure_stack_free                       PORTABLE C      */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function frees the thread's secure stack.                      */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    TX_THREAD_ERROR                       Invalid thread pointer        */
+/*    TX_CALLER_ERROR                       Invalid caller of function    */
+/*    status                                Actual completion status      */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _txm_module_kernel_call_dispatcher                                  */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Module application code                                             */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)
+{
+
+UINT return_value;
+
+    /* Call module manager dispatcher.  */
+    return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_FREE_CALL, (ALIGN_TYPE) thread_ptr, 0, 0);
+
+    /* Return value to the caller.  */
+    return(return_value);
+}
diff --git a/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h
new file mode 100644
index 00000000..e612b45c
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h
@@ -0,0 +1,65 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+/* Define port-specific dispatch functions. */
+
+/* UINT _txe_thread_secure_stack_allocate(
+    TX_THREAD *thread_ptr, -> param_0
+    ULONG stack_size -> param_1
+   ); */
+static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1)
+{
+
+ALIGN_TYPE return_value;
+
+    if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
+    {
+        if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
+            return(TXM_MODULE_INVALID_MEMORY);
+    }
+
+    return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate(
+        (TX_THREAD *) param_0,
+        (ULONG) param_1
+    );
+    return(return_value);
+}
+
+/* UINT _txe_thread_secure_stack_free(
+    TX_THREAD *thread_ptr -> param_0
+   ); */
+static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_free_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0)
+{
+
+ALIGN_TYPE return_value;
+
+    if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
+    {
+        if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
+            return(TXM_MODULE_INVALID_MEMORY);
+    }
+
+    return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free(
+        (TX_THREAD *) param_0
+    );
+    return(return_value);
+}
\ No newline at end of file
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..61f9e6ad
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S
@@ -0,0 +1,74 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_restore                        Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is not needed for Cortex-M.                           */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling routine     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                  Interrupt Service Routines    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_restore(VOID)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_thread_context_restore
+    .thumb_func
+.type _tx_thread_context_restore, function
+_tx_thread_context_restore:
+    /* Just return!  */
+    BX      lr
+// }
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S
new file mode 100644
index 00000000..5be18688
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S
@@ -0,0 +1,74 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_save                           Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is not needed for Cortex-M.                           */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */        
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_context_save(VOID)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_thread_context_save
+    .thumb_func
+.type _tx_thread_context_save, function
+_tx_thread_context_save:
+    /* Return to interrupt processing.  */
+    BX      lr
+// }
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..ac26010f
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S
@@ -0,0 +1,78 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_control                      Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for changing the interrupt lockout     */
+/*    posture of the system.                                              */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    new_posture                           New interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */        
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_control(UINT new_posture)
+// {
+    .section .text
+    .balign 4
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_thread_interrupt_control
+    .thumb_func
+.type _tx_thread_interrupt_control, function
+_tx_thread_interrupt_control:
+
+    /* Pickup current interrupt lockout posture.  */
+    MRS     r1, PRIMASK
+    MSR     PRIMASK, r0
+    MOV     r0, r1
+    BX      lr
+// }
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S
new file mode 100644
index 00000000..19d2da39
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S
@@ -0,0 +1,77 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_disable                      Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for disabling interrupts and returning */
+/*    the previous interrupt lockout posture.                             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_interrupt_disable(UINT new_posture)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_thread_interrupt_disable
+    .thumb_func
+.type _tx_thread_interrupt_disable, function
+_tx_thread_interrupt_disable:
+    /* Return current interrupt lockout posture.  */
+    MRS     r0, PRIMASK
+    CPSID   i
+    BX      lr
+// }
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S
new file mode 100644
index 00000000..13ff2fcf
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S
@@ -0,0 +1,76 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_restore                      Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for restoring the previous             */
+/*    interrupt lockout posture.                                          */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    previous_posture                      Previous interrupt posture    */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_interrupt_restore(UINT new_posture)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_thread_interrupt_restore
+    .thumb_func
+.type _tx_thread_interrupt_restore, function
+_tx_thread_interrupt_restore:
+    /* Restore previous interrupt lockout posture.  */
+    MSR     PRIMASK, r0
+    BX      lr
+// }
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S
new file mode 100644
index 00000000..97c313b4
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S
@@ -0,0 +1,617 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_schedule                             Cortex-M33/MPU/AC6  */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function waits for a thread control block pointer to appear in */
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+/*    in the variable, the corresponding thread is resumed.               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+/*    _tx_thread_system_return             Return to system from thread   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_schedule(VOID)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_thread_schedule
+    .thumb_func
+.type _tx_thread_schedule, function
+_tx_thread_schedule:
+
+    /* This function should only ever be called on Cortex-M
+       from the first schedule request. Subsequent scheduling occurs
+       from the PendSV handling routine below. */
+
+    /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets.  */
+
+    MOV     r0, #0                                  // Build value for TX_FALSE
+    LDR     r2, =_tx_thread_preempt_disable         // Build address of preempt disable flag
+    STR     r0, [r2, #0]                            // Clear preempt disable flag
+
+    /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked.  */
+
+#ifdef __ARM_FP
+    MRS     r0, CONTROL                             // Pickup current CONTROL register
+    BIC     r0, r0, #4                              // Clear the FPCA bit
+    MSR     CONTROL, r0                             // Setup new CONTROL register
+#endif
+
+    /* Enable memory fault registers.  */
+
+    LDR     r0, =0xE000ED24                         // Build SHCSR address
+    LDR     r1, =0x70000                            // Enable Usage, Bus, and MemManage faults
+    STR     r1, [r0]                                //
+
+    /* Enable interrupts */
+
+    CPSIE   i
+
+    /* Enter the scheduler for the first time.  */
+
+    MOV     r0, #0x10000000                         // Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         // Load NVIC base
+    STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB                                             // Complete all memory accesses
+    ISB                                             // Flush pipeline
+
+    /* Wait here for the PendSV to take place.  */
+
+__tx_wait_here:
+    B       __tx_wait_here                          // Wait for the PendSV to happen
+// }
+
+
+    /* Memory Exception Handler.  */
+
+    .global  MemManage_Handler
+    .global  BusFault_Handler
+    .thumb_func
+MemManage_Handler:
+    .thumb_func
+BusFault_Handler:
+
+    CPSID   i                                       // Disable interrupts
+
+    /* Now pickup and store all the fault related information.  */
+
+    LDR     r12,=_txm_module_manager_memory_fault_info  // Pickup fault info struct
+    LDR     r0, =_tx_thread_current_ptr             // Build current thread pointer address
+    LDR     r1, [r0]                                // Pickup the current thread pointer
+    STR     r1, [r12, #0]                           // Save current thread pointer in fault info structure
+    LDR     r0, =0xE000ED24                         // Build SHCSR address
+    LDR     r1, [r0]                                // Pickup SHCSR
+    STR     r1, [r12, #8]                           // Save SHCSR
+    LDR     r0, =0xE000ED28                         // Build CFSR address
+    LDR     r1, [r0]                                // Pickup CFSR
+    STR     r1, [r12, #12]                          // Save CFSR
+    LDR     r0, =0xE000ED34                         // Build MMFAR address
+    LDR     r1, [r0]                                // Pickup MMFAR
+    STR     r1, [r12, #16]                          // Save MMFAR
+    LDR     r0, =0xE000ED38                         // Build BFAR address
+    LDR     r1, [r0]                                // Pickup BFAR
+    STR     r1, [r12, #20]                          // Save BFAR
+    MRS     r0, CONTROL                             // Pickup current CONTROL register
+    STR     r0, [r12, #24]                          // Save CONTROL
+    MRS     r1, PSP                                 // Pickup thread stack pointer
+    STR     r1, [r12, #28]                          // Save thread stack pointer
+    LDR     r0, [r1]                                // Pickup saved r0
+    STR     r0, [r12, #32]                          // Save r0
+    LDR     r0, [r1, #4]                            // Pickup saved r1
+    STR     r0, [r12, #36]                          // Save r1
+    STR     r2, [r12, #40]                          // Save r2
+    STR     r3, [r12, #44]                          // Save r3
+    STR     r4, [r12, #48]                          // Save r4
+    STR     r5, [r12, #52]                          // Save r5
+    STR     r6, [r12, #56]                          // Save r6
+    STR     r7, [r12, #60]                          // Save r7
+    STR     r8, [r12, #64]                          // Save r8
+    STR     r9, [r12, #68]                          // Save r9
+    STR     r10,[r12, #72]                          // Save r10
+    STR     r11,[r12, #76]                          // Save r11
+    LDR     r0, [r1, #16]                           // Pickup saved r12
+    STR     r0, [r12, #80]                          // Save r12
+    LDR     r0, [r1, #20]                           // Pickup saved lr
+    STR     r0, [r12, #84]                          // Save lr
+    LDR     r0, [r1, #24]                           // Pickup instruction address at point of fault
+    STR     r0, [r12, #4]                           // Save point of fault
+    LDR     r0, [r1, #28]                           // Pickup xPSR
+    STR     r0, [r12, #88]                          // Save xPSR
+
+    MRS     r0, CONTROL                             // Pickup current CONTROL register
+    BIC     r0, r0, #1                              // Clear the UNPRIV bit
+    MSR     CONTROL, r0                             // Setup new CONTROL register
+
+    LDR     r0, =0xE000ED28                         // Build the Memory Management Fault Status Register (MMFSR)
+    LDRB    r1, [r0]                                // Pickup the MMFSR, with the following bit definitions:
+                                                    //     Bit 0 = 1 -> Instruction address violation
+                                                    //     Bit 1 = 1 -> Load/store address violation
+                                                    //     Bit 7 = 1 -> MMFAR is valid
+    STRB    r1, [r0]                                // Clear the MMFSR
+
+#ifdef __ARM_FP
+    LDR     r0, =0xE000EF34                         // Cleanup FPU context: Load FPCCR address
+    LDR     r1, [r0]                                // Load FPCCR
+    BIC     r1, r1, #1                              // Clear the lazy preservation active bit
+    STR     r1, [r0]                                // Store the value
+#endif
+
+    BL      _txm_module_manager_memory_fault_handler    // Call memory manager fault handler
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the thread exit function to indicate the thread is no longer executing.  */
+    CPSID   i                                       // Disable interrupts
+    BL      _tx_execution_thread_exit               // Call the thread exit function
+    CPSIE   i                                       // Enable interrupts
+#endif
+
+    MOV     r1, #0                                  // Build NULL value
+    LDR     r0, =_tx_thread_current_ptr             // Pickup address of current thread pointer
+    STR     r1, [r0]                                // Clear current thread pointer
+
+    // Return from MemManage_Handler exception
+    LDR     r0, =0xE000ED04                         // Load ICSR
+    LDR     r1, =0x10000000                         // Set PENDSVSET bit
+    STR     r1, [r0]                                // Store ICSR
+    DSB                                             // Wait for memory access to complete
+    CPSIE   i                                       // Enable interrupts
+#ifdef TX_SINGLE_MODE_SECURE
+    LDR     lr, =0xFFFFFFFD                         // Exception return to secure
+#else
+    LDR     lr, =0xFFFFFFBC                         // Exception return to non-secure
+#endif
+    BX      lr                                      // Return from exception
+
+
+    /* Generic context switching PendSV handler.  */
+
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  PendSV_Handler
+    .thumb_func
+.type PendSV_Handler, function
+    /* Get current thread value and new thread pointer.  */
+PendSV_Handler:
+__tx_ts_handler:
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the thread exit function to indicate the thread is no longer executing.  */
+    CPSID   i                                       // Disable interrupts
+    PUSH    {r0, lr}                                // Save LR (and r0 just for alignment)
+    BL      _tx_execution_thread_exit               // Call the thread exit function
+    POP     {r0, lr}                                // Recover LR
+    CPSIE   i                                       // Enable interrupts
+#endif
+
+    LDR     r0, =_tx_thread_current_ptr             // Build current thread pointer address
+    LDR     r2, =_tx_thread_execute_ptr             // Build execute thread pointer address
+    MOV     r3, #0                                  // Build NULL value
+    LDR     r1, [r0]                                // Pickup current thread pointer
+
+    /* Determine if there is a current thread to finish preserving.  */
+
+    CBZ     r1, __tx_ts_new                         // If NULL, skip preservation
+
+    /* Recover PSP and preserve current thread context.  */
+
+    STR     r3, [r0]                                // Set _tx_thread_current_ptr to NULL
+    MRS     r12, PSP                                // Pickup PSP pointer (thread's stack pointer)
+    STMDB   r12!, {r4-r11}                          // Save its remaining registers
+#ifdef __ARM_FP
+    TST     LR, #0x10                               // Determine if the VFP extended frame is present
+    BNE     _skip_vfp_save
+    VSTMDB  r12!,{s16-s31}                          // Yes, save additional VFP registers
+_skip_vfp_save:
+#endif
+    LDR     r4, =_tx_timer_time_slice               // Build address of time-slice variable
+    STMDB   r12!, {LR}                              // Save LR on the stack
+    STR     r12, [r1, #8]                           // Save the thread stack pointer
+
+#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
+    // Save secure context
+    LDR     r5, [r1,#0xC4]                          // Load secure stack index
+    CBZ     r5, _skip_secure_save                   // Skip save if there is no secure context
+    PUSH    {r0,r1,r2,r3}                           // Save scratch registers
+    MOV     r0, r1                                  // Move thread ptr to r0
+    BL      _tx_thread_secure_stack_context_save    // Save secure stack
+    POP     {r0,r1,r2,r3}                           // Restore secure registers
+_skip_secure_save:
+#endif
+
+    /* Determine if time-slice is active. If it isn't, skip time handling processing.  */
+
+    LDR     r5, [r4]                                // Pickup current time-slice
+    CBZ     r5, __tx_ts_new                         // If not active, skip processing
+
+    /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable.  */
+
+    STR     r5, [r1, #24]                           // Save current time-slice
+
+    /* Clear the global time-slice.  */
+
+    STR     r3, [r4]                                // Clear time-slice
+
+    /* Executing thread is now completely preserved!!!  */
+
+__tx_ts_new:
+
+    /* Now we are looking for a new thread to execute!  */
+
+    CPSID   i                                       // Disable interrupts
+    LDR     r1, [r2]                                // Is there another thread ready to execute?
+    CBNZ    r1, __tx_ts_restore                     // Yes, schedule it
+
+    /* The following is the idle wait processing... in this case, no threads are ready for execution and the
+       system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
+       are disabled to allow use of WFI for waiting for a thread to arrive.  */
+
+__tx_ts_wait:
+    CPSID   i                                       // Disable interrupts
+    LDR     r1, [r2]                                // Pickup the next thread to execute pointer
+    CBNZ    r1, __tx_ts_ready                       // If non-NULL, a new thread is ready!
+#ifdef TX_ENABLE_WFI
+    DSB                                             // Ensure no outstanding memory transactions
+    WFI                                             // Wait for interrupt
+    ISB                                             // Ensure pipeline is flushed
+#endif
+    CPSIE   i                                       // Enable interrupts
+    B       __tx_ts_wait                            // Loop to continue waiting
+
+    /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
+       already in the handler!  */
+
+__tx_ts_ready:
+    MOV     r7, #0x08000000                         // Build clear PendSV value
+    MOV     r8, #0xE000E000                         // Build base NVIC address
+    STR     r7, [r8, #0xD04]                        // Clear any PendSV
+
+__tx_ts_restore:
+
+    /* A thread is ready, make the current thread the new thread
+       and enable interrupts.  */
+
+    STR     r1, [r0]                                // Setup the current thread pointer to the new thread
+    CPSIE   i                                       // Enable interrupts
+
+    /* Increment the thread run count.  */
+
+    LDR     r7, [r1, #4]                            // Pickup the current thread run count
+    LDR     r4, =_tx_timer_time_slice               // Build address of time-slice variable
+    LDR     r5, [r1, #24]                           // Pickup thread's current time-slice
+    ADD     r7, r7, #1                              // Increment the thread run count
+    STR     r7, [r1, #4]                            // Store the new run count
+
+    /* Setup global time-slice with thread's current time-slice.  */
+
+    STR     r5, [r4]                                // Setup global time-slice
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    /* Call the thread entry function to indicate the thread is executing.  */
+    PUSH    {r0, r1}                                // Save r0 and r1
+    BL      _tx_execution_thread_enter              // Call the thread execution enter function
+    POP     {r0, r1}                                // Recover r0 and r1
+#endif
+
+#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
+    // Restore secure context
+    LDR     r0, [r1,#0xC4]                          // Load secure stack index
+    CBZ     r0, _skip_secure_restore                // Skip restore if there is no secure context
+    PUSH    {r0,r1}                                 // Save r1 (and dummy r0)
+    MOV     r0, r1                                  // Move thread ptr to r0
+    BL      _tx_thread_secure_stack_context_restore // Restore secure stack
+    POP     {r0,r1}                                 // Restore r1 (and dummy r0)
+_skip_secure_restore:
+#endif
+
+    /* Restore the thread context and PSP.  */
+    LDR     r12, [r1, #12]                          // Get stack start
+    MSR     PSPLIM, r12                             // Set stack limit
+    LDR     r12, [r1, #8]                           // Pickup thread's stack pointer
+
+    MRS     r5, CONTROL                             // Pickup current CONTROL register
+    LDR     r4, [r1, #0x98]                         // Pickup current user mode flag
+    BIC     r5, r5, #1                              // Clear the UNPRIV bit
+    ORR     r4, r4, r5                              // Build new CONTROL register
+    MSR     CONTROL, r4                             // Setup new CONTROL register
+
+    LDR     r0, =0xE000ED94                         // Build MPU control reg address
+    MOV     r3, #0                                  // Build disable value
+    STR     r3, [r0]                                // Disable MPU
+    LDR     r0, [r1, #0x90]                         // Pickup the module instance pointer
+    CBZ     r0, skip_mpu_setup                      // Is this thread owned by a module? No, skip MPU setup
+    LDR     r1, [r0, #0x64]                         // Pickup MPU register[0]
+    CBZ     r1, skip_mpu_setup                      // Is protection required for this module? No, skip MPU setup
+    LDR     r1, =0xE000ED9C                         // Build address of MPU base register
+
+    // Use alias registers to quickly load MPU
+    ADD     r0, r0, #0x64                           // Build address of MPU register start in thread control block
+    LDM     r0!, {r2-r9}                            // Load first four MPU regions
+    STM     r1, {r2-r9}                             // Store first four MPU regions
+    MOV     r2, #4                                  // Select region 4
+    LDR     r3, =0xE000ED98                         // Get region register
+    STR     r2, [r3]                                // Set region to 4
+    LDM     r0, {r2-r9}                             // Load second four MPU regions
+    STM     r1, {r2-r9}                             // Store second four MPU regions
+    LDR     r0, =0xE000ED94                         // Build MPU control reg address
+    MOV     r1, #5                                  // Build enable value with background region enabled
+    STR     r1, [r0]                                // Enable MPU
+skip_mpu_setup:
+    LDMIA   r12!, {LR}                              // Pickup LR
+#ifdef __ARM_FP
+    TST     LR, #0x10                               // Determine if the VFP extended frame is present
+    BNE     _skip_vfp_restore                       // If not, skip VFP restore
+    VLDMIA  r12!, {s16-s31}                         // Yes, restore additional VFP registers
+_skip_vfp_restore:
+#endif
+    LDMIA   r12!, {r4-r11}                          // Recover thread's registers
+    MSR     PSP, r12                                // Setup the thread's stack pointer
+
+    /* Return to thread.  */
+
+    BX      lr                                      // Return to thread!
+
+
+    /* SVC Handler.  */
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  SVC_Handler
+    .thumb_func
+.type SVC_Handler, function
+SVC_Handler:
+    TST     lr, #0x04                               // Determine return stack from EXC_RETURN bit 2
+    ITE     EQ
+    MRSEQ   r0, MSP                                 // Get MSP
+    MRSNE   r0, PSP                                 // Get PSP
+
+    LDR     r1, [r0,#24]                            // Load saved PC from stack
+    LDRB    r2, [r1,#-2]                            // Load SVC number
+
+#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
+    CMP     r2, #1                                  // Is it a secure stack allocate request?
+    BEQ     _tx_svc_secure_alloc                    // Yes, go there
+
+    CMP     r2, #2                                  // Is it a secure stack free request?
+    BEQ     _tx_svc_secure_free                     // Yes, go there
+#endif   // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
+
+
+    CMP     r2, #3                                  // Is it the entry into ThreadX?
+    BNE     _tx_thread_user_return                  // No, return to user mode
+
+    /* At this point we have an SVC 3, which means we are entering
+       the kernel from a module thread with user mode selected. */
+
+    LDR     r2, =_txm_module_priv                   // Load address of where we should have come from
+    CMP     r1, r2                                  // Did we come from user_mode_entry?
+    IT      NE                                      // If no (not equal), then...
+    BXNE    lr                                      // return from where we came.
+
+    LDR     r3, [r0, #20]                           // This is the saved LR
+    LDR     r1, =_tx_thread_current_ptr             // Build current thread pointer address
+    LDR     r2, [r1]                                // Pickup current thread pointer
+    MOV     r1, #0                                  // Build clear value
+    STR     r1, [r2, #0x98]                         // Clear the current user mode selection for thread
+    STR     r3, [r2, #0xA0]                         // Save the original LR in thread control block
+
+    /* If there is memory protection, use kernel stack */
+    LDR     r0, [r2, #0x90]                         // Load the module instance ptr
+    LDR     r0, [r0, #0x0C]                         // Load the module property flags
+    TST     r0, #2                                  // Check if memory protected
+    BEQ     _tx_skip_kernel_stack_enter
+
+    /* Switch to the module thread's kernel stack */
+    LDR     r0, [r2, #0xA8]                         // Load the module kernel stack end
+    LDR     r1, [r2, #0xA4]                         // Load the module kernel stack start
+    MSR     PSPLIM, r1                              // Set stack limit
+#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
+    LDR     r3, [r2, #0xAC]                         // Load the module kernel stack size
+    STR     r1, [r2, #12]                           // Set stack start
+    STR     r0, [r2, #16]                           // Set stack end
+    STR     r3, [r2, #20]                           // Set stack size
+#endif
+
+    MRS     r3, PSP                                 // Pickup thread stack pointer
+    STR     r3, [r2, #0xB0]                         // Save thread stack pointer
+
+    /* Build kernel stack by copying thread stack two registers at a time */
+    ADD     r3, r3, #32                             // Start at bottom of hardware stack
+    LDMDB   r3!,{r1-r2}
+    STMDB   r0!,{r1-r2}
+    LDMDB   r3!,{r1-r2}
+    STMDB   r0!,{r1-r2}
+    LDMDB   r3!,{r1-r2}
+    STMDB   r0!,{r1-r2}
+    LDMDB   r3!,{r1-r2}
+    STMDB   r0!,{r1-r2}
+
+    MSR     PSP, r0                                 // Set kernel stack pointer
+
+_tx_skip_kernel_stack_enter:
+    MRS     r0, CONTROL                             // Pickup current CONTROL register
+    BIC     r0, r0, #1                              // Clear the UNPRIV bit
+    MSR     CONTROL, r0                             // Setup new CONTROL register
+    BX      lr                                      // Return to thread
+
+
+_tx_thread_user_return:
+    LDR     r2, =_txm_module_user_mode_exit         // Load address of where we should have come from
+    CMP     r1, r2                                  // Did we come from user_mode_exit?
+    IT      NE                                      // If no (not equal), then...
+    BXNE    lr                                      // return from where we came
+
+    LDR     r1, =_tx_thread_current_ptr             // Build current thread pointer address
+    LDR     r2, [r1]                                // Pickup current thread pointer
+    LDR     r1, [r2, #0x9C]                         // Pick up user mode
+    STR     r1, [r2, #0x98]                         // Set the current user mode selection for thread
+
+    /* If there is memory protection, use kernel stack */
+    LDR     r0, [r2, #0x90]                         // Load the module instance ptr
+    LDR     r0, [r0, #0x0C]                         // Load the module property flags
+    TST     r0, #2                                  // Check if memory protected
+    BEQ     _tx_skip_kernel_stack_exit
+
+
+    LDR     r0, [r2, #0xB4]                         // Load the module thread stack start
+    MSR     PSPLIM, r0                              // Set stack limit
+#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
+    LDR     r1, [r2, #0xB8]                         // Load the module thread stack end
+    LDR     r3, [r2, #0xBC]                         // Load the module thread stack size
+    STR     r0, [r2, #12]                           // Set stack start
+    STR     r1, [r2, #16]                           // Set stack end
+    STR     r3, [r2, #20]                           // Set stack size
+#endif
+    LDR     r0, [r2, #0xB0]                         // Load the module thread stack pointer
+    MRS     r3, PSP                                 // Pickup kernel stack pointer
+
+    /* Copy kernel hardware stack to module thread stack. */
+    LDM     r3!,{r1-r2}
+    STM     r0!,{r1-r2}
+    LDM     r3!,{r1-r2}
+    STM     r0!,{r1-r2}
+    LDM     r3!,{r1-r2}
+    STM     r0!,{r1-r2}
+    LDM     r3!,{r1-r2}
+    STM     r0!,{r1-r2}
+    SUB     r0, r0, #32                             // Subtract 32 to get back to top of stack
+    MSR     PSP, r0                                 // Set thread stack pointer
+
+    LDR     r1, =_tx_thread_current_ptr             // Build current thread pointer address
+    LDR     r2, [r1]                                // Pickup current thread pointer
+    LDR     r1, [r2, #0x9C]                         // Pick up user mode
+
+_tx_skip_kernel_stack_exit:
+    MRS     r0, CONTROL                             // Pickup current CONTROL register
+    ORR     r0, r0, r1                              // OR in the user mode bit
+    MSR     CONTROL, r0                             // Setup new CONTROL register
+    BX      lr                                      // Return to thread
+
+
+#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
+_tx_svc_secure_alloc:
+    LDR     r2, =_tx_alloc_return                   // Load address of where we should have come from
+    CMP     r1, r2                                  // Did we come from _tx_thread_secure_stack_allocate?
+    IT      NE                                      // If no (not equal), then...
+    BXNE    lr                                      // return from where we came.
+    
+    PUSH    {r0, lr}                                // Save SP and EXC_RETURN
+    LDM     r0, {r0-r3}                             // Load function parameters from stack
+    BL      _tx_thread_secure_mode_stack_allocate
+    POP     {r12, lr}                               // Restore SP and EXC_RETURN
+    STR     r0, [r12]                               // Store function return value
+    BX      lr
+    
+_tx_svc_secure_free:
+    LDR     r2, =_tx_free_return                    // Load address of where we should have come from
+    CMP     r1, r2                                  // Did we come from _tx_thread_secure_stack_free?
+    IT      NE                                      // If no (not equal), then...
+    BXNE    lr                                      // return from where we came.
+    
+    PUSH    {r0, lr}                                // Save SP and EXC_RETURN
+    LDM     r0, {r0-r3}                             // Load function parameters from stack
+    BL      _tx_thread_secure_mode_stack_free
+    POP     {r12, lr}                               // Restore SP and EXC_RETURN
+    STR     r0, [r12]                               // Store function return value
+    BX      lr
+#endif   // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
+
+
+
+   /* Kernel entry function from user mode.  */
+
+    .global  _txm_module_manager_kernel_dispatch
+    .align 5
+    .syntax unified
+// VOID   _txm_module_manager_user_mode_entry(VOID)
+// {
+    .global  _txm_module_manager_user_mode_entry
+    .thumb_func
+_txm_module_manager_user_mode_entry:
+    SVC     3                                       // Enter kernel
+_txm_module_priv:
+    /* At this point, we are out of user mode. The original LR has been saved in the
+       thread control block. Simply call the kernel dispatch function. */
+    BL      _txm_module_manager_kernel_dispatch
+
+    /* Pickup the original LR value while still in privileged mode */
+    LDR     r2, =_tx_thread_current_ptr             // Build current thread pointer address
+    LDR     r3, [r2]                                // Pickup current thread pointer
+    LDR     lr, [r3, #0xA0]                         // Pickup saved LR from original call
+
+    SVC     4                                       // Exit kernel and return to user mode
+_txm_module_user_mode_exit:
+    BX      lr                                      // Return to the caller
+    NOP
+    NOP
+    NOP
+    NOP
+// }
+
+
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_vfp_access
+    .thumb_func
+.type _tx_vfp_access, function
+_tx_vfp_access:
+    VMOV.F32 s0, s0                                 // Simply access the VFP
+    BX       lr                                     // Return to caller
+.end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c
new file mode 100644
index 00000000..c706071d
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c
@@ -0,0 +1,480 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#include "tx_api.h"
+
+/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, 
+   no secure stack functionality is needed. */
+#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
+
+#define TX_SOURCE_CODE
+
+#include "ARMCM33_DSP_FP_TZ.h"          /* For intrinsic functions. */
+#include "tx_secure_interface.h"        /* Interface for NS code. */
+
+/* Minimum size of secure stack. */
+#ifndef TX_THREAD_SECURE_STACK_MINIMUM
+#define TX_THREAD_SECURE_STACK_MINIMUM     256
+#endif
+/* Maximum size of secure stack. */
+#ifndef TX_THREAD_SECURE_STACK_MAXIMUM
+#define TX_THREAD_SECURE_STACK_MAXIMUM     1024
+#endif
+
+/* 8 bytes added to stack size to "seal" stack. */
+#define TX_THREAD_STACK_SEAL_SIZE           8
+#define TX_THREAD_STACK_SEAL_VALUE          0xFEF5EDA5
+
+/* Secure stack info struct to hold stack start, stack limit, 
+   current stack pointer, and pointer to owning thread. 
+   This will be allocated for each thread with a secure stack. */
+typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
+{
+    VOID        *tx_thread_secure_stack_ptr;        /* Thread's secure stack current pointer */
+    VOID        *tx_thread_secure_stack_start;      /* Thread's secure stack start address */
+    VOID        *tx_thread_secure_stack_limit;      /* Thread's secure stack limit */
+    TX_THREAD   *tx_thread_ptr;                     /* Keep track of thread for error handling */
+} TX_THREAD_SECURE_STACK_INFO;
+
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_secure_stack_initialize                Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function initializes secure mode to use PSP stack.             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    __get_CONTROL                         Intrinsic to get CONTROL      */
+/*    __set_CONTROL                         Intrinsic to set CONTROL      */
+/*    __set_PSPLIM                          Intrinsic to set PSP limit    */
+/*    __set_PSP                             Intrinsic to set PSP          */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter                                         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+__attribute__((cmse_nonsecure_entry))
+void    _tx_thread_secure_stack_initialize(void)
+{
+    
+    /* Set secure mode to use PSP. */
+    __set_CONTROL(__get_CONTROL() | 2);
+    
+    /* Set process stack pointer and stack limit to 0 to throw exception when a thread
+       without a secure stack calls a secure function that tries to use secure stack. */
+    __set_PSPLIM(0);
+    __set_PSP(0);
+    
+    return;
+}
+
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_secure_mode_stack_allocate             Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function allocates a thread's secure stack.                    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*    stack_size                            Size of stack to allocates    */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    TX_THREAD_ERROR                       Invalid thread pointer        */
+/*    TX_SIZE_ERROR                         Invalid stack size            */
+/*    TX_CALLER_ERROR                       Invalid caller of function    */
+/*    status                                Actual completion status      */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    __get_IPSR                            Intrinsic to get IPSR         */
+/*    calloc                                Compiler's calloc function    */
+/*    malloc                                Compiler's malloc function    */
+/*    free                                  Compiler's free() function    */
+/*    __set_PSPLIM                          Intrinsic to set PSP limit    */
+/*    __set_PSP                             Intrinsic to set PSP          */
+/*    __TZ_get_PSPLIM_NS                    Intrinsic to get NS PSP       */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    SVC Handler                                                         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  12-31-2020      Scott Larson            Modified comment(s),          */
+/*                                            added stack sealing,        */
+/*                                            resulting in version 6.1.3  */
+/*                                                                        */
+/**************************************************************************/
+__attribute__((cmse_nonsecure_entry))
+UINT    _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
+{
+UINT    status;
+TX_THREAD_SECURE_STACK_INFO *info_ptr;
+UCHAR   *stack_mem;
+
+    status = TX_SUCCESS;
+    
+    /* Make sure function is called from interrupt (threads should not call). */
+    if (__get_IPSR() == 0)
+    {
+        status = TX_CALLER_ERROR;
+    }
+    else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM)
+    {
+        status = TX_SIZE_ERROR;
+    }
+    
+    /* Check if thread already has secure stack allocated. */
+    else if (thread_ptr -> tx_thread_secure_stack_context != 0)
+    {
+        status = TX_THREAD_ERROR;
+    }
+    
+    else
+    {
+        /* Allocate space for secure stack info. */
+        info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO));
+        
+        if(info_ptr != TX_NULL)
+        {
+            /* If stack info allocated, allocate a stack & seal. */
+            stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE);
+            
+            if(stack_mem != TX_NULL)
+            {
+                /* Secure stack has been allocated, save in the stack info struct. */
+                info_ptr -> tx_thread_secure_stack_limit = stack_mem;
+                info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size;
+                info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start;
+                info_ptr -> tx_thread_ptr = thread_ptr;
+                
+                /* Seal bottom of stack. */
+                *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE;
+                
+                /* Save info pointer in thread. */
+                thread_ptr -> tx_thread_secure_stack_context = info_ptr;
+                
+                /* Check if this thread is running by looking at its stack start and PSPLIM_NS */
+                if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS())
+                {
+                    /* If this thread is running, set Secure PSP and PSPLIM. */
+                    __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit));
+                    __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr));
+                }
+            }
+            
+            else
+            {
+                /* Stack not allocated, free the info struct. */
+                free(info_ptr);
+                status = TX_NO_MEMORY;
+            }
+        }
+        
+        else
+        {
+            status = TX_NO_MEMORY;
+        }
+    }
+    
+    return(status);
+}
+
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_secure_mode_stack_free                 Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function frees a thread's secure stack.                        */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    TX_THREAD_ERROR                       Invalid thread pointer        */
+/*    TX_CALLER_ERROR                       Invalid caller of function    */
+/*    status                                Actual completion status      */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    __get_IPSR                            Intrinsic to get IPSR         */
+/*    free                                  Compiler's free() function    */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    SVC Handler                                                         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  12-31-2020      Scott Larson            Modified comment(s),          */
+/*                                            resulting in version 6.1.3  */
+/*                                                                        */
+/**************************************************************************/
+__attribute__((cmse_nonsecure_entry))
+UINT    _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
+{
+UINT    status;
+TX_THREAD_SECURE_STACK_INFO *info_ptr;
+    
+    status = TX_SUCCESS;
+    
+    /* Pickup stack info from thread. */
+    info_ptr = thread_ptr -> tx_thread_secure_stack_context;
+    
+    /* Make sure function is called from interrupt (threads should not call). */
+    if (__get_IPSR() == 0)
+    {
+        status = TX_CALLER_ERROR;
+    }
+    
+    /* Check that this secure context is for this thread. */
+    else if (info_ptr -> tx_thread_ptr != thread_ptr)
+    {
+        status = TX_THREAD_ERROR;
+    }
+    
+    else
+    {
+        
+        /* Free secure stack. */
+        free(info_ptr -> tx_thread_secure_stack_limit);
+        
+        /* Free info struct. */
+        free(info_ptr);
+        
+        /* Clear secure context from thread. */
+        thread_ptr -> tx_thread_secure_stack_context = 0;
+    }
+    
+    return(status);
+}
+
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_secure_stack_context_save              Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves context of the secure stack.                    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    __get_IPSR                            Intrinsic to get IPSR         */
+/*    __get_PSP                             Intrinsic to get PSP          */
+/*    __set_PSPLIM                          Intrinsic to set PSP limit    */
+/*    __set_PSP                             Intrinsic to set PSP          */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    PendSV Handler                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  12-31-2020      Scott Larson            Modified comment(s),          */
+/*                                            resulting in version 6.1.3  */
+/*                                                                        */
+/**************************************************************************/
+__attribute__((cmse_nonsecure_entry))
+void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr)
+{
+TX_THREAD_SECURE_STACK_INFO *info_ptr;
+ULONG   sp;
+    
+    /* This function should be called from scheduler only. */
+    if (__get_IPSR() == 0)
+    {
+        return;
+    }
+    
+    /* Pickup the secure context pointer. */
+    info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context);
+    
+    /* Check that this secure context is for this thread. */
+    if (info_ptr -> tx_thread_ptr != thread_ptr)
+    {
+        return;
+    }
+    
+    /* Check that stack pointer is in range */
+    sp = __get_PSP();
+    if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || 
+        (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start))
+    {
+        return;
+    }
+    
+    /* Save stack pointer. */
+    *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp;
+    
+    /* Set process stack pointer and stack limit to 0 to throw exception when a thread
+       without a secure stack calls a secure function that tries to use secure stack. */
+    __set_PSPLIM(0);
+    __set_PSP(0);
+    
+    return;
+}
+
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_secure_stack_context_restore           Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function restores context of the secure stack.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    __get_IPSR                            Intrinsic to get IPSR         */
+/*    __set_PSPLIM                          Intrinsic to set PSP limit    */
+/*    __set_PSP                             Intrinsic to set PSP          */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    PendSV Handler                                                      */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  12-31-2020      Scott Larson            Modified comment(s),          */
+/*                                            resulting in version 6.1.3  */
+/*                                                                        */
+/**************************************************************************/
+__attribute__((cmse_nonsecure_entry))
+void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr)
+{
+TX_THREAD_SECURE_STACK_INFO *info_ptr;
+
+    /* This function should be called from scheduler only. */
+    if (__get_IPSR() == 0)
+    {
+        return;
+    }
+    
+    /* Pickup the secure context pointer. */
+    info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context);
+    
+    /* Check that this secure context is for this thread. */
+    if (info_ptr -> tx_thread_ptr != thread_ptr)
+    {
+        return;
+    }
+    
+    /* Set stack pointer and limit. */
+    __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit);
+    __set_PSP   ((ULONG)info_ptr -> tx_thread_secure_stack_ptr);
+    
+    return;
+}
+
+#endif
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S
new file mode 100644
index 00000000..4ff8cb4b
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S
@@ -0,0 +1,87 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_secure_stack_allocate                  Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function enters the SVC handler to allocate a secure stack.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*    stack_size                            Size of secure stack to       */
+/*                                            allocate                    */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                                Actual completion status      */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    SVC 1                                                               */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */        
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global _tx_thread_secure_stack_allocate
+    .global _tx_alloc_return
+    .thumb_func
+.type _tx_thread_secure_stack_allocate, function
+_tx_thread_secure_stack_allocate:
+#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
+    MRS     r3, PRIMASK     // Save interrupt mask
+    CPSIE   i               // Enable interrupts for SVC call
+    SVC     1
+_tx_alloc_return:
+    CMP     r3, #0          // If interrupts enabled, just return
+    BEQ     _alloc_return_interrupt_enabled
+    CPSID   i               // Otherwise, disable interrupts
+#else
+    MOV     r0, #0xFF       // Feature not enabled
+#endif
+_alloc_return_interrupt_enabled:
+    BX      lr
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S
new file mode 100644
index 00000000..248165aa
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S
@@ -0,0 +1,85 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_secure_stack_free                      Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function enters the SVC handler to free a secure stack.        */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                                Actual completion status      */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    SVC 2                                                               */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */        
+/*                                                                        */
+/**************************************************************************/
+// UINT   _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global _tx_thread_secure_stack_free
+    .global _tx_free_return
+    .thumb_func
+.type _tx_thread_secure_stack_free, function
+_tx_thread_secure_stack_free:
+#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
+    MRS     r3, PRIMASK     // Save interrupt mask
+    CPSIE   i               // Enable interrupts for SVC call
+    SVC     2
+_tx_free_return:
+    CMP     r3, #0          // If interrupts enabled, just return
+    BEQ     _free_return_interrupt_enabled
+    CPSID   i               // Otherwise, disable interrupts
+#else
+    MOV     r0, #0xFF       // Feature not enabled
+#endif
+_free_return_interrupt_enabled:
+    BX      lr
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..ec548d5e
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S
@@ -0,0 +1,140 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_stack_build                            Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread control blk */
+/*    function_ptr                          Pointer to return function    */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */        
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_thread_stack_build
+    .thumb_func
+.type _tx_thread_stack_build, function
+_tx_thread_stack_build:
+    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+       on the Cortex-M33 should look like the following after it is built:
+
+       Stack Top:
+                       LR          Interrupted LR (LR at time of PENDSV)
+                       r4          Initial value for r4
+                       r5          Initial value for r5
+                       r6          Initial value for r6
+                       r7          Initial value for r7
+                       r8          Initial value for r8
+                       r9          Initial value for r9
+                       r10         Initial value for r10
+                       r11         Initial value for r11
+                       r0          Initial value for r0    (Hardware stack starts here!!)
+                       r1          Initial value for r1
+                       r2          Initial value for r2
+                       r3          Initial value for r3
+                       r12         Initial value for r12
+                       lr          Initial value for lr
+                       pc          Initial value for pc
+                       xPSR        Initial value for xPSR
+
+    Stack Bottom: (higher memory address)  */
+
+    LDR     r2, [r0, #16]                           // Pickup end of stack area
+    BIC     r2, r2, #0x7                            // Align frame for 8-byte alignment
+    SUB     r2, r2, #68                             // Subtract frame size
+#ifdef TX_SINGLE_MODE_SECURE
+    LDR     r3, =0xFFFFFFFD                         // Build initial LR value for secure mode
+#else
+    LDR     r3, =0xFFFFFFBC                         // Build initial LR value to return to non-secure PSP
+#endif
+    STR     r3, [r2, #0]                            // Save on the stack
+
+    /* Actually build the stack frame.  */
+
+    MOV     r3, #0                                  // Build initial register value
+    STR     r3, [r2, #4]                            // Store initial r4
+    STR     r3, [r2, #8]                            // Store initial r5
+    STR     r3, [r2, #12]                           // Store initial r6
+    STR     r3, [r2, #16]                           // Store initial r7
+    STR     r3, [r2, #20]                           // Store initial r8
+    STR     r3, [r2, #24]                           // Store initial r9
+    STR     r3, [r2, #28]                           // Store initial r10
+    STR     r3, [r2, #32]                           // Store initial r11
+
+    /* Hardware stack follows.  */
+
+    STR     r3, [r2, #36]                           // Store initial r0
+    STR     r3, [r2, #40]                           // Store initial r1
+    STR     r3, [r2, #44]                           // Store initial r2
+    STR     r3, [r2, #48]                           // Store initial r3
+    STR     r3, [r2, #52]                           // Store initial r12
+    MOV     r3, #0xFFFFFFFF                         // Poison EXC_RETURN value
+    STR     r3, [r2, #56]                           // Store initial lr
+    STR     r1, [r2, #60]                           // Store initial pc
+    MOV     r3, #0x01000000                         // Only T-bit need be set
+    STR     r3, [r2, #64]                           // Store initial xPSR
+
+    /* Setup stack pointer.  */
+    // thread_ptr -> tx_thread_stack_ptr =  r2;
+
+    STR     r2, [r0, #8]                            // Save stack pointer in thread's
+                                                    //   control block
+    BX      lr                                      // Return to caller
+// }
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c
new file mode 100644
index 00000000..4c9449f3
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c
@@ -0,0 +1,97 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+/* Define the global function pointer for stack error handling. If a stack error is 
+   detected and the application has registered a stack error handler, it will be 
+   called via this function pointer.  */
+
+VOID    (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_stack_error_handler                    Cortex-M33/AC6    */
+/*                                                            6.1.3       */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function processes stack errors detected during run-time.      */
+/*                                                                        */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_terminate                                                */
+/*    _tx_thread_application_stack_error_handler                          */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX internal code                                               */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _tx_thread_stack_error_handler(TX_THREAD *thread_ptr)
+{
+
+    #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR
+    /* Is there a thread?  */
+    if (thread_ptr)
+    {
+        /* Terminate the current thread.  */
+        _tx_thread_terminate(_tx_thread_current_ptr);
+    }
+    #endif
+    
+    /* Determine if the application has registered an error handler.  */
+    if (_tx_thread_application_stack_error_handler != TX_NULL)
+    {
+
+        /* Yes, an error handler is present, simply call the application error handler.  */
+        (_tx_thread_application_stack_error_handler)(thread_ptr);
+    }
+
+}
+
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c
new file mode 100644
index 00000000..0a0527c6
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c
@@ -0,0 +1,98 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_trace.h"
+
+extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_stack_error_notify                     Cortex-M33/AC6    */
+/*                                                            6.1.3       */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function registers an application stack error handler. If      */
+/*    ThreadX detects a stack error, this application handler is called.  */
+/*                                                                        */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    stack_error_handler                   Pointer to stack error        */
+/*                                            handler, TX_NULL to disable */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                                Service return status         */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT  _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr))
+{
+
+TX_INTERRUPT_SAVE_AREA
+
+
+    /* Disable interrupts.  */
+    TX_DISABLE
+
+    /* Make entry in event log.  */
+    TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS)
+
+    /* Make entry in event log.  */
+    TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT
+
+    /* Setup global thread stack error handler.  */
+    _tx_thread_application_stack_error_handler =  stack_error_handler;
+
+    /* Restore interrupts.  */
+    TX_RESTORE
+
+    /* Return success to caller.  */
+    return(TX_SUCCESS);
+}
+
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S
new file mode 100644
index 00000000..e77e9333
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S
@@ -0,0 +1,89 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_system_return                          Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is target processor specific.  It is used to transfer */
+/*    control from a thread back to the ThreadX system.  Only a           */
+/*    minimal context is saved since the compiler assumes temp registers  */
+/*    are going to get slicked by a function call anyway.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling loop        */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */        
+/*                                                                        */
+/**************************************************************************/
+// VOID   _tx_thread_system_return(VOID)
+// {
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_thread_system_return
+    .thumb_func
+.type _tx_thread_system_return, function
+_tx_thread_system_return:
+    /* Return to real scheduler via PendSV. Note that this routine is often
+       replaced with in-line assembly in tx_port.h to improved performance.  */
+
+    MOV     r0, #0x10000000                         // Load PENDSVSET bit
+    LDR     r1, =0xE000E000                         // Load NVIC base
+    STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    MRS     r0, IPSR                                // Pickup IPSR
+    CMP     r0, #0                                  // Is it a thread returning?
+    BNE     _isr_context                            // If ISR, skip interrupt enable
+    MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
+    CPSIE   i                                       // Enable interrupts
+    MSR     PRIMASK, r1                             // Restore original interrupt posture
+_isr_context:
+    BX      lr                                      // Return to caller
+// }
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..8ffde8f1
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S
@@ -0,0 +1,246 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_timer_interrupt                               Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function processes the hardware timer interrupt.  This         */
+/*    processing includes incrementing the system clock and checking for  */
+/*    time slice and/or timer expiration.  If either is found, the        */
+/*    interrupt context save/restore functions are called along with the  */
+/*    expiration functions.                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_timer_expiration_process          Timer expiration processing   */
+/*    _tx_thread_time_slice                 Time slice interrupted thread */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    interrupt vector                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020      Scott Larson            Initial Version 6.1.3         */        
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_timer_interrupt(VOID)
+{ */
+    .section .text
+    .balign 4
+    .syntax unified
+    .eabi_attribute Tag_ABI_align_preserved, 1
+    .global  _tx_timer_interrupt
+    .thumb_func
+.type _tx_timer_interrupt, function
+_tx_timer_interrupt:
+
+    /* Upon entry to this routine, it is assumed that context save has already
+       been called, and therefore the compiler scratch registers are available
+       for use.  */
+
+    /* Increment the system clock.  */
+    // _tx_timer_system_clock++;
+
+    LDR     r1, =_tx_timer_system_clock             // Pickup address of system clock
+    LDR     r0, [r1, #0]                            // Pickup system clock
+    ADD     r0, r0, #1                              // Increment system clock
+    STR     r0, [r1, #0]                            // Store new system clock
+
+    /* Test for time-slice expiration.  */
+    // if (_tx_timer_time_slice)
+    // {
+
+    LDR     r3, =_tx_timer_time_slice               // Pickup address of time-slice
+    LDR     r2, [r3, #0]                            // Pickup time-slice
+    CBZ     r2,  __tx_timer_no_time_slice           // Is it non-active?
+                                                    // Yes, skip time-slice processing
+
+   /* Decrement the time_slice.  */
+   // _tx_timer_time_slice--;
+
+    SUB     r2, r2, #1                              // Decrement the time-slice
+    STR     r2, [r3, #0]                            // Store new time-slice value
+
+   /* Check for expiration.  */
+   // if (__tx_timer_time_slice == 0)
+
+    CBNZ    r2, __tx_timer_no_time_slice            // Has it expired?
+
+   /* Set the time-slice expired flag.  */
+   // _tx_timer_expired_time_slice =  TX_TRUE;
+
+    LDR     r3, =_tx_timer_expired_time_slice       // Pickup address of expired flag
+    MOV     r0, #1                                  // Build expired value
+    STR     r0, [r3, #0]                            // Set time-slice expiration flag
+
+    // }
+
+__tx_timer_no_time_slice:
+
+    /* Test for timer expiration.  */
+    // if (*_tx_timer_current_ptr)
+    // {
+
+    LDR     r1, =_tx_timer_current_ptr              // Pickup current timer pointer address
+    LDR     r0, [r1, #0]                            // Pickup current timer
+    LDR     r2, [r0, #0]                            // Pickup timer list entry
+    CBZ     r2, __tx_timer_no_timer                 // Is there anything in the list?
+                                                    // No, just increment the timer
+
+    /* Set expiration flag.  */
+    // _tx_timer_expired =  TX_TRUE;
+
+    LDR     r3, =_tx_timer_expired                  // Pickup expiration flag address
+    MOV     r2, #1                                  // Build expired value
+    STR     r2, [r3, #0]                            // Set expired flag
+    B       __tx_timer_done                         // Finished timer processing
+
+    // }
+    // else
+    // {
+__tx_timer_no_timer:
+
+    /* No timer expired, increment the timer pointer.  */
+    // _tx_timer_current_ptr++;
+
+    ADD     r0, r0, #4                              // Move to next timer
+
+    /* Check for wrap-around.  */
+    // if (_tx_timer_current_ptr == _tx_timer_list_end)
+
+    LDR     r3, =_tx_timer_list_end                 // Pickup addr of timer list end
+    LDR     r2, [r3, #0]                            // Pickup list end
+    CMP     r0, r2                                  // Are we at list end?
+    BNE     __tx_timer_skip_wrap                    // No, skip wrap-around logic
+
+        /* Wrap to beginning of list.  */
+        // _tx_timer_current_ptr =  _tx_timer_list_start;
+
+    LDR     r3, =_tx_timer_list_start               // Pickup addr of timer list start
+    LDR     r0, [r3, #0]                            // Set current pointer to list start
+
+__tx_timer_skip_wrap:
+
+    STR     r0, [r1, #0]                            // Store new current timer pointer
+    // }
+
+__tx_timer_done:
+
+
+    /* See if anything has expired.  */
+    // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+    // {
+
+    LDR     r3, =_tx_timer_expired_time_slice       // Pickup addr of expired flag
+    LDR     r2, [r3, #0]                            // Pickup time-slice expired flag
+    CBNZ    r2, __tx_something_expired              // Did a time-slice expire?
+                                                    // If non-zero, time-slice expired
+    LDR     r1, =_tx_timer_expired                  // Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                            // Pickup timer expired flag
+    CBZ     r0, __tx_timer_nothing_expired          // Did a timer expire?
+                                                    // No, nothing expired
+
+__tx_something_expired:
+
+    STMDB   sp!, {r0, lr}                           // Save the lr register on the stack
+                                                    //   and save r0 just to keep 8-byte alignment
+
+    /* Did a timer expire?  */
+    // if (_tx_timer_expired)
+    // {
+
+    LDR     r1, =_tx_timer_expired                  // Pickup addr of expired flag
+    LDR     r0, [r1, #0]                            // Pickup timer expired flag
+    CBZ     r0, __tx_timer_dont_activate            // Check for timer expiration
+                                                    // If not set, skip timer activation
+
+    /* Process timer expiration.  */
+    // _tx_timer_expiration_process();
+
+    BL      _tx_timer_expiration_process            // Call the timer expiration handling routine
+
+    // }
+__tx_timer_dont_activate:
+
+    /* Did time slice expire?  */
+    // if (_tx_timer_expired_time_slice)
+    // {
+
+    LDR     r3, =_tx_timer_expired_time_slice       // Pickup addr of time-slice expired
+    LDR     r2, [r3, #0]                            // Pickup the actual flag
+    CBZ     r2, __tx_timer_not_ts_expiration        // See if the flag is set
+                                                    // No, skip time-slice processing
+
+    /* Time slice interrupted thread.  */
+    // _tx_thread_time_slice();
+
+    BL      _tx_thread_time_slice                   // Call time-slice processing
+    LDR     r0, =_tx_thread_preempt_disable         // Build address of preempt disable flag
+    LDR     r1, [r0]                                // Is the preempt disable flag set?
+    CBNZ    r1, __tx_timer_skip_time_slice          // Yes, skip the PendSV logic
+    LDR     r0, =_tx_thread_current_ptr             // Build current thread pointer address
+    LDR     r1, [r0]                                // Pickup the current thread pointer
+    LDR     r2, =_tx_thread_execute_ptr             // Build execute thread pointer address
+    LDR     r3, [r2]                                // Pickup the execute thread pointer
+    LDR     r0, =0xE000ED04                         // Build address of control register
+    MOV     r2, 0x10000000                          // Build value for PendSV bit
+    CMP     r1, r3                                  // Are they the same?
+    BEQ     __tx_timer_skip_time_slice              // If the same, there was no time-slice performed
+    STR     r2, [r0]                                // Not the same, issue the PendSV for preemption
+__tx_timer_skip_time_slice:
+
+    // }
+
+__tx_timer_not_ts_expiration:
+
+    LDMIA   sp!, {r0, lr}                           // Recover lr register (r0 is just there for
+
+    // }
+
+__tx_timer_nothing_expired:
+
+    DSB                                             // Complete all memory access
+    BX      lr                                      // Return to caller
+
+// }
+    .end
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c
new file mode 100644
index 00000000..6268cba9
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c
@@ -0,0 +1,123 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_secure_stack_allocate                    PORTABLE C      */
+/*                                                            6.1.3       */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function checks for errors in the secure stack allocate        */
+/*    function call.                                                      */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*    stack_size                            Size of secure stack to       */
+/*                                            allocate                    */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    TX_THREAD_ERROR                       Invalid thread pointer        */
+/*    TX_CALLER_ERROR                       Invalid caller of function    */
+/*    status                                Actual completion status      */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_secure_stack_allocate      Actual stack alloc function   */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT    _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
+{
+#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE)
+    return(TX_FEATURE_NOT_ENABLED);
+#else
+UINT    status;
+    
+    /* Default status to success.  */
+    status =  TX_SUCCESS;
+    
+    /* Check for an invalid thread pointer.  */
+    if (thread_ptr == TX_NULL)
+    {
+
+        /* Thread pointer is invalid, return appropriate error code.  */
+        status =  TX_THREAD_ERROR;
+    }
+
+    /* Now check for invalid thread ID.  */
+    else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
+    {
+
+        /* Thread pointer is invalid, return appropriate error code.  */
+        status =  TX_THREAD_ERROR;
+    }
+    
+    /* Check for interrupt call.  */
+    if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0))
+    {
+        /* Is call from an interrupt and not initialization?  */
+        if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
+        {
+            /* Invalid caller of this function, return appropriate error code.  */
+            status =  TX_CALLER_ERROR;
+        }
+    }
+    
+    /* Determine if everything is okay.  */
+    if (status == TX_SUCCESS)
+    {
+
+        /* Call actual secure stack allocate function.  */
+        status =  _tx_thread_secure_stack_allocate(thread_ptr, stack_size);
+    }
+
+    /* Return completion status.  */
+    return(status);
+#endif
+}
+
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c
new file mode 100644
index 00000000..4e6a9ed9
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c
@@ -0,0 +1,121 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txe_thread_secure_stack_free                       PORTABLE C      */
+/*                                                            6.1.3       */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function checks for errors in the secure stack free            */
+/*    function call.                                                      */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Thread control block pointer  */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    TX_THREAD_ERROR                       Invalid thread pointer        */
+/*    TX_CALLER_ERROR                       Invalid caller of function    */
+/*    status                                Actual completion status      */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_secure_stack_free          Actual stack free function    */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT    _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)
+{
+#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE)
+    return(TX_FEATURE_NOT_ENABLED);
+#else
+UINT    status;
+    
+    /* Default status to success.  */
+    status =  TX_SUCCESS;
+    
+    /* Check for an invalid thread pointer.  */
+    if (thread_ptr == TX_NULL)
+    {
+
+        /* Thread pointer is invalid, return appropriate error code.  */
+        status =  TX_THREAD_ERROR;
+    }
+
+    /* Now check for invalid thread ID.  */
+    else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
+    {
+
+        /* Thread pointer is invalid, return appropriate error code.  */
+        status =  TX_THREAD_ERROR;
+    }
+    
+    /* Check for interrupt call.  */
+    if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0))
+    {
+        /* Is call from an interrupt and not initialization?  */
+        if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
+        {
+            /* Invalid caller of this function, return appropriate error code.  */
+            status =  TX_CALLER_ERROR;
+        }
+    }
+    
+    /* Determine if everything is okay.  */
+    if (status == TX_SUCCESS)
+    {
+
+        /* Call actual secure stack allocate function.  */
+        status =  _tx_thread_secure_stack_free(thread_ptr);
+    }
+
+    /* Return completion status.  */
+    return(status);
+#endif
+}
+
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c
new file mode 100644
index 00000000..eebd313f
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c
@@ -0,0 +1,85 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "txm_module.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_alignment_adjust            Cortex-M33/MPU/AC6  */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function adjusts the alignment and size of the code and data   */
+/*    section for a given module implementation.                          */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_preamble                   Pointer to module preamble        */
+/*    code_size                         Size of the code area (updated)   */
+/*    code_alignment                    Code area alignment (updated)     */
+/*    data_size                         Size of data area (updated)       */
+/*    data_alignment                    Data area alignment (updated)     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Initial thread stack frame                                          */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
+                                           ULONG *code_size,
+                                           ULONG *code_alignment,
+                                           ULONG *data_size,
+                                           ULONG *data_alignment)
+{
+
+    /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */
+    *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1);
+    *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1);
+    
+    /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */
+    *code_alignment =   TXM_MODULE_MPU_ALIGNMENT;
+    *data_alignment =   TXM_MODULE_MPU_ALIGNMENT;
+}
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c
new file mode 100644
index 00000000..e5d9e887
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c
@@ -0,0 +1,164 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "tx_mutex.h"
+#include "tx_queue.h"
+#include "tx_thread.h"
+#include "txm_module.h"
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_external_memory_enable      Cortex-M33/MPU/AC6  */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function creates an entry in the MPU table for a shared        */
+/*    memory space. The start_address must be 32-byte aligned.            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Module instance pointer           */
+/*    start_address                     Start address of memory           */
+/*    length                            Length of external memory         */
+/*    attributes                        Memory attributes (r/w)           */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_mutex_get                     Get protection mutex              */
+/*    _tx_mutex_put                     Release protection mutex          */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT  _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
+                                                 VOID *start_address,
+                                                 ULONG length,
+                                                 UINT attributes)
+{
+
+ULONG   address;
+ULONG   shared_index;
+
+    /* Determine if the module manager has not been initialized yet.  */
+    if (_txm_module_manager_ready != TX_TRUE)
+    {
+        /* Module manager has not been initialized.  */
+        return(TX_NOT_AVAILABLE);
+    }
+
+    /* Determine if the module is valid.  */
+    if (module_instance == TX_NULL)
+    {
+        /* Invalid module pointer.  */
+        return(TX_PTR_ERROR);
+    }
+
+    /* Get module manager protection mutex.  */
+    _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
+
+    /* Determine if the module instance is valid.  */
+    if (module_instance -> txm_module_instance_id != TXM_MODULE_ID)
+    {
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+
+        /* Invalid module pointer.  */
+        return(TX_PTR_ERROR);
+    }
+    
+    /* Determine if the module instance is in the loaded state.  */
+    if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED)
+    {
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+
+        /* Return error if the module is not ready.  */
+        return(TX_START_ERROR);
+    }
+    
+    /* Determine if there are shared memory entries available.  */
+    if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES)
+    {
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+        
+        /* No more entries available.  */
+        return(TX_NO_MEMORY);
+    }
+    
+    /* Start address must adhere to Cortex-M33 MPU alignment.  */
+    address = (ULONG) start_address;
+    if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1)))
+    {
+        /* Release the protection mutex.  */
+        _tx_mutex_put(&_txm_module_manager_mutex);
+        
+        /* Return alignment error.  */
+        return(TXM_MODULE_ALIGNMENT_ERROR);
+    }
+    
+    /* At this point, we have a valid address. Set up MPU registers.  */
+    
+    /* Pick up index into shared memory entries.  */
+    shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count;
+    
+    /* Set base address register with start address, sanitized attributes and execute never.  */
+    module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER;
+    
+    /* Set the limit address (data start + length-1), attribute index, and enable bit.  */
+    module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
+    
+    /* Keep track of shared memory address and length in module instance.  */
+    module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address;
+    module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length;
+    
+    /* Increment counter.  */
+    module_instance -> txm_module_instance_shared_memory_count++;
+    
+    /* Release the protection mutex.  */
+    _tx_mutex_put(&_txm_module_manager_mutex);
+    
+    /* Return success.  */
+    return(TX_SUCCESS);
+}
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c
new file mode 100644
index 00000000..e57e3555
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c
@@ -0,0 +1,110 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "txm_module.h"
+
+
+/* Define the user's fault notification callback function pointer.  This is
+   setup via the txm_module_manager_memory_fault_notify API.  */
+
+VOID    (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
+
+
+/* Define a macro that can be used to allocate global variables useful to
+   store information about the last fault. This macro is defined in
+   txm_module_port.h and is usually populated in the assembly language
+   fault handling prior to the code calling _txm_module_manager_memory_fault_handler.  */
+
+TXM_MODULE_MANAGER_FAULT_INFO
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_memory_fault_handler        Cortex-M33/MPU/AC6  */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function handles a fault associated with a memory protected    */
+/*    module.                                                             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_terminate              Terminate thread                  */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Fault handler                                                       */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _txm_module_manager_memory_fault_handler(VOID)
+{
+
+TXM_MODULE_INSTANCE     *module_instance_ptr;
+TX_THREAD               *thread_ptr;
+
+    /* Pickup the current thread.  */
+    thread_ptr =  _tx_thread_current_ptr;
+
+    /* Initialize the module instance pointer to NULL.  */
+    module_instance_ptr =  TX_NULL;
+    
+    /* Is there a thread?  */
+    if (thread_ptr)
+    {
+        /* Pickup the module instance.  */
+        module_instance_ptr =  thread_ptr -> tx_thread_module_instance_ptr;
+
+        /* Terminate the current thread.  */
+        _tx_thread_terminate(_tx_thread_current_ptr);
+    }
+    
+    /* Determine if there is a user memory fault notification callback.  */
+    if (_txm_module_manager_fault_notify)
+    {
+        /* Yes, call the user's notification memory fault callback.  */
+        (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr);
+    }
+}
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c
new file mode 100644
index 00000000..ec08139a
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c
@@ -0,0 +1,84 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "txm_module.h"
+
+
+/* Define the external user's fault notification callback function pointer.  This is
+   setup via the txm_module_manager_memory_fault_notify API.  */
+
+extern VOID    (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
+
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_memory_fault_notify         Cortex-M33/MPU/AC6  */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function registers an application callback when/if a memory    */
+/*    fault occurs. The supplied thread is automatically terminated, but  */
+/*    any other threads in the same module may still execute.             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    notify_function                   Memory fault notification         */
+/*                                        function, NULL disables.        */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT  _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))
+{
+    /* Setup notification function.  */
+    _txm_module_manager_fault_notify =  notify_function;
+    
+    /* Return success.  */
+    return(TX_SUCCESS);
+}
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c
new file mode 100644
index 00000000..a38602d9
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c
@@ -0,0 +1,190 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "txm_module.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_mm_register_setup             Cortex-M33/MPU    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function sets up the Cortex-M33 MPU register definitions based */
+/*    on the module's memory characteristics.                             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Pointer to module instance        */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    MPU settings for the module in module_instance                      */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    none                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _txm_module_manager_thread_create                                   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+VOID  _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
+{
+
+ULONG   data_size;
+ULONG   start_stop_stack_size;
+ULONG   callback_stack_size;
+
+    /* Setup MPU region for kernel mode entry.  */
+    /* Set base address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned.
+       Mask address to proper range, inner shareable, read only. */
+    module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_base_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY;
+    /* Set the limit address, attribute index, and enable bit.  */
+    module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_limit_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
+    /* End of kernel mode entry setup.  */
+
+
+    /* Setup MPU region for module code protection.  */
+    /* Set base address register to module code address, which should be at least 32-byte aligned.
+       Mask address to proper range, inner shareable, read only. */
+    module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_code_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY;
+    /* Set the limit address (code start + code size-1), attribute index, and enable bit.  */
+    module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_code_start + module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
+    /* End of module code protection.  */
+
+
+    /* Setup MPU region for module data protection.  */
+    /* Set base address register to module data address, which should be at least 32-byte aligned.
+       Mask address to proper range, inner shareable, read write, execute never. */
+    module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER;
+    
+    /* Adjust the size of the module elements to be aligned to the default alignment. We do this
+       so that when we partition the allocated memory, we can simply place these regions right beside
+       each other without having to align their pointers. Note this only works when they all have
+       the same alignment.  */
+    
+    data_size =             module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size;
+    start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size;
+    callback_stack_size =   module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size;
+    
+    data_size =              ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
+    start_stop_stack_size =  ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
+    callback_stack_size =    ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
+
+    /* Update the data size to include thread stacks.  */
+    data_size = data_size + start_stop_stack_size + callback_stack_size;
+    
+    /* Set the limit address (data start + data size-1), attribute index, and enable bit.  */
+    module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
+    /* End of module data protection.  */
+    
+    /* Remaining MPU entries are disabled for now and can be used for shared memory. */
+}
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_inside_data_check          Cortex-M33/MPU/AC6   */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function checks if the specified object is inside shared       */
+/*    memory.                                                             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Pointer to module instance        */
+/*    obj_ptr                           Pointer to the object             */
+/*    obj_size                          Size of the object                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    Whether the object is inside the shared memory region.              */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Module dispatch check functions                                     */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)
+{
+
+UINT shared_memory_index;
+UINT num_shared_memory_mpu_entries;
+ALIGN_TYPE shared_memory_address_start;
+ALIGN_TYPE shared_memory_address_end;
+
+    /* Check if the object is inside the module data.  */
+    if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) &&
+        ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1)))
+    {
+        return(TX_TRUE);
+    }
+
+    /* Check if the object is inside the shared memory.  */
+    num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count;
+    for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++)
+    {
+
+        shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index];
+        shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index];
+
+        if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) &&
+            ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end))
+        {
+            return(TX_TRUE);
+        }
+    }
+
+    return(TX_FALSE);
+}
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c
new file mode 100644
index 00000000..422b0826
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c
@@ -0,0 +1,115 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+#include "tx_api.h"
+#include "txm_module.h"
+#include "txm_module_manager_util.h"
+
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_port_dispatch                 Cortex-M33/AC6    */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function dispatches the module's kernel request based upon the */
+/*    ID and parameters specified in the request.                         */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    module_instance                   Module pointer                    */
+/*    kernel_request                    Module's kernel request           */
+/*    param_0                           First parameter                   */
+/*    param_1                           Second parameter                  */
+/*    param_2                           Third parameter                   */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    status                            Completion status                 */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    Port-specific ThreadX API Calls                                     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _txm_module_manager_kernel_dispatch                                 */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)
+{
+
+ALIGN_TYPE return_value = TX_NOT_AVAILABLE;
+
+    switch(kernel_request)
+    {
+        case TXM_THREAD_SECURE_STACK_ALLOCATE_CALL:
+        {
+            if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
+            {
+                if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
+                    return(TXM_MODULE_INVALID_MEMORY);
+            }
+
+            return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate(
+                (TX_THREAD *) param_0,
+                (ULONG) param_1
+            );
+            break;
+        }
+        
+        case TXM_THREAD_SECURE_STACK_FREE_CALL:
+        {
+            if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
+            {
+                if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
+                    return(TXM_MODULE_INVALID_MEMORY);
+            }
+
+            return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free(
+                (TX_THREAD *) param_0
+            );
+            break;
+        }
+        
+        default:
+        {
+            /* Unhandled kernel request, return an error!  */
+            break;
+        }
+    }
+    
+    return(return_value);
+}
diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S
new file mode 100644
index 00000000..9d49531c
--- /dev/null
+++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S
@@ -0,0 +1,143 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Module Manager                                                      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+    .text
+    .align 4
+    .syntax unified
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _txm_module_manager_thread_stack_build          Cortex-M33/MPU/AC6  */
+/*                                                           6.1.3        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Scott Larson, Microsoft Corporation                                 */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread             */
+/*    function_ptr                          Pointer to shell function     */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  12-31-2020     Scott Larson             Initial Version 6.1.3         */
+/*                                                                        */
+/**************************************************************************/
+// VOID   _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
+// {
+    .global  _txm_module_manager_thread_stack_build
+    .thumb_func
+_txm_module_manager_thread_stack_build:
+
+    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+       on the Cortex-M should look like the following after it is built:
+
+       Stack Top:
+                    LR          Interrupted LR (LR at time of PENDSV)
+                    r4          Initial value for r4
+                    r5          Initial value for r5
+                    r6          Initial value for r6
+                    r7          Initial value for r7
+                    r8          Initial value for r8
+                    r9          Initial value for r9
+                    r10         Initial value for r10
+                    r11         Initial value for r11
+                    r0          Initial value for r0    (Hardware stack starts here!!)
+                    r1          Initial value for r1
+                    r2          Initial value for r2
+                    r3          Initial value for r3
+                    r12         Initial value for r12
+                    lr          Initial value for lr
+                    pc          Initial value for pc
+                    xPSR        Initial value for xPSR
+
+    Stack Bottom: (higher memory address)  */
+
+    LDR     r2, [r0, #16]                       // Pickup end of stack area
+    BIC     r2, r2, #0x7                        // Align frame
+    SUB     r2, r2, #68                         // Subtract frame size
+#ifdef TX_SINGLE_MODE_SECURE
+    LDR     r3, =0xFFFFFFFD                     // Build initial LR value for secure mode
+#else
+    LDR     r3, =0xFFFFFFBC                     // Build initial LR value to return to non-secure PSP
+#endif
+    STR     r3, [r2, #0]                        // Save on the stack
+
+    /* Actually build the stack frame.  */
+
+    MOV     r3, #0                              // Build initial register value
+    STR     r3, [r2, #4]                        // Store initial r4
+    STR     r3, [r2, #8]                        // Store initial r5
+    STR     r3, [r2, #12]                       // Store initial r6
+    STR     r3, [r2, #16]                       // Store initial r7
+    STR     r3, [r2, #20]                       // Store initial r8
+    STR     r3, [r2, #28]                       // Store initial r10
+    STR     r3, [r2, #32]                       // Store initial r11
+
+    /* Hardware stack follows.  */
+
+    STR     r0, [r2, #36]                       // Store initial r0, which is the thread control block
+
+    LDR     r3, [r0, #8]                        // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
+                                                //   It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
+                                                //   function with the actual, initial stack pointer.
+    STR     r3, [r2, #40]                       // Store initial r1, which is the module entry information.
+    LDR     r3, [r3, #8]                        // Pickup data base register from the module information
+    STR     r3, [r2, #24]                       // Store initial r9 (data base register)
+    MOV     r3, #0                              // Clear r3 again
+
+    STR     r3, [r2, #44]                       // Store initial r2
+    STR     r3, [r2, #48]                       // Store initial r3
+    STR     r3, [r2, #52]                       // Store initial r12
+    MOV     r3, #0xFFFFFFFF                     // Poison EXC_RETURN value
+    STR     r3, [r2, #56]                       // Store initial lr
+    STR     r1, [r2, #60]                       // Store initial pc
+    MOV     r3, #0x01000000                     // Only T-bit need be set
+    STR     r3, [r2, #64]                       // Store initial xPSR
+
+    /* Setup stack pointer.  */
+    // thread_ptr -> tx_thread_stack_ptr =  r2;
+
+    STR     r2, [r0, #8]                        // Save stack pointer in thread's control block
+    BX      lr                                  // Return to caller
+// }
diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml
deleted file mode 100644
index 006b16bf..00000000
--- a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml
+++ /dev/null
@@ -1,4594 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-    	
-    <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" name="Debug">
-        		
-        <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-            			
-            <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-890320463837788586" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true" store-entries-with-project="true">
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
-                				
-                <language id="com.arm.eclipse.builder.armcc.lang.c.ac6">
-                    					
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-                    <entry kind="macro" name="__clang_major__" value="11">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__clang_minor__" value="0">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__clang_patchlevel__" value="0">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__clang_version__" value="&quot;11.0.0 &quot;">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cplusplus" value="201402L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_aggregate_nsdmi" value="201304L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_alias_templates" value="200704L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_attributes" value="200809L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_binary_literals" value="201304L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_constexpr" value="201304L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_constexpr_in_decltype" value="201711L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_decltype" value="200707L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_decltype_auto" value="201304L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_delegating_constructors" value="200604L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_digit_separators" value="201309L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_generic_lambdas" value="201304L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_impl_destroying_delete" value="201806L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_inheriting_constructors" value="201511L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_init_captures" value="201304L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_initializer_lists" value="200806L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_lambdas" value="200907L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_nsdmi" value="200809L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_range_based_for" value="200907">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_raw_strings" value="200710L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_ref_qualifiers" value="200710L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_return_type_deduction" value="201304L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_rtti" value="199711L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_rvalue_references" value="200610L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_static_assert" value="200410">
-                        						
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-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_threadsafe_static_init" value="200806L">
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-                        					
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-                    <entry kind="macro" name="__cpp_unicode_characters" value="200704L">
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-                        					
-                    </entry>
-                    					
-                    <entry kind="macro" name="__cpp_unicode_literals" value="200710L">
-                        						
-                        <flag value="BUILTIN|READONLY"/>
-                        					
-                    </entry>
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-                    <entry kind="macro" name="__cpp_user_defined_literals" value="200809L">
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-                        					
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-                    <entry kind="macro" name="__cpp_variable_templates" value="201304L">
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-                    <entry kind="macro" name="__cpp_variadic_templates" value="200704L">
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-                        					
-                    </entry>
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-                    <entry kind="macro" name="__sizeof_long" value="8">
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-                        					
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-                    <entry kind="macro" name="__sizeof_ptr" value="8">
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-                        					
-                    </entry>
-                    				
-                </language>
-                			
-            </provider>
-            		
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-        	
-    </configuration>
-    
-</project>
diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat
new file mode 100644
index 00000000..1288a328
--- /dev/null
+++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat
@@ -0,0 +1,262 @@
+;********************************************************
+; Scatter file for Armv8-A Startup code on FVP Base model
+; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
+; Use, modification and redistribution of this file is subject to your
+; possession of a valid DS-5 end user licence agreement and your compliance
+; with all applicable terms and conditions of such licence agreement.
+;********************************************************
+
+LOAD 0x80000000
+{
+    EXEC +0
+    {
+        startup.o (StartUp, +FIRST)
+        * (+RO, +RW, +ZI)
+        
+    }
+    ;XTABLES +0 ALIGN 0x1000
+    ;{
+    ;   xtables.o (*) 
+    ;}
+    
+    SYS_STACK +0 ALIGN 8 EMPTY 0x1000
+    {
+    }
+
+    ;
+    ; Separate heap - import symbol __use_two_region_memory
+    ; in source code for this to work correctly
+    ;
+    ARM_LIB_HEAP     +0 ALIGN 64 EMPTY 0xA0000 {}
+
+    ;
+    ; App stacks for all CPUs
+    ; All stacks and heap are aligned to a cache-line boundary
+    ;
+    ARM_LIB_STACK    +0 ALIGN 64 EMPTY 4 * 0x4000 {}
+    
+    ;
+    ; Handler stacks for all CPUs
+    ; All stacks and heap are aligned to a cache-line boundary
+    ;
+    HANDLER_STACK    +0 ALIGN 64 EMPTY 4 * 0x4000 {}
+    
+    ;
+    ; Stacks for EL3
+    ;
+    EL3_STACKS       +0 ALIGN 64 EMPTY 4 * 0x1000 {}
+    ;
+    ; Strictly speaking, the L1 tables don't need to
+    ; be so strongly aligned, but no matter
+    ;
+    TTB0_L1          +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    ;
+    ; Various sets of L2 tables
+    ;
+    ; Alignment is 4KB, since the code uses a 4K page
+    ; granularity - larger granularities would require
+    ; correspondingly stricter alignment
+    ;
+    TTB0_L2_RAM      +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    TTB0_L2_PRIVATE  +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    TTB0_L2_PERIPH   +0 ALIGN 4096 EMPTY 0x1000 {}
+
+    ;
+    ; The startup code uses the end of this region to calculate
+    ; the top of memory - don't place any RAM regions after it
+    ;
+    TOP_OF_RAM  +0 EMPTY 4 {}
+
+    ;
+    ; CS3 Peripherals is a 64MB region from 0x1c000000
+    ; that includes the following:
+    ; System Registers             at 0x1C010000
+    ; UART0 (PL011)                at 0x1C090000
+    ; Color LCD Controller (PL111) at 0x1C1F0000
+    ; plus a number of others.
+    ; CS3_PERIPHERALS is used by the startup code for page-table generation
+    ; This region is not truly empty, but we have no
+    ; predefined objects that live within it
+    ;
+    CS3_PERIPHERALS  0x1c000000 EMPTY 0x90000 {}
+
+    ;
+    ; Place the UART peripheral registers data structure
+    ; This is only really needed if USE_SERIAL_PORT is defined, but
+    ; the linker will remove unused sections if not needed
+;    PL011  0x1c090000 UNINIT 0x1000
+;    {
+;        uart.o (+ZI)
+;    }
+    ; Note that some other CS3_PERIPHERALS follow this
+
+    ;
+    ; GICv3 distributor
+    ;
+    GICD  0x2f000000 UNINIT 0x8000
+    {
+        GICv3_gicd.o (.bss.distributor)
+    }
+
+    ;
+    ; GICv3 redistributors
+    ; 128KB for each redistributor in the system
+    ;
+    GICR  0x2f100000 UNINIT 0x80000
+    {
+        GICv3_gicr.o (.bss.redistributor)
+    }
+}
+
+
+
+
+
+; Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+;
+; Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without specific
+; prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+
+;RO AlignExpr(0x80000000, 0x1000)
+;{
+;    C_SYNCH_SP0 +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_synch_sp0)
+;    }
+;    C_IRQ_SP0 +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_irq_sp0)
+;    }
+;    C_FIQ_SP0 +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_fiq_sp0)
+;    }
+;    C_SERROR_SP0 +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_serror_sp0)
+;    }
+;
+;    C_SYNCH_SPX +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_synch_spx)
+;    }
+;    C_IRQ_SPX +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_irq_spx)
+;    }
+;    C_FIQ_SPX +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_fiq_spx)
+;    }
+;    C_SERROR_SPX +0 ALIGN 0x80
+;    {
+;        vectors.o (_c_serror_spx)
+;    }
+;
+;    L64_SYNCH +0 ALIGN 0x80
+;    {
+;        vectors.o (_l64_synch)
+;    }
+;    L64_IRQ +0 ALIGN 0x80
+;    {
+;        vectors.o (_l64_irq)
+;    }
+;    L64_FIQ +0 ALIGN 0x80
+;    {
+;        vectors.o (_l64_fiq)
+;    }
+;    L64_SERROR +0 ALIGN 0x80
+;    {
+;        vectors.o (_l64_serror)
+;    }
+;
+;    L32_SYNCH +0 ALIGN 0x80
+;    {
+;        vectors.o (_l32_synch)
+;    }
+;    L32_IRQ +0 ALIGN 0x80
+;    {
+;        vectors.o (_l32_irq)
+;    }
+;    L32_FIQ +0 ALIGN 0x80
+;    {
+;        vectors.o (_l32_fiq)
+;    }
+;    L32_SERROR +0 ALIGN 0x80
+;    {
+;        vectors.o (_l32_serror)
+;    }
+;
+;    ROSEC +0 ALIGN 8
+;    {
+;        *( +RO )
+;    }
+;    
+;    XTABLES +0 ALIGN 0x1000
+;    {
+;        xtables.o (*) 
+;    }
+;}
+;
+;RW AlignExpr(ImageLimit(XTABLES), 0x1000)
+;{   
+;    RWSEC +0
+;    {
+;        *( +RW )
+;    }
+;    
+;    ZISEC +0
+;    {
+;        *( +ZI )
+;    }
+;    
+;    SYS_STACK +0 ALIGN 8 EMPTY 0x1000
+;    {
+;    }
+;    
+;    ; 512 MiB heap
+;    HEAP +0 ALIGN 8 EMPTY 0x10000000
+;    {
+;    }
+;    
+;    ; Free Memory section
+;    FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000
+;    {
+;    }
+;
+;    ; Per-CPU 128 MiB task stacks
+;    TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000)
+;    {
+;    }
+;    
+;    ; Per-CPU 128 MiB handler stacks
+;    HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000)
+;    {
+;    }
+;}
diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.settings/language.settings.xml
deleted file mode 100644
index 4cc349c4..00000000
--- a/ports_smp/cortex_a35_smp/ac6/example_build/tx/.settings/language.settings.xml
+++ /dev/null
@@ -1,48 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-    	
-    <configuration id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944" name="Debug">
-        		
-        <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-            			
-            <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-890320463837788586" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
-                			
-            </provider>
-            		
-        </extension>
-        	
-    </configuration>
-    	
-    <configuration id="com.arm.eclipse.build.config.v6.lib.release.base.597173224" name="Release">
-        		
-        <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-            			
-            <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-            			
-            <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-936373864897685072" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
-                				
-                <language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
-                			
-            </provider>
-            		
-        </extension>
-        	
-    </configuration>
-    
-</project>