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Release 6.1.6
This commit is contained in:
Yuxin Zhou
154
ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt
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154
ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt
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@@ -0,0 +1,154 @@
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# Parameters:
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# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
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#----------------------------------------------------------------------------------------------
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cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
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idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
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cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
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cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
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fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
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fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
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fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
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fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
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fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
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fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
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fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
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fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
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fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
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fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
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fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
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fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
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fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
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fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
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fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
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fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
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fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
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fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
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fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
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fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
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fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
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fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
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fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
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fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
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fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
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fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
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fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
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fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
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fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
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fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
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fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
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fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
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fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
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fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
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fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
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fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
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fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
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fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
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fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
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fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
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fvp_mps2.sse200.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
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fvp_mps2.sse200.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
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fvp_mps2.sse200.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
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fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
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fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
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fvp_mps2.sse200.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.sse200.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
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fvp_mps2.sse200.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
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fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
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fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:48:c5" # (string, init-time) default = '00:02:f7:ef:48:c5' : Host/model MAC address
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fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
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fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
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fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
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fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
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fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
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fvp_mps2.sse200.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
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fvp_mps2.sse200.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
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fvp_mps2.sse200.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
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fvp_mps2.sse200.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
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fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
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fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
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fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
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fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
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fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
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fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
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fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
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fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
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fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
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fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
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fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
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fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
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fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
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fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
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fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
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fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
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fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
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fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
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fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
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fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
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fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
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fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
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fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
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fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
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fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
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fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
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fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
|
||||
fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
|
||||
fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
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||||
fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
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||||
fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
|
||||
fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
|
||||
fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
|
||||
fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
|
||||
fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
|
||||
fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
|
||||
fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
|
||||
fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
|
||||
fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
|
||||
fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
|
||||
fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
|
||||
fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
|
||||
#----------------------------------------------------------------------------------------------
|
||||
36
ports_module/cortex_m23/ac6/example_build/AzureRTOS.uvmpw
Normal file
36
ports_module/cortex_m23/ac6/example_build/AzureRTOS.uvmpw
Normal file
@@ -0,0 +1,36 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<WorkspaceName>WorkSpace</WorkspaceName>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\demo_secure_zone\demo_secure_zone.uvprojx</PathAndName>
|
||||
<NodeIsActive>1</NodeIsActive>
|
||||
<NodeIsExpanded>1</NodeIsExpanded>
|
||||
</project>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx</PathAndName>
|
||||
<NodeIsExpanded>1</NodeIsExpanded>
|
||||
</project>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\ThreadX_Library.uvprojx</PathAndName>
|
||||
<NodeIsExpanded>1</NodeIsExpanded>
|
||||
</project>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\sample_threadx_module\sample_threadx_module.uvprojx</PathAndName>
|
||||
<NodeIsExpanded>1</NodeIsExpanded>
|
||||
</project>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\txm\txm.uvprojx</PathAndName>
|
||||
<NodeIsExpanded>1</NodeIsExpanded>
|
||||
</project>
|
||||
|
||||
</ProjectWorkspace>
|
||||
5
ports_module/cortex_m23/ac6/example_build/Debug.ini
Normal file
5
ports_module/cortex_m23/ac6/example_build/Debug.ini
Normal file
@@ -0,0 +1,5 @@
|
||||
LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental
|
||||
LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental
|
||||
LOAD "..\\sample_threadx_module\\Objects\\sample_threadx_module.axf" incremental
|
||||
RESET
|
||||
g, \\demo_secure_zone\main_s\main
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'ThreadX_Library'
|
||||
* Target: 'ThreadX_Library_Project'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM23_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
2960
ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx
Normal file
2960
ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx
Normal file
File diff suppressed because it is too large
Load Diff
1588
ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx
Normal file
1588
ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,81 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc
|
||||
; command above MUST be in first line (no comment above!)
|
||||
|
||||
/*
|
||||
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Flash Configuration ----------------------------------
|
||||
; <h> Flash Configuration
|
||||
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __ROM_BASE 0x00000000
|
||||
#define __ROM_SIZE 0x00040000
|
||||
|
||||
/*--------------------- Embedded RAM Configuration ---------------------------
|
||||
; <h> RAM Configuration
|
||||
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_BASE 0x20000000
|
||||
#define __RAM_SIZE 0x00020000
|
||||
|
||||
/*--------------------- Stack / Heap Configuration ---------------------------
|
||||
; <h> Stack / Heap Configuration
|
||||
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_SIZE 0x00000200
|
||||
#define __HEAP_SIZE 0x00000C00
|
||||
|
||||
/*
|
||||
;------------- <<< end of configuration section >>> ---------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
User Stack & Heap boundary definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
|
||||
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Scatter File Definitions definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RO_BASE __ROM_BASE
|
||||
#define __RO_SIZE __ROM_SIZE
|
||||
|
||||
#define __RW_BASE __RAM_BASE
|
||||
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
|
||||
|
||||
|
||||
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
|
||||
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
; *(Veneer$$CMSE) ; uncomment for secure applications
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
RW_RAM __RW_BASE __RW_SIZE { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
#if __HEAP_SIZE > 0
|
||||
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
|
||||
}
|
||||
#endif
|
||||
|
||||
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
|
||||
}
|
||||
SEAL +0
|
||||
{
|
||||
*.o(.seal+FIRST)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,832 @@
|
||||
/**************************************************************************//**
|
||||
* @file partition_ARMCM23.h
|
||||
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
|
||||
* @version V1.0.0
|
||||
* @date 09. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef PARTITION_ARMCM23_H
|
||||
#define PARTITION_ARMCM23_H
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize Security Attribution Unit (SAU) CTRL register
|
||||
*/
|
||||
#define SAU_INIT_CTRL 1
|
||||
|
||||
/*
|
||||
// <q> Enable SAU
|
||||
// <i> Value for SAU->CTRL register bit ENABLE
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ENABLE 1
|
||||
|
||||
/*
|
||||
// <o> When SAU is disabled
|
||||
// <0=> All Memory is Secure
|
||||
// <1=> All Memory is Non-Secure
|
||||
// <i> Value for SAU->CTRL register bit ALLNS
|
||||
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ALLNS 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Initialize Security Attribution Unit (SAU) Address Regions
|
||||
// <i>SAU configuration specifies regions to be one of:
|
||||
// <i> - Secure and Non-Secure Callable
|
||||
// <i> - Non-Secure
|
||||
// <i>Note: All memory regions not configured by SAU are Secure
|
||||
*/
|
||||
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 0
|
||||
// <i> Setup SAU Region 0 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION0 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC0 1
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 1
|
||||
// <i> Setup SAU Region 1 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION1 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START1 0x00040000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END1 0x0007FFFF
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC1 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 2
|
||||
// <i> Setup SAU Region 2 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION2 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START2 0x20020000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END2 0x200FFFFF
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC2 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 3
|
||||
// <i> Setup SAU Region 3 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION3 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x40000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x40040000
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 4
|
||||
// <i> Setup SAU Region 4 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION4 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x00200000 /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x002fffff /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 5
|
||||
// <i> Setup SAU Region 5 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION5 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x00000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x00000000
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 6
|
||||
// <i> Setup SAU Region 6 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 7
|
||||
// <i> Setup SAU Region 7 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Sleep and Exception Handling
|
||||
*/
|
||||
#define SCB_CSR_AIRCR_INIT 1
|
||||
|
||||
/*
|
||||
// <o> Deep Sleep can be enabled by
|
||||
// <0=>Secure and Non-Secure state
|
||||
// <1=>Secure state only
|
||||
// <i> Value for SCB->CSR register bit DEEPSLEEPS
|
||||
*/
|
||||
#define SCB_CSR_DEEPSLEEPS_VAL 1
|
||||
|
||||
/*
|
||||
// <o>System reset request accessible from
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
|
||||
*/
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL 1
|
||||
|
||||
/*
|
||||
// <o>Priority of Non-Secure exceptions is
|
||||
// <0=> Not altered
|
||||
// <1=> Lowered to 0x80-0xFF
|
||||
// <i> Value for SCB->AIRCR register bit PRIS
|
||||
*/
|
||||
#define SCB_AIRCR_PRIS_VAL 1
|
||||
|
||||
/*
|
||||
// <o>BusFault, HardFault, and NMI target
|
||||
// <0=> Secure state
|
||||
// <1=> Non-Secure state
|
||||
// <i> Value for SCB->AIRCR register bit BFHFNMINS
|
||||
*/
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of single SysTick
|
||||
*/
|
||||
#define SCB_ICSR_INIT 0
|
||||
|
||||
/*
|
||||
// <o> in a single SysTick implementation, SysTick is
|
||||
// <0=>Secure
|
||||
// <1=>Non-Secure
|
||||
// <i> Value for SCB->ICSR register bit STTNS
|
||||
// <i> only for single SysTick implementation
|
||||
*/
|
||||
#define SCB_ICSR_STTNS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
// <h>Setup Interrupt Target
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 0 (Interrupts 0..31)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0 1
|
||||
|
||||
/*
|
||||
// Interrupts 0..31
|
||||
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 1 (Interrupts 32..63)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1 1
|
||||
|
||||
/*
|
||||
// Interrupts 32..63
|
||||
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 2 (Interrupts 64..95)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2 0
|
||||
|
||||
/*
|
||||
// Interrupts 64..95
|
||||
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 3 (Interrupts 96..127)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3 0
|
||||
|
||||
/*
|
||||
// Interrupts 96..127
|
||||
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 4 (Interrupts 128..159)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4 0
|
||||
|
||||
/*
|
||||
// Interrupts 128..159
|
||||
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 5 (Interrupts 160..191)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS5 0
|
||||
|
||||
/*
|
||||
// Interrupts 160..191
|
||||
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS5_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 6 (Interrupts 192..223)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS6 0
|
||||
|
||||
/*
|
||||
// Interrupts 192..223
|
||||
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS6_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 7 (Interrupts 224..255)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS7 0
|
||||
|
||||
/*
|
||||
// Interrupts 224..255
|
||||
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS7_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
max 128 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
__STATIC_INLINE void TZ_SAU_Setup (void)
|
||||
{
|
||||
|
||||
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
|
||||
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
|
||||
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
|
||||
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
|
||||
SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) |
|
||||
((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
|
||||
#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
|
||||
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
|
||||
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
|
||||
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
|
||||
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
|
||||
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible ITNS elements */
|
||||
|
||||
}
|
||||
|
||||
#endif /* PARTITION_ARMCM23_H */
|
||||
@@ -0,0 +1,154 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCM23.c
|
||||
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device
|
||||
* @version V2.0.3
|
||||
* @date 31. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM23)
|
||||
#include "ARMCM23.h"
|
||||
#elif defined (ARMCM23_TZ)
|
||||
#include "ARMCM23_TZ.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __INITIAL_SP;
|
||||
extern uint32_t __STACK_LIMIT;
|
||||
|
||||
extern __NO_RETURN void __PROGRAM_START(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler (void);
|
||||
void Default_Handler(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpedantic"
|
||||
#endif
|
||||
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
|
||||
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
Reset_Handler, /* Reset Handler */
|
||||
NMI_Handler, /* -14 NMI Handler */
|
||||
HardFault_Handler, /* -13 Hard Fault Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
SVC_Handler, /* -5 SVCall Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
PendSV_Handler, /* -2 PendSV Handler */
|
||||
SysTick_Handler, /* -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
Interrupt0_Handler, /* 0 Interrupt 0 */
|
||||
Interrupt1_Handler, /* 1 Interrupt 1 */
|
||||
Interrupt2_Handler, /* 2 Interrupt 2 */
|
||||
Interrupt3_Handler, /* 3 Interrupt 3 */
|
||||
Interrupt4_Handler, /* 4 Interrupt 4 */
|
||||
Interrupt5_Handler, /* 5 Interrupt 5 */
|
||||
Interrupt6_Handler, /* 6 Interrupt 6 */
|
||||
Interrupt7_Handler, /* 7 Interrupt 7 */
|
||||
Interrupt8_Handler, /* 8 Interrupt 8 */
|
||||
Interrupt9_Handler /* 9 Interrupt 9 */
|
||||
/* Interrupts 10 .. 223 are left out */
|
||||
};
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
/* The linker will place this value at the bottom of the stack to seal the secure main stack. */
|
||||
const int stack_seal __attribute__((section (".seal"))) = 0xFEF5EDA5;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler(void)
|
||||
{
|
||||
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
|
||||
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wmissing-noreturn"
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Hard Fault Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic pop
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,96 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM23.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM23 Device
|
||||
* @version V1.0.1
|
||||
* @date 15. November 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM23)
|
||||
#include "ARMCM23.h"
|
||||
#elif defined (ARMCM23_TZ)
|
||||
#include "ARMCM23_TZ.h"
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#include "partition_ARMCM23.h"
|
||||
#endif
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (50000000UL) /* Oscillator frequency */
|
||||
|
||||
#define SYSTEM_CLOCK (XTAL / 2U)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System initialization function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
TZ_SAU_Setup();
|
||||
#endif
|
||||
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
|
||||
*(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */
|
||||
*(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */
|
||||
}
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
|
||||
}
|
||||
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'demo_secure_zone'
|
||||
* Target: 'FVP Simulation Model'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM23_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,467 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
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<SchemaVersion>1.0</SchemaVersion>
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<Header>### uVision Project, (C) Keil Software</Header>
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<Extensions>
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<cExt>*.c</cExt>
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<aExt>*.s*; *.src; *.a*</aExt>
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<oExt>*.obj; *.o</oExt>
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<lExt>*.lib</lExt>
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<tExt>*.txt; *.h; *.inc</tExt>
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<pExt>*.plm</pExt>
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<CppX>*.cpp</CppX>
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<nMigrate>0</nMigrate>
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<DaveTm>
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<TargetName>FVP Simulation Model</TargetName>
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<ToolsetNumber>0x4</ToolsetNumber>
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<ToolsetName>ARM-ADS</ToolsetName>
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<TargetOption>
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<ListingPath>.\Listings\</ListingPath>
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<tvExp>1</tvExp>
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<IsCurrentTarget>1</IsCurrentTarget>
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</OPTFL>
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<CpuCode>7</CpuCode>
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<DebugOpt>
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<uSim>0</uSim>
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<uTrg>1</uTrg>
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<tDlgPa></tDlgPa>
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<tIfile>..\Debug.ini</tIfile>
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<pMon>BIN\DbgFMv8M.DLL</pMon>
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</DebugOpt>
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<TargetDriverDllRegistry>
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<SetRegEntry>
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<Number>0</Number>
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<Key>UL2V8M</Key>
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<Name>UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000</Name>
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<SetRegEntry>
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<Number>0</Number>
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<Key>DbgFMv8M</Key>
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<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_TZ_config.txt" -PF -MA</Name>
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<Key>DLGTARM</Key>
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<Name>(6010=851,404,1328,1000,0)(6018=-1,-1,-1,-1,0)(6019=105,137,294,473,0)(6008=1511,0,1805,185,0)(6009=137,177,431,362,0)(6014=1310,310,1568,1041,0)(6015=1547,312,1805,934,0)(6003=1122,384,1704,920,0)(6000=758,242,1211,574,0)</Name>
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<Name>(105=-1,-1,-1,-1,0)(106=1039,107,1805,421,0)(107=-1,-1,-1,-1,0)</Name>
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<BreakIfRCount>1</BreakIfRCount>
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<Filename><2>.\sample_threadx_module_manager.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
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<Expression>\\demo_threadx_non_secure_zone\sample_threadx_module_manager.c\120</Expression>
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<ExecCommand></ExecCommand>
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<Filename><1>RTE\Device\ARMCM23_TZ\system_ARMCM23.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\demo_secure_zone\RTE/Device/ARMCM23_TZ/system_ARMCM23.c\87</Expression>
|
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|
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|
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|
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<ExecCommand></ExecCommand>
|
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<Expression>\\demo_threadx_non_secure_zone\../../../../common/src/tx_timer_initialize.c\274</Expression>
|
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|
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|
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|
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|
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<Expression>\\sample_threadx_module\sample_threadx_module.c\304</Expression>
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<WatchWindow1>
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<Ww>
|
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<count>0</count>
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|
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|
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</Ww>
|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<WinNumber>1</WinNumber>
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|
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|
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|
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<WinNumber>1</WinNumber>
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</Ww>
|
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</Ww>
|
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<WinNumber>1</WinNumber>
|
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|
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<Ww>
|
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<count>8</count>
|
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<WinNumber>1</WinNumber>
|
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<ItemText>_tx_thread_current_ptr</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>9</count>
|
||||
<WinNumber>1</WinNumber>
|
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<ItemText>_tx_thread_execute_ptr</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>10</count>
|
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<WinNumber>1</WinNumber>
|
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<ItemText>my_module</ItemText>
|
||||
</Ww>
|
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<Ww>
|
||||
<count>11</count>
|
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<WinNumber>1</WinNumber>
|
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<ItemText>_tx_timer_system_clock</ItemText>
|
||||
</Ww>
|
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</WatchWindow1>
|
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<MemoryWindow1>
|
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<Mm>
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<WinNumber>1</WinNumber>
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|
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<MemoryWindow2>
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|
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|
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|
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<Tracepoint>
|
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|
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|
||||
<DebugFlag>
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|
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|
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|
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</DebugFlag>
|
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<LintExecutable></LintExecutable>
|
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<LintConfigFile></LintConfigFile>
|
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|
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<pMisraName></pMisraName>
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<pszMrule></pszMrule>
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<pSingCmds></pSingCmds>
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<pszMrulep></pszMrulep>
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<pSingCmdsp></pSingCmdsp>
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<pMultCmdsp></pMultCmdsp>
|
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</TargetOption>
|
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</Target>
|
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|
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<Group>
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<GroupName>Secure Code</GroupName>
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<tvExp>1</tvExp>
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<File>
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<bDave2>0</bDave2>
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<PathWithFileName>.\main_s.c</PathWithFileName>
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<FilenameWithoutPath>main_s.c</FilenameWithoutPath>
|
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<GroupNumber>1</GroupNumber>
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<FileType>1</FileType>
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<tvExpOptDlg>0</tvExpOptDlg>
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<bDave2>0</bDave2>
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<PathWithFileName>..\..\module_manager\src\tx_thread_secure_stack.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tx_thread_secure_stack.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
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|
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|
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|
||||
|
||||
<Group>
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||||
<GroupName>Interface</GroupName>
|
||||
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|
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<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\interface.c</PathWithFileName>
|
||||
<FilenameWithoutPath>interface.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -0,0 +1,521 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>ARMCM23_TZ</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<PackID>ARM.CMSIS.5.7.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile></SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>demo_secure_zone</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>1</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName></SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll></SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMV8M.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>0</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>0</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M23"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>1</nSecure>
|
||||
<RoSelD>4</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x200000</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>7</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>3</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>3</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\..\..\..\common\inc, ..\..\inc</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\RTE\Device\ARMCM23_TZ\ARMCM23_AC6.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Secure Code</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main_s.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main_s.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tx_thread_secure_stack.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\module_manager\src\tx_thread_secure_stack.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Interface</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>interface.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\interface.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.4.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.0.0">
|
||||
<instance index="0" removed="1">RTE\CMSIS\RTX_Config.c</instance>
|
||||
<component Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.0.0" condition="RTOS2 RTX5 NS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM23\Source\ARM\ARMCM23_ac6.sct" version="1.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" condition="TZ Secure" name="Device\ARM\ARMCM23\Include\Template\partition_ARMCM23.h" version="1.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM23_TZ\partition_ARMCM23.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM23\Source\startup_ARMCM23.c" version="2.0.3">
|
||||
<instance index="0">RTE\Device\ARMCM23_TZ\startup_ARMCM23.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM23\Source\system_ARMCM23.c" version="1.0.1">
|
||||
<instance index="0">RTE\Device\ARMCM23_TZ\system_ARMCM23.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" condition="TZ Secure" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.1">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayDesc></LayDesc>
|
||||
<LayUrl></LayUrl>
|
||||
<LayKeys></LayKeys>
|
||||
<LayCat></LayCat>
|
||||
<LayLic></LayLic>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* interface.c Secure/non-secure callable application code
|
||||
*
|
||||
* Version 1.0
|
||||
* Initial Release
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include <arm_cmse.h> // CMSE definitions
|
||||
#include "interface.h" // Header file with secure interface API
|
||||
|
||||
/* typedef for non-secure callback functions */
|
||||
typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));
|
||||
|
||||
/* Non-secure callable (entry) function */
|
||||
int func1(int x) __attribute__((cmse_nonsecure_entry)) {
|
||||
return x+3;
|
||||
}
|
||||
|
||||
/* Non-secure callable (entry) function, calling a non-secure callback function */
|
||||
int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) {
|
||||
funcptr_NS callback_NS; // non-secure callback function pointer
|
||||
int y;
|
||||
|
||||
/* return function pointer with cleared LSB */
|
||||
callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);
|
||||
|
||||
y = callback_NS (x+1);
|
||||
|
||||
return (y+2);
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* interface.h API definition for the non-secure state
|
||||
*
|
||||
* Version 1.0
|
||||
* Initial Release
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/* Function pointer declaration */
|
||||
typedef int (*funcptr)(int);
|
||||
|
||||
/* Non-secure callable functions */
|
||||
extern int func1(int x);
|
||||
extern int func2(funcptr callback, int x);
|
||||
@@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* main_ns.c Non-secure main function - RTOS demo
|
||||
*
|
||||
* Version 1.0
|
||||
* Initial Release
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "..\demo_secure_zone\interface.h" // Interface API
|
||||
//#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
|
||||
|
||||
//static osStatus_t Status;
|
||||
|
||||
//static osThreadId_t ThreadA_Id;
|
||||
//static osThreadId_t ThreadB_Id;
|
||||
//static osThreadId_t ThreadC_Id;
|
||||
|
||||
void ThreadA (void *argument);
|
||||
void ThreadB (void *argument);
|
||||
void ThreadC (void *argument);
|
||||
|
||||
|
||||
extern volatile int counterA;
|
||||
extern volatile int counterB;
|
||||
extern volatile int counterC;
|
||||
|
||||
volatile int counterA;
|
||||
volatile int counterB;
|
||||
volatile int counterC;
|
||||
|
||||
/*
|
||||
static int callbackA (int val) {
|
||||
return (val);
|
||||
}
|
||||
|
||||
__attribute__((noreturn))
|
||||
void ThreadA (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {
|
||||
counterA = func1 (counterA);
|
||||
counterA = func2 (callbackA, counterA);
|
||||
osDelay(2U);
|
||||
}
|
||||
}
|
||||
|
||||
static int callbackB (int val) {
|
||||
uint32_t flags;
|
||||
|
||||
flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever);
|
||||
if (flags == 1U) {
|
||||
return (val+1);
|
||||
} else {
|
||||
return (0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
__attribute__((noreturn))
|
||||
void ThreadB (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {
|
||||
counterB = func1 (counterB);
|
||||
counterB = func2 (callbackB, counterB);
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((noreturn))
|
||||
void ThreadC (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {
|
||||
counterC = counterC + 1;
|
||||
if ((counterC % 0x10) == 0) {
|
||||
osThreadFlagsSet (ThreadB_Id, 1);
|
||||
}
|
||||
osDelay(1U);
|
||||
}
|
||||
}
|
||||
|
||||
static const osThreadAttr_t ThreadAttr = {
|
||||
.tz_module = 1U, // indicate calls to secure mode
|
||||
};
|
||||
*/
|
||||
#if 1
|
||||
int main (void) {
|
||||
|
||||
//Status = osKernelInitialize();
|
||||
|
||||
//ThreadA_Id = osThreadNew(ThreadA, NULL, &ThreadAttr);
|
||||
//ThreadB_Id = osThreadNew(ThreadB, NULL, &ThreadAttr);
|
||||
//ThreadC_Id = osThreadNew(ThreadC, NULL, NULL);
|
||||
|
||||
//Status = osKernelStart();
|
||||
|
||||
for (;;);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 15. October 2016
|
||||
* $Revision: 1.1.0
|
||||
*
|
||||
* Project: TrustZone for ARMv8-M
|
||||
* Title: Code template for secure main function
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/* Use CMSE intrinsics */
|
||||
#include <arm_cmse.h>
|
||||
#include <stdlib.h>
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* TZ_START_NS: Start address of non-secure application */
|
||||
#ifndef TZ_START_NS
|
||||
#define TZ_START_NS (0x00040000U)
|
||||
#endif
|
||||
|
||||
/* typedef for non-secure callback functions */
|
||||
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
|
||||
|
||||
/* Secure main() */
|
||||
int main(void) {
|
||||
funcptr_void NonSecure_ResetHandler;
|
||||
|
||||
/* Add user setup code for secure part here*/
|
||||
|
||||
/* Set non-secure main stack (MSP_NS) */
|
||||
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
|
||||
|
||||
/* Get non-secure reset handler */
|
||||
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
|
||||
|
||||
/* Start non-secure state software application */
|
||||
NonSecure_ResetHandler();
|
||||
|
||||
/* Non-secure software does not return, this code is not executed */
|
||||
while (1) {
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 15. October 2016
|
||||
* $Revision: 1.1.0
|
||||
*
|
||||
* Project: TrustZone for ARMv8-M
|
||||
* Title: Context Management for ARMv8-M TrustZone - Sample implementation
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "tz_context.h"
|
||||
|
||||
/// Number of process slots (threads may call secure library code)
|
||||
#ifndef TZ_PROCESS_STACK_SLOTS
|
||||
#define TZ_PROCESS_STACK_SLOTS 8U
|
||||
#endif
|
||||
|
||||
/// Stack size of the secure library code
|
||||
#ifndef TZ_PROCESS_STACK_SIZE
|
||||
#define TZ_PROCESS_STACK_SIZE 256U
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint32_t sp_top; // stack space top
|
||||
uint32_t sp_limit; // stack space limit
|
||||
uint32_t sp; // current stack pointer
|
||||
} stack_info_t;
|
||||
|
||||
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
|
||||
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
|
||||
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
|
||||
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_InitContextSystem_S (void) {
|
||||
uint32_t n;
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
|
||||
ProcessStackInfo[n].sp = 0U;
|
||||
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
|
||||
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
|
||||
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
|
||||
}
|
||||
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
|
||||
|
||||
ProcessStackFreeSlot = 0U;
|
||||
|
||||
// Default process stack pointer and stack limit
|
||||
__set_PSPLIM((uint32_t)ProcessStackMemory);
|
||||
__set_PSP ((uint32_t)ProcessStackMemory);
|
||||
|
||||
// Privileged Thread Mode using PSP
|
||||
__set_CONTROL(0x02U);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
|
||||
uint32_t slot;
|
||||
|
||||
(void)module; // Ignore (fixed Stack size)
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
|
||||
return 0U; // No slot available
|
||||
}
|
||||
|
||||
slot = ProcessStackFreeSlot;
|
||||
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
|
||||
|
||||
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
|
||||
|
||||
return (slot + 1U);
|
||||
}
|
||||
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
ProcessStackInfo[slot].sp = 0U;
|
||||
|
||||
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
|
||||
ProcessStackFreeSlot = slot;
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
|
||||
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
|
||||
return 0U; // Thread Mode or using Main Stack for threads
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
|
||||
// Setup process stack pointer and stack limit
|
||||
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
|
||||
__set_PSP (ProcessStackInfo[slot].sp);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
uint32_t sp;
|
||||
|
||||
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
|
||||
return 0U; // Thread Mode or using Main Stack for threads
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
|
||||
sp = __get_PSP();
|
||||
if ((sp < ProcessStackInfo[slot].sp_limit) ||
|
||||
(sp > ProcessStackInfo[slot].sp_top)) {
|
||||
return 0U; // SP out of range
|
||||
}
|
||||
ProcessStackInfo[slot].sp = sp;
|
||||
|
||||
// Default process stack pointer and stack limit
|
||||
__set_PSPLIM((uint32_t)ProcessStackMemory);
|
||||
__set_PSP ((uint32_t)ProcessStackMemory);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*
|
||||
* $Revision: V5.1.0
|
||||
*
|
||||
* Project: CMSIS-RTOS RTX
|
||||
* Title: RTX Configuration
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "cmsis_compiler.h"
|
||||
#include "rtx_os.h"
|
||||
|
||||
// OS Idle Thread
|
||||
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
|
||||
(void)argument;
|
||||
|
||||
for (;;) {}
|
||||
}
|
||||
|
||||
// OS Error Callback function
|
||||
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
|
||||
(void)object_id;
|
||||
|
||||
switch (code) {
|
||||
case osRtxErrorStackUnderflow:
|
||||
// Stack overflow detected for thread (thread_id=object_id)
|
||||
break;
|
||||
case osRtxErrorISRQueueOverflow:
|
||||
// ISR Queue overflow detected when inserting object (object_id)
|
||||
break;
|
||||
case osRtxErrorTimerQueueOverflow:
|
||||
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
|
||||
break;
|
||||
case osRtxErrorClibSpace:
|
||||
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
|
||||
break;
|
||||
case osRtxErrorClibMutex:
|
||||
// Standard C/C++ library mutex initialization failed
|
||||
break;
|
||||
default:
|
||||
// Reserved
|
||||
break;
|
||||
}
|
||||
for (;;) {}
|
||||
//return 0U;
|
||||
}
|
||||
@@ -0,0 +1,578 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*
|
||||
* $Revision: V5.5.0
|
||||
*
|
||||
* Project: CMSIS-RTOS RTX
|
||||
* Title: RTX Configuration definitions
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef RTX_CONFIG_H_
|
||||
#define RTX_CONFIG_H_
|
||||
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
|
||||
#ifdef RTE_RTX_CONFIG_H
|
||||
#include RTE_RTX_CONFIG_H
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>System Configuration
|
||||
// =======================
|
||||
|
||||
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined global dynamic memory size.
|
||||
// <i> Default: 4096
|
||||
#ifndef OS_DYNAMIC_MEM_SIZE
|
||||
#define OS_DYNAMIC_MEM_SIZE 4096
|
||||
#endif
|
||||
|
||||
// <o>Kernel Tick Frequency [Hz] <1-1000000>
|
||||
// <i> Defines base time unit for delays and timeouts.
|
||||
// <i> Default: 1000 (1ms tick)
|
||||
#ifndef OS_TICK_FREQ
|
||||
#define OS_TICK_FREQ 1000
|
||||
#endif
|
||||
|
||||
// <e>Round-Robin Thread switching
|
||||
// <i> Enables Round-Robin Thread switching.
|
||||
#ifndef OS_ROBIN_ENABLE
|
||||
#define OS_ROBIN_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o>Round-Robin Timeout <1-1000>
|
||||
// <i> Defines how many ticks a thread will execute before a thread switch.
|
||||
// <i> Default: 5
|
||||
#ifndef OS_ROBIN_TIMEOUT
|
||||
#define OS_ROBIN_TIMEOUT 5
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>ISR FIFO Queue
|
||||
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
|
||||
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
|
||||
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
|
||||
// <i> RTOS Functions called from ISR store requests to this buffer.
|
||||
// <i> Default: 16 entries
|
||||
#ifndef OS_ISR_FIFO_QUEUE
|
||||
#define OS_ISR_FIFO_QUEUE 16
|
||||
#endif
|
||||
|
||||
// <q>Object Memory usage counters
|
||||
// <i> Enables object memory usage counters (requires RTX source variant).
|
||||
#ifndef OS_OBJ_MEM_USAGE
|
||||
#define OS_OBJ_MEM_USAGE 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Thread Configuration
|
||||
// =======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_THREAD_OBJ_MEM
|
||||
#define OS_THREAD_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of user Threads <1-1000>
|
||||
// <i> Defines maximum number of user threads that can be active at the same time.
|
||||
// <i> Applies to user threads with system provided memory for control blocks.
|
||||
#ifndef OS_THREAD_NUM
|
||||
#define OS_THREAD_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Number of user Threads with default Stack size <0-1000>
|
||||
// <i> Defines maximum number of user threads with default stack size.
|
||||
// <i> Applies to user threads with zero stack size specified.
|
||||
#ifndef OS_THREAD_DEF_STACK_NUM
|
||||
#define OS_THREAD_DEF_STACK_NUM 0
|
||||
#endif
|
||||
|
||||
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
|
||||
// <i> Defines the combined stack size for user threads with user-provided stack size.
|
||||
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_THREAD_USER_STACK_SIZE
|
||||
#define OS_THREAD_USER_STACK_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
|
||||
// <i> Defines stack size for threads with zero stack size specified.
|
||||
// <i> Default: 256
|
||||
#ifndef OS_STACK_SIZE
|
||||
#define OS_STACK_SIZE 256
|
||||
#endif
|
||||
|
||||
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
|
||||
// <i> Defines stack size for Idle thread.
|
||||
// <i> Default: 256
|
||||
#ifndef OS_IDLE_THREAD_STACK_SIZE
|
||||
#define OS_IDLE_THREAD_STACK_SIZE 256
|
||||
#endif
|
||||
|
||||
// <o>Idle Thread TrustZone Module Identifier
|
||||
// <i> Defines TrustZone Thread Context Management Identifier.
|
||||
// <i> Applies only to cores with TrustZone technology.
|
||||
// <i> Default: 0 (not used)
|
||||
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
|
||||
#define OS_IDLE_THREAD_TZ_MOD_ID 0
|
||||
#endif
|
||||
|
||||
// <q>Stack overrun checking
|
||||
// <i> Enables stack overrun check at thread switch.
|
||||
// <i> Enabling this option increases slightly the execution time of a thread switch.
|
||||
#ifndef OS_STACK_CHECK
|
||||
#define OS_STACK_CHECK 1
|
||||
#endif
|
||||
|
||||
// <q>Stack usage watermark
|
||||
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
|
||||
// <i> Enabling this option increases significantly the execution time of thread creation.
|
||||
#ifndef OS_STACK_WATERMARK
|
||||
#define OS_STACK_WATERMARK 0
|
||||
#endif
|
||||
|
||||
// <o>Processor mode for Thread execution
|
||||
// <0=> Unprivileged mode
|
||||
// <1=> Privileged mode
|
||||
// <i> Default: Privileged mode
|
||||
#ifndef OS_PRIVILEGE_MODE
|
||||
#define OS_PRIVILEGE_MODE 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Timer Configuration
|
||||
// ======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_TIMER_OBJ_MEM
|
||||
#define OS_TIMER_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Timer objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_TIMER_NUM
|
||||
#define OS_TIMER_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>Timer Thread Priority
|
||||
// <8=> Low
|
||||
// <16=> Below Normal <24=> Normal <32=> Above Normal
|
||||
// <40=> High
|
||||
// <48=> Realtime
|
||||
// <i> Defines priority for timer thread
|
||||
// <i> Default: High
|
||||
#ifndef OS_TIMER_THREAD_PRIO
|
||||
#define OS_TIMER_THREAD_PRIO 40
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
|
||||
// <i> Defines stack size for Timer thread.
|
||||
// <i> May be set to 0 when timers are not used.
|
||||
// <i> Default: 256
|
||||
#ifndef OS_TIMER_THREAD_STACK_SIZE
|
||||
#define OS_TIMER_THREAD_STACK_SIZE 256
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread TrustZone Module Identifier
|
||||
// <i> Defines TrustZone Thread Context Management Identifier.
|
||||
// <i> Applies only to cores with TrustZone technology.
|
||||
// <i> Default: 0 (not used)
|
||||
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
|
||||
#define OS_TIMER_THREAD_TZ_MOD_ID 0
|
||||
#endif
|
||||
|
||||
// <o>Timer Callback Queue entries <0-256>
|
||||
// <i> Number of concurrent active timer callback functions.
|
||||
// <i> May be set to 0 when timers are not used.
|
||||
// <i> Default: 4
|
||||
#ifndef OS_TIMER_CB_QUEUE
|
||||
#define OS_TIMER_CB_QUEUE 4
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Event Flags Configuration
|
||||
// ============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_EVFLAGS_OBJ_MEM
|
||||
#define OS_EVFLAGS_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Event Flags objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_EVFLAGS_NUM
|
||||
#define OS_EVFLAGS_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Mutex Configuration
|
||||
// ======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MUTEX_OBJ_MEM
|
||||
#define OS_MUTEX_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Mutex objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MUTEX_NUM
|
||||
#define OS_MUTEX_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Semaphore Configuration
|
||||
// ==========================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_SEMAPHORE_OBJ_MEM
|
||||
#define OS_SEMAPHORE_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Semaphore objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_SEMAPHORE_NUM
|
||||
#define OS_SEMAPHORE_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Memory Pool Configuration
|
||||
// ============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MEMPOOL_OBJ_MEM
|
||||
#define OS_MEMPOOL_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Memory Pool objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MEMPOOL_NUM
|
||||
#define OS_MEMPOOL_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined data storage memory size.
|
||||
// <i> Applies to objects with system provided memory for data storage.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_MEMPOOL_DATA_SIZE
|
||||
#define OS_MEMPOOL_DATA_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Message Queue Configuration
|
||||
// ==============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MSGQUEUE_OBJ_MEM
|
||||
#define OS_MSGQUEUE_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Message Queue objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MSGQUEUE_NUM
|
||||
#define OS_MSGQUEUE_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined data storage memory size.
|
||||
// <i> Applies to objects with system provided memory for data storage.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_MSGQUEUE_DATA_SIZE
|
||||
#define OS_MSGQUEUE_DATA_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Event Recorder Configuration
|
||||
// ===============================
|
||||
|
||||
// <e>Global Initialization
|
||||
// <i> Initialize Event Recorder during 'osKernelInitialize'.
|
||||
#ifndef OS_EVR_INIT
|
||||
#define OS_EVR_INIT 0
|
||||
#endif
|
||||
|
||||
// <q>Start recording
|
||||
// <i> Start event recording after initialization.
|
||||
#ifndef OS_EVR_START
|
||||
#define OS_EVR_START 1
|
||||
#endif
|
||||
|
||||
// <h>Global Event Filter Setup
|
||||
// <i> Initial recording level applied to all components.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_LEVEL
|
||||
#define OS_EVR_LEVEL 0x00U
|
||||
#endif
|
||||
|
||||
// <h>RTOS Event Filter Setup
|
||||
// <i> Recording levels for RTX components.
|
||||
// <i> Only applicable if events for the respective component are generated.
|
||||
|
||||
// <h>Memory Management
|
||||
// <i> Recording level for Memory Management events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_MEMORY_LEVEL
|
||||
#define OS_EVR_MEMORY_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Kernel
|
||||
// <i> Recording level for Kernel events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_KERNEL_LEVEL
|
||||
#define OS_EVR_KERNEL_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Thread
|
||||
// <i> Recording level for Thread events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_THREAD_LEVEL
|
||||
#define OS_EVR_THREAD_LEVEL 0x05U
|
||||
#endif
|
||||
|
||||
// <h>Generic Wait
|
||||
// <i> Recording level for Generic Wait events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_WAIT_LEVEL
|
||||
#define OS_EVR_WAIT_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Thread Flags
|
||||
// <i> Recording level for Thread Flags events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_THFLAGS_LEVEL
|
||||
#define OS_EVR_THFLAGS_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Event Flags
|
||||
// <i> Recording level for Event Flags events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_EVFLAGS_LEVEL
|
||||
#define OS_EVR_EVFLAGS_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Timer
|
||||
// <i> Recording level for Timer events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_TIMER_LEVEL
|
||||
#define OS_EVR_TIMER_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Mutex
|
||||
// <i> Recording level for Mutex events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_MUTEX_LEVEL
|
||||
#define OS_EVR_MUTEX_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Semaphore
|
||||
// <i> Recording level for Semaphore events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_SEMAPHORE_LEVEL
|
||||
#define OS_EVR_SEMAPHORE_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Memory Pool
|
||||
// <i> Recording level for Memory Pool events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_MEMPOOL_LEVEL
|
||||
#define OS_EVR_MEMPOOL_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// <h>Message Queue
|
||||
// <i> Recording level for Message Queue events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_MSGQUEUE_LEVEL
|
||||
#define OS_EVR_MSGQUEUE_LEVEL 0x01U
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <h>RTOS Event Generation
|
||||
// <i> Enables event generation for RTX components (requires RTX source variant).
|
||||
|
||||
// <q>Memory Management
|
||||
// <i> Enables Memory Management event generation.
|
||||
#ifndef OS_EVR_MEMORY
|
||||
#define OS_EVR_MEMORY 1
|
||||
#endif
|
||||
|
||||
// <q>Kernel
|
||||
// <i> Enables Kernel event generation.
|
||||
#ifndef OS_EVR_KERNEL
|
||||
#define OS_EVR_KERNEL 1
|
||||
#endif
|
||||
|
||||
// <q>Thread
|
||||
// <i> Enables Thread event generation.
|
||||
#ifndef OS_EVR_THREAD
|
||||
#define OS_EVR_THREAD 1
|
||||
#endif
|
||||
|
||||
// <q>Generic Wait
|
||||
// <i> Enables Generic Wait event generation.
|
||||
#ifndef OS_EVR_WAIT
|
||||
#define OS_EVR_WAIT 1
|
||||
#endif
|
||||
|
||||
// <q>Thread Flags
|
||||
// <i> Enables Thread Flags event generation.
|
||||
#ifndef OS_EVR_THFLAGS
|
||||
#define OS_EVR_THFLAGS 1
|
||||
#endif
|
||||
|
||||
// <q>Event Flags
|
||||
// <i> Enables Event Flags event generation.
|
||||
#ifndef OS_EVR_EVFLAGS
|
||||
#define OS_EVR_EVFLAGS 1
|
||||
#endif
|
||||
|
||||
// <q>Timer
|
||||
// <i> Enables Timer event generation.
|
||||
#ifndef OS_EVR_TIMER
|
||||
#define OS_EVR_TIMER 1
|
||||
#endif
|
||||
|
||||
// <q>Mutex
|
||||
// <i> Enables Mutex event generation.
|
||||
#ifndef OS_EVR_MUTEX
|
||||
#define OS_EVR_MUTEX 1
|
||||
#endif
|
||||
|
||||
// <q>Semaphore
|
||||
// <i> Enables Semaphore event generation.
|
||||
#ifndef OS_EVR_SEMAPHORE
|
||||
#define OS_EVR_SEMAPHORE 1
|
||||
#endif
|
||||
|
||||
// <q>Memory Pool
|
||||
// <i> Enables Memory Pool event generation.
|
||||
#ifndef OS_EVR_MEMPOOL
|
||||
#define OS_EVR_MEMPOOL 1
|
||||
#endif
|
||||
|
||||
// <q>Message Queue
|
||||
// <i> Enables Message Queue event generation.
|
||||
#ifndef OS_EVR_MSGQUEUE
|
||||
#define OS_EVR_MSGQUEUE 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </h>
|
||||
|
||||
// Number of Threads which use standard C/C++ library libspace
|
||||
// (when thread specific memory allocation is not used).
|
||||
#if (OS_THREAD_OBJ_MEM == 0)
|
||||
#define OS_THREAD_LIBSPACE_NUM 4
|
||||
#else
|
||||
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
|
||||
#endif
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
|
||||
#endif // RTX_CONFIG_H_
|
||||
@@ -0,0 +1,85 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc
|
||||
; command above MUST be in first line (no comment above!)
|
||||
|
||||
/*
|
||||
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Flash Configuration ----------------------------------
|
||||
; <h> Flash Configuration
|
||||
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __ROM_BASE 0x00040000
|
||||
#define __ROM_SIZE 0x00040000
|
||||
|
||||
/*--------------------- Embedded RAM Configuration ---------------------------
|
||||
; <h> RAM Configuration
|
||||
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
|
||||
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_BASE 0x20020000
|
||||
#define __RAM_SIZE 0x00020000
|
||||
|
||||
#define SHARED_MEM_BASE 0x20040000
|
||||
#define SHARED_MEM_SIZE 0x00000100
|
||||
|
||||
/*--------------------- Stack / Heap Configuration ---------------------------
|
||||
; <h> Stack / Heap Configuration
|
||||
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_SIZE 0x00000200
|
||||
#define __HEAP_SIZE 0x00000C00
|
||||
|
||||
/*
|
||||
;------------- <<< end of configuration section >>> ---------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
User Stack & Heap boundary definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
|
||||
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Scatter File Definitions definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RO_BASE __ROM_BASE
|
||||
#define __RO_SIZE __ROM_SIZE
|
||||
|
||||
#define __RW_BASE __RAM_BASE
|
||||
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
|
||||
|
||||
|
||||
|
||||
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
|
||||
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
; *(Veneer$$CMSE) ; uncomment for secure applications
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
RW_RAM __RW_BASE __RW_SIZE { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
SHARED_MEM SHARED_MEM_BASE SHARED_MEM_SIZE {
|
||||
sample_threadx_module_manager.o (sharedmem)
|
||||
}
|
||||
|
||||
#if __HEAP_SIZE > 0
|
||||
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
|
||||
}
|
||||
#endif
|
||||
|
||||
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,151 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCM23.c
|
||||
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device
|
||||
* @version V2.0.3
|
||||
* @date 31. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM23)
|
||||
#include "ARMCM23.h"
|
||||
#elif defined (ARMCM23_TZ)
|
||||
#include "ARMCM23_TZ.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __INITIAL_SP;
|
||||
extern uint32_t __STACK_LIMIT;
|
||||
|
||||
extern __NO_RETURN void __PROGRAM_START(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler (void);
|
||||
void Default_Handler(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpedantic"
|
||||
#endif
|
||||
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
|
||||
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
Reset_Handler, /* Reset Handler */
|
||||
NMI_Handler, /* -14 NMI Handler */
|
||||
HardFault_Handler, /* -13 Hard Fault Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
SVC_Handler, /* -5 SVCall Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
PendSV_Handler, /* -2 PendSV Handler */
|
||||
SysTick_Handler, /* -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
Interrupt0_Handler, /* 0 Interrupt 0 */
|
||||
Interrupt1_Handler, /* 1 Interrupt 1 */
|
||||
Interrupt2_Handler, /* 2 Interrupt 2 */
|
||||
Interrupt3_Handler, /* 3 Interrupt 3 */
|
||||
Interrupt4_Handler, /* 4 Interrupt 4 */
|
||||
Interrupt5_Handler, /* 5 Interrupt 5 */
|
||||
Interrupt6_Handler, /* 6 Interrupt 6 */
|
||||
Interrupt7_Handler, /* 7 Interrupt 7 */
|
||||
Interrupt8_Handler, /* 8 Interrupt 8 */
|
||||
Interrupt9_Handler /* 9 Interrupt 9 */
|
||||
/* Interrupts 10 .. 223 are left out */
|
||||
};
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler(void)
|
||||
{
|
||||
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
|
||||
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wmissing-noreturn"
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Hard Fault Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic pop
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,80 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM23.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM23 Device
|
||||
* @version V1.0.1
|
||||
* @date 15. November 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCM23)
|
||||
#include "ARMCM23.h"
|
||||
#elif defined (ARMCM23_TZ)
|
||||
#include "ARMCM23_TZ.h"
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#include "partition_ARMCM23.h"
|
||||
#endif
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (50000000UL) /* Oscillator frequency */
|
||||
|
||||
#define SYSTEM_CLOCK (XTAL / 2U)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System initialization function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
TZ_SAU_Setup();
|
||||
#endif
|
||||
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'demo_threadx_non-secure_zone'
|
||||
* Target: 'FVP Simulation Model'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM23_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'ThreadX_Library'
|
||||
* Target: 'ThreadX_Library_Project'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,305 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>ThreadX_Demo</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>1</RunSim>
|
||||
<RunTarget>0</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>1</uSim>
|
||||
<uTrg>0</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>0</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>0</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>0</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>-1</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon></pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGDARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name>-T5F</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>-UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<WatchWindow1>
|
||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_0_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>1</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_1_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>2</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_2_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>3</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_3_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>4</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_4_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>5</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_5_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>6</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>_tx_thread_current_ptr</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source Group</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\tx_initialize_low_level.s</PathWithFileName>
|
||||
<FilenameWithoutPath>tx_initialize_low_level.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\demo_threadx.c</PathWithFileName>
|
||||
<FilenameWithoutPath>demo_threadx.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
<WindowPosition>
|
||||
<length>44</length>
|
||||
<flags>0</flags>
|
||||
<showCmd>1</showCmd>
|
||||
<MinPosition>
|
||||
<xPos>-1</xPos>
|
||||
<yPos>-1</yPos>
|
||||
</MinPosition>
|
||||
<MaxPosition>
|
||||
<xPos>-1</xPos>
|
||||
<yPos>-1</yPos>
|
||||
</MaxPosition>
|
||||
<NormalPosition>
|
||||
<Top>56</Top>
|
||||
<Left>12</Left>
|
||||
<Right>1633</Right>
|
||||
<Bottom>671</Bottom>
|
||||
</NormalPosition>
|
||||
</WindowPosition>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Library_Group</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>4</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\ThreadX_Library.lib</PathWithFileName>
|
||||
<FilenameWithoutPath>ThreadX_Library.lib</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -0,0 +1,556 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||
|
||||
<SchemaVersion>1.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>ThreadX_Demo</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>Cortex-M4 FPU</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll></FlashDriverDll>
|
||||
<DeviceId>5237</DeviceId>
|
||||
<RegisterFile></RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile></SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath>Luminary\</RegisterFilePath>
|
||||
<DBRegisterFilePath>Luminary\</DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\</OutputDirectory>
|
||||
<OutputName>threadx_demo</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4F</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4F</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>1</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>0</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>0</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>0</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>0</RestoreTracepoints>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>-1</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver></Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>0</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>0</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>0</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>0</RoSelD>
|
||||
<RwSelD>0</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
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|
||||
<Type>1</Type>
|
||||
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|
||||
<Size>0x0</Size>
|
||||
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|
||||
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|
||||
<Type>1</Type>
|
||||
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|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
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|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>0</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
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<pXoBase></pXoBase>
|
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<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--first __tx_vectors --entry=__main</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
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</TargetOption>
|
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<Groups>
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<Group>
|
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<GroupName>Source Group</GroupName>
|
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<GroupOption>
|
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<CommonProperty>
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<UseCPPCompiler>0</UseCPPCompiler>
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<RVCTCodeConst>1</RVCTCodeConst>
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<RVCTZI>1</RVCTZI>
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<RVCTOtherData>0</RVCTOtherData>
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<ModuleSelection>0</ModuleSelection>
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<IncludeInBuild>2</IncludeInBuild>
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<AlwaysBuild>2</AlwaysBuild>
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<GenerateAssemblyFile>2</GenerateAssemblyFile>
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<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
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<PublicsOnly>2</PublicsOnly>
|
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<StopOnExitCode>11</StopOnExitCode>
|
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<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>0</ComprImg>
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</CommonProperty>
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||||
<GroupArmAds>
|
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<Cads>
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<interw>0</interw>
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<Optim>0</Optim>
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<oTime>2</oTime>
|
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<SplitLS>2</SplitLS>
|
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<OneElfS>2</OneElfS>
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||||
<Strict>2</Strict>
|
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<EnumInt>2</EnumInt>
|
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<PlainCh>2</PlainCh>
|
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<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<wLevel>0</wLevel>
|
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<uThumb>2</uThumb>
|
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<uSurpInc>2</uSurpInc>
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<uC99>2</uC99>
|
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<uGnu>2</uGnu>
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<useXO>2</useXO>
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<v6Lang>0</v6Lang>
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<v6LangP>0</v6LangP>
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<vShortEn>2</vShortEn>
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<vShortWch>2</vShortWch>
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<v6Lto>2</v6Lto>
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||||
<v6WtE>2</v6WtE>
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||||
<v6Rtti>2</v6Rtti>
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||||
<VariousControls>
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||||
<MiscControls></MiscControls>
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<Define></Define>
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<Undefine></Undefine>
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||||
<IncludePath></IncludePath>
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</VariousControls>
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</Cads>
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<Aads>
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<interw>2</interw>
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<Ropi>2</Ropi>
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<Rwpi>2</Rwpi>
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<thumb>2</thumb>
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<SplitLS>2</SplitLS>
|
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<SwStkChk>2</SwStkChk>
|
||||
<NoWarn>2</NoWarn>
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<uSurpInc>2</uSurpInc>
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||||
<useXO>2</useXO>
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||||
<uClangAs>2</uClangAs>
|
||||
<VariousControls>
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||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
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||||
<Undefine></Undefine>
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||||
<IncludePath></IncludePath>
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||||
</VariousControls>
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||||
</Aads>
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||||
</GroupArmAds>
|
||||
</GroupOption>
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<Files>
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<File>
|
||||
<FileName>tx_initialize_low_level.s</FileName>
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||||
<FileType>2</FileType>
|
||||
<FilePath>.\tx_initialize_low_level.s</FilePath>
|
||||
<FileOption>
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<CommonProperty>
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<UseCPPCompiler>2</UseCPPCompiler>
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<RVCTCodeConst>0</RVCTCodeConst>
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<RVCTZI>0</RVCTZI>
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||||
<RVCTOtherData>0</RVCTOtherData>
|
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<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>2</IncludeInBuild>
|
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<AlwaysBuild>2</AlwaysBuild>
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||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
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||||
<CustomArgument></CustomArgument>
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<IncludeLibraryModules></IncludeLibraryModules>
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<ComprImg>1</ComprImg>
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</CommonProperty>
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<FileArmAds>
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<Aads>
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<interw>2</interw>
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<Ropi>2</Ropi>
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<Rwpi>2</Rwpi>
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<thumb>1</thumb>
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<SplitLS>2</SplitLS>
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<SwStkChk>2</SwStkChk>
|
||||
<NoWarn>2</NoWarn>
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<uSurpInc>2</uSurpInc>
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<useXO>2</useXO>
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<uClangAs>2</uClangAs>
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||||
<VariousControls>
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||||
<MiscControls></MiscControls>
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||||
<Define></Define>
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||||
<Undefine></Undefine>
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||||
<IncludePath></IncludePath>
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||||
</VariousControls>
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||||
</Aads>
|
||||
</FileArmAds>
|
||||
</FileOption>
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||||
</File>
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<File>
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<FileName>demo_threadx.c</FileName>
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||||
<FileType>1</FileType>
|
||||
<FilePath>.\demo_threadx.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Library_Group</GroupName>
|
||||
<Files>
|
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<File>
|
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<FileName>ThreadX_Library.lib</FileName>
|
||||
<FileType>4</FileType>
|
||||
<FilePath>.\ThreadX_Library.lib</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,335 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
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<AsmCond>1</AsmCond>
|
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<AsmSymb>1</AsmSymb>
|
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<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>0</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>15</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>..\Debug.ini</tIfile>
|
||||
<pMon>BIN\DbgFMv8M.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2V8M</Key>
|
||||
<Name>UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DbgFMv8M</Key>
|
||||
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -PF -MA</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>PWSTATINFO</Key>
|
||||
<Name>200,50,700</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(6010=1243,118,1720,714,0)(6018=1284,352,1473,701,0)(6019=1328,34,1517,370,0)(6008=-1,-1,-1,-1,0)(6009=969,18,1263,203,0)(6014=1111,129,1369,860,0)(6015=872,146,1130,768,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)(106=511,345,1277,660,0)(107=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<WatchWindow1>
|
||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_0_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>1</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_1_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>2</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_2_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>3</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_3_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>4</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_4_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>5</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_5_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>6</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_6_counter</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>7</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>thread_7_counter</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<MemoryWindow1>
|
||||
<Mm>
|
||||
<WinNumber>1</WinNumber>
|
||||
<SubType>2</SubType>
|
||||
<ItemText>0x20200a10</ItemText>
|
||||
<AccSizeX>0</AccSizeX>
|
||||
</Mm>
|
||||
</MemoryWindow1>
|
||||
<MemoryWindow2>
|
||||
<Mm>
|
||||
<WinNumber>2</WinNumber>
|
||||
<SubType>2</SubType>
|
||||
<ItemText>0xE000ED28</ItemText>
|
||||
<AccSizeX>0</AccSizeX>
|
||||
</Mm>
|
||||
</MemoryWindow2>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Non-secure Code</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>4</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\ThreadX_Library.lib</PathWithFileName>
|
||||
<FilenameWithoutPath>ThreadX_Library.lib</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\sample_threadx_module_manager.c</PathWithFileName>
|
||||
<FilenameWithoutPath>sample_threadx_module_manager.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>CMSE Library</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\demo_secure_zone\interface.h</PathWithFileName>
|
||||
<FilenameWithoutPath>interface.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>3</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</PathWithFileName>
|
||||
<FilenameWithoutPath>demo_secure_zone_CMSE_Lib.o</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -0,0 +1,596 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>ARMCM23_TZ</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<PackID>ARM.CMSIS.5.7.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile></SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>demo_threadx_non-secure_zone</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>1</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName></SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll></SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMV8M.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>0</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M23"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>4</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x200000</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls>-Wno-unused-function -Wno-visibility -Wno-missing-noreturn -Wno-unused-parameter</MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\..\..\..\common\inc, ..\..\inc, ..\..\..\..\..\common_modules\inc</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\RTE\Device\ARMCM23_TZ\ARMCM23_AC6.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Non-secure Code</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>ThreadX_Library.lib</FileName>
|
||||
<FileType>4</FileType>
|
||||
<FilePath>..\ThreadX_Library.lib</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>sample_threadx_module_manager.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\sample_threadx_module_manager.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSE Library</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>interface.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\demo_secure_zone\interface.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>demo_secure_zone_CMSE_Lib.o</FileName>
|
||||
<FileType>3</FileType>
|
||||
<FilePath>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.4.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
|
||||
<instance index="0" removed="1">RTE\CMSIS\RTX_Config.c</instance>
|
||||
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 NS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
|
||||
<instance index="0" removed="1">RTE\CMSIS\RTX_Config.h</instance>
|
||||
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 NS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM23\Source\ARM\ARMCM23_ac6.sct" version="1.0.0">
|
||||
<instance index="0">RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM23\Source\startup_ARMCM23.c" version="2.0.3">
|
||||
<instance index="0">RTE\Device\ARMCM23_TZ\startup_ARMCM23.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM23\Source\system_ARMCM23.c" version="1.0.1">
|
||||
<instance index="0">RTE\Device\ARMCM23_TZ\system_ARMCM23.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM23 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="linkerScript" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.1">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.2-dev5"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_TZ\partition_ARMCM33.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_TZ\startup_ARMCM33.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMCM33_TZ\system_ARMCM33.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="Device\ARM\ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMv8MBL\partition_ARMv8MBL.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMv8MBL\Source\ARM\startup_ARMv8MBL.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMv8MBL\startup_ARMv8MBL.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMv8MBL\Source\system_ARMv8MBL.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\ARMv8MBL\system_ARMv8MBL.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="CMSIS\Config\RTE_Device.h" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
|
||||
<package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="header" name="Device\CMSDK_ARMv8MBL\Include\Template\partition_CMSDK_ARMv8MBL.h" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
|
||||
<package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" condition="ARMCC" name="Device\CMSDK_ARMv8MBL\Source\ARM\startup_CMSDK_ARMv8MBL.s" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
|
||||
<package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Device\CMSDK_ARMv8MBL\Source\system_CMSDK_ARMv8MBL.c" version="1.0.0">
|
||||
<instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
|
||||
<package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayDesc></LayDesc>
|
||||
<LayUrl></LayUrl>
|
||||
<LayKeys></LayKeys>
|
||||
<LayCat></LayCat>
|
||||
<LayLic></LayLic>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,131 @@
|
||||
/* Small demonstration of the ThreadX module manager. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
static TX_THREAD module_manager;
|
||||
static TXM_MODULE_INSTANCE my_module;
|
||||
|
||||
|
||||
/* Define the object pool area. */
|
||||
|
||||
static UCHAR object_memory[16384];
|
||||
|
||||
|
||||
/* Define the module data pool area. */
|
||||
|
||||
#define MODULE_DATA_SIZE (64 * 1024)
|
||||
static UCHAR module_data_area[MODULE_DATA_SIZE];
|
||||
|
||||
|
||||
/* The module code should be loaded here. */
|
||||
|
||||
#define MODULE_CODE (0x00200000)
|
||||
|
||||
|
||||
/* Define the shared memory area. */
|
||||
|
||||
#define SHARED_MEMORY_SIZE (256)
|
||||
__attribute__((section("sharedmem")))
|
||||
static UCHAR shared_memory[SHARED_MEMORY_SIZE] __attribute__((aligned (32)));
|
||||
|
||||
|
||||
/* Define the count of memory faults. */
|
||||
|
||||
static ULONG memory_faults;
|
||||
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void module_manager_entry(ULONG thread_input);
|
||||
|
||||
|
||||
/* Define fault handler. */
|
||||
|
||||
static VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module)
|
||||
{
|
||||
|
||||
/* Just increment the fault counter. */
|
||||
memory_faults++;
|
||||
}
|
||||
|
||||
/* Define main entry point. */
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
/* Enter the ThreadX kernel. */
|
||||
tx_kernel_enter();
|
||||
}
|
||||
|
||||
|
||||
/* Define what the initial system looks like. */
|
||||
|
||||
void tx_application_define(void *first_unused_memory)
|
||||
{
|
||||
|
||||
CHAR *pointer = (CHAR*)first_unused_memory;
|
||||
|
||||
|
||||
tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
pointer = pointer + DEMO_STACK_SIZE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void module_manager_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
(void)thread_input;
|
||||
|
||||
tx_thread_secure_stack_allocate(&module_manager, 256);
|
||||
|
||||
/* Initialize the module manager. */
|
||||
txm_module_manager_initialize((void *) module_data_area, MODULE_DATA_SIZE);
|
||||
|
||||
txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
|
||||
|
||||
/* Register a fault handler. */
|
||||
txm_module_manager_memory_fault_notify(module_fault_handler);
|
||||
|
||||
/* Load the module that is already there, in this example it is placed there by the multiple image download. */
|
||||
txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE);
|
||||
|
||||
/* Enable a read/write shared memory region. */
|
||||
txm_module_manager_external_memory_enable(&my_module, (void *) shared_memory, SHARED_MEMORY_SIZE, TXM_MODULE_ATTRIBUTE_READ_WRITE);
|
||||
|
||||
/* Start the module. */
|
||||
txm_module_manager_start(&my_module);
|
||||
|
||||
/* Sleep for a while.... */
|
||||
tx_thread_sleep(1000);
|
||||
|
||||
/* Stop the module. */
|
||||
txm_module_manager_stop(&my_module);
|
||||
|
||||
/* Unload the module. */
|
||||
txm_module_manager_unload(&my_module);
|
||||
|
||||
/* Load the module that is already there. */
|
||||
txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE);
|
||||
|
||||
/* Start the module again. */
|
||||
txm_module_manager_start(&my_module);
|
||||
|
||||
/* Now just spin... */
|
||||
while(1)
|
||||
{
|
||||
|
||||
tx_thread_sleep(100);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'sample_threadx_module'
|
||||
* Target: 'FVP Simulation Model'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM23_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,438 @@
|
||||
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
|
||||
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
|
||||
event flags group, byte pool, and block pool. */
|
||||
|
||||
/* Specify that this is a module! */
|
||||
|
||||
#define TXM_MODULE
|
||||
|
||||
|
||||
/* Include the ThreadX module definitions. */
|
||||
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
#include "interface.h"
|
||||
|
||||
/* Define constants. */
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
#define DEMO_BYTE_POOL_SIZE 9120
|
||||
#define DEMO_BLOCK_POOL_SIZE 100
|
||||
#define DEMO_QUEUE_SIZE 100
|
||||
|
||||
|
||||
/* Define the external memory area. */
|
||||
|
||||
#define EXTERNAL_MEMORY (0x20040000)
|
||||
|
||||
|
||||
/* Define the pool space in the bss section of the module. ULONG is used to
|
||||
get the word alignment. */
|
||||
|
||||
ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4];
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD *thread_0;
|
||||
TX_THREAD *thread_1;
|
||||
TX_THREAD *thread_2;
|
||||
TX_THREAD *thread_3;
|
||||
TX_THREAD *thread_4;
|
||||
TX_THREAD *thread_5;
|
||||
TX_THREAD *thread_6;
|
||||
TX_THREAD *thread_7;
|
||||
TX_QUEUE *queue_0;
|
||||
TX_SEMAPHORE *semaphore_0;
|
||||
TX_MUTEX *mutex_0;
|
||||
TX_EVENT_FLAGS_GROUP *event_flags_0;
|
||||
TX_BYTE_POOL *byte_pool_0;
|
||||
TX_BLOCK_POOL *block_pool_0;
|
||||
|
||||
|
||||
/* Define the counters used in the demo application... */
|
||||
|
||||
ULONG thread_0_counter;
|
||||
ULONG thread_1_counter;
|
||||
ULONG thread_1_messages_sent;
|
||||
ULONG thread_2_counter;
|
||||
ULONG thread_2_messages_received;
|
||||
ULONG thread_3_counter;
|
||||
ULONG thread_4_counter;
|
||||
ULONG thread_5_counter;
|
||||
ULONG thread_6_counter;
|
||||
ULONG thread_7_counter;
|
||||
ULONG semaphore_0_puts;
|
||||
ULONG event_0_sets;
|
||||
ULONG queue_0_sends;
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input);
|
||||
void thread_1_entry(ULONG thread_input);
|
||||
void thread_2_entry(ULONG thread_input);
|
||||
void thread_3_and_4_entry(ULONG thread_input);
|
||||
void thread_5_entry(ULONG thread_input);
|
||||
void thread_6_and_7_entry(ULONG thread_input);
|
||||
|
||||
void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
|
||||
{
|
||||
|
||||
if (semaphore_ptr == semaphore_0)
|
||||
semaphore_0_puts++;
|
||||
}
|
||||
|
||||
|
||||
void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
|
||||
{
|
||||
|
||||
if (event_flag_group_ptr == event_flags_0)
|
||||
event_0_sets++;
|
||||
}
|
||||
|
||||
|
||||
void queue_0_notify(TX_QUEUE *queue_ptr)
|
||||
{
|
||||
|
||||
if (queue_ptr == queue_0)
|
||||
queue_0_sends++;
|
||||
}
|
||||
|
||||
|
||||
/* Define the module start function. */
|
||||
|
||||
void demo_module_start(ULONG id)
|
||||
{
|
||||
|
||||
CHAR *pointer;
|
||||
|
||||
/* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within
|
||||
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
|
||||
the control block(s). */
|
||||
txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
|
||||
txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
|
||||
txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
|
||||
txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
|
||||
txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
|
||||
txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
|
||||
|
||||
|
||||
/* Create a byte memory pool from which to allocate the thread stacks. */
|
||||
tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
|
||||
|
||||
/* Put system definition stuff in here, e.g. thread creates and other assorted
|
||||
create information. */
|
||||
|
||||
/* Allocate the stack for thread 0. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create the main thread. */
|
||||
tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
|
||||
/* Allocate the stack for thread 1. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 1 and 2. These threads pass information through a ThreadX
|
||||
message queue. It is also interesting to note that these threads have a time
|
||||
slice. */
|
||||
tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 2. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 3. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
|
||||
An interesting thing here is that both threads share the same instruction area. */
|
||||
tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 4. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 5. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create thread 5. This thread simply pends on an event flag which will be set
|
||||
by thread_0. */
|
||||
tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 6. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
|
||||
tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 7. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the message queue. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
|
||||
|
||||
/* Create the message queue shared by threads 1 and 2. */
|
||||
tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
|
||||
|
||||
tx_queue_send_notify(queue_0, queue_0_notify);
|
||||
|
||||
/* Create the semaphore used by threads 3 and 4. */
|
||||
tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
|
||||
|
||||
tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
|
||||
|
||||
/* Create the event flags group used by threads 1 and 5. */
|
||||
tx_event_flags_create(event_flags_0, "module event flags 0");
|
||||
|
||||
tx_event_flags_set_notify(event_flags_0, event_0_notify);
|
||||
|
||||
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
|
||||
tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
|
||||
|
||||
/* Allocate the memory for a small block pool. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create a block memory pool to allocate a message buffer from. */
|
||||
tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
|
||||
|
||||
/* Allocate a block and release the block memory. */
|
||||
tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
|
||||
|
||||
/* Release the block back to the pool. */
|
||||
tx_block_release(pointer);
|
||||
}
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
tx_thread_secure_stack_allocate(thread_0, 256);
|
||||
thread_0_counter = func1(thread_0_counter);
|
||||
tx_thread_secure_stack_free(thread_0);
|
||||
|
||||
/* This thread simply sits in while-forever-sleep loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_0_counter++;
|
||||
|
||||
/* Sleep for 10 ticks. */
|
||||
tx_thread_sleep(10);
|
||||
|
||||
/* Set event flag 0 to wakeup thread 5. */
|
||||
status = tx_event_flags_set(event_flags_0, 0x1, TX_OR);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_1_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sends messages to a queue shared by thread 2. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_1_counter++;
|
||||
|
||||
/* Send message to queue 0. */
|
||||
status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Increment the message sent. */
|
||||
thread_1_messages_sent++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_2_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
ULONG received_message;
|
||||
UINT status;
|
||||
|
||||
/* This thread retrieves messages placed on the queue by thread 1. */
|
||||
while(1)
|
||||
{
|
||||
/* Test external memory sharing. */
|
||||
*(ULONG *)EXTERNAL_MEMORY = 0xABABABAB;
|
||||
*(ULONG *)0x20040004 = 0x01010101;
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_2_counter++;
|
||||
|
||||
/* Retrieve a message from the queue. */
|
||||
status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status and make sure the message is what we
|
||||
expected. */
|
||||
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
|
||||
break;
|
||||
|
||||
/* Otherwise, all is okay. Increment the received message count. */
|
||||
thread_2_messages_received++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_3_and_4_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 3 and thread 4. As the loop
|
||||
below shows, these function compete for ownership of semaphore_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 3)
|
||||
thread_3_counter++;
|
||||
else
|
||||
thread_4_counter++;
|
||||
|
||||
/* Get the semaphore with suspension. */
|
||||
status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the semaphore. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the semaphore. */
|
||||
status = tx_semaphore_put(semaphore_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_5_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
ULONG actual_flags;
|
||||
|
||||
|
||||
/* This thread simply waits for an event in a forever loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_5_counter++;
|
||||
|
||||
/* Wait for event flag 0. */
|
||||
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
|
||||
&actual_flags, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_6_and_7_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 6 and thread 7. As the loop
|
||||
below shows, these function compete for ownership of mutex_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 6)
|
||||
thread_6_counter++;
|
||||
else
|
||||
thread_7_counter++;
|
||||
|
||||
/* Get the mutex with suspension. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Get the mutex again with suspension. This shows
|
||||
that an owning thread may retrieve the mutex it
|
||||
owns multiple times. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the mutex. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the mutex. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Release the mutex again. This will actually
|
||||
release ownership since it was obtained twice. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,236 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
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|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>15</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\DbgFMv8M.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2V8M</Key>
|
||||
<Name>UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Module Code</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\sample_threadx_module.c</PathWithFileName>
|
||||
<FilenameWithoutPath>sample_threadx_module.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\txm_module_preamble.S</PathWithFileName>
|
||||
<FilenameWithoutPath>txm_module_preamble.S</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>4</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\txm\Objects\txm.lib</PathWithFileName>
|
||||
<FilenameWithoutPath>txm.lib</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>3</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</PathWithFileName>
|
||||
<FilenameWithoutPath>demo_secure_zone_CMSE_Lib.o</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -0,0 +1,453 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>FVP Simulation Model</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>ARMCM23_TZ</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<PackID>ARM.CMSIS.5.5.1</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile></SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>sample_threadx_module</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName></SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll></SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMV8M.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>0</Capability>
|
||||
<DriverSelection>4101</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M23"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>4</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x200000</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>2</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>1</Ropi>
|
||||
<Rwpi>1</Rwpi>
|
||||
<wLevel>3</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>3</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\..\..\..\common_modules\inc, ..\..\..\..\..\common\inc, ..\..\..\..\..\ports_module\cortex_m23\ac6\inc, ..\demo_secure_zone</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>1</Ropi>
|
||||
<Rwpi>1</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>1</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>1</Ropi>
|
||||
<Rwpi>1</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00200000</TextAddressRange>
|
||||
<DataAddressRange>0x00000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--entry demo_module_start --first __txm_module_preamble</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Module Code</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>sample_threadx_module.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\sample_threadx_module.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_module_preamble.S</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\txm_module_preamble.S</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm.lib</FileName>
|
||||
<FileType>4</FileType>
|
||||
<FilePath>..\txm\Objects\txm.lib</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>demo_secure_zone_CMSE_Lib.o</FileName>
|
||||
<FileType>3</FileType>
|
||||
<FilePath>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<packages>
|
||||
<filter>
|
||||
<targetInfos/>
|
||||
</filter>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1">
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model" versionMatchMode="fixed"/>
|
||||
</targetInfos>
|
||||
</package>
|
||||
</packages>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="FVP Simulation Model"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayDesc></LayDesc>
|
||||
<LayUrl></LayUrl>
|
||||
<LayKeys></LayKeys>
|
||||
<LayCat></LayCat>
|
||||
<LayLic></LayLic>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,66 @@
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
.section RESET
|
||||
|
||||
// Define public symbols
|
||||
.global __txm_module_preamble
|
||||
|
||||
// Define application-specific start/stop entry points for the module
|
||||
.global demo_module_start
|
||||
|
||||
// Define common external references
|
||||
.global _txm_module_thread_shell_entry
|
||||
.global _txm_module_callback_request_thread_entry
|
||||
|
||||
.eabi_attribute Tag_ABI_PCS_RO_data, 1
|
||||
.eabi_attribute Tag_ABI_PCS_R9_use, 1
|
||||
.eabi_attribute Tag_ABI_PCS_RW_data, 2
|
||||
|
||||
__txm_module_preamble:
|
||||
.dc.l 0x4D4F4455 // Module ID
|
||||
.dc.l 0x6 // Module Major Version
|
||||
.dc.l 0x1 // Module Minor Version
|
||||
.dc.l 32 // Module Preamble Size in 32-bit words
|
||||
.dc.l 0x12345678 // Module ID (application defined)
|
||||
.dc.l 0x01000007 // Module Properties where:
|
||||
// Bits 31-24: Compiler ID
|
||||
// 0 -> IAR
|
||||
// 1 -> ARM
|
||||
// 2 -> GNU
|
||||
// Bit 0: 0 -> Privileged mode execution
|
||||
// 1 -> User mode execution
|
||||
// Bit 1: 0 -> No MPU protection
|
||||
// 1 -> MPU protection (must have user mode selected)
|
||||
// Bit 2: 0 -> Disable shared/external memory access
|
||||
// 1 -> Enable shared/external memory access
|
||||
.dc.l _txm_module_thread_shell_entry - __txm_module_preamble // Module Shell Entry Point
|
||||
.dc.l demo_module_start - __txm_module_preamble // Module Start Thread Entry Point
|
||||
.dc.l 0 // Module Stop Thread Entry Point
|
||||
.dc.l 1 // Module Start/Stop Thread Priority
|
||||
.dc.l 1024 // Module Start/Stop Thread Stack Size
|
||||
.dc.l _txm_module_callback_request_thread_entry - __txm_module_preamble // Module Callback Thread Entry
|
||||
.dc.l 1 // Module Callback Thread Priority
|
||||
.dc.l 1024 // Module Callback Thread Stack Size
|
||||
//the tools can't add two symbols together, but it should look like this:
|
||||
//.dc.l Image$$ER_RO$$Length + Image$$ER_RW$$Length // Module Code Size
|
||||
//.dc.l Image$$ER_RW$$Length + Image$$ER_ZI$$ZI$$Length // Module Data Size
|
||||
//so instead we'll define hard values:
|
||||
.dc.l 0x4000 // Module Code Size
|
||||
.dc.l 0x4000 // Module Data Size
|
||||
.dc.l 0 // Reserved 0
|
||||
.dc.l 0 // Reserved 1
|
||||
.dc.l 0 // Reserved 2
|
||||
.dc.l 0 // Reserved 3
|
||||
.dc.l 0 // Reserved 4
|
||||
.dc.l 0 // Reserved 5
|
||||
.dc.l 0 // Reserved 6
|
||||
.dc.l 0 // Reserved 7
|
||||
.dc.l 0 // Reserved 8
|
||||
.dc.l 0 // Reserved 9
|
||||
.dc.l 0 // Reserved 10
|
||||
.dc.l 0 // Reserved 11
|
||||
.dc.l 0 // Reserved 12
|
||||
.dc.l 0 // Reserved 13
|
||||
.dc.l 0 // Reserved 14
|
||||
.dc.l 0 // Reserved 15
|
||||
@@ -0,0 +1,210 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Initialize */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
SYSTEM_CLOCK = 6000000
|
||||
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
|
||||
|
||||
/* Setup the stack and heap areas. */
|
||||
|
||||
STACK_SIZE = 0x00000400
|
||||
HEAP_SIZE = 0x00000000
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_initialize_low_level Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for any low-level processor */
|
||||
/* initialization, including setting up interrupt vectors, setting */
|
||||
/* up a periodic timer interrupt source, saving the system stack */
|
||||
/* pointer for use in ISR processing later, and finding the first */
|
||||
/* available RAM memory address for tx_application_define. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_initialize_low_level(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_initialize_low_level
|
||||
.thumb_func
|
||||
.type _tx_initialize_low_level, function
|
||||
_tx_initialize_low_level:
|
||||
|
||||
/* Disable interrupts during ThreadX initialization. */
|
||||
CPSID i
|
||||
|
||||
/* Set base of available memory to end of non-initialised RAM area. */
|
||||
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
|
||||
LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address
|
||||
ADDS r1, r1, #4 //
|
||||
STR r1, [r0] // Setup first unused memory pointer
|
||||
|
||||
/* Setup Vector Table Offset Register. */
|
||||
LDR r0, =0xE000ED08 // Build address of NVIC registers
|
||||
LDR r1, =__Vectors // Pickup address of vector table
|
||||
STR r1, [r0] // Set vector table address
|
||||
|
||||
// /* Enable the cycle count register. */
|
||||
//
|
||||
// LDR r0, =0xE0001000 // Build address of DWT register
|
||||
// LDR r1, [r0] // Pickup the current value
|
||||
// ORR r1, r1, #1 // Set the CYCCNTENA bit
|
||||
// STR r1, [r0] // Enable the cycle count register
|
||||
|
||||
/* Set system stack pointer from vector value. */
|
||||
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
|
||||
LDR r1, =__Vectors // Pickup address of vector table
|
||||
LDR r1, [r1] // Pickup reset stack pointer
|
||||
STR r1, [r0] // Save system stack pointer
|
||||
|
||||
/* Configure SysTick. */
|
||||
LDR r0, =0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] // Setup SysTick Reload Value
|
||||
MOVW r1, #0x7 // Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] // Setup SysTick Control
|
||||
|
||||
/* Configure handler priorities. */
|
||||
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
|
||||
LDR r0, =0xE000E000 // Build address of NVIC registers
|
||||
LDR r2, =0xD18 //
|
||||
ADD r0, r0, r2 //
|
||||
STR r1, [r0] // Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
|
||||
LDR r0, =0xE000E000 // Build address of NVIC registers
|
||||
LDR r2, =0xD1C //
|
||||
ADD r0, r0, r2 //
|
||||
STR r1, [r0] // Setup System Handlers 8-11 Priority Registers
|
||||
// Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
|
||||
LDR r0, =0xE000E000 // Build address of NVIC registers
|
||||
LDR r2, =0xD20 //
|
||||
ADD r0, r0, r2 //
|
||||
STR r1, [r0] // Setup System Handlers 12-15 Priority Registers
|
||||
// Note: PnSV must be lowest priority, which is 0xFF
|
||||
|
||||
/* Return to caller. */
|
||||
BX lr
|
||||
// }
|
||||
|
||||
|
||||
/* Define shells for each of the unused vectors. */
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_BadHandler
|
||||
.thumb_func
|
||||
.type __tx_BadHandler, function
|
||||
__tx_BadHandler:
|
||||
B __tx_BadHandler
|
||||
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_IntHandler
|
||||
.thumb_func
|
||||
.type __tx_IntHandler, function
|
||||
__tx_IntHandler:
|
||||
// VOID InterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
|
||||
/* Do interrupt handler work here */
|
||||
/* .... */
|
||||
|
||||
POP {r0, r1}
|
||||
MOV lr, r1
|
||||
BX lr
|
||||
// }
|
||||
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global SysTick_Handler
|
||||
.thumb_func
|
||||
.type SysTick_Handler, function
|
||||
SysTick_Handler:
|
||||
// VOID TimerInterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
BL _tx_timer_interrupt
|
||||
POP {r0, r1}
|
||||
MOV lr, r1
|
||||
BX lr
|
||||
// }
|
||||
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global HardFault_Handler
|
||||
.thumb_func
|
||||
.type HardFault_Handler, function
|
||||
HardFault_Handler:
|
||||
// A stack overflow will trigger a hardfault.
|
||||
// There is no CFSR in M23, so we will not try to
|
||||
// determine if the fault is caused by a stack overflow
|
||||
// or some other condition.
|
||||
B HardFault_Handler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'txm'
|
||||
* Target: 'ThreadX Module Library'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCM23_TZ.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
1412
ports_module/cortex_m23/ac6/example_build/txm/txm.uvoptx
Normal file
1412
ports_module/cortex_m23/ac6/example_build/txm/txm.uvoptx
Normal file
File diff suppressed because it is too large
Load Diff
943
ports_module/cortex_m23/ac6/example_build/txm/txm.uvprojx
Normal file
943
ports_module/cortex_m23/ac6/example_build/txm/txm.uvprojx
Normal file
@@ -0,0 +1,943 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>ThreadX Module Library</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>ARMCM23_TZ</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<PackID>ARM.CMSIS.5.5.1</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile></SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>txm</OutputName>
|
||||
<CreateExecutable>0</CreateExecutable>
|
||||
<CreateLib>1</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName></SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll></SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMV8M.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M23"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>4</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x200000</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>2</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>1</Ropi>
|
||||
<Rwpi>1</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>3</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
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<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_relinquish.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_reset.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_resume.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_sleep.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_stack_error_notify.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_suspend.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_terminate.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_time_slice_change.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_wait_abort.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_time_get.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_time_get.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_time_set.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_time_set.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_timer_activate.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_timer_change.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_change.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_timer_create.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_create.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_timer_deactivate.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_timer_delete.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_timer_info_get.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_timer_performance_info_get.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_timer_performance_system_info_get.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_buffer_full_notify.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_disable.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_enable.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_event_filter.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_event_unfilter.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_interrupt_control.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_interrupt_control.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_isr_enter_insert.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_isr_exit_insert.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_trace_user_event_insert.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_module_initialize.S</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\module_lib\src\txm_module_initialize.S</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_module_thread_shell_entry.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\module_lib\src\txm_module_thread_shell_entry.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_secure_stack_allocate.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\module_lib\src\txm_thread_secure_stack_allocate.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>txm_thread_secure_stack_free.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\module_lib\src\txm_thread_secure_stack_free.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<packages>
|
||||
<filter>
|
||||
<targetInfos/>
|
||||
</filter>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1">
|
||||
<targetInfos>
|
||||
<targetInfo name="ThreadX Module Library" versionMatchMode="fixed"/>
|
||||
</targetInfos>
|
||||
</package>
|
||||
</packages>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="ThreadX Module Library"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayDesc></LayDesc>
|
||||
<LayUrl></LayUrl>
|
||||
<LayKeys></LayKeys>
|
||||
<LayCat></LayCat>
|
||||
<LayLic></LayLic>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
584
ports_module/cortex_m23/ac6/inc/tx_port.h
Normal file
584
ports_module/cortex_m23/ac6/inc/tx_port.h
Normal file
@@ -0,0 +1,584 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Port Specific */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* PORT SPECIFIC C INFORMATION RELEASE */
|
||||
/* */
|
||||
/* tx_port.h Cortex-M23/AC6 */
|
||||
/* 6.1.6 */
|
||||
/* */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file contains data type definitions that make the ThreadX */
|
||||
/* real-time kernel function identically on a variety of different */
|
||||
/* processor architectures. For example, the size or number of bits */
|
||||
/* in an "int" data type vary between microprocessor architectures and */
|
||||
/* even C compilers for the same microprocessor. ThreadX does not */
|
||||
/* directly use native C data types. Instead, ThreadX creates its */
|
||||
/* own special types that can be mapped to actual data types by this */
|
||||
/* file to guarantee consistency in the interface and functionality. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TX_PORT_H
|
||||
#define TX_PORT_H
|
||||
|
||||
/* Determine if the optional ThreadX user define file should be used. */
|
||||
#ifdef TX_INCLUDE_USER_DEFINE_FILE
|
||||
|
||||
/* Yes, include the user defines in tx_user.h. The defines in this file may
|
||||
alternately be defined on the command line. */
|
||||
|
||||
#include "tx_user.h"
|
||||
#endif
|
||||
|
||||
/* Define compiler library include files. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <arm_compat.h>
|
||||
#include "ARMCM23_TZ.h" /* For intrinsic functions. */
|
||||
|
||||
/* Define ThreadX basic types for this port. */
|
||||
|
||||
#define VOID void
|
||||
typedef char CHAR;
|
||||
typedef unsigned char UCHAR;
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
typedef unsigned long long ULONG64;
|
||||
typedef short SHORT;
|
||||
typedef unsigned short USHORT;
|
||||
#define ULONG64_DEFINED
|
||||
|
||||
/* Function prototypes for this port. */
|
||||
struct TX_THREAD_STRUCT;
|
||||
UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size);
|
||||
UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
|
||||
UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
|
||||
UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
|
||||
|
||||
/* This hardware has stack checking that we take advantage of - do NOT define. */
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#error "Do not define TX_ENABLE_STACK_CHECKING"
|
||||
#endif
|
||||
|
||||
/* If user does not want to terminate thread on stack overflow,
|
||||
#define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol.
|
||||
The thread will be rescheduled and continue to cause the exception.
|
||||
It is suggested user code handle this by registering a notification with the
|
||||
tx_thread_stack_error_notify function. */
|
||||
/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */
|
||||
|
||||
/* Define the system API mappings based on the error checking
|
||||
selected by the user. Note: this section is only applicable to
|
||||
application source code, hence the conditional that turns off this
|
||||
stuff when the include file is processed by the ThreadX source. */
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Determine if error checking is desired. If so, map API functions
|
||||
to the appropriate error checking front-ends. Otherwise, map API
|
||||
functions to the core functions that actually perform the work.
|
||||
Note: error checking is enabled by default. */
|
||||
|
||||
#ifdef TX_DISABLE_ERROR_CHECKING
|
||||
|
||||
/* Services without error checking. */
|
||||
|
||||
#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate
|
||||
#define tx_thread_secure_stack_free _tx_thread_secure_stack_free
|
||||
|
||||
#else
|
||||
|
||||
/* Services with error checking. */
|
||||
|
||||
#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate
|
||||
#define tx_thread_secure_stack_free _txe_thread_secure_stack_free
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Define the priority levels for ThreadX. Legal values range
|
||||
from 32 to 1024 and MUST be evenly divisible by 32. */
|
||||
|
||||
#ifndef TX_MAX_PRIORITIES
|
||||
#define TX_MAX_PRIORITIES 32
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
|
||||
thread creation is less than this value, the thread create call will return an error. */
|
||||
|
||||
#ifndef TX_MINIMUM_STACK
|
||||
#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the system timer thread's default stack size and priority. These are only applicable
|
||||
if TX_TIMER_PROCESS_IN_ISR is not defined. */
|
||||
|
||||
#ifndef TX_TIMER_THREAD_STACK_SIZE
|
||||
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
|
||||
#endif
|
||||
|
||||
#ifndef TX_TIMER_THREAD_PRIORITY
|
||||
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define various constants for the ThreadX Cortex-M23 port. */
|
||||
|
||||
#define TX_INT_DISABLE 1 /* Disable interrupts */
|
||||
#define TX_INT_ENABLE 0 /* Enable interrupts */
|
||||
|
||||
|
||||
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
|
||||
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
|
||||
source constants would be:
|
||||
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
|
||||
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
|
||||
|
||||
*/
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#ifndef TX_TRACE_TIME_SOURCE
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
|
||||
#endif
|
||||
#else
|
||||
ULONG _tx_misra_time_stamp_get(VOID);
|
||||
#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get()
|
||||
#endif
|
||||
|
||||
#ifndef TX_TRACE_TIME_MASK
|
||||
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the port specific options for the _tx_build_options variable. This variable indicates
|
||||
how the ThreadX library was built. */
|
||||
|
||||
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
|
||||
|
||||
|
||||
/* Define the in-line initialization constant so that modules with in-line
|
||||
initialization capabilities can prevent their initialization from being
|
||||
a function call. */
|
||||
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
#define TX_DISABLE_INLINE
|
||||
#else
|
||||
#define TX_INLINE_INITIALIZATION
|
||||
#endif
|
||||
|
||||
|
||||
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
|
||||
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
|
||||
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
|
||||
define is negated, thereby forcing the stack fill which is necessary for the stack checking
|
||||
logic. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#undef TX_DISABLE_STACK_FILLING
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the TX_THREAD control block extensions for this port. The main reason
|
||||
for the multiple macros is so that backward compatibility can be maintained with
|
||||
existing ThreadX kernel awareness modules. */
|
||||
|
||||
#define TX_THREAD_EXTENSION_0
|
||||
#define TX_THREAD_EXTENSION_1
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
ULONG tx_thread_module_saved_lr; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved; \
|
||||
VOID *tx_thread_secure_stack_context;
|
||||
#else
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
ULONG tx_thread_module_saved_lr; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved;
|
||||
#endif
|
||||
#define TX_THREAD_EXTENSION_3
|
||||
|
||||
|
||||
/* Define the port extensions of the remaining ThreadX objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_EXTENSION
|
||||
#define TX_BYTE_POOL_EXTENSION
|
||||
#define TX_MUTEX_EXTENSION
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
|
||||
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
|
||||
|
||||
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
|
||||
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
|
||||
|
||||
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
|
||||
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
|
||||
|
||||
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
|
||||
VOID (*tx_timer_module_expiration_function)(ULONG id);
|
||||
|
||||
|
||||
/* Define the user extension field of the thread control block. Nothing
|
||||
additional is needed for this port so it is defined as white space. */
|
||||
|
||||
#ifndef TX_THREAD_USER_EXTENSION
|
||||
#define TX_THREAD_USER_EXTENSION
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
|
||||
tx_thread_shell_entry, and tx_thread_terminate. */
|
||||
|
||||
|
||||
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);}
|
||||
#else
|
||||
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
|
||||
#endif
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */
|
||||
#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256
|
||||
#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE);
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
|
||||
inline static unsigned int _get_ipsr(void);
|
||||
inline static unsigned int _get_ipsr(void)
|
||||
{
|
||||
unsigned int _ipsr;
|
||||
__asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
|
||||
return _ipsr;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __ARM_PCS_VFP
|
||||
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
|
||||
ULONG _tx_misra_control_get(void);
|
||||
void _tx_misra_control_set(ULONG value);
|
||||
ULONG _tx_misra_fpccr_get(void);
|
||||
void _tx_misra_vfp_touch(void);
|
||||
|
||||
#else
|
||||
|
||||
#ifdef TX_SOURCE_CODE
|
||||
|
||||
static unsigned int _get_control(void);
|
||||
static unsigned int _get_control(void)
|
||||
{
|
||||
unsigned int _control;
|
||||
__asm("MRS %[result], control" : [result] "=r" (_control) : );
|
||||
return _control;
|
||||
}
|
||||
|
||||
static void _set_control(unsigned int _control);
|
||||
static void _set_control(unsigned int _control)
|
||||
{
|
||||
__asm("MSR control, %[input]" : : [input] "r" (_control));
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
|
||||
in order to ensure no lazy stacking will occur. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _get_control(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_set_control(_tx_vfp_state);; \
|
||||
}
|
||||
#else
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
|
||||
If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
|
||||
this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush
|
||||
the lazy FPU save, then restore the CONTROL.FPCA state. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
void _tx_vfp_access(void);
|
||||
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_system_state; \
|
||||
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
|
||||
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _get_control(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_set_control(_tx_vfp_state); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
ULONG _tx_fpccr; \
|
||||
_tx_fpccr = *((ULONG *) 0xE000EF34); \
|
||||
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
|
||||
if (_tx_fpccr == ((ULONG) 0x01)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _get_control(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
|
||||
_tx_vfp_access(); \
|
||||
if (_tx_vfp_state == ((ULONG) 0)) \
|
||||
{ \
|
||||
_tx_vfp_state = _get_control(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_set_control(_tx_vfp_state); \
|
||||
} \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_system_state; \
|
||||
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
|
||||
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
ULONG _tx_fpccr; \
|
||||
_tx_fpccr = _tx_misra_fpccr_get(); \
|
||||
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
|
||||
if (_tx_fpccr == ((ULONG) 0x01)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
|
||||
_tx_misra_vfp_touch(); \
|
||||
if (_tx_vfp_state == ((ULONG) 0)) \
|
||||
{ \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
} \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the ThreadX object creation extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the ThreadX object deletion extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the get system state macro. */
|
||||
|
||||
#ifndef TX_THREAD_GET_SYSTEM_STATE
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr())
|
||||
#else
|
||||
ULONG _tx_misra_ipsr_get(VOID);
|
||||
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get())
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value
|
||||
indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
|
||||
for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
|
||||
zero after initialization for Cortex-M ports. */
|
||||
|
||||
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
|
||||
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
|
||||
#endif
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
/* Initialize secure stacks for threads calling secure functions. */
|
||||
extern void _tx_thread_secure_stack_initialize(void);
|
||||
#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize();
|
||||
#endif
|
||||
|
||||
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
|
||||
prevent early scheduling on Cortex-M parts. */
|
||||
|
||||
#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++;
|
||||
|
||||
|
||||
/* Determine if the ARM architecture has the CLZ instruction. This is available on
|
||||
architectures v5 and above. If available, redefine the macro for calculating the
|
||||
lowest bit set. */
|
||||
|
||||
#ifndef TX_DISABLE_INLINE
|
||||
|
||||
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__clz(__rbit((m)));
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Define ThreadX interrupt lockout and restore macros for protection on
|
||||
access of critical kernel information. The restore interrupt macro must
|
||||
restore the interrupt posture of the running thread prior to the value
|
||||
present prior to the disable macro. In most cases, the save area macro
|
||||
is used to define a local function save area for the disable and restore
|
||||
macros. */
|
||||
|
||||
#ifdef TX_DISABLE_INLINE
|
||||
|
||||
UINT _tx_thread_interrupt_disable(VOID);
|
||||
VOID _tx_thread_interrupt_restore(UINT previous_posture);
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
|
||||
|
||||
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
|
||||
|
||||
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
|
||||
|
||||
#else
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA UINT was_masked;
|
||||
#define TX_DISABLE was_masked = __disable_irq();
|
||||
#define TX_RESTORE if (was_masked == 0) __enable_irq();
|
||||
|
||||
#define _tx_thread_system_return _tx_thread_system_return_inline
|
||||
|
||||
|
||||
static void _tx_thread_system_return_inline(void)
|
||||
{
|
||||
unsigned int was_masked;
|
||||
|
||||
|
||||
/* Set PendSV to invoke ThreadX scheduler. */
|
||||
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
|
||||
if (_get_ipsr() == 0)
|
||||
{
|
||||
was_masked = __disable_irq();
|
||||
__enable_irq();
|
||||
if (was_masked != 0)
|
||||
__disable_irq();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the version ID of ThreadX. This may be utilized by the application. */
|
||||
|
||||
#ifdef TX_THREAD_INIT
|
||||
CHAR _tx_version_id[] =
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.6 *";
|
||||
#else
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
extern CHAR _tx_version_id[100];
|
||||
#else
|
||||
extern CHAR _tx_version_id[];
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
60
ports_module/cortex_m23/ac6/inc/tx_secure_interface.h
Normal file
60
ports_module/cortex_m23/ac6/inc/tx_secure_interface.h
Normal file
@@ -0,0 +1,60 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* COMPONENT DEFINITION RELEASE */
|
||||
/* */
|
||||
/* tx_secure_interface.h PORTABLE C */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file defines the ThreadX secure thread stack components, */
|
||||
/* including data types and external references. */
|
||||
/* It is assumed that tx_api.h and tx_port.h have already been */
|
||||
/* included. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TX_SECURE_INTERFACE_H
|
||||
#define TX_SECURE_INTERFACE_H
|
||||
|
||||
/* Define internal secure thread stack function prototypes. */
|
||||
|
||||
extern void _tx_thread_secure_stack_initialize(void);
|
||||
extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size);
|
||||
extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr);
|
||||
extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr);
|
||||
extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr);
|
||||
|
||||
#endif
|
||||
352
ports_module/cortex_m23/ac6/inc/txm_module_port.h
Normal file
352
ports_module/cortex_m23/ac6/inc/txm_module_port.h
Normal file
@@ -0,0 +1,352 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* APPLICATION INTERFACE DEFINITION RELEASE */
|
||||
/* */
|
||||
/* txm_module_port.h Cortex-M23/AC6 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file defines the basic module constants, interface structures, */
|
||||
/* and function prototypes. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TXM_MODULE_PORT_H
|
||||
#define TXM_MODULE_PORT_H
|
||||
|
||||
/* Determine if the optional Modules user define file should be used. */
|
||||
|
||||
#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
|
||||
|
||||
/* Yes, include the user defines in txm_module_user.h. The defines in this file may
|
||||
alternately be defined on the command line. */
|
||||
|
||||
#include "txm_module_user.h"
|
||||
#endif
|
||||
|
||||
/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
|
||||
following extensions to the ThreadX thread control block (this code should replace
|
||||
the corresponding macro define in tx_port.h):
|
||||
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
ULONG tx_thread_module_saved_lr; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved;
|
||||
|
||||
The following extensions must also be defined in tx_port.h:
|
||||
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
|
||||
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
|
||||
|
||||
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
|
||||
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
|
||||
|
||||
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
|
||||
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
|
||||
|
||||
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
|
||||
VOID (*tx_timer_module_expiration_function)(ULONG id);
|
||||
*/
|
||||
|
||||
/* Define the kernel stack size for a module thread. */
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
|
||||
#define TXM_MODULE_KERNEL_STACK_SIZE 768
|
||||
#endif
|
||||
|
||||
/* Define constants specific to the tools the module can be built with for this particular modules port. */
|
||||
|
||||
#define TXM_MODULE_IAR_COMPILER 0x00000000
|
||||
#define TXM_MODULE_RVDS_COMPILER 0x01000000
|
||||
#define TXM_MODULE_GNU_COMPILER 0x02000000
|
||||
#define TXM_MODULE_COMPILER_MASK 0xFF000000
|
||||
#define TXM_MODULE_OPTIONS_MASK 0x000000FF
|
||||
|
||||
|
||||
/* Define the properties for this particular module port. */
|
||||
|
||||
#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
|
||||
#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
|
||||
#else
|
||||
#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
|
||||
#endif
|
||||
|
||||
#define TXM_MODULE_USER_MODE 0x00000001
|
||||
#define TXM_MODULE_MEMORY_PROTECTION 0x00000002
|
||||
#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004
|
||||
|
||||
|
||||
/* Define the supported options for this module. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
|
||||
#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0
|
||||
|
||||
|
||||
/* Define offset adjustments according to the compiler used to build the module. */
|
||||
|
||||
#define TXM_MODULE_IAR_SHELL_ADJUST 24
|
||||
#define TXM_MODULE_IAR_START_ADJUST 28
|
||||
#define TXM_MODULE_IAR_STOP_ADJUST 32
|
||||
#define TXM_MODULE_IAR_CALLBACK_ADJUST 44
|
||||
|
||||
#define TXM_MODULE_RVDS_SHELL_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_START_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_STOP_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0
|
||||
|
||||
#define TXM_MODULE_GNU_SHELL_ADJUST 24
|
||||
#define TXM_MODULE_GNU_START_ADJUST 28
|
||||
#define TXM_MODULE_GNU_STOP_ADJUST 32
|
||||
#define TXM_MODULE_GNU_CALLBACK_ADJUST 44
|
||||
|
||||
|
||||
/* Define other module port-specific constants. */
|
||||
|
||||
/* Define INLINE_DECLARE to inline for ARM compiler. */
|
||||
|
||||
#define INLINE_DECLARE inline
|
||||
|
||||
/* Define the number of MPU entries assigned to the code and data sections.
|
||||
On Cortex-M23 devices, there are 8 total entries. ThreadX uses one for access
|
||||
to the kernel entry function, one for module code protection, one for module data protection,
|
||||
leaving five regions available for shared memory. */
|
||||
#define TXM_MODULE_MPU_TOTAL_ENTRIES 8
|
||||
#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0
|
||||
#define TXM_MODULE_MPU_CODE_INDEX 1
|
||||
#define TXM_MODULE_MPU_DATA_INDEX 2
|
||||
|
||||
#define TXM_MODULE_MPU_SHARED_INDEX 3
|
||||
#define TXM_MODULE_MPU_SHARED_ENTRIES 5
|
||||
|
||||
#define TXM_MODULE_ATTRIBUTE_NON_SHAREABLE 0x00
|
||||
#define TXM_MODULE_ATTRIBUTE_OUTER_SHAREABLE 0x10
|
||||
#define TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE 0x18
|
||||
#define TXM_MODULE_ATTRIBUTE_READ_WRITE 0x02
|
||||
#define TXM_MODULE_ATTRIBUTE_READ_ONLY 0x06
|
||||
#define TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER 0x01
|
||||
#define TXM_MODULE_ATTRIBUTE_REGION_ENABLE 0x01
|
||||
#define TXM_MODULE_ATTRIBUTE_MASK 0x1E
|
||||
#define TXM_MODULE_ATTRIBUTE_INDEX 0x00
|
||||
|
||||
/* MAIR_ATTR settings
|
||||
Device-nGnRE : 0b [Outer]0000 [Inner]0100
|
||||
Code WT RA : 0b [Outer]1010 [Inner]1010
|
||||
DATA WBWA RA : 0b [Outer]1111 [Inner]1111
|
||||
*/
|
||||
|
||||
/* Data aligned to 8 bytes (stacks must be 8-byte aligned). */
|
||||
#define TXM_MODULE_DATA_ALIGNMENT 8
|
||||
|
||||
/* MPU regions must be 32-byte aligned. */
|
||||
#define TXM_MODULE_MPU_ALIGNMENT 32
|
||||
|
||||
#define TXM_THREAD_SECURE_STACK_ALLOCATE_CALL TXM_MODULE_PORT_EXTENSION_API_ID_START
|
||||
#define TXM_THREAD_SECURE_STACK_FREE_CALL (TXM_MODULE_PORT_EXTENSION_API_ID_START+1)
|
||||
|
||||
/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RLAR. */
|
||||
typedef struct TXM_MODULE_MPU_INFO_STRUCT
|
||||
{
|
||||
ULONG txm_module_mpu_region_base_address;
|
||||
ULONG txm_module_mpu_region_limit_address;
|
||||
} TXM_MODULE_MPU_INFO;
|
||||
|
||||
/* Define the port-extensions to the module manager instance structure. */
|
||||
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
|
||||
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \
|
||||
ULONG txm_module_instance_shared_memory_count; \
|
||||
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
|
||||
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
|
||||
|
||||
|
||||
/* Define the memory fault information structure that is populated when a memory fault occurs. */
|
||||
|
||||
typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
|
||||
{
|
||||
TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr;
|
||||
VOID *txm_module_manager_memory_fault_info_code_location;
|
||||
ULONG txm_module_manager_memory_fault_info_shcsr;
|
||||
ULONG txm_module_manager_memory_fault_info_cfsr;
|
||||
ULONG txm_module_manager_memory_fault_info_mmfar;
|
||||
ULONG txm_module_manager_memory_fault_info_bfar;
|
||||
ULONG txm_module_manager_memory_fault_info_control;
|
||||
ULONG txm_module_manager_memory_fault_info_sp;
|
||||
ULONG txm_module_manager_memory_fault_info_r0;
|
||||
ULONG txm_module_manager_memory_fault_info_r1;
|
||||
ULONG txm_module_manager_memory_fault_info_r2;
|
||||
ULONG txm_module_manager_memory_fault_info_r3;
|
||||
ULONG txm_module_manager_memory_fault_info_r4;
|
||||
ULONG txm_module_manager_memory_fault_info_r5;
|
||||
ULONG txm_module_manager_memory_fault_info_r6;
|
||||
ULONG txm_module_manager_memory_fault_info_r7;
|
||||
ULONG txm_module_manager_memory_fault_info_r8;
|
||||
ULONG txm_module_manager_memory_fault_info_r9;
|
||||
ULONG txm_module_manager_memory_fault_info_r10;
|
||||
ULONG txm_module_manager_memory_fault_info_r11;
|
||||
ULONG txm_module_manager_memory_fault_info_r12;
|
||||
ULONG txm_module_manager_memory_fault_info_lr;
|
||||
ULONG txm_module_manager_memory_fault_info_xpsr;
|
||||
} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
|
||||
|
||||
|
||||
#define TXM_MODULE_MANAGER_FAULT_INFO \
|
||||
TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info;
|
||||
|
||||
|
||||
/* Define the macro to check the code alignment. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \
|
||||
{ \
|
||||
ULONG temp; \
|
||||
temp = (ULONG) module_location; \
|
||||
temp = temp & (code_alignment - 1); \
|
||||
if (temp) \
|
||||
{ \
|
||||
_tx_mutex_put(&_txm_module_manager_mutex); \
|
||||
return(TXM_MODULE_ALIGNMENT_ERROR); \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to adjust the alignment and size for code/data areas. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment);
|
||||
|
||||
|
||||
/* Define the macro to adjust the symbols in the module preamble. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
|
||||
if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \
|
||||
} \
|
||||
else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to populate the thread control block with module port-specific information.
|
||||
Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
|
||||
*/
|
||||
|
||||
#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \
|
||||
thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \
|
||||
thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \
|
||||
if (thread_ptr -> tx_thread_module_user_mode) \
|
||||
{ \
|
||||
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to populate the module control block with module port-specific information.
|
||||
If memory protection is enabled, set up the MPU registers.
|
||||
*/
|
||||
#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \
|
||||
{ \
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \
|
||||
{ \
|
||||
_txm_module_manager_mm_register_setup(module_instance); \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
/* Do nothing. */ \
|
||||
}
|
||||
|
||||
/* Define the macro to perform port-specific functions when unloading the module. */
|
||||
/* Nothing needs to be done for this port. */
|
||||
#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
|
||||
|
||||
|
||||
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
|
||||
|
||||
/* Define macro to make sure object is inside the module's data. */
|
||||
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
|
||||
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
|
||||
|
||||
/* Define some internal prototypes to this module port. */
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef TX_SOURCE_CODE
|
||||
|
||||
#endif
|
||||
|
||||
#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \
|
||||
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \
|
||||
VOID _txm_module_manager_memory_fault_handler(VOID); \
|
||||
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \
|
||||
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
|
||||
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \
|
||||
ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2);
|
||||
|
||||
|
||||
#define TXM_MODULE_MANAGER_VERSION_ID \
|
||||
CHAR _txm_module_manager_version_id[] = \
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/AC6 Version 6.1.6 *";
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,118 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
.global __use_two_region_memory
|
||||
.global __scatterload
|
||||
|
||||
.eabi_attribute Tag_ABI_PCS_RO_data, 1
|
||||
.eabi_attribute Tag_ABI_PCS_R9_use, 1
|
||||
.eabi_attribute Tag_ABI_PCS_RW_data, 2
|
||||
|
||||
.text
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_initialize Cortex-M23/AC6 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function initializes the module c runtime. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __scatterload Initialize C runtime */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_thread_shell_entry Start module thread */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _txm_module_initialize(VOID)
|
||||
.global _txm_module_initialize
|
||||
.thumb_func
|
||||
_txm_module_initialize:
|
||||
MOV r0, r8 // Copy r8-r11
|
||||
MOV r1, r9
|
||||
MOV r2, r10
|
||||
MOV r3, r11
|
||||
PUSH {r0-r7} // Save r4-r11
|
||||
MOV r0, r12
|
||||
MOV r1, lr
|
||||
PUSH {r0-r1} // Save r12, lr
|
||||
|
||||
//B __scatterload // Call ARM func to initialize variables
|
||||
|
||||
// Override the __rt_exit function.
|
||||
.global __rt_exit
|
||||
.thumb_func
|
||||
__rt_exit:
|
||||
POP {r0-r1} // Restore r4-r12 and LR
|
||||
MOV r12, r0
|
||||
MOV lr, r1
|
||||
POP {r0-r7}
|
||||
MOV r8, r0
|
||||
MOV r9, r1
|
||||
MOV r10, r2
|
||||
MOV r11, r3
|
||||
BX lr // Return to caller
|
||||
|
||||
#define TXM_MODULE_HEAP_SIZE 512
|
||||
|
||||
// returns heap start address in R0
|
||||
// returns heap end address in R2
|
||||
// does not touch SP, it is already set up before the module runs
|
||||
.global __user_setup_stackheap
|
||||
.thumb_func
|
||||
__user_setup_stackheap:
|
||||
LDR r1, _txm_heap // load heap offset
|
||||
MOV r2, TXM_MODULE_HEAP_SIZE // load heap size
|
||||
ADD r2, r2, r0 // calculate heap end address
|
||||
BX lr
|
||||
|
||||
// dummy main function
|
||||
.global main
|
||||
.thumb_func
|
||||
main:
|
||||
BX lr
|
||||
|
||||
.align 8
|
||||
_txm_heap:
|
||||
.zero TXM_MODULE_HEAP_SIZE
|
||||
@@ -0,0 +1,172 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TXM_MODULE
|
||||
#define TXM_MODULE
|
||||
#endif
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
#define TX_SOURCE_CODE
|
||||
#endif
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "txm_module.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/* Define the global module entry pointer from the start thread of the module. */
|
||||
|
||||
TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
|
||||
|
||||
|
||||
/* Define the dispatch function pointer used in the module implementation. */
|
||||
|
||||
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
|
||||
|
||||
|
||||
/* Define the ARM cstartup code. */
|
||||
extern VOID _txm_module_initialize(VOID);
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_thread_shell_entry Cortex-M23/AC6 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function calls the specified entry function of the thread. It */
|
||||
/* also provides a place for the thread's entry function to return. */
|
||||
/* If the thread returns, this function places the thread in a */
|
||||
/* "COMPLETED" state. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to current thread */
|
||||
/* thread_info Pointer to thread entry info */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_module_initialize cstartup initialization */
|
||||
/* thread_entry Thread's entry function */
|
||||
/* tx_thread_resume Resume the module callback thread */
|
||||
/* _txm_module_thread_system_suspend Module thread suspension routine */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Initial thread stack frame */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
|
||||
{
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
VOID (*entry_exit_notify)(TX_THREAD *, UINT);
|
||||
#endif
|
||||
|
||||
|
||||
/* Determine if this is the start thread. If so, we must prepare the module for
|
||||
execution. If not, simply skip the C startup code. */
|
||||
if (thread_info -> txm_module_thread_entry_info_start_thread)
|
||||
{
|
||||
/* Initialize the ARM C environment. */
|
||||
_txm_module_initialize();
|
||||
|
||||
/* Save the entry info pointer, for later use. */
|
||||
_txm_module_entry_info = thread_info;
|
||||
|
||||
/* Save the kernel function dispatch address. This is used to make all resident calls from
|
||||
the module. */
|
||||
_txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
|
||||
|
||||
/* Ensure that we have a valid pointer. */
|
||||
while (!_txm_module_kernel_call_dispatcher)
|
||||
{
|
||||
/* Loop here, if an error is present getting the dispatch function pointer!
|
||||
An error here typically indicates the resident portion of _tx_thread_schedule
|
||||
is not supporting the trap to obtain the function pointer. */
|
||||
}
|
||||
|
||||
/* Resume the module's callback thread, already created in the manager. */
|
||||
_txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
|
||||
}
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
/* Pickup the entry/exit application callback routine. */
|
||||
entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify;
|
||||
|
||||
/* Determine if an application callback routine is specified. */
|
||||
if (entry_exit_notify != TX_NULL)
|
||||
{
|
||||
|
||||
/* Yes, notify application that this thread has been entered! */
|
||||
(entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call current thread's entry function. */
|
||||
(thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
|
||||
|
||||
/* Suspend thread with a "completed" state. */
|
||||
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
/* Pickup the entry/exit application callback routine again. */
|
||||
entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify;
|
||||
|
||||
/* Determine if an application callback routine is specified. */
|
||||
if (entry_exit_notify != TX_NULL)
|
||||
{
|
||||
|
||||
/* Yes, notify application that this thread has exited! */
|
||||
(entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call actual thread suspension routine. */
|
||||
_txm_module_thread_system_suspend(thread_ptr);
|
||||
|
||||
#ifdef TX_SAFETY_CRITICAL
|
||||
|
||||
/* If we ever get here, raise safety critical exception. */
|
||||
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TXM_MODULE
|
||||
#include "txm_module.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_allocate PORTABLE C */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function allocate a secure stack for the thread. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of secure stack to */
|
||||
/* allocate */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of this function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_module_kernel_call_dispatcher */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Module application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
{
|
||||
|
||||
UINT return_value;
|
||||
|
||||
/* Call module manager dispatcher. */
|
||||
return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_ALLOCATE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) stack_size, 0);
|
||||
|
||||
/* Return value to the caller. */
|
||||
return(return_value);
|
||||
}
|
||||
@@ -0,0 +1,75 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TXM_MODULE
|
||||
#include "txm_module.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_free PORTABLE C */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function frees the thread's secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_module_kernel_call_dispatcher */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Module application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)
|
||||
{
|
||||
|
||||
UINT return_value;
|
||||
|
||||
/* Call module manager dispatcher. */
|
||||
return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_FREE_CALL, (ALIGN_TYPE) thread_ptr, 0, 0);
|
||||
|
||||
/* Return value to the caller. */
|
||||
return(return_value);
|
||||
}
|
||||
@@ -0,0 +1,65 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
/* Define port-specific dispatch functions. */
|
||||
|
||||
/* UINT _txe_thread_secure_stack_allocate(
|
||||
TX_THREAD *thread_ptr, -> param_0
|
||||
ULONG stack_size -> param_1
|
||||
); */
|
||||
static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1)
|
||||
{
|
||||
|
||||
ALIGN_TYPE return_value;
|
||||
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
|
||||
{
|
||||
if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
|
||||
return(TXM_MODULE_INVALID_MEMORY);
|
||||
}
|
||||
|
||||
return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate(
|
||||
(TX_THREAD *) param_0,
|
||||
(ULONG) param_1
|
||||
);
|
||||
return(return_value);
|
||||
}
|
||||
|
||||
/* UINT _txe_thread_secure_stack_free(
|
||||
TX_THREAD *thread_ptr -> param_0
|
||||
); */
|
||||
static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_free_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0)
|
||||
{
|
||||
|
||||
ALIGN_TYPE return_value;
|
||||
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
|
||||
{
|
||||
if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
|
||||
return(TXM_MODULE_INVALID_MEMORY);
|
||||
}
|
||||
|
||||
return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free(
|
||||
(TX_THREAD *) param_0
|
||||
);
|
||||
return(return_value);
|
||||
}
|
||||
@@ -0,0 +1,74 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_context_restore Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is not needed for Cortex-M. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_context_restore(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_context_restore
|
||||
.thumb_func
|
||||
.type _tx_thread_context_restore, function
|
||||
_tx_thread_context_restore:
|
||||
/* Return to interrupt processing. */
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,74 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_context_save Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is not needed for Cortex-M. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_context_save(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_context_save
|
||||
.thumb_func
|
||||
.type _tx_thread_context_save, function
|
||||
_tx_thread_context_save:
|
||||
/* Return to interrupt processing. */
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,78 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_control Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for changing the interrupt lockout */
|
||||
/* posture of the system. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* new_posture New interrupt lockout posture */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* old_posture Old interrupt lockout posture */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_interrupt_control
|
||||
.thumb_func
|
||||
.type _tx_thread_interrupt_control, function
|
||||
_tx_thread_interrupt_control:
|
||||
|
||||
/* Pickup current interrupt lockout posture. */
|
||||
MRS r1, PRIMASK
|
||||
MSR PRIMASK, r0
|
||||
MOV r0, r1
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,77 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_disable Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for disabling interrupts and returning */
|
||||
/* the previous interrupt lockout posture. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* old_posture Old interrupt lockout posture */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_interrupt_disable(UINT new_posture)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_interrupt_disable
|
||||
.thumb_func
|
||||
.type _tx_thread_interrupt_disable, function
|
||||
_tx_thread_interrupt_disable:
|
||||
/* Return current interrupt lockout posture. */
|
||||
MRS r0, PRIMASK
|
||||
CPSID i
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,76 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_restore Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for restoring the previous */
|
||||
/* interrupt lockout posture. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* previous_posture Previous interrupt posture */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_interrupt_restore(UINT new_posture)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_interrupt_restore
|
||||
.thumb_func
|
||||
.type _tx_thread_interrupt_restore, function
|
||||
_tx_thread_interrupt_restore:
|
||||
/* Restore previous interrupt lockout posture. */
|
||||
MSR PRIMASK, r0
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,643 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_schedule Cortex-M23/AC6 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function waits for a thread control block pointer to appear in */
|
||||
/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
/* in the variable, the corresponding thread is resumed. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* _tx_thread_system_return Return to system from thread */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_schedule(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_schedule
|
||||
.thumb_func
|
||||
.type _tx_thread_schedule, function
|
||||
_tx_thread_schedule:
|
||||
|
||||
/* This function should only ever be called on Cortex-M
|
||||
from the first schedule request. Subsequent scheduling occurs
|
||||
from the PendSV handling routine below. */
|
||||
|
||||
/* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
|
||||
MOVW r0, #0 // Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
STR r0, [r2, #0] // Clear preempt disable flag
|
||||
|
||||
/* Enable memory fault registers. */
|
||||
|
||||
LDR r0, =0xE000ED24 // Build SHCSR address
|
||||
LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
|
||||
STR r1, [r0] //
|
||||
|
||||
/* Enable interrupts */
|
||||
|
||||
CPSIE i
|
||||
|
||||
/* Enter the scheduler for the first time. */
|
||||
|
||||
LDR r0, =0x10000000 // Load PENDSVSET bit
|
||||
LDR r1, =0xE000ED04 // Load ICSR address
|
||||
STR r0, [r1] // Set PENDSVBIT in ICSR
|
||||
DSB // Complete all memory accesses
|
||||
ISB // Flush pipeline
|
||||
|
||||
/* Wait here for the PendSV to take place. */
|
||||
|
||||
__tx_wait_here:
|
||||
B __tx_wait_here // Wait for the PendSV to happen
|
||||
// }
|
||||
|
||||
|
||||
/* Memory Exception Handler. */
|
||||
|
||||
.global MemManage_Handler
|
||||
.global BusFault_Handler
|
||||
.thumb_func
|
||||
MemManage_Handler:
|
||||
.thumb_func
|
||||
BusFault_Handler:
|
||||
|
||||
CPSID i // Disable interrupts
|
||||
|
||||
/* Now pickup and store all the fault related information. */
|
||||
|
||||
LDR r2,=_txm_module_manager_memory_fault_info // Pickup fault info struct
|
||||
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r1, [r0] // Pickup the current thread pointer
|
||||
STR r1, [r2, #0] // Save current thread pointer in fault info structure
|
||||
LDR r0, =0xE000ED24 // Build SHCSR address
|
||||
LDR r1, [r0] // Pickup SHCSR
|
||||
STR r1, [r2, #8] // Save SHCSR
|
||||
LDR r0, =0xE000ED28 // Build CFSR address
|
||||
LDR r1, [r0] // Pickup CFSR
|
||||
STR r1, [r2, #12] // Save CFSR
|
||||
LDR r0, =0xE000ED34 // Build MMFAR address
|
||||
LDR r1, [r0] // Pickup MMFAR
|
||||
STR r1, [r2, #16] // Save MMFAR
|
||||
LDR r0, =0xE000ED38 // Build BFAR address
|
||||
LDR r1, [r0] // Pickup BFAR
|
||||
STR r1, [r2, #20] // Save BFAR
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
STR r0, [r2, #24] // Save CONTROL
|
||||
MRS r1, PSP // Pickup thread stack pointer
|
||||
STR r1, [r2, #28] // Save thread stack pointer
|
||||
LDR r0, [r1] // Pickup saved r0
|
||||
STR r0, [r2, #32] // Save r0
|
||||
LDR r0, [r1, #4] // Pickup saved r1
|
||||
STR r0, [r2, #36] // Save r1
|
||||
LDR r0, [r1, #8] // Pickup saved r2
|
||||
STR r0, [r2, #40] // Save r2
|
||||
STR r3, [r2, #44] // Save r3
|
||||
STR r4, [r2, #48] // Save r4
|
||||
STR r5, [r2, #52] // Save r5
|
||||
STR r6, [r2, #56] // Save r6
|
||||
STR r7, [r2, #60] // Save r7
|
||||
MOV r0, r8 // Move r8 to moveable register
|
||||
STR r0, [r2, #64] // Save r8
|
||||
MOV r0, r9 // Move r9 to moveable register
|
||||
STR r0, [r2, #68] // Save r9
|
||||
MOV r0, r10 // Move r10 to moveable register
|
||||
STR r0, [r2, #72] // Save r10
|
||||
MOV r0, r11 // Move r11 to moveable register
|
||||
STR r0, [r2, #76] // Save r11
|
||||
LDR r0, [r1, #16] // Pickup saved r12
|
||||
STR r0, [r2, #80] // Save r12
|
||||
LDR r0, [r1, #20] // Pickup saved lr
|
||||
STR r0, [r2, #84] // Save lr
|
||||
LDR r0, [r1, #24] // Pickup instruction address at point of fault
|
||||
STR r0, [r2, #4] // Save point of fault
|
||||
LDR r0, [r1, #28] // Pickup xPSR
|
||||
STR r0, [r2, #88] // Save xPSR
|
||||
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
MOVW r1, #0x1 //
|
||||
BICS r0, r0, r1 // Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
|
||||
LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR)
|
||||
LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions:
|
||||
// Bit 0 = 1 -> Instruction address violation
|
||||
// Bit 1 = 1 -> Load/store address violation
|
||||
// Bit 7 = 1 -> MMFAR is valid
|
||||
STRB r1, [r0] // Clear the MMFSR
|
||||
|
||||
BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
CPSID i // Disable interrupts
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
CPSIE i // Enable interrupts
|
||||
#endif
|
||||
|
||||
MOVW r1, #0 // Build NULL value
|
||||
LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer
|
||||
STR r1, [r0] // Clear current thread pointer
|
||||
|
||||
// Return from MemManage_Handler exception
|
||||
LDR r0, =0xE000ED04 // Load ICSR
|
||||
LDR r1, =0x10000000 // Set PENDSVSET bit
|
||||
STR r1, [r0] // Store ICSR
|
||||
DSB // Wait for memory access to complete
|
||||
CPSIE i // Enable interrupts
|
||||
#ifdef TX_SINGLE_MODE_SECURE
|
||||
LDR r0, =0xFFFFFFFD // Exception return to secure
|
||||
#else
|
||||
LDR r0, =0xFFFFFFBC // Exception return to non-secure
|
||||
#endif
|
||||
MOV lr, r0 // Move exception return to lr
|
||||
BX lr // Return from exception
|
||||
|
||||
|
||||
/* Generic context switching PendSV handler. */
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global PendSV_Handler
|
||||
.thumb_func
|
||||
.type PendSV_Handler, function
|
||||
/* Get current thread value and new thread pointer. */
|
||||
PendSV_Handler:
|
||||
__tx_ts_handler:
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
CPSID i // Disable interrupts
|
||||
PUSH {r0, lr} // Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
POP {r0, r1} // Recover LR
|
||||
MOV lr, r1
|
||||
CPSIE i // Enable interrupts
|
||||
#endif
|
||||
|
||||
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
|
||||
|
||||
MOVW r3, #0 // Build NULL value
|
||||
LDR r1, [r0] // Pickup current thread pointer
|
||||
|
||||
/* Determine if there is a current thread to finish preserving. */
|
||||
|
||||
CBZ r1, __tx_ts_new // If NULL, skip preservation
|
||||
|
||||
/* Recover PSP and preserve current thread context. */
|
||||
|
||||
STR r3, [r0] // Set _tx_thread_current_ptr to NULL
|
||||
MRS r3, PSP // Pickup PSP pointer (thread's stack pointer)
|
||||
SUBS r3, r3, #16 // Allocate stack space
|
||||
STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
|
||||
MOV r4, r8 //
|
||||
MOV r5, r9 //
|
||||
MOV r6, r10 //
|
||||
MOV r7, r11 //
|
||||
SUBS r3, r3, #32 // Allocate stack space
|
||||
STM r3!, {r4-r7} //
|
||||
SUBS r3, r3, #20 // Allocate stack space
|
||||
MOV r5, lr //
|
||||
STR r5, [r3] // Save LR on the stack
|
||||
STR r3, [r1, #8] // Save the thread stack pointer
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
// Save secure context
|
||||
LDR r5, =0xC4 // Secure stack index offset
|
||||
LDR r5, [r1, r5] // Load secure stack index
|
||||
CBZ r5, _skip_secure_save // Skip save if there is no secure context
|
||||
PUSH {r0-r3} // Save scratch registers
|
||||
MOV r0, r1 // Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_save // Save secure stack
|
||||
POP {r0-r3} // Restore secure registers
|
||||
_skip_secure_save:
|
||||
#endif
|
||||
|
||||
/* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
|
||||
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
|
||||
LDR r5, [r4] // Pickup current time-slice
|
||||
CBZ r5, __tx_ts_new // If not active, skip processing
|
||||
|
||||
/* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
|
||||
STR r5, [r1, #24] // Save current time-slice
|
||||
|
||||
/* Clear the global time-slice. */
|
||||
|
||||
MOVW r5, #0 // Build clear value
|
||||
STR r5, [r4] // Clear time-slice
|
||||
|
||||
/* Executing thread is now completely preserved!!! */
|
||||
|
||||
__tx_ts_new:
|
||||
|
||||
/* Now we are looking for a new thread to execute! */
|
||||
|
||||
CPSID i // Disable interrupts
|
||||
LDR r1, [r2] // Is there another thread ready to execute?
|
||||
CBNZ r1, __tx_ts_restore // Yes, schedule it
|
||||
|
||||
/* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
|
||||
__tx_ts_wait:
|
||||
CPSID i // Disable interrupts
|
||||
LDR r1, [r2] // Pickup the next thread to execute pointer
|
||||
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
|
||||
#ifdef TX_ENABLE_WFI
|
||||
DSB // Ensure no outstanding memory transactions
|
||||
WFI // Wait for interrupt
|
||||
ISB // Ensure pipeline is flushed
|
||||
#endif
|
||||
CPSIE i // Enable interrupts
|
||||
B __tx_ts_wait // Loop to continue waiting
|
||||
|
||||
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
already in the handler! */
|
||||
|
||||
__tx_ts_ready:
|
||||
LDR r7, =0x08000000 // Build clear PendSV value
|
||||
LDR r5, =0xE000ED04 // Build base NVIC address
|
||||
STR r7, [r5] // Clear any PendSV
|
||||
|
||||
__tx_ts_restore:
|
||||
|
||||
/* A thread is ready, make the current thread the new thread
|
||||
and enable interrupts. */
|
||||
|
||||
STR r1, [r0] // Setup the current thread pointer to the new thread
|
||||
CPSIE i // Enable interrupts
|
||||
|
||||
/* Increment the thread run count. */
|
||||
|
||||
LDR r7, [r1, #4] // Pickup the current thread run count
|
||||
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
|
||||
LDR r5, [r1, #24] // Pickup thread's current time-slice
|
||||
ADDS r7, r7, #1 // Increment the thread run count
|
||||
STR r7, [r1, #4] // Store the new run count
|
||||
|
||||
/* Setup global time-slice with thread's current time-slice. */
|
||||
|
||||
STR r5, [r4] // Setup global time-slice
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Call the thread entry function to indicate the thread is executing. */
|
||||
PUSH {r0, r1} // Save r0 and r1
|
||||
BL _tx_execution_thread_enter // Call the thread execution enter function
|
||||
POP {r0, r1} // Recover r0 and r1
|
||||
#endif
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
// Restore secure context
|
||||
LDR r5, =0xC4 // Secure stack index offset
|
||||
LDR r0, [r1, r5] // Load secure stack index
|
||||
CBZ r0, _skip_secure_restore // Skip restore if there is no secure context
|
||||
PUSH {r0, r1} // Save r1 (and dummy r0)
|
||||
MOV r0, r1 // Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_restore // Restore secure stack
|
||||
POP {r0, r1} // Restore r1 (and dummy r0)
|
||||
_skip_secure_restore:
|
||||
#endif
|
||||
|
||||
// Set up CONTROL register based on user mode flag (privileged/unprivileged mode)
|
||||
MRS r5, CONTROL // Pickup current CONTROL register
|
||||
MOVS r2, #0x98 // Index of current user mode flag
|
||||
LDR r4, [r1, r2] // Pickup current user mode flag
|
||||
MOVW r0, #0x1
|
||||
BICS r5, r5, r0 // Clear the UNPRIV bit
|
||||
ORRS r4, r4, r5 // Build new CONTROL register
|
||||
MSR CONTROL, r4 // Setup new CONTROL register
|
||||
|
||||
// Determine if MPU needs to be configured
|
||||
LDR r0, =0xE000ED94 // Build MPU control reg address
|
||||
MOVW r3, #0 // Build disable value
|
||||
STR r3, [r0] // Disable MPU
|
||||
MOVS r2, #0x90 // Index of module instance pointer
|
||||
LDR r0, [r1, r2] // Pickup the module instance pointer
|
||||
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
|
||||
MOV r8, r1 // Copy thread ptr
|
||||
LDR r1, [r0, #0x64] // Pickup MPU register[0]
|
||||
CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
|
||||
|
||||
// Initialize loop to configure MPU registers
|
||||
MOVS r3, #0x64 // Index of MPU register settings in thread control block
|
||||
ADD r0, r0, r3 // Build address of MPU register start in thread control block
|
||||
MOVS r5, #0 // Select region 0
|
||||
LDR r4, =0xE000ED98 // Region register address
|
||||
// Loop to load MPU registers
|
||||
_tx_mpu_loop:
|
||||
LDR r1, =0xE000ED9C // Build address of MPU base register
|
||||
STR r5, [r4] // Set region
|
||||
LDM r0!, {r2-r3} // Get MPU settings from the module
|
||||
STM r1!, {r2-r3} // Set MPU registers for region
|
||||
ADDS r5, r5, #1 // Increment to next region
|
||||
CMP r5, #8 // Check if all regions have been set
|
||||
BNE _tx_mpu_loop
|
||||
|
||||
LDR r0, =0xE000ED94 // Build MPU control reg address
|
||||
MOVS r1, #5 // Build enable value with background region enabled
|
||||
STR r1, [r0] // Enable MPU
|
||||
MOV r1, r8 // Get copied thread ptr
|
||||
|
||||
skip_mpu_setup:
|
||||
|
||||
// Restore the thread context and PSP
|
||||
LDR r3, [r1, #8] // Pickup thread's stack pointer
|
||||
LDR r5, [r3] // Recover saved LR
|
||||
ADDS r3, r3, #4 // Position past LR
|
||||
MOV lr, r5 // Restore LR
|
||||
LDM r3!, {r4-r7} // Recover thread's registers (r8-r11)
|
||||
MOV r11, r7
|
||||
MOV r10, r6
|
||||
MOV r9, r5
|
||||
MOV r8, r4
|
||||
LDM r3!, {r4-r7} // Recover thread's registers (r4-r7)
|
||||
MSR PSP, r3 // Setup the thread's stack pointer
|
||||
|
||||
BX lr // Return to thread!
|
||||
|
||||
|
||||
|
||||
/* SVC Handler. */
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global SVC_Handler
|
||||
.thumb_func
|
||||
.type SVC_Handler, function
|
||||
SVC_Handler:
|
||||
MOV r0, lr
|
||||
MOVS r1, #0x04
|
||||
TST r1, r0 // Determine return stack from EXC_RETURN bit 2
|
||||
BEQ _tx_load_msp
|
||||
MRS r0, PSP // Get PSP
|
||||
B _tx_get_svc
|
||||
_tx_load_msp:
|
||||
MRS r0, MSP // Get MSP
|
||||
_tx_get_svc:
|
||||
LDR r1, [r0,#24] // Load saved PC from stack
|
||||
LDR r3, =-2
|
||||
LDRB r2, [r1,r3] // Load SVC number
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
CMP r2, #1 // Is it a secure stack allocate request?
|
||||
BEQ _tx_svc_secure_alloc // Yes, go there
|
||||
|
||||
CMP r2, #2 // Is it a secure stack free request?
|
||||
BEQ _tx_svc_secure_free // Yes, go there
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
|
||||
|
||||
CMP r2, #3 // Is it the entry into ThreadX?
|
||||
BNE _tx_thread_user_return // No, return to user mode
|
||||
|
||||
/* At this point we have an SVC 3, which means we are entering
|
||||
the kernel from a module thread with user mode selected. */
|
||||
|
||||
LDR r2, =_txm_module_priv // Load address of where we should have come from
|
||||
CMP r1, r2 // Did we come from user_mode_entry?
|
||||
BEQ _tx_entry_continue // If no (not equal), then...
|
||||
BX lr // return from where we came.
|
||||
_tx_entry_continue:
|
||||
LDR r3, [r0, #20] // This is the saved LR
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
MOVS r1, #0 // Build clear value
|
||||
MOVS r0, #0x98 // Index of current user mode
|
||||
STR r1, [r2, r0] // Clear the current user mode selection for thread
|
||||
MOVS r0, #0xA0 // Index of saved LR
|
||||
STR r3, [r2, r0] // Save the original LR in thread control block
|
||||
|
||||
/* If there is memory protection, use kernel stack */
|
||||
MOVS r0, #0x90 // Index of module instance ptr
|
||||
LDR r0, [r2, r0] // Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] // Load the module property flags
|
||||
MOVS r1, #2 // MPU protection flag
|
||||
TST r0, r1 // Check if memory protected
|
||||
BEQ _tx_skip_kernel_stack_enter
|
||||
|
||||
/* Switch to the module thread's kernel stack */
|
||||
MOVS r0, #0xA8 // Index of module kernel stack end
|
||||
LDR r0, [r2, r0] // Load the module kernel stack end
|
||||
MOVS r1, #0xA4 // Index of module kernel stack start
|
||||
LDR r1, [r2, r1] // Load the module kernel stack start
|
||||
MSR PSPLIM, r1 // Set stack limit
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
MOVS r3, #0xAC // Index of module kernel stack size
|
||||
LDR r3, [r2, r3] // Load the module kernel stack size
|
||||
STR r1, [r2, #12] // Set stack start
|
||||
STR r0, [r2, #16] // Set stack end
|
||||
STR r3, [r2, #20] // Set stack size
|
||||
#endif
|
||||
|
||||
MRS r3, PSP // Pickup thread stack pointer
|
||||
MOVS r1, #0xB0 // Index of module stack pointer
|
||||
STR r3, [r2, r1] // Save thread stack pointer
|
||||
|
||||
/* Build kernel stack by copying thread stack two registers at a time */
|
||||
SUBS r0, r0, #32 // Start at top of hardware stack
|
||||
LDMIA r3!, {r1,r2} // Get r0, r1 from thread stack
|
||||
STMIA r0!, {r1,r2} // Insert r0, r1 into kernel stack
|
||||
LDMIA r3!, {r1,r2} // Get r2, r3 from thread stack
|
||||
STMIA r0!, {r1,r2} // Insert r2, r3 into kernel stack
|
||||
LDMIA r3!, {r1,r2} // Get r12, lr from thread stack
|
||||
STMIA r0!, {r1,r2} // Insert r12, lr into kernel stack
|
||||
LDMIA r3!, {r1,r2} // Get pc, xpsr from thread stack
|
||||
STMIA r0!, {r1,r2} // Insert pc, xpsr into kernel stack
|
||||
SUBS r0, r0, #32 // Go back to top of stack
|
||||
|
||||
MSR PSP, r0 // Set kernel stack pointer
|
||||
|
||||
_tx_skip_kernel_stack_enter:
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
MOVW r1, #0x1 //
|
||||
BICS r0, r0, r1 // Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
BX lr // Return to thread
|
||||
|
||||
|
||||
_tx_thread_user_return:
|
||||
LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from
|
||||
CMP r1, r2 // Did we come from user_mode_exit?
|
||||
BEQ _tx_exit_continue // If no (not equal), then...
|
||||
BX lr // return from where we came.
|
||||
_tx_exit_continue:
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
MOVS r1, #0x9C // Index of user mode
|
||||
MOVS r3, #0x98 // Index of current user mode
|
||||
LDR r1, [r2, r1] // Pick up user mode
|
||||
STR r1, [r2, r3] // Set the current user mode selection for thread
|
||||
|
||||
/* If there is memory protection, use kernel stack */
|
||||
MOVS r0, #0x90 // Index of module instance ptr
|
||||
LDR r0, [r2, r0] // Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] // Load the module property flags
|
||||
MOVS r1, #2 // MPU protection flag
|
||||
TST r0, r1 // Check if memory protected
|
||||
BEQ _tx_skip_kernel_stack_exit
|
||||
|
||||
MOVS r0, #0xB4 // Index of module thread stack start
|
||||
LDR r0, [r2, r0] // Load the module thread stack start
|
||||
MSR PSPLIM, r0 // Set stack limit
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
MOVS r1, #0xB8 // Index of module thread stack end
|
||||
LDR r1, [r2, r1] // Load the module thread stack end
|
||||
MOVS r3, #0xBC // Index of module thread stack size
|
||||
LDR r3, [r2, r3] // Load the module thread stack size
|
||||
STR r0, [r2, #12] // Set stack start
|
||||
STR r1, [r2, #16] // Set stack end
|
||||
STR r3, [r2, #20] // Set stack size
|
||||
#endif
|
||||
MOVS r1, #0xB0 // Index of module thread stack pointer
|
||||
LDR r0, [r2, r1] // Load the module thread stack pointer
|
||||
MRS r3, PSP // Pickup kernel stack pointer
|
||||
|
||||
/* Copy kernel hardware stack to module thread stack. */
|
||||
LDM r3!,{r1-r2} // Get r0, r1 from kernel stack
|
||||
STM r0!,{r1-r2} // Insert r0, r1 into thread stack
|
||||
LDM r3!,{r1-r2} // Get r2, r3 from kernel stack
|
||||
STM r0!,{r1-r2} // Insert r2, r3 into thread stack
|
||||
LDM r3!,{r1-r2} // Get r12, lr from kernel stack
|
||||
STM r0!,{r1-r2} // Insert r12, lr into thread stack
|
||||
LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack
|
||||
STM r0!,{r1-r2} // Insert pc, xpsr into thread stack
|
||||
SUBS r0, r0, #32 // Subtract 32 to get back to top of stack
|
||||
MSR PSP, r0 // Set thread stack pointer
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
MOVS r1, #0x9C // Index of user mode
|
||||
LDR r1, [r2, r1] // Pick up user mode
|
||||
|
||||
_tx_skip_kernel_stack_exit:
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
ORRS r0, r0, r1 // OR in the user mode bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
BX lr // Return to thread
|
||||
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
_tx_svc_secure_alloc:
|
||||
LDR r2, =_tx_alloc_return // Load address of where we should have come from
|
||||
CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate?
|
||||
BEQ _tx_alloc_continue // If no (not equal), then...
|
||||
BX lr // return from where we came.
|
||||
_tx_alloc_continue:
|
||||
PUSH {r0, lr} // Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} // Load function parameters from stack
|
||||
BL _tx_thread_secure_mode_stack_allocate
|
||||
POP {r1, r2} // Restore SP and EXC_RETURN
|
||||
STR r0, [r1] // Store function return value
|
||||
MOV lr, r2
|
||||
BX lr
|
||||
|
||||
_tx_svc_secure_free:
|
||||
LDR r2, =_tx_free_return // Load address of where we should have come from
|
||||
CMP r1, r2 // Did we come from _tx_thread_secure_stack_free?
|
||||
BEQ _tx_free_continue // If no (not equal), then...
|
||||
BX lr // return from where we came.
|
||||
_tx_free_continue:
|
||||
PUSH {r0, lr} // Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} // Load function parameters from stack
|
||||
BL _tx_thread_secure_mode_stack_free
|
||||
POP {r1, r2} // Restore SP and EXC_RETURN
|
||||
STR r0, [r1] // Store function return value
|
||||
MOV lr, r2
|
||||
BX lr
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
|
||||
|
||||
|
||||
/* Kernel entry function from user mode. */
|
||||
|
||||
.global _txm_module_manager_kernel_dispatch
|
||||
.align 5
|
||||
.syntax unified
|
||||
// VOID _txm_module_manager_user_mode_entry(VOID)
|
||||
// {
|
||||
.global _txm_module_manager_user_mode_entry
|
||||
.thumb_func
|
||||
_txm_module_manager_user_mode_entry:
|
||||
SVC 3 // Enter kernel
|
||||
_txm_module_priv:
|
||||
/* At this point, we are out of user mode. The original LR has been saved in the
|
||||
thread control block. Simply call the kernel dispatch function. */
|
||||
BL _txm_module_manager_kernel_dispatch
|
||||
|
||||
/* Pickup the original LR value while still in privileged mode */
|
||||
LDR r2, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r3, [r2] // Pickup current thread pointer
|
||||
LDR r2, =0xA0 // Index of saved LR
|
||||
LDR r1, [r3, r2] // Pickup saved LR from original call
|
||||
MOV lr, r1
|
||||
SVC 4 // Exit kernel and return to user mode
|
||||
_txm_module_user_mode_exit:
|
||||
BX lr // Return to the caller
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
// }
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,485 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
#include "tx_api.h"
|
||||
|
||||
/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined,
|
||||
no secure stack functionality is needed. */
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "ARMCM23_TZ.h" /* For intrinsic functions. */
|
||||
#include "tx_secure_interface.h" /* Interface for NS code. */
|
||||
|
||||
/* Minimum size of secure stack. */
|
||||
#ifndef TX_THREAD_SECURE_STACK_MINIMUM
|
||||
#define TX_THREAD_SECURE_STACK_MINIMUM 256
|
||||
#endif
|
||||
/* Maximum size of secure stack. */
|
||||
#ifndef TX_THREAD_SECURE_STACK_MAXIMUM
|
||||
#define TX_THREAD_SECURE_STACK_MAXIMUM 1024
|
||||
#endif
|
||||
|
||||
/* 8 bytes added to stack size to "seal" stack. */
|
||||
#define TX_THREAD_STACK_SEAL_SIZE 8
|
||||
#define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5
|
||||
|
||||
/* Secure stack info struct to hold stack start, stack limit,
|
||||
current stack pointer, and pointer to owning thread.
|
||||
This will be allocated for each thread with a secure stack. */
|
||||
typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
{
|
||||
VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */
|
||||
VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */
|
||||
VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */
|
||||
TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */
|
||||
} TX_THREAD_SECURE_STACK_INFO;
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function initializes secure mode to use PSP stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_CONTROL Intrinsic to get CONTROL */
|
||||
/* __set_CONTROL Intrinsic to set CONTROL */
|
||||
/* __set_PSPLIM Intrinsic to set PSP limit */
|
||||
/* __set_PSP Intrinsic to set PSP */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_initialize(void)
|
||||
{
|
||||
|
||||
/* Set secure mode to use PSP. */
|
||||
__set_CONTROL(__get_CONTROL() | 2);
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
__set_PSPLIM(0);
|
||||
__set_PSP(0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_mode_stack_allocate Cortex-M23/AC6 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function allocates a thread's secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of stack to allocates */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_SIZE_ERROR Invalid stack size */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_IPSR Intrinsic to get IPSR */
|
||||
/* calloc Compiler's calloc function */
|
||||
/* malloc Compiler's malloc function */
|
||||
/* free Compiler's free() function */
|
||||
/* __set_PSPLIM Intrinsic to set PSP limit */
|
||||
/* __set_PSP Intrinsic to set PSP */
|
||||
/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* SVC Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* added stack sealing, */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
{
|
||||
UINT status;
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
UCHAR *stack_mem;
|
||||
ULONG sp;
|
||||
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM)
|
||||
{
|
||||
status = TX_SIZE_ERROR;
|
||||
}
|
||||
|
||||
/* Check if thread already has secure stack allocated. */
|
||||
else if (thread_ptr -> tx_thread_secure_stack_context != 0)
|
||||
{
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Allocate space for secure stack info. */
|
||||
info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO));
|
||||
|
||||
if(info_ptr != TX_NULL)
|
||||
{
|
||||
/* If stack info allocated, allocate a stack & seal. */
|
||||
stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE);
|
||||
|
||||
if(stack_mem != TX_NULL)
|
||||
{
|
||||
/* Secure stack has been allocated, save in the stack info struct. */
|
||||
info_ptr -> tx_thread_secure_stack_limit = stack_mem;
|
||||
info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size;
|
||||
info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start;
|
||||
info_ptr -> tx_thread_ptr = thread_ptr;
|
||||
|
||||
/* Seal bottom of stack. */
|
||||
*(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE;
|
||||
|
||||
/* Save info pointer in thread. */
|
||||
thread_ptr -> tx_thread_secure_stack_context = info_ptr;
|
||||
|
||||
/* Check if this thread is running by looking at PSP_NS and seeing if it is within
|
||||
the stack_start and stack_end range. */
|
||||
sp = __TZ_get_PSP_NS();
|
||||
if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end))
|
||||
{
|
||||
/* If this thread is running, set Secure PSP and PSPLIM. */
|
||||
__set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit));
|
||||
__set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr));
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Stack not allocated, free the info struct. */
|
||||
free(info_ptr);
|
||||
status = TX_NO_MEMORY;
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
status = TX_NO_MEMORY;
|
||||
}
|
||||
}
|
||||
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_mode_stack_free Cortex-M23/AC6 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function frees a thread's secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_IPSR Intrinsic to get IPSR */
|
||||
/* free Compiler's free() function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* SVC Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
|
||||
{
|
||||
UINT status;
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Pickup stack info from thread. */
|
||||
info_ptr = thread_ptr -> tx_thread_secure_stack_context;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
else if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
|
||||
/* Free secure stack. */
|
||||
free(info_ptr -> tx_thread_secure_stack_limit);
|
||||
|
||||
/* Free info struct. */
|
||||
free(info_ptr);
|
||||
|
||||
/* Clear secure context from thread. */
|
||||
thread_ptr -> tx_thread_secure_stack_context = 0;
|
||||
}
|
||||
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_save Cortex-M23/AC6 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function saves context of the secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_IPSR Intrinsic to get IPSR */
|
||||
/* __get_PSP Intrinsic to get PSP */
|
||||
/* __set_PSPLIM Intrinsic to set PSP limit */
|
||||
/* __set_PSP Intrinsic to set PSP */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* PendSV Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr)
|
||||
{
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
ULONG sp;
|
||||
|
||||
/* This function should be called from scheduler only. */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Pickup the secure context pointer. */
|
||||
info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context);
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Check that stack pointer is in range */
|
||||
sp = __get_PSP();
|
||||
if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) ||
|
||||
(sp > (ULONG)info_ptr -> tx_thread_secure_stack_start))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Save stack pointer. */
|
||||
*(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp;
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
__set_PSPLIM(0);
|
||||
__set_PSP(0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_restore Cortex-M23/AC6 */
|
||||
/* 6.1.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function restores context of the secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __get_IPSR Intrinsic to get IPSR */
|
||||
/* __set_PSPLIM Intrinsic to set PSP limit */
|
||||
/* __set_PSP Intrinsic to set PSP */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* PendSV Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr)
|
||||
{
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
|
||||
/* This function should be called from scheduler only. */
|
||||
if (__get_IPSR() == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Pickup the secure context pointer. */
|
||||
info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context);
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set stack pointer and limit. */
|
||||
__set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit);
|
||||
__set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,88 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_allocate Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function enters the SVC handler to allocate a secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of secure stack to */
|
||||
/* allocate */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* SVC 1 */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_secure_stack_allocate
|
||||
.global _tx_alloc_return
|
||||
.thumb_func
|
||||
.type _tx_thread_secure_stack_allocate, function
|
||||
_tx_thread_secure_stack_allocate:
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
MRS r3, PRIMASK // Save interrupt mask
|
||||
CPSIE i // Enable interrupts for SVC call
|
||||
SVC 1
|
||||
_tx_alloc_return:
|
||||
CMP r3, #0 // If interrupts enabled, just return
|
||||
BEQ _alloc_return_interrupt_enabled
|
||||
CPSID i // Otherwise, disable interrupts
|
||||
#else
|
||||
// Executing in single mode - this function is not needed.
|
||||
MOVS r0, #0xFF // Feature not enabled
|
||||
#endif
|
||||
_alloc_return_interrupt_enabled:
|
||||
BX lr
|
||||
.end
|
||||
@@ -0,0 +1,86 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_free Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function enters the SVC handler to free a secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* SVC 2 */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_secure_stack_free
|
||||
.global _tx_free_return
|
||||
.thumb_func
|
||||
.type _tx_thread_secure_stack_free, function
|
||||
_tx_thread_secure_stack_free:
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
MRS r3, PRIMASK // Save interrupt mask
|
||||
CPSIE i // Enable interrupts for SVC call
|
||||
SVC 2
|
||||
_tx_free_return:
|
||||
CMP r3, #0 // If interrupts enabled, just return
|
||||
BEQ _free_return_interrupt_enabled
|
||||
CPSID i // Otherwise, disable interrupts
|
||||
#else
|
||||
// Executing in single mode - this function is not needed.
|
||||
MOVS r0, #0xFF // Feature not enabled
|
||||
#endif
|
||||
_free_return_interrupt_enabled:
|
||||
BX lr
|
||||
.end
|
||||
@@ -0,0 +1,141 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_build Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function builds a stack frame on the supplied thread's stack. */
|
||||
/* The stack frame results in a fake interrupt return to the supplied */
|
||||
/* function pointer. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to thread control blk */
|
||||
/* function_ptr Pointer to return function */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_thread_create Create thread service */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_stack_build
|
||||
.thumb_func
|
||||
.type _tx_thread_stack_build, function
|
||||
_tx_thread_stack_build:
|
||||
/* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
on the Cortex-M23 should look like the following after it is built:
|
||||
|
||||
Stack Top:
|
||||
LR Interrupted LR (LR at time of PENDSV)
|
||||
r8 Initial value for r8
|
||||
r9 Initial value for r9
|
||||
r10 Initial value for r10
|
||||
r11 Initial value for r11
|
||||
r4 Initial value for r4
|
||||
r5 Initial value for r5
|
||||
r6 Initial value for r6
|
||||
r7 Initial value for r7
|
||||
r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
r1 Initial value for r1
|
||||
r2 Initial value for r2
|
||||
r3 Initial value for r3
|
||||
r12 Initial value for r12
|
||||
lr Initial value for lr
|
||||
pc Initial value for pc
|
||||
xPSR Initial value for xPSR
|
||||
|
||||
Stack Bottom: (higher memory address) */
|
||||
|
||||
LDR r2, [r0, #16] // Pickup end of stack area
|
||||
MOVW r3, #0x7 //
|
||||
BICS r2, r2, r3 // Align frame for 8-byte alignment
|
||||
SUBS r2, r2, #68 // Subtract frame size
|
||||
#ifdef TX_SINGLE_MODE_SECURE
|
||||
LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode
|
||||
#else
|
||||
LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP
|
||||
#endif
|
||||
STR r3, [r2, #0] // Save on the stack
|
||||
|
||||
/* Actually build the stack frame. */
|
||||
|
||||
MOVW r3, #0 // Build initial register value
|
||||
STR r3, [r2, #4] // Store initial r8
|
||||
STR r3, [r2, #8] // Store initial r9
|
||||
STR r3, [r2, #12] // Store initial r10
|
||||
STR r3, [r2, #16] // Store initial r11
|
||||
STR r3, [r2, #20] // Store initial r4
|
||||
STR r3, [r2, #24] // Store initial r5
|
||||
STR r3, [r2, #28] // Store initial r6
|
||||
STR r3, [r2, #32] // Store initial r7
|
||||
|
||||
/* Hardware stack follows. */
|
||||
|
||||
STR r3, [r2, #36] // Store initial r0
|
||||
STR r3, [r2, #40] // Store initial r1
|
||||
STR r3, [r2, #44] // Store initial r2
|
||||
STR r3, [r2, #48] // Store initial r3
|
||||
STR r3, [r2, #52] // Store initial r12
|
||||
LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] // Store initial lr
|
||||
STR r1, [r2, #60] // Store initial pc
|
||||
LDR r3, =0x01000000 // Only T-bit need be set
|
||||
STR r3, [r2, #64] // Store initial xPSR
|
||||
|
||||
/* Setup stack pointer. */
|
||||
// thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
|
||||
STR r2, [r0, #8] // Save stack pointer in thread's
|
||||
// control block
|
||||
BX lr // Return to caller
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,93 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/* Define the global function pointer for stack error handling. If a stack error is
|
||||
detected and the application has registered a stack error handler, it will be
|
||||
called via this function pointer. */
|
||||
|
||||
VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_error_handler Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function processes stack errors detected during run-time. */
|
||||
/* */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_terminate */
|
||||
/* _tx_thread_application_stack_error_handler */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* ThreadX internal code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr)
|
||||
{
|
||||
#ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR
|
||||
/* Is there a thread? */
|
||||
if (thread_ptr)
|
||||
{
|
||||
/* Terminate the current thread. */
|
||||
_tx_thread_terminate(_tx_thread_current_ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Determine if the application has registered an error handler. */
|
||||
if (_tx_thread_application_stack_error_handler != TX_NULL)
|
||||
{
|
||||
/* Yes, an error handler is present, simply call the application error handler. */
|
||||
(_tx_thread_application_stack_error_handler)(thread_ptr);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,96 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "tx_trace.h"
|
||||
|
||||
extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_error_notify Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function registers an application stack error handler. If */
|
||||
/* ThreadX detects a stack error, this application handler is called. */
|
||||
/* */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* stack_error_handler Pointer to stack error */
|
||||
/* handler, TX_NULL to disable */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Service return status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr))
|
||||
{
|
||||
|
||||
TX_INTERRUPT_SAVE_AREA
|
||||
|
||||
/* Disable interrupts. */
|
||||
TX_DISABLE
|
||||
|
||||
/* Make entry in event log. */
|
||||
TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS)
|
||||
|
||||
/* Make entry in event log. */
|
||||
TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT
|
||||
|
||||
/* Setup global thread stack error handler. */
|
||||
_tx_thread_application_stack_error_handler = stack_error_handler;
|
||||
|
||||
/* Restore interrupts. */
|
||||
TX_RESTORE
|
||||
|
||||
/* Return success to caller. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,89 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_system_return Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is target processor specific. It is used to transfer */
|
||||
/* control from a thread back to the ThreadX system. Only a */
|
||||
/* minimal context is saved since the compiler assumes temp registers */
|
||||
/* are going to get slicked by a function call anyway. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_schedule Thread scheduling loop */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* ThreadX components */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_system_return(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_system_return
|
||||
.thumb_func
|
||||
.type _tx_thread_system_return, function
|
||||
_tx_thread_system_return:
|
||||
/* Return to real scheduler via PendSV. Note that this routine is often
|
||||
replaced with in-line assembly in tx_port.h to improved performance. */
|
||||
|
||||
LDR r0, =0x10000000 // Load PENDSVSET bit
|
||||
LDR r1, =0xE000ED04 // Load ICSR address
|
||||
STR r0, [r1] // Set PENDSVBIT in ICSR
|
||||
MRS r0, IPSR // Pickup IPSR
|
||||
CMP r0, #0 // Is it a thread returning?
|
||||
BNE _isr_context // If ISR, skip interrupt enable
|
||||
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
|
||||
CPSIE i // Enable interrupts
|
||||
MSR PRIMASK, r1 // Restore original interrupt posture
|
||||
_isr_context:
|
||||
BX lr // Return to caller
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,262 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Timer */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_timer_interrupt Cortex-M23/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function processes the hardware timer interrupt. This */
|
||||
/* processing includes incrementing the system clock and checking for */
|
||||
/* time slice and/or timer expiration. If either is found, the */
|
||||
/* interrupt context save/restore functions are called along with the */
|
||||
/* expiration functions. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_timer_expiration_process Timer expiration processing */
|
||||
/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* interrupt vector */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
/* VOID _tx_timer_interrupt(VOID)
|
||||
{ */
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_timer_interrupt
|
||||
.thumb_func
|
||||
.type _tx_timer_interrupt, function
|
||||
_tx_timer_interrupt:
|
||||
|
||||
/* Upon entry to this routine, it is assumed that the compiler scratch registers are available
|
||||
for use. */
|
||||
|
||||
/* Increment the system clock. */
|
||||
// _tx_timer_system_clock++;
|
||||
|
||||
MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock
|
||||
MOVT r1, #:upper16:_tx_timer_system_clock
|
||||
LDR r0, [r1, #0] // Pickup system clock
|
||||
ADDS r0, r0, #1 // Increment system clock
|
||||
STR r0, [r1, #0] // Store new system clock
|
||||
|
||||
/* Test for time-slice expiration. */
|
||||
// if (_tx_timer_time_slice)
|
||||
// {
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice
|
||||
MOVT r3, #:upper16:_tx_timer_time_slice
|
||||
LDR r2, [r3, #0] // Pickup time-slice
|
||||
CBZ r2, __tx_timer_no_time_slice // Is it non-active?
|
||||
// Yes, skip time-slice processing
|
||||
|
||||
/* Decrement the time_slice. */
|
||||
// _tx_timer_time_slice--;
|
||||
|
||||
SUBS r2, r2, #1 // Decrement the time-slice
|
||||
STR r2, [r3, #0] // Store new time-slice value
|
||||
|
||||
/* Check for expiration. */
|
||||
// if (__tx_timer_time_slice == 0)
|
||||
|
||||
CBNZ r2, __tx_timer_no_time_slice // Has it expired?
|
||||
|
||||
/* Set the time-slice expired flag. */
|
||||
// _tx_timer_expired_time_slice = TX_TRUE;
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag
|
||||
MOVT r3, #:upper16:_tx_timer_expired_time_slice
|
||||
MOVW r0, #1 // Build expired value
|
||||
STR r0, [r3, #0] // Set time-slice expiration flag
|
||||
|
||||
// }
|
||||
|
||||
__tx_timer_no_time_slice:
|
||||
|
||||
/* Test for timer expiration. */
|
||||
// if (*_tx_timer_current_ptr)
|
||||
// {
|
||||
|
||||
MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address
|
||||
MOVT r1, #:upper16:_tx_timer_current_ptr
|
||||
LDR r0, [r1, #0] // Pickup current timer
|
||||
LDR r2, [r0, #0] // Pickup timer list entry
|
||||
CBZ r2, __tx_timer_no_timer // Is there anything in the list?
|
||||
// No, just increment the timer
|
||||
|
||||
/* Set expiration flag. */
|
||||
// _tx_timer_expired = TX_TRUE;
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address
|
||||
MOVT r3, #:upper16:_tx_timer_expired
|
||||
MOVW r2, #1 // Build expired value
|
||||
STR r2, [r3, #0] // Set expired flag
|
||||
B __tx_timer_done // Finished timer processing
|
||||
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
__tx_timer_no_timer:
|
||||
|
||||
/* No timer expired, increment the timer pointer. */
|
||||
// _tx_timer_current_ptr++;
|
||||
|
||||
ADDS r0, r0, #4 // Move to next timer
|
||||
|
||||
/* Check for wrap-around. */
|
||||
// if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end
|
||||
MOVT r3, #:upper16:_tx_timer_list_end
|
||||
LDR r2, [r3, #0] // Pickup list end
|
||||
CMP r0, r2 // Are we at list end?
|
||||
BNE __tx_timer_skip_wrap // No, skip wrap-around logic
|
||||
|
||||
/* Wrap to beginning of list. */
|
||||
// _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start
|
||||
MOVT r3, #:upper16:_tx_timer_list_start
|
||||
LDR r0, [r3, #0] // Set current pointer to list start
|
||||
|
||||
__tx_timer_skip_wrap:
|
||||
|
||||
STR r0, [r1, #0] // Store new current timer pointer
|
||||
// }
|
||||
|
||||
__tx_timer_done:
|
||||
|
||||
|
||||
/* See if anything has expired. */
|
||||
// if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
// {
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag
|
||||
MOVT r3, #:upper16:_tx_timer_expired_time_slice
|
||||
LDR r2, [r3, #0] // Pickup time-slice expired flag
|
||||
CBNZ r2, __tx_something_expired // Did a time-slice expire?
|
||||
// If non-zero, time-slice expired
|
||||
MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag
|
||||
MOVT r1, #:upper16:_tx_timer_expired
|
||||
LDR r0, [r1, #0] // Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_nothing_expired // Did a timer expire?
|
||||
// No, nothing expired
|
||||
|
||||
__tx_something_expired:
|
||||
|
||||
PUSH {r0, lr} // Save the lr register on the stack
|
||||
// and save r0 just to keep 8-byte alignment
|
||||
|
||||
/* Did a timer expire? */
|
||||
// if (_tx_timer_expired)
|
||||
// {
|
||||
|
||||
MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag
|
||||
MOVT r1, #:upper16:_tx_timer_expired
|
||||
LDR r0, [r1, #0] // Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_dont_activate // Check for timer expiration
|
||||
// If not set, skip timer activation
|
||||
|
||||
/* Process timer expiration. */
|
||||
// _tx_timer_expiration_process();
|
||||
|
||||
BL _tx_timer_expiration_process // Call the timer expiration handling routine
|
||||
|
||||
// }
|
||||
__tx_timer_dont_activate:
|
||||
|
||||
/* Did time slice expire? */
|
||||
// if (_tx_timer_expired_time_slice)
|
||||
// {
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired
|
||||
MOVT r3, #:upper16:_tx_timer_expired_time_slice
|
||||
LDR r2, [r3, #0] // Pickup the actual flag
|
||||
CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set
|
||||
// No, skip time-slice processing
|
||||
|
||||
/* Time slice interrupted thread. */
|
||||
// _tx_thread_time_slice();
|
||||
|
||||
BL _tx_thread_time_slice // Call time-slice processing
|
||||
MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
MOVT r0, #:upper16:_tx_thread_preempt_disable
|
||||
|
||||
LDR r1, [r0] // Is the preempt disable flag set?
|
||||
CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic
|
||||
MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address
|
||||
MOVT r0, #:upper16:_tx_thread_current_ptr
|
||||
|
||||
LDR r1, [r0] // Pickup the current thread pointer
|
||||
MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address
|
||||
MOVT r2, #:upper16:_tx_thread_execute_ptr
|
||||
|
||||
LDR r3, [r2] // Pickup the execute thread pointer
|
||||
LDR r0, =0xE000ED04 // Build address of control register
|
||||
LDR r2, =0x10000000 // Build value for PendSV bit
|
||||
CMP r1, r3 // Are they the same?
|
||||
BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed
|
||||
STR r2, [r0] // Not the same, issue the PendSV for preemption
|
||||
__tx_timer_skip_time_slice:
|
||||
// }
|
||||
|
||||
__tx_timer_not_ts_expiration:
|
||||
|
||||
POP {r0, r1} // Recover lr register (r0 is just there for
|
||||
MOV lr, r1 // the 8-byte stack alignment
|
||||
|
||||
// }
|
||||
|
||||
__tx_timer_nothing_expired:
|
||||
|
||||
DSB // Complete all memory access
|
||||
BX lr // Return to caller
|
||||
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,119 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_initialize.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_allocate Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function checks for errors in the secure stack allocate */
|
||||
/* function call. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of secure stack to */
|
||||
/* allocate */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_allocate Actual stack alloc function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
{
|
||||
#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
return(TX_FEATURE_NOT_ENABLED);
|
||||
#else
|
||||
UINT status;
|
||||
|
||||
/* Default status to success. */
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Check for an invalid thread pointer. */
|
||||
if (thread_ptr == TX_NULL)
|
||||
{
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Now check for invalid thread ID. */
|
||||
else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
|
||||
{
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Check for interrupt call. */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0))
|
||||
{
|
||||
/* Is call from an interrupt and not initialization? */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
|
||||
{
|
||||
/* Invalid caller of this function, return appropriate error code. */
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine if everything is okay. */
|
||||
if (status == TX_SUCCESS)
|
||||
{
|
||||
/* Call actual secure stack allocate function. */
|
||||
status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size);
|
||||
}
|
||||
|
||||
/* Return completion status. */
|
||||
return(status);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_initialize.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_free Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function checks for errors in the secure stack free */
|
||||
/* function call. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_free Actual stack free function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)
|
||||
{
|
||||
#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
return(TX_FEATURE_NOT_ENABLED);
|
||||
#else
|
||||
UINT status;
|
||||
|
||||
/* Default status to success. */
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Check for an invalid thread pointer. */
|
||||
if (thread_ptr == TX_NULL)
|
||||
{
|
||||
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Now check for invalid thread ID. */
|
||||
else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
|
||||
{
|
||||
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Check for interrupt call. */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0))
|
||||
{
|
||||
/* Is call from an interrupt and not initialization? */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
|
||||
{
|
||||
/* Invalid caller of this function, return appropriate error code. */
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine if everything is okay. */
|
||||
if (status == TX_SUCCESS)
|
||||
{
|
||||
|
||||
/* Call actual secure stack allocate function. */
|
||||
status = _tx_thread_secure_stack_free(thread_ptr);
|
||||
}
|
||||
|
||||
/* Return completion status. */
|
||||
return(status);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_alignment_adjust Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function adjusts the alignment and size of the code and data */
|
||||
/* section for a given module implementation. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_preamble Pointer to module preamble */
|
||||
/* code_size Size of the code area (updated) */
|
||||
/* code_alignment Code area alignment (updated) */
|
||||
/* data_size Size of data area (updated) */
|
||||
/* data_alignment Data area alignment (updated) */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Initial thread stack frame */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
|
||||
ULONG *code_size,
|
||||
ULONG *code_alignment,
|
||||
ULONG *data_size,
|
||||
ULONG *data_alignment)
|
||||
{
|
||||
|
||||
/* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */
|
||||
*code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1);
|
||||
*data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1);
|
||||
|
||||
/* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */
|
||||
*code_alignment = TXM_MODULE_MPU_ALIGNMENT;
|
||||
*data_alignment = TXM_MODULE_MPU_ALIGNMENT;
|
||||
}
|
||||
@@ -0,0 +1,164 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_mutex.h"
|
||||
#include "tx_queue.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_external_memory_enable Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function creates an entry in the MPU table for a shared */
|
||||
/* memory space. The start_address must be 32-byte aligned. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Module instance pointer */
|
||||
/* start_address Start address of memory */
|
||||
/* length Length of external memory */
|
||||
/* attributes Memory attributes (r/w) */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_mutex_get Get protection mutex */
|
||||
/* _tx_mutex_put Release protection mutex */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
|
||||
VOID *start_address,
|
||||
ULONG length,
|
||||
UINT attributes)
|
||||
{
|
||||
|
||||
ULONG address;
|
||||
ULONG shared_index;
|
||||
|
||||
/* Determine if the module manager has not been initialized yet. */
|
||||
if (_txm_module_manager_ready != TX_TRUE)
|
||||
{
|
||||
/* Module manager has not been initialized. */
|
||||
return(TX_NOT_AVAILABLE);
|
||||
}
|
||||
|
||||
/* Determine if the module is valid. */
|
||||
if (module_instance == TX_NULL)
|
||||
{
|
||||
/* Invalid module pointer. */
|
||||
return(TX_PTR_ERROR);
|
||||
}
|
||||
|
||||
/* Get module manager protection mutex. */
|
||||
_tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
|
||||
|
||||
/* Determine if the module instance is valid. */
|
||||
if (module_instance -> txm_module_instance_id != TXM_MODULE_ID)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Invalid module pointer. */
|
||||
return(TX_PTR_ERROR);
|
||||
}
|
||||
|
||||
/* Determine if the module instance is in the loaded state. */
|
||||
if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return error if the module is not ready. */
|
||||
return(TX_START_ERROR);
|
||||
}
|
||||
|
||||
/* Determine if there are shared memory entries available. */
|
||||
if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* No more entries available. */
|
||||
return(TX_NO_MEMORY);
|
||||
}
|
||||
|
||||
/* Start address must adhere to Cortex-M23 MPU alignment. */
|
||||
address = (ULONG) start_address;
|
||||
if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1)))
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return alignment error. */
|
||||
return(TXM_MODULE_ALIGNMENT_ERROR);
|
||||
}
|
||||
|
||||
/* At this point, we have a valid address. Set up MPU registers. */
|
||||
|
||||
/* Pick up index into shared memory entries. */
|
||||
shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count;
|
||||
|
||||
/* Set base address register with start address, sanitized attributes and execute never. */
|
||||
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER;
|
||||
|
||||
/* Set the limit address (data start + length-1), attribute index, and enable bit. */
|
||||
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
|
||||
|
||||
/* Keep track of shared memory address and length in module instance. */
|
||||
module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address;
|
||||
module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length;
|
||||
|
||||
/* Increment counter. */
|
||||
module_instance -> txm_module_instance_shared_memory_count++;
|
||||
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return success. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,110 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define the user's fault notification callback function pointer. This is
|
||||
setup via the txm_module_manager_memory_fault_notify API. */
|
||||
|
||||
VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
|
||||
|
||||
|
||||
/* Define a macro that can be used to allocate global variables useful to
|
||||
store information about the last fault. This macro is defined in
|
||||
txm_module_port.h and is usually populated in the assembly language
|
||||
fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */
|
||||
|
||||
TXM_MODULE_MANAGER_FAULT_INFO
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_memory_fault_handler Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function handles a fault associated with a memory protected */
|
||||
/* module. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_terminate Terminate thread */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Fault handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_memory_fault_handler(VOID)
|
||||
{
|
||||
|
||||
TXM_MODULE_INSTANCE *module_instance_ptr;
|
||||
TX_THREAD *thread_ptr;
|
||||
|
||||
/* Pickup the current thread. */
|
||||
thread_ptr = _tx_thread_current_ptr;
|
||||
|
||||
/* Initialize the module instance pointer to NULL. */
|
||||
module_instance_ptr = TX_NULL;
|
||||
|
||||
/* Is there a thread? */
|
||||
if (thread_ptr)
|
||||
{
|
||||
/* Pickup the module instance. */
|
||||
module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr;
|
||||
|
||||
/* Terminate the current thread. */
|
||||
_tx_thread_terminate(_tx_thread_current_ptr);
|
||||
}
|
||||
|
||||
/* Determine if there is a user memory fault notification callback. */
|
||||
if (_txm_module_manager_fault_notify)
|
||||
{
|
||||
/* Yes, call the user's notification memory fault callback. */
|
||||
(_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define the external user's fault notification callback function pointer. This is
|
||||
setup via the txm_module_manager_memory_fault_notify API. */
|
||||
|
||||
extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_memory_fault_notify Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function registers an application callback when/if a memory */
|
||||
/* fault occurs. The supplied thread is automatically terminated, but */
|
||||
/* any other threads in the same module may still execute. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* notify_function Memory fault notification */
|
||||
/* function, NULL disables. */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))
|
||||
{
|
||||
/* Setup notification function. */
|
||||
_txm_module_manager_fault_notify = notify_function;
|
||||
|
||||
/* Return success. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,196 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_mm_register_setup Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function sets up the Cortex-M23 MPU register definitions based */
|
||||
/* on the module's memory characteristics. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Pointer to module instance */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* MPU settings for the module in module_instance */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* none */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_manager_thread_create */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
|
||||
{
|
||||
|
||||
ULONG data_size;
|
||||
ULONG start_stop_stack_size;
|
||||
ULONG callback_stack_size;
|
||||
|
||||
/* Setup MPU region for kernel mode entry. */
|
||||
/* Set base address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned.
|
||||
Mask address to proper range, inner shareable, read only. */
|
||||
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_base_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY;
|
||||
/* Set the limit address, attribute index, and enable bit. */
|
||||
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_limit_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
|
||||
/* End of kernel mode entry setup. */
|
||||
|
||||
|
||||
/* Setup MPU region for module code protection. */
|
||||
/* Set base address register to module code address, which should be at least 32-byte aligned.
|
||||
Mask address to proper range, inner shareable, read only. */
|
||||
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_code_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY;
|
||||
/* Set the limit address (code start + code size-1), attribute index, and enable bit. */
|
||||
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_code_start + module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
|
||||
/* End of module code protection. */
|
||||
|
||||
|
||||
/* Setup MPU region for module data protection. */
|
||||
/* Set base address register to module data address, which should be at least 32-byte aligned.
|
||||
Mask address to proper range, inner shareable, read write, execute never. */
|
||||
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER;
|
||||
|
||||
/* Adjust the size of the module elements to be aligned to the default alignment. We do this
|
||||
so that when we partition the allocated memory, we can simply place these regions right beside
|
||||
each other without having to align their pointers. Note this only works when they all have
|
||||
the same alignment. */
|
||||
|
||||
data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size;
|
||||
start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size;
|
||||
callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size;
|
||||
|
||||
data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
|
||||
start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
|
||||
callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
|
||||
|
||||
/* Update the data size to include thread stacks. */
|
||||
data_size = data_size + start_stop_stack_size + callback_stack_size;
|
||||
|
||||
/* Set the limit address (data start + data size-1), attribute index, and enable bit. */
|
||||
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
|
||||
/* End of module data protection. */
|
||||
|
||||
/* Remaining MPU entries are disabled for now and can be used for shared memory. */
|
||||
}
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_inside_data_check Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function checks if the specified object is inside shared */
|
||||
/* memory. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Pointer to module instance */
|
||||
/* obj_ptr Pointer to the object */
|
||||
/* obj_size Size of the object */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* Whether the object is inside the shared memory region. */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Module dispatch check functions */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size)
|
||||
{
|
||||
|
||||
UINT shared_memory_index;
|
||||
UINT num_shared_memory_mpu_entries;
|
||||
ALIGN_TYPE shared_memory_address_start;
|
||||
ALIGN_TYPE shared_memory_address_end;
|
||||
|
||||
/* Check for overflow. */
|
||||
if ((obj_ptr) > ((obj_ptr) + (obj_size)))
|
||||
{
|
||||
return(TX_FALSE);
|
||||
}
|
||||
|
||||
/* Check if the object is inside the module data. */
|
||||
if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) &&
|
||||
((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1)))
|
||||
{
|
||||
return(TX_TRUE);
|
||||
}
|
||||
|
||||
/* Check if the object is inside the shared memory. */
|
||||
num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count;
|
||||
for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++)
|
||||
{
|
||||
|
||||
shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index];
|
||||
shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index];
|
||||
|
||||
if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) &&
|
||||
((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end))
|
||||
{
|
||||
return(TX_TRUE);
|
||||
}
|
||||
}
|
||||
|
||||
return(TX_FALSE);
|
||||
}
|
||||
@@ -0,0 +1,115 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
#include "txm_module_manager_util.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_port_dispatch Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function dispatches the module's kernel request based upon the */
|
||||
/* ID and parameters specified in the request. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Module pointer */
|
||||
/* kernel_request Module's kernel request */
|
||||
/* param_0 First parameter */
|
||||
/* param_1 Second parameter */
|
||||
/* param_2 Third parameter */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* Port-specific ThreadX API Calls */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_manager_kernel_dispatch */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)
|
||||
{
|
||||
|
||||
ALIGN_TYPE return_value = TX_NOT_AVAILABLE;
|
||||
|
||||
switch(kernel_request)
|
||||
{
|
||||
case TXM_THREAD_SECURE_STACK_ALLOCATE_CALL:
|
||||
{
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
|
||||
{
|
||||
if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
|
||||
return(TXM_MODULE_INVALID_MEMORY);
|
||||
}
|
||||
|
||||
return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate(
|
||||
(TX_THREAD *) param_0,
|
||||
(ULONG) param_1
|
||||
);
|
||||
break;
|
||||
}
|
||||
|
||||
case TXM_THREAD_SECURE_STACK_FREE_CALL:
|
||||
{
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
|
||||
{
|
||||
if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
|
||||
return(TXM_MODULE_INVALID_MEMORY);
|
||||
}
|
||||
|
||||
return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free(
|
||||
(TX_THREAD *) param_0
|
||||
);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
/* Unhandled kernel request, return an error! */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return(return_value);
|
||||
}
|
||||
@@ -0,0 +1,144 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_thread_stack_build Cortex-M23/AC6 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function builds a stack frame on the supplied thread's stack. */
|
||||
/* The stack frame results in a fake interrupt return to the supplied */
|
||||
/* function pointer. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to thread */
|
||||
/* function_ptr Pointer to shell function */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_thread_create Create thread service */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
|
||||
// {
|
||||
.global _txm_module_manager_thread_stack_build
|
||||
.thumb_func
|
||||
_txm_module_manager_thread_stack_build:
|
||||
|
||||
/* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
on the Cortex-M should look like the following after it is built:
|
||||
|
||||
Stack Top:
|
||||
LR Interrupted LR (LR at time of PENDSV)
|
||||
r8 Initial value for r8
|
||||
r9 Initial value for r9
|
||||
r10 Initial value for r10
|
||||
r11 Initial value for r11
|
||||
r4 Initial value for r4
|
||||
r5 Initial value for r5
|
||||
r6 Initial value for r6
|
||||
r7 Initial value for r7
|
||||
r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
r1 Initial value for r1
|
||||
r2 Initial value for r2
|
||||
r3 Initial value for r3
|
||||
r12 Initial value for r12
|
||||
lr Initial value for lr
|
||||
pc Initial value for pc
|
||||
xPSR Initial value for xPSR
|
||||
|
||||
Stack Bottom: (higher memory address) */
|
||||
|
||||
LDR r2, [r0, #16] // Pickup end of stack area
|
||||
MOVW r3, #0x7 //
|
||||
BICS r2, r2, r3 // Align frame for 8-byte alignment
|
||||
SUBS r2, r2, #68 // Subtract frame size
|
||||
#ifdef TX_SINGLE_MODE_SECURE
|
||||
LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode
|
||||
#else
|
||||
LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP
|
||||
#endif
|
||||
STR r3, [r2, #0] // Save on the stack
|
||||
|
||||
/* Actually build the stack frame. */
|
||||
|
||||
MOVW r3, #0 // Build initial register value
|
||||
STR r3, [r2, #4] // Store initial r8
|
||||
STR r3, [r2, #12] // Store initial r10
|
||||
STR r3, [r2, #16] // Store initial r11
|
||||
STR r3, [r2, #20] // Store initial r4
|
||||
STR r3, [r2, #24] // Store initial r5
|
||||
STR r3, [r2, #28] // Store initial r6
|
||||
STR r3, [r2, #32] // Store initial r7
|
||||
|
||||
/* Hardware stack follows. */
|
||||
|
||||
STR r0, [r2, #36] // Store initial r0, which is the thread control block
|
||||
|
||||
LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
|
||||
// It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
|
||||
// function with the actual, initial stack pointer.
|
||||
STR r3, [r2, #40] // Store initial r1, which is the module entry information.
|
||||
LDR r3, [r3, #8] // Pickup data base register from the module information
|
||||
STR r3, [r2, #8] // Store initial r9 (data base register)
|
||||
MOVW r3, #0 // Clear r3 again
|
||||
|
||||
STR r3, [r2, #44] // Store initial r2
|
||||
STR r3, [r2, #48] // Store initial r3
|
||||
STR r3, [r2, #52] // Store initial r12
|
||||
LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] // Store initial lr
|
||||
STR r1, [r2, #60] // Store initial pc
|
||||
LDR r3, =0x01000000 // Only T-bit need be set
|
||||
STR r3, [r2, #64] // Store initial xPSR
|
||||
|
||||
/* Setup stack pointer. */
|
||||
// thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
|
||||
STR r2, [r0, #8] // Save stack pointer in thread's control block
|
||||
BX lr // Return to caller
|
||||
// }
|
||||
249
ports_module/cortex_m23/gnu/example_build/build_threadx.bat
Normal file
249
ports_module/cortex_m23/gnu/example_build/build_threadx.bat
Normal file
@@ -0,0 +1,249 @@
|
||||
del tx.a
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_initialize_low_level.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_context_restore.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_context_save.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_interrupt_control.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_interrupt_disable.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_interrupt_restore.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_schedule.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_secure_stack_allocate.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_secure_stack_free.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_stack_build.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_system_return.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_timer_interrupt.S
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/txm_module_manager_thread_stack_build.S
|
||||
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../module_manager/src/txe_thread_secure_stack_allocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../module_manager/src/txe_thread_secure_stack_free.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../module_manager/src/tx_thread_stack_error_handler.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../module_manager/src/tx_thread_stack_error_notify.c
|
||||
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_alignment_adjust.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_external_memory_enable.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_memory_fault_handler.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_memory_fault_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_mm_register_setup.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/module_manager/inc -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_port_dispatch.c
|
||||
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
|
||||
|
||||
arm-none-eabi-ar -r tx.a txm_module_manager_thread_stack_build.o txm_module_manager_alignment_adjust.o txm_module_manager_external_memory_enable.o
|
||||
arm-none-eabi-ar -r tx.a txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_mm_register_setup.o txm_module_manager_port_dispatch.o
|
||||
|
||||
arm-none-eabi-ar -r tx.a tx_thread_secure_stack_allocate.o txe_thread_secure_stack_allocate.o tx_thread_secure_stack_free.o txe_thread_secure_stack_free.o
|
||||
arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
|
||||
arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_initialize_low_level.o
|
||||
arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
|
||||
arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
|
||||
arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
|
||||
arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
|
||||
arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
|
||||
arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
|
||||
arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
|
||||
arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
|
||||
arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
|
||||
arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o
|
||||
arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
|
||||
arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
|
||||
arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
|
||||
arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
|
||||
arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
|
||||
arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
|
||||
arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
|
||||
arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
|
||||
arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
|
||||
arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
|
||||
arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o
|
||||
arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
|
||||
arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
|
||||
arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o
|
||||
arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o
|
||||
arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o
|
||||
arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
|
||||
arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
|
||||
arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
|
||||
arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
|
||||
arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o
|
||||
arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
|
||||
arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
|
||||
@@ -0,0 +1,104 @@
|
||||
del txm.a
|
||||
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c
|
||||
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_release.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c
|
||||
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c
|
||||
|
||||
arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o txm_time_get.o txm_time_set.o
|
||||
arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o
|
||||
arm-none-eabi-ar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o
|
||||
@@ -0,0 +1,428 @@
|
||||
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
|
||||
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
|
||||
event flags group, byte pool, and block pool. */
|
||||
|
||||
/* Specify that this is a module! */
|
||||
|
||||
#define TXM_MODULE
|
||||
|
||||
|
||||
/* Include the ThreadX module definitions. */
|
||||
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define constants. */
|
||||
|
||||
#define DEMO_STACK_SIZE 512
|
||||
#define DEMO_BYTE_POOL_SIZE 6000
|
||||
#define DEMO_BLOCK_POOL_SIZE 100
|
||||
#define DEMO_QUEUE_SIZE 100
|
||||
|
||||
|
||||
/* Define the pool space in the bss section of the module. ULONG is used to
|
||||
get the word alignment. */
|
||||
|
||||
ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4];
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD *thread_0;
|
||||
TX_THREAD *thread_1;
|
||||
TX_THREAD *thread_2;
|
||||
TX_THREAD *thread_3;
|
||||
TX_THREAD *thread_4;
|
||||
TX_THREAD *thread_5;
|
||||
TX_THREAD *thread_6;
|
||||
TX_THREAD *thread_7;
|
||||
TX_QUEUE *queue_0;
|
||||
TX_SEMAPHORE *semaphore_0;
|
||||
TX_MUTEX *mutex_0;
|
||||
TX_EVENT_FLAGS_GROUP *event_flags_0;
|
||||
TX_BYTE_POOL *byte_pool_0;
|
||||
TX_BLOCK_POOL *block_pool_0;
|
||||
|
||||
|
||||
/* Define the counters used in the demo application... */
|
||||
|
||||
ULONG thread_0_counter;
|
||||
ULONG thread_1_counter;
|
||||
ULONG thread_1_messages_sent;
|
||||
ULONG thread_2_counter;
|
||||
ULONG thread_2_messages_received;
|
||||
ULONG thread_3_counter;
|
||||
ULONG thread_4_counter;
|
||||
ULONG thread_5_counter;
|
||||
ULONG thread_6_counter;
|
||||
ULONG thread_7_counter;
|
||||
ULONG semaphore_0_puts;
|
||||
ULONG event_0_sets;
|
||||
ULONG queue_0_sends;
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input);
|
||||
void thread_1_entry(ULONG thread_input);
|
||||
void thread_2_entry(ULONG thread_input);
|
||||
void thread_3_and_4_entry(ULONG thread_input);
|
||||
void thread_5_entry(ULONG thread_input);
|
||||
void thread_6_and_7_entry(ULONG thread_input);
|
||||
|
||||
void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
|
||||
{
|
||||
|
||||
if (semaphore_ptr == semaphore_0)
|
||||
semaphore_0_puts++;
|
||||
}
|
||||
|
||||
|
||||
void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
|
||||
{
|
||||
|
||||
if (event_flag_group_ptr == event_flags_0)
|
||||
event_0_sets++;
|
||||
}
|
||||
|
||||
|
||||
void queue_0_notify(TX_QUEUE *queue_ptr)
|
||||
{
|
||||
|
||||
if (queue_ptr == queue_0)
|
||||
queue_0_sends++;
|
||||
}
|
||||
|
||||
|
||||
/* Define the module start function. */
|
||||
|
||||
void demo_module_start(ULONG id)
|
||||
{
|
||||
|
||||
CHAR *pointer;
|
||||
|
||||
/* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within
|
||||
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
|
||||
the control block(s). */
|
||||
txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
|
||||
txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
|
||||
txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
|
||||
txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
|
||||
txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
|
||||
txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
|
||||
|
||||
|
||||
/* Create a byte memory pool from which to allocate the thread stacks. */
|
||||
tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
|
||||
|
||||
/* Put system definition stuff in here, e.g. thread creates and other assorted
|
||||
create information. */
|
||||
|
||||
/* Allocate the stack for thread 0. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create the main thread. */
|
||||
tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
|
||||
/* Allocate the stack for thread 1. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 1 and 2. These threads pass information through a ThreadX
|
||||
message queue. It is also interesting to note that these threads have a time
|
||||
slice. */
|
||||
tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 2. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 3. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
|
||||
An interesting thing here is that both threads share the same instruction area. */
|
||||
tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 4. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 5. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create thread 5. This thread simply pends on an event flag which will be set
|
||||
by thread_0. */
|
||||
tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 6. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
|
||||
tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 7. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the message queue. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
|
||||
|
||||
/* Create the message queue shared by threads 1 and 2. */
|
||||
tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
|
||||
|
||||
tx_queue_send_notify(queue_0, queue_0_notify);
|
||||
|
||||
/* Create the semaphore used by threads 3 and 4. */
|
||||
tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
|
||||
|
||||
tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
|
||||
|
||||
/* Create the event flags group used by threads 1 and 5. */
|
||||
tx_event_flags_create(event_flags_0, "module event flags 0");
|
||||
|
||||
tx_event_flags_set_notify(event_flags_0, event_0_notify);
|
||||
|
||||
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
|
||||
tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
|
||||
|
||||
/* Allocate the memory for a small block pool. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create a block memory pool to allocate a message buffer from. */
|
||||
tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
|
||||
|
||||
/* Allocate a block and release the block memory. */
|
||||
tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
|
||||
|
||||
/* Release the block back to the pool. */
|
||||
tx_block_release(pointer);
|
||||
}
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sits in while-forever-sleep loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_0_counter++;
|
||||
|
||||
/* Sleep for 10 ticks. */
|
||||
tx_thread_sleep(10);
|
||||
|
||||
/* Set event flag 0 to wakeup thread 5. */
|
||||
status = tx_event_flags_set(event_flags_0, 0x1, TX_OR);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_1_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sends messages to a queue shared by thread 2. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_1_counter++;
|
||||
|
||||
/* Send message to queue 0. */
|
||||
status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Increment the message sent. */
|
||||
thread_1_messages_sent++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_2_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
ULONG received_message;
|
||||
UINT status;
|
||||
|
||||
/* This thread retrieves messages placed on the queue by thread 1. */
|
||||
while(1)
|
||||
{
|
||||
/* Test memory handler. */
|
||||
*(ULONG *)0x20010000 = 0xCDCDCDCD;
|
||||
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_2_counter++;
|
||||
|
||||
/* Retrieve a message from the queue. */
|
||||
status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status and make sure the message is what we
|
||||
expected. */
|
||||
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
|
||||
break;
|
||||
|
||||
/* Otherwise, all is okay. Increment the received message count. */
|
||||
thread_2_messages_received++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_3_and_4_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 3 and thread 4. As the loop
|
||||
below shows, these function compete for ownership of semaphore_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 3)
|
||||
thread_3_counter++;
|
||||
else
|
||||
thread_4_counter++;
|
||||
|
||||
/* Get the semaphore with suspension. */
|
||||
status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the semaphore. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the semaphore. */
|
||||
status = tx_semaphore_put(semaphore_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_5_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
ULONG actual_flags;
|
||||
|
||||
|
||||
/* This thread simply waits for an event in a forever loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_5_counter++;
|
||||
|
||||
/* Wait for event flag 0. */
|
||||
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
|
||||
&actual_flags, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_6_and_7_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 6 and thread 7. As the loop
|
||||
below shows, these function compete for ownership of mutex_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 6)
|
||||
thread_6_counter++;
|
||||
else
|
||||
thread_7_counter++;
|
||||
|
||||
/* Get the mutex with suspension. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Get the mutex again with suspension. This shows
|
||||
that an owning thread may retrieve the mutex it
|
||||
owns multiple times. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the mutex. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the mutex. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Release the mutex again. This will actually
|
||||
release ownership since it was obtained twice. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
|
||||
/* Define public symbols. */
|
||||
.global __txm_module_preamble
|
||||
|
||||
/* Define application-specific start/stop entry points for the module. */
|
||||
.global demo_module_start
|
||||
|
||||
/* Define common external refrences. */
|
||||
.global _txm_module_thread_shell_entry
|
||||
.global _txm_module_callback_request_thread_entry
|
||||
|
||||
__txm_module_preamble:
|
||||
.dc.l 0x4D4F4455 // Module ID
|
||||
.dc.l 0x6 // Module Major Version
|
||||
.dc.l 0x1 // Module Minor Version
|
||||
.dc.l 32 // Module Preamble Size in 32-bit words
|
||||
.dc.l 0x12345678 // Module ID (application defined)
|
||||
.dc.l 0x02000007 // Module Properties where:
|
||||
// Bits 31-24: Compiler ID
|
||||
// 0 -> IAR
|
||||
// 1 -> ARM
|
||||
// 2 -> GNU
|
||||
// Bits 23-3: Reserved
|
||||
// Bit 2: 0 -> Disable shared/external memory access
|
||||
// 1 -> Enable shared/external memory access
|
||||
// Bit 1: 0 -> No MPU protection
|
||||
// 1 -> MPU protection (must have user mode selected - bit 0 set)
|
||||
// Bit 0: 0 -> Privileged mode execution
|
||||
// 1 -> User mode execution
|
||||
.dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point
|
||||
.dc.l demo_module_start - . - 0 // Module Start Thread Entry Point
|
||||
.dc.l 0 // Module Stop Thread Entry Point
|
||||
.dc.l 1 // Module Start/Stop Thread Priority
|
||||
.dc.l 1024 // Module Start/Stop Thread Stack Size
|
||||
.dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry
|
||||
.dc.l 1 // Module Callback Thread Priority
|
||||
.dc.l 1024 // Module Callback Thread Stack Size
|
||||
.dc.l __code_size__ // Module Code Size
|
||||
.dc.l __data_size__ // Module Data Size
|
||||
.dc.l 0 // Reserved 0
|
||||
.dc.l 0 // Reserved 1
|
||||
.dc.l 0 // Reserved 2
|
||||
.dc.l 0 // Reserved 3
|
||||
.dc.l 0 // Reserved 4
|
||||
.dc.l 0 // Reserved 5
|
||||
.dc.l 0 // Reserved 6
|
||||
.dc.l 0 // Reserved 7
|
||||
.dc.l 0 // Reserved 8
|
||||
.dc.l 0 // Reserved 9
|
||||
.dc.l 0 // Reserved 10
|
||||
.dc.l 0 // Reserved 11
|
||||
.dc.l 0 // Reserved 12
|
||||
.dc.l 0 // Reserved 13
|
||||
.dc.l 0 // Reserved 14
|
||||
.dc.l 0 // Reserved 15
|
||||
485
ports_module/cortex_m23/gnu/inc/tx_port.h
Normal file
485
ports_module/cortex_m23/gnu/inc/tx_port.h
Normal file
@@ -0,0 +1,485 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Port Specific */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* PORT SPECIFIC C INFORMATION RELEASE */
|
||||
/* */
|
||||
/* tx_port.h Cortex-M23/GNU */
|
||||
/* 6.1.6 */
|
||||
/* */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file contains data type definitions that make the ThreadX */
|
||||
/* real-time kernel function identically on a variety of different */
|
||||
/* processor architectures. For example, the size or number of bits */
|
||||
/* in an "int" data type vary between microprocessor architectures and */
|
||||
/* even C compilers for the same microprocessor. ThreadX does not */
|
||||
/* directly use native C data types. Instead, ThreadX creates its */
|
||||
/* own special types that can be mapped to actual data types by this */
|
||||
/* file to guarantee consistency in the interface and functionality. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 04-02-2021 Scott Larson Modified comment(s), */
|
||||
/* remove unneeded headers, */
|
||||
/* use builtins, added */
|
||||
/* ULONG64_DEFINED,updated */
|
||||
/* macro definition, */
|
||||
/* resulting in version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TX_PORT_H
|
||||
#define TX_PORT_H
|
||||
|
||||
/* Determine if the optional ThreadX user define file should be used. */
|
||||
#ifdef TX_INCLUDE_USER_DEFINE_FILE
|
||||
|
||||
/* Yes, include the user defines in tx_user.h. The defines in this file may
|
||||
alternately be defined on the command line. */
|
||||
|
||||
#include "tx_user.h"
|
||||
#endif
|
||||
|
||||
/* Define compiler library include files. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
/* Define ThreadX basic types for this port. */
|
||||
|
||||
#define VOID void
|
||||
typedef char CHAR;
|
||||
typedef unsigned char UCHAR;
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
typedef unsigned long long ULONG64;
|
||||
typedef short SHORT;
|
||||
typedef unsigned short USHORT;
|
||||
#define ULONG64_DEFINED
|
||||
|
||||
/* Function prototypes for this port. */
|
||||
struct TX_THREAD_STRUCT;
|
||||
UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size);
|
||||
UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr);
|
||||
UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size);
|
||||
UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread);
|
||||
|
||||
/* This hardware has stack checking that we take advantage of - do NOT define. */
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#error "Do not define TX_ENABLE_STACK_CHECKING"
|
||||
#endif
|
||||
|
||||
/* If user does not want to terminate thread on stack overflow,
|
||||
#define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol.
|
||||
The thread will be rescheduled and continue to cause the exception.
|
||||
It is suggested user code handle this by registering a notification with the
|
||||
tx_thread_stack_error_notify function. */
|
||||
/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */
|
||||
|
||||
/* Define the system API mappings based on the error checking
|
||||
selected by the user. Note: this section is only applicable to
|
||||
application source code, hence the conditional that turns off this
|
||||
stuff when the include file is processed by the ThreadX source. */
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Determine if error checking is desired. If so, map API functions
|
||||
to the appropriate error checking front-ends. Otherwise, map API
|
||||
functions to the core functions that actually perform the work.
|
||||
Note: error checking is enabled by default. */
|
||||
|
||||
#ifdef TX_DISABLE_ERROR_CHECKING
|
||||
|
||||
/* Services without error checking. */
|
||||
|
||||
#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate
|
||||
#define tx_thread_secure_stack_free _tx_thread_secure_stack_free
|
||||
|
||||
#else
|
||||
|
||||
/* Services with error checking. */
|
||||
|
||||
#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate
|
||||
#define tx_thread_secure_stack_free _txe_thread_secure_stack_free
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Define the priority levels for ThreadX. Legal values range
|
||||
from 32 to 1024 and MUST be evenly divisible by 32. */
|
||||
|
||||
#ifndef TX_MAX_PRIORITIES
|
||||
#define TX_MAX_PRIORITIES 32
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
|
||||
thread creation is less than this value, the thread create call will return an error. */
|
||||
|
||||
#ifndef TX_MINIMUM_STACK
|
||||
#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the system timer thread's default stack size and priority. These are only applicable
|
||||
if TX_TIMER_PROCESS_IN_ISR is not defined. */
|
||||
|
||||
#ifndef TX_TIMER_THREAD_STACK_SIZE
|
||||
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
|
||||
#endif
|
||||
|
||||
#ifndef TX_TIMER_THREAD_PRIORITY
|
||||
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define various constants for the ThreadX Cortex-M23 port. */
|
||||
|
||||
#define TX_INT_DISABLE 1 /* Disable interrupts */
|
||||
#define TX_INT_ENABLE 0 /* Enable interrupts */
|
||||
|
||||
|
||||
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
|
||||
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
|
||||
source constants would be:
|
||||
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
|
||||
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
|
||||
|
||||
*/
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#ifndef TX_TRACE_TIME_SOURCE
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
|
||||
#endif
|
||||
#else
|
||||
ULONG _tx_misra_time_stamp_get(VOID);
|
||||
#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get()
|
||||
#endif
|
||||
|
||||
#ifndef TX_TRACE_TIME_MASK
|
||||
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the port specific options for the _tx_build_options variable. This variable indicates
|
||||
how the ThreadX library was built. */
|
||||
|
||||
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
|
||||
|
||||
|
||||
/* Define the in-line initialization constant so that modules with in-line
|
||||
initialization capabilities can prevent their initialization from being
|
||||
a function call. */
|
||||
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
#define TX_DISABLE_INLINE
|
||||
#else
|
||||
#define TX_INLINE_INITIALIZATION
|
||||
#endif
|
||||
|
||||
|
||||
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
|
||||
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
|
||||
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
|
||||
define is negated, thereby forcing the stack fill which is necessary for the stack checking
|
||||
logic. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#undef TX_DISABLE_STACK_FILLING
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the TX_THREAD control block extensions for this port. The main reason
|
||||
for the multiple macros is so that backward compatibility can be maintained with
|
||||
existing ThreadX kernel awareness modules. */
|
||||
|
||||
#define TX_THREAD_EXTENSION_0
|
||||
#define TX_THREAD_EXTENSION_1
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
ULONG tx_thread_module_saved_lr; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved; \
|
||||
VOID *tx_thread_secure_stack_context;
|
||||
#else
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
ULONG tx_thread_module_saved_lr; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved;
|
||||
#endif
|
||||
#define TX_THREAD_EXTENSION_3
|
||||
|
||||
|
||||
/* Define the port extensions of the remaining ThreadX objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_EXTENSION
|
||||
#define TX_BYTE_POOL_EXTENSION
|
||||
#define TX_MUTEX_EXTENSION
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
|
||||
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
|
||||
|
||||
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
|
||||
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
|
||||
|
||||
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
|
||||
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
|
||||
|
||||
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
|
||||
VOID (*tx_timer_module_expiration_function)(ULONG id);
|
||||
|
||||
|
||||
/* Define the user extension field of the thread control block. Nothing
|
||||
additional is needed for this port so it is defined as white space. */
|
||||
|
||||
#ifndef TX_THREAD_USER_EXTENSION
|
||||
#define TX_THREAD_USER_EXTENSION
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
|
||||
tx_thread_shell_entry, and tx_thread_terminate. */
|
||||
|
||||
|
||||
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);}
|
||||
#else
|
||||
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
|
||||
#endif
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */
|
||||
#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256
|
||||
#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE);
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
inline static unsigned int _get_ipsr(void)
|
||||
{
|
||||
unsigned int _ipsr;
|
||||
__asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
|
||||
return _ipsr;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
|
||||
|
||||
|
||||
/* Define the ThreadX object creation extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the ThreadX object deletion extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the get system state macro. */
|
||||
|
||||
#ifndef TX_THREAD_GET_SYSTEM_STATE
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr())
|
||||
#else
|
||||
ULONG _tx_misra_ipsr_get(VOID);
|
||||
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get())
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value
|
||||
indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
|
||||
for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
|
||||
zero after initialization for Cortex-M ports. */
|
||||
|
||||
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
|
||||
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
|
||||
#endif
|
||||
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
/* Initialize secure stacks for threads calling secure functions. */
|
||||
extern void _tx_thread_secure_stack_initialize(void);
|
||||
#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize();
|
||||
#endif
|
||||
|
||||
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
|
||||
prevent early scheduling on Cortex-M parts. */
|
||||
|
||||
#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++;
|
||||
|
||||
|
||||
/* Determine if the ARM architecture has the CLZ instruction. This is available on
|
||||
architectures v5 and above. If available, redefine the macro for calculating the
|
||||
lowest bit set. */
|
||||
|
||||
#ifndef TX_DISABLE_INLINE
|
||||
|
||||
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __builtin_ctz(m);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Define ThreadX interrupt lockout and restore macros for protection on
|
||||
access of critical kernel information. The restore interrupt macro must
|
||||
restore the interrupt posture of the running thread prior to the value
|
||||
present prior to the disable macro. In most cases, the save area macro
|
||||
is used to define a local function save area for the disable and restore
|
||||
macros. */
|
||||
|
||||
#ifndef TX_DISABLE_INLINE
|
||||
|
||||
/* Define GNU specific macros, with in-line assembly for performance. */
|
||||
|
||||
__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void)
|
||||
{
|
||||
|
||||
unsigned int primask_value;
|
||||
|
||||
__asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) );
|
||||
__asm__ volatile (" CPSID i" : : : "memory" );
|
||||
return(primask_value);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value)
|
||||
{
|
||||
|
||||
__asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" );
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void)
|
||||
{
|
||||
|
||||
unsigned int primask_value;
|
||||
|
||||
__asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) );
|
||||
return(primask_value);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
|
||||
{
|
||||
|
||||
__asm__ volatile (" CPSIE i": : : "memory" );
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void)
|
||||
{
|
||||
unsigned int interrupt_save;
|
||||
|
||||
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
|
||||
if (_get_ipsr() == 0)
|
||||
{
|
||||
interrupt_save = __get_primask_value();
|
||||
__enable_interrupts();
|
||||
__restore_interrupts(interrupt_save);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
|
||||
|
||||
#define TX_DISABLE interrupt_save = __disable_interrupts();
|
||||
#define TX_RESTORE __restore_interrupts(interrupt_save);
|
||||
|
||||
|
||||
/* Redefine _tx_thread_system_return for improved performance. */
|
||||
|
||||
#define _tx_thread_system_return _tx_thread_system_return_inline
|
||||
|
||||
|
||||
#else
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
|
||||
|
||||
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
|
||||
#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save);
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the version ID of ThreadX. This may be utilized by the application. */
|
||||
|
||||
#ifdef TX_THREAD_INIT
|
||||
CHAR _tx_version_id[] =
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.6 *";
|
||||
#else
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
extern CHAR _tx_version_id[100];
|
||||
#else
|
||||
extern CHAR _tx_version_id[];
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
60
ports_module/cortex_m23/gnu/inc/tx_secure_interface.h
Normal file
60
ports_module/cortex_m23/gnu/inc/tx_secure_interface.h
Normal file
@@ -0,0 +1,60 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* COMPONENT DEFINITION RELEASE */
|
||||
/* */
|
||||
/* tx_secure_interface.h Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file defines the ThreadX secure thread stack components, */
|
||||
/* including data types and external references. */
|
||||
/* It is assumed that tx_api.h and tx_port.h have already been */
|
||||
/* included. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TX_SECURE_INTERFACE_H
|
||||
#define TX_SECURE_INTERFACE_H
|
||||
|
||||
/* Define internal secure thread stack function prototypes. */
|
||||
|
||||
extern void _tx_thread_secure_stack_initialize(void);
|
||||
extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size);
|
||||
extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr);
|
||||
extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr);
|
||||
extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr);
|
||||
|
||||
#endif
|
||||
352
ports_module/cortex_m23/gnu/inc/txm_module_port.h
Normal file
352
ports_module/cortex_m23/gnu/inc/txm_module_port.h
Normal file
@@ -0,0 +1,352 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* APPLICATION INTERFACE DEFINITION RELEASE */
|
||||
/* */
|
||||
/* txm_module_port.h Cortex-M23/GNU */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file defines the basic module constants, interface structures, */
|
||||
/* and function prototypes. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TXM_MODULE_PORT_H
|
||||
#define TXM_MODULE_PORT_H
|
||||
|
||||
/* Determine if the optional Modules user define file should be used. */
|
||||
|
||||
#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
|
||||
|
||||
/* Yes, include the user defines in txm_module_user.h. The defines in this file may
|
||||
alternately be defined on the command line. */
|
||||
|
||||
#include "txm_module_user.h"
|
||||
#endif
|
||||
|
||||
/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
|
||||
following extensions to the ThreadX thread control block (this code should replace
|
||||
the corresponding macro define in tx_port.h):
|
||||
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
ULONG tx_thread_module_saved_lr; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved;
|
||||
|
||||
The following extensions must also be defined in tx_port.h:
|
||||
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
|
||||
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
|
||||
|
||||
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
|
||||
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
|
||||
|
||||
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
|
||||
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
|
||||
|
||||
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
|
||||
VOID (*tx_timer_module_expiration_function)(ULONG id);
|
||||
*/
|
||||
|
||||
/* Define the kernel stack size for a module thread. */
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
|
||||
#define TXM_MODULE_KERNEL_STACK_SIZE 768
|
||||
#endif
|
||||
|
||||
/* Define constants specific to the tools the module can be built with for this particular modules port. */
|
||||
|
||||
#define TXM_MODULE_IAR_COMPILER 0x00000000
|
||||
#define TXM_MODULE_RVDS_COMPILER 0x01000000
|
||||
#define TXM_MODULE_GNU_COMPILER 0x02000000
|
||||
#define TXM_MODULE_COMPILER_MASK 0xFF000000
|
||||
#define TXM_MODULE_OPTIONS_MASK 0x000000FF
|
||||
|
||||
|
||||
/* Define the properties for this particular module port. */
|
||||
|
||||
#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
|
||||
#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
|
||||
#else
|
||||
#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
|
||||
#endif
|
||||
|
||||
#define TXM_MODULE_USER_MODE 0x00000001
|
||||
#define TXM_MODULE_MEMORY_PROTECTION 0x00000002
|
||||
#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004
|
||||
|
||||
|
||||
/* Define the supported options for this module. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
|
||||
#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0
|
||||
|
||||
|
||||
/* Define offset adjustments according to the compiler used to build the module. */
|
||||
|
||||
#define TXM_MODULE_IAR_SHELL_ADJUST 24
|
||||
#define TXM_MODULE_IAR_START_ADJUST 28
|
||||
#define TXM_MODULE_IAR_STOP_ADJUST 32
|
||||
#define TXM_MODULE_IAR_CALLBACK_ADJUST 44
|
||||
|
||||
#define TXM_MODULE_RVDS_SHELL_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_START_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_STOP_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0
|
||||
|
||||
#define TXM_MODULE_GNU_SHELL_ADJUST 24
|
||||
#define TXM_MODULE_GNU_START_ADJUST 28
|
||||
#define TXM_MODULE_GNU_STOP_ADJUST 32
|
||||
#define TXM_MODULE_GNU_CALLBACK_ADJUST 44
|
||||
|
||||
|
||||
/* Define other module port-specific constants. */
|
||||
|
||||
/* Define INLINE_DECLARE to inline for ARM compiler. */
|
||||
|
||||
#define INLINE_DECLARE inline
|
||||
|
||||
/* Define the number of MPU entries assigned to the code and data sections.
|
||||
On Cortex-M23 devices, there are 8 total entries. ThreadX uses one for access
|
||||
to the kernel entry function, one for module code protection, one for module data protection,
|
||||
leaving five regions available for shared memory. */
|
||||
#define TXM_MODULE_MPU_TOTAL_ENTRIES 8
|
||||
#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0
|
||||
#define TXM_MODULE_MPU_CODE_INDEX 1
|
||||
#define TXM_MODULE_MPU_DATA_INDEX 2
|
||||
|
||||
#define TXM_MODULE_MPU_SHARED_INDEX 3
|
||||
#define TXM_MODULE_MPU_SHARED_ENTRIES 5
|
||||
|
||||
#define TXM_MODULE_ATTRIBUTE_NON_SHAREABLE 0x00
|
||||
#define TXM_MODULE_ATTRIBUTE_OUTER_SHAREABLE 0x10
|
||||
#define TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE 0x18
|
||||
#define TXM_MODULE_ATTRIBUTE_READ_WRITE 0x02
|
||||
#define TXM_MODULE_ATTRIBUTE_READ_ONLY 0x06
|
||||
#define TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER 0x01
|
||||
#define TXM_MODULE_ATTRIBUTE_REGION_ENABLE 0x01
|
||||
#define TXM_MODULE_ATTRIBUTE_MASK 0x1E
|
||||
#define TXM_MODULE_ATTRIBUTE_INDEX 0x00
|
||||
|
||||
/* MAIR_ATTR settings
|
||||
Device-nGnRE : 0b [Outer]0000 [Inner]0100
|
||||
Code WT RA : 0b [Outer]1010 [Inner]1010
|
||||
DATA WBWA RA : 0b [Outer]1111 [Inner]1111
|
||||
*/
|
||||
|
||||
/* Data aligned to 8 bytes (stacks must be 8-byte aligned). */
|
||||
#define TXM_MODULE_DATA_ALIGNMENT 8
|
||||
|
||||
/* MPU regions must be 32-byte aligned. */
|
||||
#define TXM_MODULE_MPU_ALIGNMENT 32
|
||||
|
||||
#define TXM_THREAD_SECURE_STACK_ALLOCATE_CALL TXM_MODULE_PORT_EXTENSION_API_ID_START
|
||||
#define TXM_THREAD_SECURE_STACK_FREE_CALL (TXM_MODULE_PORT_EXTENSION_API_ID_START+1)
|
||||
|
||||
/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RLAR. */
|
||||
typedef struct TXM_MODULE_MPU_INFO_STRUCT
|
||||
{
|
||||
ULONG txm_module_mpu_region_base_address;
|
||||
ULONG txm_module_mpu_region_limit_address;
|
||||
} TXM_MODULE_MPU_INFO;
|
||||
|
||||
/* Define the port-extensions to the module manager instance structure. */
|
||||
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
|
||||
TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \
|
||||
ULONG txm_module_instance_shared_memory_count; \
|
||||
ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \
|
||||
ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES];
|
||||
|
||||
|
||||
/* Define the memory fault information structure that is populated when a memory fault occurs. */
|
||||
|
||||
typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
|
||||
{
|
||||
TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr;
|
||||
VOID *txm_module_manager_memory_fault_info_code_location;
|
||||
ULONG txm_module_manager_memory_fault_info_shcsr;
|
||||
ULONG txm_module_manager_memory_fault_info_cfsr;
|
||||
ULONG txm_module_manager_memory_fault_info_mmfar;
|
||||
ULONG txm_module_manager_memory_fault_info_bfar;
|
||||
ULONG txm_module_manager_memory_fault_info_control;
|
||||
ULONG txm_module_manager_memory_fault_info_sp;
|
||||
ULONG txm_module_manager_memory_fault_info_r0;
|
||||
ULONG txm_module_manager_memory_fault_info_r1;
|
||||
ULONG txm_module_manager_memory_fault_info_r2;
|
||||
ULONG txm_module_manager_memory_fault_info_r3;
|
||||
ULONG txm_module_manager_memory_fault_info_r4;
|
||||
ULONG txm_module_manager_memory_fault_info_r5;
|
||||
ULONG txm_module_manager_memory_fault_info_r6;
|
||||
ULONG txm_module_manager_memory_fault_info_r7;
|
||||
ULONG txm_module_manager_memory_fault_info_r8;
|
||||
ULONG txm_module_manager_memory_fault_info_r9;
|
||||
ULONG txm_module_manager_memory_fault_info_r10;
|
||||
ULONG txm_module_manager_memory_fault_info_r11;
|
||||
ULONG txm_module_manager_memory_fault_info_r12;
|
||||
ULONG txm_module_manager_memory_fault_info_lr;
|
||||
ULONG txm_module_manager_memory_fault_info_xpsr;
|
||||
} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
|
||||
|
||||
|
||||
#define TXM_MODULE_MANAGER_FAULT_INFO \
|
||||
TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info;
|
||||
|
||||
|
||||
/* Define the macro to check the code alignment. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \
|
||||
{ \
|
||||
ULONG temp; \
|
||||
temp = (ULONG) module_location; \
|
||||
temp = temp & (code_alignment - 1); \
|
||||
if (temp) \
|
||||
{ \
|
||||
_tx_mutex_put(&_txm_module_manager_mutex); \
|
||||
return(TXM_MODULE_ALIGNMENT_ERROR); \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to adjust the alignment and size for code/data areas. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment);
|
||||
|
||||
|
||||
/* Define the macro to adjust the symbols in the module preamble. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
|
||||
if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \
|
||||
} \
|
||||
else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to populate the thread control block with module port-specific information.
|
||||
Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
|
||||
*/
|
||||
|
||||
#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \
|
||||
thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \
|
||||
thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \
|
||||
if (thread_ptr -> tx_thread_module_user_mode) \
|
||||
{ \
|
||||
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to populate the module control block with module port-specific information.
|
||||
If memory protection is enabled, set up the MPU registers.
|
||||
*/
|
||||
#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \
|
||||
{ \
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \
|
||||
{ \
|
||||
_txm_module_manager_mm_register_setup(module_instance); \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
/* Do nothing. */ \
|
||||
}
|
||||
|
||||
/* Define the macro to perform port-specific functions when unloading the module. */
|
||||
/* Nothing needs to be done for this port. */
|
||||
#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
|
||||
|
||||
|
||||
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
|
||||
|
||||
/* Define macro to make sure object is inside the module's data. */
|
||||
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
|
||||
_txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size)
|
||||
|
||||
/* Define some internal prototypes to this module port. */
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef TX_SOURCE_CODE
|
||||
|
||||
#endif
|
||||
|
||||
#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \
|
||||
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \
|
||||
VOID _txm_module_manager_memory_fault_handler(VOID); \
|
||||
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \
|
||||
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
|
||||
UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \
|
||||
ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2);
|
||||
|
||||
|
||||
#define TXM_MODULE_MANAGER_VERSION_ID \
|
||||
CHAR _txm_module_manager_version_id[] = \
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/GNU Version 6.1.6 *";
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,174 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TXM_MODULE
|
||||
#define TXM_MODULE
|
||||
#endif
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
#define TX_SOURCE_CODE
|
||||
#endif
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "txm_module.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/* Define the global module entry pointer from the start thread of the module. */
|
||||
|
||||
TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
|
||||
|
||||
|
||||
/* Define the dispatch function pointer used in the module implementation. */
|
||||
|
||||
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
|
||||
|
||||
|
||||
/* Define the GCC startup code that clears the uninitialized global data and sets up the
|
||||
preset global variables. */
|
||||
|
||||
extern VOID _gcc_setup(TXM_MODULE_INSTANCE *);
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_thread_shell_entry Cortex-M23/GNU */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function calls the specified entry function of the thread. It */
|
||||
/* also provides a place for the thread's entry function to return. */
|
||||
/* If the thread returns, this function places the thread in a */
|
||||
/* "COMPLETED" state. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to current thread */
|
||||
/* thread_info Pointer to thread entry info */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _gcc_setup GNU global init function */
|
||||
/* thread_entry Thread's entry function */
|
||||
/* tx_thread_resume Resume the module callback thread */
|
||||
/* _txm_module_thread_system_suspend Module thread suspension routine */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Initial thread stack frame */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
|
||||
{
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
VOID (*entry_exit_notify)(TX_THREAD *, UINT);
|
||||
#endif
|
||||
|
||||
|
||||
/* Determine if this is the start thread. If so, we must prepare the module for
|
||||
execution. If not, simply skip the C startup code. */
|
||||
if (thread_info -> txm_module_thread_entry_info_start_thread)
|
||||
{
|
||||
/* Initialize the GNU C environment. */
|
||||
_gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address);
|
||||
|
||||
/* Save the entry info pointer, for later use. */
|
||||
_txm_module_entry_info = thread_info;
|
||||
|
||||
/* Save the kernel function dispatch address. This is used to make all resident calls from
|
||||
the module. */
|
||||
_txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
|
||||
|
||||
/* Ensure that we have a valid pointer. */
|
||||
while (!_txm_module_kernel_call_dispatcher)
|
||||
{
|
||||
/* Loop here, if an error is present getting the dispatch function pointer!
|
||||
An error here typically indicates the resident portion of _tx_thread_schedule
|
||||
is not supporting the trap to obtain the function pointer. */
|
||||
}
|
||||
|
||||
/* Resume the module's callback thread, already created in the manager. */
|
||||
_txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
|
||||
}
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
/* Pickup the entry/exit application callback routine. */
|
||||
entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify;
|
||||
|
||||
/* Determine if an application callback routine is specified. */
|
||||
if (entry_exit_notify != TX_NULL)
|
||||
{
|
||||
|
||||
/* Yes, notify application that this thread has been entered! */
|
||||
(entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call current thread's entry function. */
|
||||
(thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
|
||||
|
||||
/* Suspend thread with a "completed" state. */
|
||||
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
/* Pickup the entry/exit application callback routine again. */
|
||||
entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify;
|
||||
|
||||
/* Determine if an application callback routine is specified. */
|
||||
if (entry_exit_notify != TX_NULL)
|
||||
{
|
||||
|
||||
/* Yes, notify application that this thread has exited! */
|
||||
(entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call actual thread suspension routine. */
|
||||
_txm_module_thread_system_suspend(thread_ptr);
|
||||
|
||||
#ifdef TX_SAFETY_CRITICAL
|
||||
|
||||
/* If we ever get here, raise safety critical exception. */
|
||||
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TXM_MODULE
|
||||
#include "txm_module.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_allocate PORTABLE C */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function allocate a secure stack for the thread. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of secure stack to */
|
||||
/* allocate */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of this function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_module_kernel_call_dispatcher */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Module application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
{
|
||||
|
||||
UINT return_value;
|
||||
|
||||
/* Call module manager dispatcher. */
|
||||
return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_ALLOCATE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) stack_size, 0);
|
||||
|
||||
/* Return value to the caller. */
|
||||
return(return_value);
|
||||
}
|
||||
@@ -0,0 +1,75 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TXM_MODULE
|
||||
#include "txm_module.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_free PORTABLE C */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function frees the thread's secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_module_kernel_call_dispatcher */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Module application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)
|
||||
{
|
||||
|
||||
UINT return_value;
|
||||
|
||||
/* Call module manager dispatcher. */
|
||||
return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_FREE_CALL, (ALIGN_TYPE) thread_ptr, 0, 0);
|
||||
|
||||
/* Return value to the caller. */
|
||||
return(return_value);
|
||||
}
|
||||
@@ -0,0 +1,65 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
/* Define port-specific dispatch functions. */
|
||||
|
||||
/* UINT _txe_thread_secure_stack_allocate(
|
||||
TX_THREAD *thread_ptr, -> param_0
|
||||
ULONG stack_size -> param_1
|
||||
); */
|
||||
static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1)
|
||||
{
|
||||
|
||||
ALIGN_TYPE return_value;
|
||||
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
|
||||
{
|
||||
if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
|
||||
return(TXM_MODULE_INVALID_MEMORY);
|
||||
}
|
||||
|
||||
return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate(
|
||||
(TX_THREAD *) param_0,
|
||||
(ULONG) param_1
|
||||
);
|
||||
return(return_value);
|
||||
}
|
||||
|
||||
/* UINT _txe_thread_secure_stack_free(
|
||||
TX_THREAD *thread_ptr -> param_0
|
||||
); */
|
||||
static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_free_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0)
|
||||
{
|
||||
|
||||
ALIGN_TYPE return_value;
|
||||
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)
|
||||
{
|
||||
if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD)))
|
||||
return(TXM_MODULE_INVALID_MEMORY);
|
||||
}
|
||||
|
||||
return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free(
|
||||
(TX_THREAD *) param_0
|
||||
);
|
||||
return(return_value);
|
||||
}
|
||||
@@ -0,0 +1,210 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Initialize */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
SYSTEM_CLOCK = 6000000
|
||||
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
|
||||
|
||||
/* Setup the stack and heap areas. */
|
||||
|
||||
STACK_SIZE = 0x00000400
|
||||
HEAP_SIZE = 0x00000000
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_initialize_low_level Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for any low-level processor */
|
||||
/* initialization, including setting up interrupt vectors, setting */
|
||||
/* up a periodic timer interrupt source, saving the system stack */
|
||||
/* pointer for use in ISR processing later, and finding the first */
|
||||
/* available RAM memory address for tx_application_define. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_initialize_low_level(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_initialize_low_level
|
||||
.thumb_func
|
||||
.type _tx_initialize_low_level, function
|
||||
_tx_initialize_low_level:
|
||||
|
||||
/* Disable interrupts during ThreadX initialization. */
|
||||
CPSID i
|
||||
|
||||
/* Set base of available memory to end of non-initialised RAM area. */
|
||||
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
|
||||
LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address
|
||||
ADDS r1, r1, #4 //
|
||||
STR r1, [r0] // Setup first unused memory pointer
|
||||
|
||||
/* Setup Vector Table Offset Register. */
|
||||
LDR r0, =0xE000ED08 // Build address of NVIC registers
|
||||
LDR r1, =__Vectors // Pickup address of vector table
|
||||
STR r1, [r0] // Set vector table address
|
||||
|
||||
// /* Enable the cycle count register. */
|
||||
//
|
||||
// LDR r0, =0xE0001000 // Build address of DWT register
|
||||
// LDR r1, [r0] // Pickup the current value
|
||||
// ORR r1, r1, #1 // Set the CYCCNTENA bit
|
||||
// STR r1, [r0] // Enable the cycle count register
|
||||
|
||||
/* Set system stack pointer from vector value. */
|
||||
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
|
||||
LDR r1, =__Vectors // Pickup address of vector table
|
||||
LDR r1, [r1] // Pickup reset stack pointer
|
||||
STR r1, [r0] // Save system stack pointer
|
||||
|
||||
/* Configure SysTick. */
|
||||
LDR r0, =0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] // Setup SysTick Reload Value
|
||||
MOVW r1, #0x7 // Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] // Setup SysTick Control
|
||||
|
||||
/* Configure handler priorities. */
|
||||
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
|
||||
LDR r0, =0xE000E000 // Build address of NVIC registers
|
||||
LDR r2, =0xD18 //
|
||||
ADD r0, r0, r2 //
|
||||
STR r1, [r0] // Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
|
||||
LDR r0, =0xE000E000 // Build address of NVIC registers
|
||||
LDR r2, =0xD1C //
|
||||
ADD r0, r0, r2 //
|
||||
STR r1, [r0] // Setup System Handlers 8-11 Priority Registers
|
||||
// Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
|
||||
LDR r0, =0xE000E000 // Build address of NVIC registers
|
||||
LDR r2, =0xD20 //
|
||||
ADD r0, r0, r2 //
|
||||
STR r1, [r0] // Setup System Handlers 12-15 Priority Registers
|
||||
// Note: PnSV must be lowest priority, which is 0xFF
|
||||
|
||||
/* Return to caller. */
|
||||
BX lr
|
||||
// }
|
||||
|
||||
|
||||
/* Define shells for each of the unused vectors. */
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_BadHandler
|
||||
.thumb_func
|
||||
.type __tx_BadHandler, function
|
||||
__tx_BadHandler:
|
||||
B __tx_BadHandler
|
||||
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_IntHandler
|
||||
.thumb_func
|
||||
.type __tx_IntHandler, function
|
||||
__tx_IntHandler:
|
||||
// VOID InterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
|
||||
/* Do interrupt handler work here */
|
||||
/* .... */
|
||||
|
||||
POP {r0, r1}
|
||||
MOV lr, r1
|
||||
BX lr
|
||||
// }
|
||||
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global SysTick_Handler
|
||||
.thumb_func
|
||||
.type SysTick_Handler, function
|
||||
SysTick_Handler:
|
||||
// VOID TimerInterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
BL _tx_timer_interrupt
|
||||
POP {r0, r1}
|
||||
MOV lr, r1
|
||||
BX lr
|
||||
// }
|
||||
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global HardFault_Handler
|
||||
.thumb_func
|
||||
.type HardFault_Handler, function
|
||||
HardFault_Handler:
|
||||
// A stack overflow will trigger a hardfault.
|
||||
// There is no CFSR in M23, so we will not try to
|
||||
// determine if the fault is caused by a stack overflow
|
||||
// or some other condition.
|
||||
B HardFault_Handler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,74 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_context_restore Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is not needed for Cortex-M. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_context_restore(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_context_restore
|
||||
.thumb_func
|
||||
.type _tx_thread_context_restore, function
|
||||
_tx_thread_context_restore:
|
||||
/* Return to interrupt processing. */
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,74 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_context_save Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is not needed for Cortex-M. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_context_save(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_context_save
|
||||
.thumb_func
|
||||
.type _tx_thread_context_save, function
|
||||
_tx_thread_context_save:
|
||||
/* Return to interrupt processing. */
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,78 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_control Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for changing the interrupt lockout */
|
||||
/* posture of the system. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* new_posture New interrupt lockout posture */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* old_posture Old interrupt lockout posture */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_interrupt_control
|
||||
.thumb_func
|
||||
.type _tx_thread_interrupt_control, function
|
||||
_tx_thread_interrupt_control:
|
||||
|
||||
/* Pickup current interrupt lockout posture. */
|
||||
MRS r1, PRIMASK
|
||||
MSR PRIMASK, r0
|
||||
MOV r0, r1
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,77 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_disable Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for disabling interrupts and returning */
|
||||
/* the previous interrupt lockout posture. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* old_posture Old interrupt lockout posture */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_interrupt_disable(UINT new_posture)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_interrupt_disable
|
||||
.thumb_func
|
||||
.type _tx_thread_interrupt_disable, function
|
||||
_tx_thread_interrupt_disable:
|
||||
/* Return current interrupt lockout posture. */
|
||||
MRS r0, PRIMASK
|
||||
CPSID i
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,76 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_interrupt_restore Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for restoring the previous */
|
||||
/* interrupt lockout posture. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* previous_posture Previous interrupt posture */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_interrupt_restore(UINT new_posture)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_interrupt_restore
|
||||
.thumb_func
|
||||
.type _tx_thread_interrupt_restore, function
|
||||
_tx_thread_interrupt_restore:
|
||||
/* Restore previous interrupt lockout posture. */
|
||||
MSR PRIMASK, r0
|
||||
BX lr
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,645 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_schedule Cortex-M23/GNU */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function waits for a thread control block pointer to appear in */
|
||||
/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
/* in the variable, the corresponding thread is resumed. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* _tx_thread_system_return Return to system from thread */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_schedule(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_schedule
|
||||
.thumb_func
|
||||
.type _tx_thread_schedule, function
|
||||
_tx_thread_schedule:
|
||||
|
||||
/* This function should only ever be called on Cortex-M
|
||||
from the first schedule request. Subsequent scheduling occurs
|
||||
from the PendSV handling routine below. */
|
||||
|
||||
/* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
|
||||
MOVW r0, #0 // Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
STR r0, [r2, #0] // Clear preempt disable flag
|
||||
|
||||
/* Enable memory fault registers. */
|
||||
|
||||
LDR r0, =0xE000ED24 // Build SHCSR address
|
||||
LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
|
||||
STR r1, [r0] //
|
||||
|
||||
/* Enable interrupts */
|
||||
|
||||
CPSIE i
|
||||
|
||||
/* Enter the scheduler for the first time. */
|
||||
|
||||
LDR r0, =0x10000000 // Load PENDSVSET bit
|
||||
LDR r1, =0xE000ED04 // Load ICSR address
|
||||
STR r0, [r1] // Set PENDSVBIT in ICSR
|
||||
DSB // Complete all memory accesses
|
||||
ISB // Flush pipeline
|
||||
|
||||
/* Wait here for the PendSV to take place. */
|
||||
|
||||
__tx_wait_here:
|
||||
B __tx_wait_here // Wait for the PendSV to happen
|
||||
// }
|
||||
|
||||
|
||||
/* Memory Exception Handler. */
|
||||
|
||||
.global MemManage_Handler
|
||||
.global BusFault_Handler
|
||||
.thumb_func
|
||||
MemManage_Handler:
|
||||
.thumb_func
|
||||
BusFault_Handler:
|
||||
|
||||
CPSID i // Disable interrupts
|
||||
|
||||
/* Now pickup and store all the fault related information. */
|
||||
|
||||
LDR r2,=_txm_module_manager_memory_fault_info // Pickup fault info struct
|
||||
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r1, [r0] // Pickup the current thread pointer
|
||||
STR r1, [r2, #0] // Save current thread pointer in fault info structure
|
||||
LDR r0, =0xE000ED24 // Build SHCSR address
|
||||
LDR r1, [r0] // Pickup SHCSR
|
||||
STR r1, [r2, #8] // Save SHCSR
|
||||
LDR r0, =0xE000ED28 // Build CFSR address
|
||||
LDR r1, [r0] // Pickup CFSR
|
||||
STR r1, [r2, #12] // Save CFSR
|
||||
LDR r0, =0xE000ED34 // Build MMFAR address
|
||||
LDR r1, [r0] // Pickup MMFAR
|
||||
STR r1, [r2, #16] // Save MMFAR
|
||||
LDR r0, =0xE000ED38 // Build BFAR address
|
||||
LDR r1, [r0] // Pickup BFAR
|
||||
STR r1, [r2, #20] // Save BFAR
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
STR r0, [r2, #24] // Save CONTROL
|
||||
MRS r1, PSP // Pickup thread stack pointer
|
||||
STR r1, [r2, #28] // Save thread stack pointer
|
||||
LDR r0, [r1] // Pickup saved r0
|
||||
STR r0, [r2, #32] // Save r0
|
||||
LDR r0, [r1, #4] // Pickup saved r1
|
||||
STR r0, [r2, #36] // Save r1
|
||||
LDR r0, [r1, #8] // Pickup saved r2
|
||||
STR r0, [r2, #40] // Save r2
|
||||
STR r3, [r2, #44] // Save r3
|
||||
STR r4, [r2, #48] // Save r4
|
||||
STR r5, [r2, #52] // Save r5
|
||||
STR r6, [r2, #56] // Save r6
|
||||
STR r7, [r2, #60] // Save r7
|
||||
MOV r0, r8 // Move r8 to moveable register
|
||||
STR r0, [r2, #64] // Save r8
|
||||
MOV r0, r9 // Move r9 to moveable register
|
||||
STR r0, [r2, #68] // Save r9
|
||||
MOV r0, r10 // Move r10 to moveable register
|
||||
STR r0, [r2, #72] // Save r10
|
||||
MOV r0, r11 // Move r11 to moveable register
|
||||
STR r0, [r2, #76] // Save r11
|
||||
LDR r0, [r1, #16] // Pickup saved r12
|
||||
STR r0, [r2, #80] // Save r12
|
||||
LDR r0, [r1, #20] // Pickup saved lr
|
||||
STR r0, [r2, #84] // Save lr
|
||||
LDR r0, [r1, #24] // Pickup instruction address at point of fault
|
||||
STR r0, [r2, #4] // Save point of fault
|
||||
LDR r0, [r1, #28] // Pickup xPSR
|
||||
STR r0, [r2, #88] // Save xPSR
|
||||
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
MOVW r1, #0x1 //
|
||||
BICS r0, r0, r1 // Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
|
||||
LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR)
|
||||
LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions:
|
||||
// Bit 0 = 1 -> Instruction address violation
|
||||
// Bit 1 = 1 -> Load/store address violation
|
||||
// Bit 7 = 1 -> MMFAR is valid
|
||||
STRB r1, [r0] // Clear the MMFSR
|
||||
|
||||
BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
CPSID i // Disable interrupts
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
CPSIE i // Enable interrupts
|
||||
#endif
|
||||
|
||||
MOVW r1, #0 // Build NULL value
|
||||
LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer
|
||||
STR r1, [r0] // Clear current thread pointer
|
||||
|
||||
// Return from MemManage_Handler exception
|
||||
LDR r0, =0xE000ED04 // Load ICSR
|
||||
LDR r1, =0x10000000 // Set PENDSVSET bit
|
||||
STR r1, [r0] // Store ICSR
|
||||
DSB // Wait for memory access to complete
|
||||
CPSIE i // Enable interrupts
|
||||
#ifdef TX_SINGLE_MODE_SECURE
|
||||
LDR r0, =0xFFFFFFFD // Exception return to secure
|
||||
#else
|
||||
LDR r0, =0xFFFFFFBC // Exception return to non-secure
|
||||
#endif
|
||||
MOV lr, r0 // Move exception return to lr
|
||||
BX lr // Return from exception
|
||||
|
||||
|
||||
/* Generic context switching PendSV handler. */
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global PendSV_Handler
|
||||
.thumb_func
|
||||
.type PendSV_Handler, function
|
||||
/* Get current thread value and new thread pointer. */
|
||||
PendSV_Handler:
|
||||
__tx_ts_handler:
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
CPSID i // Disable interrupts
|
||||
PUSH {r0, lr} // Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit // Call the thread exit function
|
||||
POP {r0, r1} // Recover LR
|
||||
MOV lr, r1
|
||||
CPSIE i // Enable interrupts
|
||||
#endif
|
||||
|
||||
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address
|
||||
|
||||
MOVW r3, #0 // Build NULL value
|
||||
LDR r1, [r0] // Pickup current thread pointer
|
||||
|
||||
/* Determine if there is a current thread to finish preserving. */
|
||||
|
||||
CBZ r1, __tx_ts_new // If NULL, skip preservation
|
||||
|
||||
/* Recover PSP and preserve current thread context. */
|
||||
|
||||
STR r3, [r0] // Set _tx_thread_current_ptr to NULL
|
||||
MRS r3, PSP // Pickup PSP pointer (thread's stack pointer)
|
||||
SUBS r3, r3, #16 // Allocate stack space
|
||||
STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
|
||||
MOV r4, r8 //
|
||||
MOV r5, r9 //
|
||||
MOV r6, r10 //
|
||||
MOV r7, r11 //
|
||||
SUBS r3, r3, #32 // Allocate stack space
|
||||
STM r3!, {r4-r7} //
|
||||
SUBS r3, r3, #20 // Allocate stack space
|
||||
MOV r5, lr //
|
||||
STR r5, [r3] // Save LR on the stack
|
||||
STR r3, [r1, #8] // Save the thread stack pointer
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
// Save secure context
|
||||
LDR r5, =0xC4 // Secure stack index offset
|
||||
LDR r5, [r1, r5] // Load secure stack index
|
||||
CBZ r5, _skip_secure_save // Skip save if there is no secure context
|
||||
PUSH {r0-r3} // Save scratch registers
|
||||
MOV r0, r1 // Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_save // Save secure stack
|
||||
POP {r0-r3} // Restore secure registers
|
||||
_skip_secure_save:
|
||||
#endif
|
||||
|
||||
/* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
|
||||
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
|
||||
LDR r5, [r4] // Pickup current time-slice
|
||||
CBZ r5, __tx_ts_new // If not active, skip processing
|
||||
|
||||
/* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
|
||||
STR r5, [r1, #24] // Save current time-slice
|
||||
|
||||
/* Clear the global time-slice. */
|
||||
|
||||
MOVW r5, #0 // Build clear value
|
||||
STR r5, [r4] // Clear time-slice
|
||||
|
||||
/* Executing thread is now completely preserved!!! */
|
||||
|
||||
__tx_ts_new:
|
||||
|
||||
/* Now we are looking for a new thread to execute! */
|
||||
|
||||
CPSID i // Disable interrupts
|
||||
LDR r1, [r2] // Is there another thread ready to execute?
|
||||
CBNZ r1, __tx_ts_restore // Yes, schedule it
|
||||
|
||||
/* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
|
||||
__tx_ts_wait:
|
||||
CPSID i // Disable interrupts
|
||||
LDR r1, [r2] // Pickup the next thread to execute pointer
|
||||
CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready!
|
||||
#ifdef TX_ENABLE_WFI
|
||||
DSB // Ensure no outstanding memory transactions
|
||||
WFI // Wait for interrupt
|
||||
ISB // Ensure pipeline is flushed
|
||||
#endif
|
||||
CPSIE i // Enable interrupts
|
||||
B __tx_ts_wait // Loop to continue waiting
|
||||
|
||||
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
already in the handler! */
|
||||
|
||||
__tx_ts_ready:
|
||||
LDR r7, =0x08000000 // Build clear PendSV value
|
||||
LDR r5, =0xE000ED04 // Build base NVIC address
|
||||
STR r7, [r5] // Clear any PendSV
|
||||
|
||||
__tx_ts_restore:
|
||||
|
||||
/* A thread is ready, make the current thread the new thread
|
||||
and enable interrupts. */
|
||||
|
||||
STR r1, [r0] // Setup the current thread pointer to the new thread
|
||||
CPSIE i // Enable interrupts
|
||||
|
||||
/* Increment the thread run count. */
|
||||
|
||||
LDR r7, [r1, #4] // Pickup the current thread run count
|
||||
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
|
||||
LDR r5, [r1, #24] // Pickup thread's current time-slice
|
||||
ADDS r7, r7, #1 // Increment the thread run count
|
||||
STR r7, [r1, #4] // Store the new run count
|
||||
|
||||
/* Setup global time-slice with thread's current time-slice. */
|
||||
|
||||
STR r5, [r4] // Setup global time-slice
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Call the thread entry function to indicate the thread is executing. */
|
||||
PUSH {r0, r1} // Save r0 and r1
|
||||
BL _tx_execution_thread_enter // Call the thread execution enter function
|
||||
POP {r0, r1} // Recover r0 and r1
|
||||
#endif
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
// Restore secure context
|
||||
LDR r5, =0xC4 // Secure stack index offset
|
||||
LDR r0, [r1, r5] // Load secure stack index
|
||||
CBZ r0, _skip_secure_restore // Skip restore if there is no secure context
|
||||
PUSH {r0, r1} // Save r1 (and dummy r0)
|
||||
MOV r0, r1 // Move thread ptr to r0
|
||||
BL _tx_thread_secure_stack_context_restore // Restore secure stack
|
||||
POP {r0, r1} // Restore r1 (and dummy r0)
|
||||
_skip_secure_restore:
|
||||
#endif
|
||||
|
||||
// Set up CONTROL register based on user mode flag (privileged/unprivileged mode)
|
||||
MRS r5, CONTROL // Pickup current CONTROL register
|
||||
MOVS r2, #0x98 // Index of current user mode flag
|
||||
LDR r4, [r1, r2] // Pickup current user mode flag
|
||||
MOVW r0, #0x1
|
||||
BICS r5, r5, r0 // Clear the UNPRIV bit
|
||||
ORRS r4, r4, r5 // Build new CONTROL register
|
||||
MSR CONTROL, r4 // Setup new CONTROL register
|
||||
|
||||
// Determine if MPU needs to be configured
|
||||
LDR r0, =0xE000ED94 // Build MPU control reg address
|
||||
MOVW r3, #0 // Build disable value
|
||||
STR r3, [r0] // Disable MPU
|
||||
MOVS r2, #0x90 // Index of module instance pointer
|
||||
LDR r0, [r1, r2] // Pickup the module instance pointer
|
||||
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
|
||||
MOV r8, r1 // Copy thread ptr
|
||||
LDR r1, [r0, #0x64] // Pickup MPU register[0]
|
||||
CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
|
||||
|
||||
// Initialize loop to configure MPU registers
|
||||
// Order doesn't matter, so txm_module_instance_mpu_registers[0]
|
||||
// will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0.
|
||||
MOVS r3, #0x64 // Index of MPU register settings in thread control block
|
||||
ADD r0, r0, r3 // Build address of MPU register start in thread control block
|
||||
MOVS r5, #0 // Select region 0
|
||||
LDR r4, =0xE000ED98 // Region register address
|
||||
// Loop to load MPU registers
|
||||
_tx_mpu_loop:
|
||||
LDR r1, =0xE000ED9C // Build address of MPU base register
|
||||
STR r5, [r4] // Set region
|
||||
LDM r0!, {r2-r3} // Get MPU settings from the module
|
||||
STM r1!, {r2-r3} // Set MPU registers for region
|
||||
ADDS r5, r5, #1 // Increment to next region
|
||||
CMP r5, #8 // Check if all regions have been set
|
||||
BNE _tx_mpu_loop
|
||||
|
||||
LDR r0, =0xE000ED94 // Build MPU control reg address
|
||||
MOVS r1, #5 // Build enable value with background region enabled
|
||||
STR r1, [r0] // Enable MPU
|
||||
MOV r1, r8 // Get copied thread ptr
|
||||
|
||||
skip_mpu_setup:
|
||||
|
||||
// Restore the thread context and PSP
|
||||
LDR r3, [r1, #8] // Pickup thread's stack pointer
|
||||
LDR r5, [r3] // Recover saved LR
|
||||
ADDS r3, r3, #4 // Position past LR
|
||||
MOV lr, r5 // Restore LR
|
||||
LDM r3!, {r4-r7} // Recover thread's registers (r8-r11)
|
||||
MOV r11, r7
|
||||
MOV r10, r6
|
||||
MOV r9, r5
|
||||
MOV r8, r4
|
||||
LDM r3!, {r4-r7} // Recover thread's registers (r4-r7)
|
||||
MSR PSP, r3 // Setup the thread's stack pointer
|
||||
|
||||
BX lr // Return to thread!
|
||||
|
||||
|
||||
|
||||
/* SVC Handler. */
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global SVC_Handler
|
||||
.thumb_func
|
||||
.type SVC_Handler, function
|
||||
SVC_Handler:
|
||||
MOV r0, lr
|
||||
MOVS r1, #0x04
|
||||
TST r1, r0 // Determine return stack from EXC_RETURN bit 2
|
||||
BEQ _tx_load_msp
|
||||
MRS r0, PSP // Get PSP
|
||||
B _tx_get_svc
|
||||
_tx_load_msp:
|
||||
MRS r0, MSP // Get MSP
|
||||
_tx_get_svc:
|
||||
LDR r1, [r0,#24] // Load saved PC from stack
|
||||
LDR r3, =-2
|
||||
LDRB r2, [r1,r3] // Load SVC number
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
CMP r2, #1 // Is it a secure stack allocate request?
|
||||
BEQ _tx_svc_secure_alloc // Yes, go there
|
||||
|
||||
CMP r2, #2 // Is it a secure stack free request?
|
||||
BEQ _tx_svc_secure_free // Yes, go there
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
|
||||
|
||||
CMP r2, #3 // Is it the entry into ThreadX?
|
||||
BNE _tx_thread_user_return // No, return to user mode
|
||||
|
||||
/* At this point we have an SVC 3, which means we are entering
|
||||
the kernel from a module thread with user mode selected. */
|
||||
|
||||
LDR r2, =_txm_module_priv // Load address of where we should have come from
|
||||
CMP r1, r2 // Did we come from user_mode_entry?
|
||||
BEQ _tx_entry_continue // If no (not equal), then...
|
||||
BX lr // return from where we came.
|
||||
_tx_entry_continue:
|
||||
LDR r3, [r0, #20] // This is the saved LR
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
MOVS r1, #0 // Build clear value
|
||||
MOVS r0, #0x98 // Index of current user mode
|
||||
STR r1, [r2, r0] // Clear the current user mode selection for thread
|
||||
MOVS r0, #0xA0 // Index of saved LR
|
||||
STR r3, [r2, r0] // Save the original LR in thread control block
|
||||
|
||||
/* If there is memory protection, use kernel stack */
|
||||
MOVS r0, #0x90 // Index of module instance ptr
|
||||
LDR r0, [r2, r0] // Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] // Load the module property flags
|
||||
MOVS r1, #2 // MPU protection flag
|
||||
TST r0, r1 // Check if memory protected
|
||||
BEQ _tx_skip_kernel_stack_enter
|
||||
|
||||
/* Switch to the module thread's kernel stack */
|
||||
MOVS r0, #0xA8 // Index of module kernel stack end
|
||||
LDR r0, [r2, r0] // Load the module kernel stack end
|
||||
MOVS r1, #0xA4 // Index of module kernel stack start
|
||||
LDR r1, [r2, r1] // Load the module kernel stack start
|
||||
MSR PSPLIM, r1 // Set stack limit
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
MOVS r3, #0xAC // Index of module kernel stack size
|
||||
LDR r3, [r2, r3] // Load the module kernel stack size
|
||||
STR r1, [r2, #12] // Set stack start
|
||||
STR r0, [r2, #16] // Set stack end
|
||||
STR r3, [r2, #20] // Set stack size
|
||||
#endif
|
||||
|
||||
MRS r3, PSP // Pickup thread stack pointer
|
||||
MOVS r1, #0xB0 // Index of module stack pointer
|
||||
STR r3, [r2, r1] // Save thread stack pointer
|
||||
|
||||
/* Build kernel stack by copying thread stack two registers at a time */
|
||||
SUBS r0, r0, #32 // Start at top of hardware stack
|
||||
LDMIA r3!, {r1,r2} // Get r0, r1 from thread stack
|
||||
STMIA r0!, {r1,r2} // Insert r0, r1 into kernel stack
|
||||
LDMIA r3!, {r1,r2} // Get r2, r3 from thread stack
|
||||
STMIA r0!, {r1,r2} // Insert r2, r3 into kernel stack
|
||||
LDMIA r3!, {r1,r2} // Get r12, lr from thread stack
|
||||
STMIA r0!, {r1,r2} // Insert r12, lr into kernel stack
|
||||
LDMIA r3!, {r1,r2} // Get pc, xpsr from thread stack
|
||||
STMIA r0!, {r1,r2} // Insert pc, xpsr into kernel stack
|
||||
SUBS r0, r0, #32 // Go back to top of stack
|
||||
|
||||
MSR PSP, r0 // Set kernel stack pointer
|
||||
|
||||
_tx_skip_kernel_stack_enter:
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
MOVW r1, #0x1 //
|
||||
BICS r0, r0, r1 // Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
BX lr // Return to thread
|
||||
|
||||
|
||||
_tx_thread_user_return:
|
||||
LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from
|
||||
CMP r1, r2 // Did we come from user_mode_exit?
|
||||
BEQ _tx_exit_continue // If no (not equal), then...
|
||||
BX lr // return from where we came.
|
||||
_tx_exit_continue:
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
MOVS r1, #0x9C // Index of user mode
|
||||
MOVS r3, #0x98 // Index of current user mode
|
||||
LDR r1, [r2, r1] // Pick up user mode
|
||||
STR r1, [r2, r3] // Set the current user mode selection for thread
|
||||
|
||||
/* If there is memory protection, use kernel stack */
|
||||
MOVS r0, #0x90 // Index of module instance ptr
|
||||
LDR r0, [r2, r0] // Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] // Load the module property flags
|
||||
MOVS r1, #2 // MPU protection flag
|
||||
TST r0, r1 // Check if memory protected
|
||||
BEQ _tx_skip_kernel_stack_exit
|
||||
|
||||
MOVS r0, #0xB4 // Index of module thread stack start
|
||||
LDR r0, [r2, r0] // Load the module thread stack start
|
||||
MSR PSPLIM, r0 // Set stack limit
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
MOVS r1, #0xB8 // Index of module thread stack end
|
||||
LDR r1, [r2, r1] // Load the module thread stack end
|
||||
MOVS r3, #0xBC // Index of module thread stack size
|
||||
LDR r3, [r2, r3] // Load the module thread stack size
|
||||
STR r0, [r2, #12] // Set stack start
|
||||
STR r1, [r2, #16] // Set stack end
|
||||
STR r3, [r2, #20] // Set stack size
|
||||
#endif
|
||||
MOVS r1, #0xB0 // Index of module thread stack pointer
|
||||
LDR r0, [r2, r1] // Load the module thread stack pointer
|
||||
MRS r3, PSP // Pickup kernel stack pointer
|
||||
|
||||
/* Copy kernel hardware stack to module thread stack. */
|
||||
LDM r3!,{r1-r2} // Get r0, r1 from kernel stack
|
||||
STM r0!,{r1-r2} // Insert r0, r1 into thread stack
|
||||
LDM r3!,{r1-r2} // Get r2, r3 from kernel stack
|
||||
STM r0!,{r1-r2} // Insert r2, r3 into thread stack
|
||||
LDM r3!,{r1-r2} // Get r12, lr from kernel stack
|
||||
STM r0!,{r1-r2} // Insert r12, lr into thread stack
|
||||
LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack
|
||||
STM r0!,{r1-r2} // Insert pc, xpsr into thread stack
|
||||
SUBS r0, r0, #32 // Subtract 32 to get back to top of stack
|
||||
MSR PSP, r0 // Set thread stack pointer
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r2, [r1] // Pickup current thread pointer
|
||||
MOVS r1, #0x9C // Index of user mode
|
||||
LDR r1, [r2, r1] // Pick up user mode
|
||||
|
||||
_tx_skip_kernel_stack_exit:
|
||||
MRS r0, CONTROL // Pickup current CONTROL register
|
||||
ORRS r0, r0, r1 // OR in the user mode bit
|
||||
MSR CONTROL, r0 // Setup new CONTROL register
|
||||
BX lr // Return to thread
|
||||
|
||||
|
||||
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
|
||||
_tx_svc_secure_alloc:
|
||||
LDR r2, =_tx_alloc_return // Load address of where we should have come from
|
||||
CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate?
|
||||
BEQ _tx_alloc_continue // If no (not equal), then...
|
||||
BX lr // return from where we came.
|
||||
_tx_alloc_continue:
|
||||
PUSH {r0, lr} // Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} // Load function parameters from stack
|
||||
BL _tx_thread_secure_mode_stack_allocate
|
||||
POP {r1, r2} // Restore SP and EXC_RETURN
|
||||
STR r0, [r1] // Store function return value
|
||||
MOV lr, r2
|
||||
BX lr
|
||||
|
||||
_tx_svc_secure_free:
|
||||
LDR r2, =_tx_free_return // Load address of where we should have come from
|
||||
CMP r1, r2 // Did we come from _tx_thread_secure_stack_free?
|
||||
BEQ _tx_free_continue // If no (not equal), then...
|
||||
BX lr // return from where we came.
|
||||
_tx_free_continue:
|
||||
PUSH {r0, lr} // Save SP and EXC_RETURN
|
||||
LDM r0, {r0-r3} // Load function parameters from stack
|
||||
BL _tx_thread_secure_mode_stack_free
|
||||
POP {r1, r2} // Restore SP and EXC_RETURN
|
||||
STR r0, [r1] // Store function return value
|
||||
MOV lr, r2
|
||||
BX lr
|
||||
#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE
|
||||
|
||||
|
||||
|
||||
/* Kernel entry function from user mode. */
|
||||
|
||||
.global _txm_module_manager_kernel_dispatch
|
||||
.align 5
|
||||
.syntax unified
|
||||
// VOID _txm_module_manager_user_mode_entry(VOID)
|
||||
// {
|
||||
.global _txm_module_manager_user_mode_entry
|
||||
.thumb_func
|
||||
_txm_module_manager_user_mode_entry:
|
||||
SVC 3 // Enter kernel
|
||||
_txm_module_priv:
|
||||
/* At this point, we are out of user mode. The original LR has been saved in the
|
||||
thread control block. Simply call the kernel dispatch function. */
|
||||
BL _txm_module_manager_kernel_dispatch
|
||||
|
||||
/* Pickup the original LR value while still in privileged mode */
|
||||
LDR r2, =_tx_thread_current_ptr // Build current thread pointer address
|
||||
LDR r3, [r2] // Pickup current thread pointer
|
||||
LDR r2, =0xA0 // Index of saved LR
|
||||
LDR r1, [r3, r2] // Pickup saved LR from original call
|
||||
MOV lr, r1
|
||||
SVC 4 // Exit kernel and return to user mode
|
||||
_txm_module_user_mode_exit:
|
||||
BX lr // Return to the caller
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
// }
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,497 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
#include "tx_api.h"
|
||||
|
||||
/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined,
|
||||
no secure stack functionality is needed. */
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_secure_interface.h" /* Interface for NS code. */
|
||||
|
||||
/* Minimum size of secure stack. */
|
||||
#ifndef TX_THREAD_SECURE_STACK_MINIMUM
|
||||
#define TX_THREAD_SECURE_STACK_MINIMUM 256
|
||||
#endif
|
||||
/* Maximum size of secure stack. */
|
||||
#ifndef TX_THREAD_SECURE_STACK_MAXIMUM
|
||||
#define TX_THREAD_SECURE_STACK_MAXIMUM 1024
|
||||
#endif
|
||||
|
||||
/* 8 bytes added to stack size to "seal" stack. */
|
||||
#define TX_THREAD_STACK_SEAL_SIZE 8
|
||||
#define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5
|
||||
|
||||
/* Secure stack info struct to hold stack start, stack limit,
|
||||
current stack pointer, and pointer to owning thread.
|
||||
This will be allocated for each thread with a secure stack. */
|
||||
typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
|
||||
{
|
||||
VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */
|
||||
VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */
|
||||
VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */
|
||||
TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */
|
||||
} TX_THREAD_SECURE_STACK_INFO;
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */
|
||||
/* 6.1.3 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function initializes secure mode to use PSP stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 12-31-2020 Scott Larson Modified comment(s), and */
|
||||
/* fixed M23 GCC build, */
|
||||
/* resulting in version 6.1.3 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_initialize(void)
|
||||
{
|
||||
ULONG control;
|
||||
|
||||
/* Set secure mode to use PSP. */
|
||||
asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */
|
||||
control |= 2; /* Use PSP. */
|
||||
asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
asm volatile("MSR PSPLIM, %0" :: "r" (0));
|
||||
asm volatile("MSR PSP, %0" :: "r" (0));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_mode_stack_allocate Cortex-M23/GNU */
|
||||
/* 6.1.3 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function allocates a thread's secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of stack to allocates */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_SIZE_ERROR Invalid stack size */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* calloc Compiler's calloc function */
|
||||
/* malloc Compiler's malloc function */
|
||||
/* free Compiler's free() function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* SVC Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* added stack sealing, */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 12-31-2020 Scott Larson Modified comment(s), and */
|
||||
/* fixed M23 GCC build, */
|
||||
/* resulting in version 6.1.3 */
|
||||
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
{
|
||||
UINT status;
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
UCHAR *stack_mem;
|
||||
ULONG ipsr;
|
||||
ULONG psplim_ns;
|
||||
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
|
||||
if (ipsr == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM)
|
||||
{
|
||||
status = TX_SIZE_ERROR;
|
||||
}
|
||||
|
||||
/* Check if thread already has secure stack allocated. */
|
||||
else if (thread_ptr -> tx_thread_secure_stack_context != 0)
|
||||
{
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Allocate space for secure stack info. */
|
||||
info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO));
|
||||
|
||||
if(info_ptr != TX_NULL)
|
||||
{
|
||||
/* If stack info allocated, allocate a stack & seal. */
|
||||
stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE);
|
||||
|
||||
if(stack_mem != TX_NULL)
|
||||
{
|
||||
/* Secure stack has been allocated, save in the stack info struct. */
|
||||
info_ptr -> tx_thread_secure_stack_limit = stack_mem;
|
||||
info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size;
|
||||
info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start;
|
||||
info_ptr -> tx_thread_ptr = thread_ptr;
|
||||
|
||||
/* Seal bottom of stack. */
|
||||
*(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE;
|
||||
|
||||
/* Save info pointer in thread. */
|
||||
thread_ptr -> tx_thread_secure_stack_context = info_ptr;
|
||||
|
||||
/* Check if this thread is running by looking at its stack start and PSPLIM_NS */
|
||||
asm volatile("MRS %0, PSPLIM_NS" : "=r" (psplim_ns)); /* Get PSPLIM_NS register. */
|
||||
if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == psplim_ns)
|
||||
{
|
||||
/* If this thread is running, set Secure PSP and PSPLIM. */
|
||||
asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_limit)));
|
||||
asm volatile("MSR PSP, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)));
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Stack not allocated, free the info struct. */
|
||||
free(info_ptr);
|
||||
status = TX_NO_MEMORY;
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
status = TX_NO_MEMORY;
|
||||
}
|
||||
}
|
||||
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_mode_stack_free Cortex-M23/GNU */
|
||||
/* 6.1.3 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function frees a thread's secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* free Compiler's free() function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* SVC Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 12-31-2020 Scott Larson Modified comment(s), and */
|
||||
/* fixed M23 GCC build, */
|
||||
/* resulting in version 6.1.3 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
|
||||
{
|
||||
UINT status;
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
ULONG ipsr;
|
||||
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Pickup stack info from thread. */
|
||||
info_ptr = thread_ptr -> tx_thread_secure_stack_context;
|
||||
|
||||
/* Make sure function is called from interrupt (threads should not call). */
|
||||
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
|
||||
if (ipsr == 0)
|
||||
{
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
else if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
|
||||
/* Free secure stack. */
|
||||
free(info_ptr -> tx_thread_secure_stack_limit);
|
||||
|
||||
/* Free info struct. */
|
||||
free(info_ptr);
|
||||
|
||||
/* Clear secure context from thread. */
|
||||
thread_ptr -> tx_thread_secure_stack_context = 0;
|
||||
}
|
||||
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_save Cortex-M23/GNU */
|
||||
/* 6.1.3 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function saves context of the secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* PendSV Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 12-31-2020 Scott Larson Modified comment(s), and */
|
||||
/* fixed M23 GCC build, */
|
||||
/* resulting in version 6.1.3 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr)
|
||||
{
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
ULONG sp;
|
||||
ULONG ipsr;
|
||||
|
||||
/* This function should be called from scheduler only. */
|
||||
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
|
||||
if (ipsr == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Pickup the secure context pointer. */
|
||||
info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context);
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Check that stack pointer is in range */
|
||||
asm volatile("MRS %0, PSP" : "=r" (sp)); /* Get PSP register. */
|
||||
if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) ||
|
||||
(sp > (ULONG)info_ptr -> tx_thread_secure_stack_start))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Save stack pointer. */
|
||||
*(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp;
|
||||
|
||||
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
|
||||
without a secure stack calls a secure function that tries to use secure stack. */
|
||||
asm volatile("MSR PSPLIM, %0" :: "r" (0));
|
||||
asm volatile("MSR PSP, %0" :: "r" (0));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_context_restore Cortex-M23/GNU */
|
||||
/* 6.1.3 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function restores context of the secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* PendSV Handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* 10-16-2020 Scott Larson Modified comment(s), */
|
||||
/* resulting in version 6.1.1 */
|
||||
/* 12-31-2020 Scott Larson Modified comment(s), and */
|
||||
/* fixed M23 GCC build, */
|
||||
/* resulting in version 6.1.3 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr)
|
||||
{
|
||||
TX_THREAD_SECURE_STACK_INFO *info_ptr;
|
||||
ULONG ipsr;
|
||||
|
||||
/* This function should be called from scheduler only. */
|
||||
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
|
||||
if (ipsr == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Pickup the secure context pointer. */
|
||||
info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context);
|
||||
|
||||
/* Check that this secure context is for this thread. */
|
||||
if (info_ptr -> tx_thread_ptr != thread_ptr)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set stack pointer and limit. */
|
||||
asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_limit));
|
||||
asm volatile("MSR PSP, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_ptr));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,88 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_allocate Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function enters the SVC handler to allocate a secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of secure stack to */
|
||||
/* allocate */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* SVC 1 */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_secure_stack_allocate
|
||||
.global _tx_alloc_return
|
||||
.thumb_func
|
||||
.type _tx_thread_secure_stack_allocate, function
|
||||
_tx_thread_secure_stack_allocate:
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
MRS r3, PRIMASK // Save interrupt mask
|
||||
CPSIE i // Enable interrupts for SVC call
|
||||
SVC 1
|
||||
_tx_alloc_return:
|
||||
CMP r3, #0 // If interrupts enabled, just return
|
||||
BEQ _alloc_return_interrupt_enabled
|
||||
CPSID i // Otherwise, disable interrupts
|
||||
#else
|
||||
// Executing in single mode - this function is not needed.
|
||||
MOVS r0, #0xFF // Feature not enabled
|
||||
#endif
|
||||
_alloc_return_interrupt_enabled:
|
||||
BX lr
|
||||
.end
|
||||
@@ -0,0 +1,86 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_free Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function enters the SVC handler to free a secure stack. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* SVC 2 */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_secure_stack_free
|
||||
.global _tx_free_return
|
||||
.thumb_func
|
||||
.type _tx_thread_secure_stack_free, function
|
||||
_tx_thread_secure_stack_free:
|
||||
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
MRS r3, PRIMASK // Save interrupt mask
|
||||
CPSIE i // Enable interrupts for SVC call
|
||||
SVC 2
|
||||
_tx_free_return:
|
||||
CMP r3, #0 // If interrupts enabled, just return
|
||||
BEQ _free_return_interrupt_enabled
|
||||
CPSID i // Otherwise, disable interrupts
|
||||
#else
|
||||
// Executing in single mode - this function is not needed.
|
||||
MOVS r0, #0xFF // Feature not enabled
|
||||
#endif
|
||||
_free_return_interrupt_enabled:
|
||||
BX lr
|
||||
.end
|
||||
@@ -0,0 +1,141 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_build Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function builds a stack frame on the supplied thread's stack. */
|
||||
/* The stack frame results in a fake interrupt return to the supplied */
|
||||
/* function pointer. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to thread control blk */
|
||||
/* function_ptr Pointer to return function */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_thread_create Create thread service */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_stack_build
|
||||
.thumb_func
|
||||
.type _tx_thread_stack_build, function
|
||||
_tx_thread_stack_build:
|
||||
/* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
on the Cortex-M23 should look like the following after it is built:
|
||||
|
||||
Stack Top:
|
||||
LR Interrupted LR (LR at time of PENDSV)
|
||||
r8 Initial value for r8
|
||||
r9 Initial value for r9
|
||||
r10 Initial value for r10
|
||||
r11 Initial value for r11
|
||||
r4 Initial value for r4
|
||||
r5 Initial value for r5
|
||||
r6 Initial value for r6
|
||||
r7 Initial value for r7
|
||||
r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
r1 Initial value for r1
|
||||
r2 Initial value for r2
|
||||
r3 Initial value for r3
|
||||
r12 Initial value for r12
|
||||
lr Initial value for lr
|
||||
pc Initial value for pc
|
||||
xPSR Initial value for xPSR
|
||||
|
||||
Stack Bottom: (higher memory address) */
|
||||
|
||||
LDR r2, [r0, #16] // Pickup end of stack area
|
||||
MOVW r3, #0x7 //
|
||||
BICS r2, r2, r3 // Align frame for 8-byte alignment
|
||||
SUBS r2, r2, #68 // Subtract frame size
|
||||
#ifdef TX_SINGLE_MODE_SECURE
|
||||
LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode
|
||||
#else
|
||||
LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP
|
||||
#endif
|
||||
STR r3, [r2, #0] // Save on the stack
|
||||
|
||||
/* Actually build the stack frame. */
|
||||
|
||||
MOVW r3, #0 // Build initial register value
|
||||
STR r3, [r2, #4] // Store initial r8
|
||||
STR r3, [r2, #8] // Store initial r9
|
||||
STR r3, [r2, #12] // Store initial r10
|
||||
STR r3, [r2, #16] // Store initial r11
|
||||
STR r3, [r2, #20] // Store initial r4
|
||||
STR r3, [r2, #24] // Store initial r5
|
||||
STR r3, [r2, #28] // Store initial r6
|
||||
STR r3, [r2, #32] // Store initial r7
|
||||
|
||||
/* Hardware stack follows. */
|
||||
|
||||
STR r3, [r2, #36] // Store initial r0
|
||||
STR r3, [r2, #40] // Store initial r1
|
||||
STR r3, [r2, #44] // Store initial r2
|
||||
STR r3, [r2, #48] // Store initial r3
|
||||
STR r3, [r2, #52] // Store initial r12
|
||||
LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] // Store initial lr
|
||||
STR r1, [r2, #60] // Store initial pc
|
||||
LDR r3, =0x01000000 // Only T-bit need be set
|
||||
STR r3, [r2, #64] // Store initial xPSR
|
||||
|
||||
/* Setup stack pointer. */
|
||||
// thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
|
||||
STR r2, [r0, #8] // Save stack pointer in thread's
|
||||
// control block
|
||||
BX lr // Return to caller
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,93 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/* Define the global function pointer for stack error handling. If a stack error is
|
||||
detected and the application has registered a stack error handler, it will be
|
||||
called via this function pointer. */
|
||||
|
||||
VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_error_handler Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function processes stack errors detected during run-time. */
|
||||
/* */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_terminate */
|
||||
/* _tx_thread_application_stack_error_handler */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* ThreadX internal code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr)
|
||||
{
|
||||
#ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR
|
||||
/* Is there a thread? */
|
||||
if (thread_ptr)
|
||||
{
|
||||
/* Terminate the current thread. */
|
||||
_tx_thread_terminate(_tx_thread_current_ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Determine if the application has registered an error handler. */
|
||||
if (_tx_thread_application_stack_error_handler != TX_NULL)
|
||||
{
|
||||
/* Yes, an error handler is present, simply call the application error handler. */
|
||||
(_tx_thread_application_stack_error_handler)(thread_ptr);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,96 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "tx_trace.h"
|
||||
|
||||
extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr);
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_stack_error_notify Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function registers an application stack error handler. If */
|
||||
/* ThreadX detects a stack error, this application handler is called. */
|
||||
/* */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* stack_error_handler Pointer to stack error */
|
||||
/* handler, TX_NULL to disable */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Service return status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr))
|
||||
{
|
||||
|
||||
TX_INTERRUPT_SAVE_AREA
|
||||
|
||||
/* Disable interrupts. */
|
||||
TX_DISABLE
|
||||
|
||||
/* Make entry in event log. */
|
||||
TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS)
|
||||
|
||||
/* Make entry in event log. */
|
||||
TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT
|
||||
|
||||
/* Setup global thread stack error handler. */
|
||||
_tx_thread_application_stack_error_handler = stack_error_handler;
|
||||
|
||||
/* Restore interrupts. */
|
||||
TX_RESTORE
|
||||
|
||||
/* Return success to caller. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,89 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_thread_system_return Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is target processor specific. It is used to transfer */
|
||||
/* control from a thread back to the ThreadX system. Only a */
|
||||
/* minimal context is saved since the compiler assumes temp registers */
|
||||
/* are going to get slicked by a function call anyway. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_schedule Thread scheduling loop */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* ThreadX components */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_thread_system_return(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_thread_system_return
|
||||
.thumb_func
|
||||
.type _tx_thread_system_return, function
|
||||
_tx_thread_system_return:
|
||||
/* Return to real scheduler via PendSV. Note that this routine is often
|
||||
replaced with in-line assembly in tx_port.h to improved performance. */
|
||||
|
||||
LDR r0, =0x10000000 // Load PENDSVSET bit
|
||||
LDR r1, =0xE000ED04 // Load ICSR address
|
||||
STR r0, [r1] // Set PENDSVBIT in ICSR
|
||||
MRS r0, IPSR // Pickup IPSR
|
||||
CMP r0, #0 // Is it a thread returning?
|
||||
BNE _isr_context // If ISR, skip interrupt enable
|
||||
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
|
||||
CPSIE i // Enable interrupts
|
||||
MSR PRIMASK, r1 // Restore original interrupt posture
|
||||
_isr_context:
|
||||
BX lr // Return to caller
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,262 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Timer */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_timer_interrupt Cortex-M23/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function processes the hardware timer interrupt. This */
|
||||
/* processing includes incrementing the system clock and checking for */
|
||||
/* time slice and/or timer expiration. If either is found, the */
|
||||
/* interrupt context save/restore functions are called along with the */
|
||||
/* expiration functions. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_timer_expiration_process Timer expiration processing */
|
||||
/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* interrupt vector */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
/* VOID _tx_timer_interrupt(VOID)
|
||||
{ */
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_timer_interrupt
|
||||
.thumb_func
|
||||
.type _tx_timer_interrupt, function
|
||||
_tx_timer_interrupt:
|
||||
|
||||
/* Upon entry to this routine, it is assumed that the compiler scratch registers are available
|
||||
for use. */
|
||||
|
||||
/* Increment the system clock. */
|
||||
// _tx_timer_system_clock++;
|
||||
|
||||
MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock
|
||||
MOVT r1, #:upper16:_tx_timer_system_clock
|
||||
LDR r0, [r1, #0] // Pickup system clock
|
||||
ADDS r0, r0, #1 // Increment system clock
|
||||
STR r0, [r1, #0] // Store new system clock
|
||||
|
||||
/* Test for time-slice expiration. */
|
||||
// if (_tx_timer_time_slice)
|
||||
// {
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice
|
||||
MOVT r3, #:upper16:_tx_timer_time_slice
|
||||
LDR r2, [r3, #0] // Pickup time-slice
|
||||
CBZ r2, __tx_timer_no_time_slice // Is it non-active?
|
||||
// Yes, skip time-slice processing
|
||||
|
||||
/* Decrement the time_slice. */
|
||||
// _tx_timer_time_slice--;
|
||||
|
||||
SUBS r2, r2, #1 // Decrement the time-slice
|
||||
STR r2, [r3, #0] // Store new time-slice value
|
||||
|
||||
/* Check for expiration. */
|
||||
// if (__tx_timer_time_slice == 0)
|
||||
|
||||
CBNZ r2, __tx_timer_no_time_slice // Has it expired?
|
||||
|
||||
/* Set the time-slice expired flag. */
|
||||
// _tx_timer_expired_time_slice = TX_TRUE;
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag
|
||||
MOVT r3, #:upper16:_tx_timer_expired_time_slice
|
||||
MOVW r0, #1 // Build expired value
|
||||
STR r0, [r3, #0] // Set time-slice expiration flag
|
||||
|
||||
// }
|
||||
|
||||
__tx_timer_no_time_slice:
|
||||
|
||||
/* Test for timer expiration. */
|
||||
// if (*_tx_timer_current_ptr)
|
||||
// {
|
||||
|
||||
MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address
|
||||
MOVT r1, #:upper16:_tx_timer_current_ptr
|
||||
LDR r0, [r1, #0] // Pickup current timer
|
||||
LDR r2, [r0, #0] // Pickup timer list entry
|
||||
CBZ r2, __tx_timer_no_timer // Is there anything in the list?
|
||||
// No, just increment the timer
|
||||
|
||||
/* Set expiration flag. */
|
||||
// _tx_timer_expired = TX_TRUE;
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address
|
||||
MOVT r3, #:upper16:_tx_timer_expired
|
||||
MOVW r2, #1 // Build expired value
|
||||
STR r2, [r3, #0] // Set expired flag
|
||||
B __tx_timer_done // Finished timer processing
|
||||
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
__tx_timer_no_timer:
|
||||
|
||||
/* No timer expired, increment the timer pointer. */
|
||||
// _tx_timer_current_ptr++;
|
||||
|
||||
ADDS r0, r0, #4 // Move to next timer
|
||||
|
||||
/* Check for wrap-around. */
|
||||
// if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end
|
||||
MOVT r3, #:upper16:_tx_timer_list_end
|
||||
LDR r2, [r3, #0] // Pickup list end
|
||||
CMP r0, r2 // Are we at list end?
|
||||
BNE __tx_timer_skip_wrap // No, skip wrap-around logic
|
||||
|
||||
/* Wrap to beginning of list. */
|
||||
// _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start
|
||||
MOVT r3, #:upper16:_tx_timer_list_start
|
||||
LDR r0, [r3, #0] // Set current pointer to list start
|
||||
|
||||
__tx_timer_skip_wrap:
|
||||
|
||||
STR r0, [r1, #0] // Store new current timer pointer
|
||||
// }
|
||||
|
||||
__tx_timer_done:
|
||||
|
||||
|
||||
/* See if anything has expired. */
|
||||
// if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
// {
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag
|
||||
MOVT r3, #:upper16:_tx_timer_expired_time_slice
|
||||
LDR r2, [r3, #0] // Pickup time-slice expired flag
|
||||
CBNZ r2, __tx_something_expired // Did a time-slice expire?
|
||||
// If non-zero, time-slice expired
|
||||
MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag
|
||||
MOVT r1, #:upper16:_tx_timer_expired
|
||||
LDR r0, [r1, #0] // Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_nothing_expired // Did a timer expire?
|
||||
// No, nothing expired
|
||||
|
||||
__tx_something_expired:
|
||||
|
||||
PUSH {r0, lr} // Save the lr register on the stack
|
||||
// and save r0 just to keep 8-byte alignment
|
||||
|
||||
/* Did a timer expire? */
|
||||
// if (_tx_timer_expired)
|
||||
// {
|
||||
|
||||
MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag
|
||||
MOVT r1, #:upper16:_tx_timer_expired
|
||||
LDR r0, [r1, #0] // Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_dont_activate // Check for timer expiration
|
||||
// If not set, skip timer activation
|
||||
|
||||
/* Process timer expiration. */
|
||||
// _tx_timer_expiration_process();
|
||||
|
||||
BL _tx_timer_expiration_process // Call the timer expiration handling routine
|
||||
|
||||
// }
|
||||
__tx_timer_dont_activate:
|
||||
|
||||
/* Did time slice expire? */
|
||||
// if (_tx_timer_expired_time_slice)
|
||||
// {
|
||||
|
||||
MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired
|
||||
MOVT r3, #:upper16:_tx_timer_expired_time_slice
|
||||
LDR r2, [r3, #0] // Pickup the actual flag
|
||||
CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set
|
||||
// No, skip time-slice processing
|
||||
|
||||
/* Time slice interrupted thread. */
|
||||
// _tx_thread_time_slice();
|
||||
|
||||
BL _tx_thread_time_slice // Call time-slice processing
|
||||
MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag
|
||||
MOVT r0, #:upper16:_tx_thread_preempt_disable
|
||||
|
||||
LDR r1, [r0] // Is the preempt disable flag set?
|
||||
CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic
|
||||
MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address
|
||||
MOVT r0, #:upper16:_tx_thread_current_ptr
|
||||
|
||||
LDR r1, [r0] // Pickup the current thread pointer
|
||||
MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address
|
||||
MOVT r2, #:upper16:_tx_thread_execute_ptr
|
||||
|
||||
LDR r3, [r2] // Pickup the execute thread pointer
|
||||
LDR r0, =0xE000ED04 // Build address of control register
|
||||
LDR r2, =0x10000000 // Build value for PendSV bit
|
||||
CMP r1, r3 // Are they the same?
|
||||
BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed
|
||||
STR r2, [r0] // Not the same, issue the PendSV for preemption
|
||||
__tx_timer_skip_time_slice:
|
||||
// }
|
||||
|
||||
__tx_timer_not_ts_expiration:
|
||||
|
||||
POP {r0, r1} // Recover lr register (r0 is just there for
|
||||
MOV lr, r1 // the 8-byte stack alignment
|
||||
|
||||
// }
|
||||
|
||||
__tx_timer_nothing_expired:
|
||||
|
||||
DSB // Complete all memory access
|
||||
BX lr // Return to caller
|
||||
|
||||
// }
|
||||
.end
|
||||
@@ -0,0 +1,119 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_initialize.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_allocate Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function checks for errors in the secure stack allocate */
|
||||
/* function call. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* stack_size Size of secure stack to */
|
||||
/* allocate */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_allocate Actual stack alloc function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
|
||||
{
|
||||
#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
return(TX_FEATURE_NOT_ENABLED);
|
||||
#else
|
||||
UINT status;
|
||||
|
||||
/* Default status to success. */
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Check for an invalid thread pointer. */
|
||||
if (thread_ptr == TX_NULL)
|
||||
{
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Now check for invalid thread ID. */
|
||||
else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
|
||||
{
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Check for interrupt call. */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0))
|
||||
{
|
||||
/* Is call from an interrupt and not initialization? */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
|
||||
{
|
||||
/* Invalid caller of this function, return appropriate error code. */
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine if everything is okay. */
|
||||
if (status == TX_SUCCESS)
|
||||
{
|
||||
/* Call actual secure stack allocate function. */
|
||||
status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size);
|
||||
}
|
||||
|
||||
/* Return completion status. */
|
||||
return(status);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Thread */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_initialize.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txe_thread_secure_stack_free Cortex-M23 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function checks for errors in the secure stack free */
|
||||
/* function call. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Thread control block pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* TX_THREAD_ERROR Invalid thread pointer */
|
||||
/* TX_CALLER_ERROR Invalid caller of function */
|
||||
/* status Actual completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_secure_stack_free Actual stack free function */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr)
|
||||
{
|
||||
#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE)
|
||||
return(TX_FEATURE_NOT_ENABLED);
|
||||
#else
|
||||
UINT status;
|
||||
|
||||
/* Default status to success. */
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Check for an invalid thread pointer. */
|
||||
if (thread_ptr == TX_NULL)
|
||||
{
|
||||
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Now check for invalid thread ID. */
|
||||
else if (thread_ptr -> tx_thread_id != TX_THREAD_ID)
|
||||
{
|
||||
|
||||
/* Thread pointer is invalid, return appropriate error code. */
|
||||
status = TX_THREAD_ERROR;
|
||||
}
|
||||
|
||||
/* Check for interrupt call. */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0))
|
||||
{
|
||||
/* Is call from an interrupt and not initialization? */
|
||||
if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
|
||||
{
|
||||
/* Invalid caller of this function, return appropriate error code. */
|
||||
status = TX_CALLER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine if everything is okay. */
|
||||
if (status == TX_SUCCESS)
|
||||
{
|
||||
|
||||
/* Call actual secure stack allocate function. */
|
||||
status = _tx_thread_secure_stack_free(thread_ptr);
|
||||
}
|
||||
|
||||
/* Return completion status. */
|
||||
return(status);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_alignment_adjust Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function adjusts the alignment and size of the code and data */
|
||||
/* section for a given module implementation. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_preamble Pointer to module preamble */
|
||||
/* code_size Size of the code area (updated) */
|
||||
/* code_alignment Code area alignment (updated) */
|
||||
/* data_size Size of data area (updated) */
|
||||
/* data_alignment Data area alignment (updated) */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Initial thread stack frame */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
|
||||
ULONG *code_size,
|
||||
ULONG *code_alignment,
|
||||
ULONG *data_size,
|
||||
ULONG *data_alignment)
|
||||
{
|
||||
|
||||
/* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */
|
||||
*code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1);
|
||||
*data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1);
|
||||
|
||||
/* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */
|
||||
*code_alignment = TXM_MODULE_MPU_ALIGNMENT;
|
||||
*data_alignment = TXM_MODULE_MPU_ALIGNMENT;
|
||||
}
|
||||
@@ -0,0 +1,164 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_mutex.h"
|
||||
#include "tx_queue.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_external_memory_enable Cortex-M23 */
|
||||
/* 6.1.6 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function creates an entry in the MPU table for a shared */
|
||||
/* memory space. The start_address must be 32-byte aligned. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Module instance pointer */
|
||||
/* start_address Start address of memory */
|
||||
/* length Length of external memory */
|
||||
/* attributes Memory attributes (r/w) */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_mutex_get Get protection mutex */
|
||||
/* _tx_mutex_put Release protection mutex */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 04-02-2021 Scott Larson Initial Version 6.1.6 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
|
||||
VOID *start_address,
|
||||
ULONG length,
|
||||
UINT attributes)
|
||||
{
|
||||
|
||||
ULONG address;
|
||||
ULONG shared_index;
|
||||
|
||||
/* Determine if the module manager has not been initialized yet. */
|
||||
if (_txm_module_manager_ready != TX_TRUE)
|
||||
{
|
||||
/* Module manager has not been initialized. */
|
||||
return(TX_NOT_AVAILABLE);
|
||||
}
|
||||
|
||||
/* Determine if the module is valid. */
|
||||
if (module_instance == TX_NULL)
|
||||
{
|
||||
/* Invalid module pointer. */
|
||||
return(TX_PTR_ERROR);
|
||||
}
|
||||
|
||||
/* Get module manager protection mutex. */
|
||||
_tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
|
||||
|
||||
/* Determine if the module instance is valid. */
|
||||
if (module_instance -> txm_module_instance_id != TXM_MODULE_ID)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Invalid module pointer. */
|
||||
return(TX_PTR_ERROR);
|
||||
}
|
||||
|
||||
/* Determine if the module instance is in the loaded state. */
|
||||
if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return error if the module is not ready. */
|
||||
return(TX_START_ERROR);
|
||||
}
|
||||
|
||||
/* Determine if there are shared memory entries available. */
|
||||
if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* No more entries available. */
|
||||
return(TX_NO_MEMORY);
|
||||
}
|
||||
|
||||
/* Start address must adhere to Cortex-M23 MPU alignment. */
|
||||
address = (ULONG) start_address;
|
||||
if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1)))
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return alignment error. */
|
||||
return(TXM_MODULE_ALIGNMENT_ERROR);
|
||||
}
|
||||
|
||||
/* At this point, we have a valid address. Set up MPU registers. */
|
||||
|
||||
/* Pick up index into shared memory entries. */
|
||||
shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count;
|
||||
|
||||
/* Set base address register with start address, sanitized attributes and execute never. */
|
||||
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER;
|
||||
|
||||
/* Set the limit address (data start + length-1), attribute index, and enable bit. */
|
||||
module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE;
|
||||
|
||||
/* Keep track of shared memory address and length in module instance. */
|
||||
module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address;
|
||||
module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length;
|
||||
|
||||
/* Increment counter. */
|
||||
module_instance -> txm_module_instance_shared_memory_count++;
|
||||
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return success. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
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Reference in New Issue
Block a user