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Release 6.1.12

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This commit is contained in:
Yuxin Zhou
2022-07-26 02:04:40 +00:00
parent 54cda6ee9e
commit 8c3c08f108
217 changed files with 13398 additions and 13432 deletions
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59
ports_module/cortex_m4/ac5/inc/txm_module_port.h
View File

@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M4/AC5 */
/* 6.1.9 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -41,6 +41,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 07-29-2022 Scott Larson Enabled user-defined and */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
@@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h:
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
#endif
/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15)
are not used by ThreadX. These may be defined by the user. */
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0
/* Users can define these default MPU configuration values.
If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled
when a thread that is not owned by a module is running
and the defines below are not used.
If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the
below values when a thread that is not owned by a module is running. */
#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0
#define TXM_MODULE_MPU_DEFAULT_RASR_0 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0
#define TXM_MODULE_MPU_DEFAULT_RASR_1 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0
#define TXM_MODULE_MPU_DEFAULT_RASR_2 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0
#define TXM_MODULE_MPU_DEFAULT_RASR_3 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0
#define TXM_MODULE_MPU_DEFAULT_RASR_4 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0
#define TXM_MODULE_MPU_DEFAULT_RASR_5 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0
#define TXM_MODULE_MPU_DEFAULT_RASR_6 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0
#define TXM_MODULE_MPU_DEFAULT_RASR_7 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0
#define TXM_MODULE_MPU_DEFAULT_RASR_8 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0
#define TXM_MODULE_MPU_DEFAULT_RASR_9 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0
#define TXM_MODULE_MPU_DEFAULT_RASR_10 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0
#define TXM_MODULE_MPU_DEFAULT_RASR_11 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0
#define TXM_MODULE_MPU_DEFAULT_RASR_12 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0
#define TXM_MODULE_MPU_DEFAULT_RASR_13 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0
#define TXM_MODULE_MPU_DEFAULT_RASR_14 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0
#define TXM_MODULE_MPU_DEFAULT_RASR_15 0
/* Define constants specific to the tools the module can be built with for this particular modules port. */
#define TXM_MODULE_IAR_COMPILER 0x00000000

51
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s
View File

@@ -40,7 +40,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M4/AC5 */
/* 6.1.11 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -76,6 +76,10 @@
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* added BASEPRI support, */
/* resulting in version 6.1.11 */
/* 07-29-2022 Scott Larson Removed the code path to skip */
/* MPU reloading, optional */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -385,26 +389,33 @@ __tx_ts_restore
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r3, #0 // Build disable value
CPSID i // Disable interrupts
STR r3, [r0] // Disable MPU
LDR r0, [r1, #0x90] // Pickup the module instance pointer
#ifdef TXM_MODULE_MPU_DEFAULT
CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup
#else
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
#endif
LDR r2, [r0, #0x8C] // Pickup MPU region 5 address
#ifdef TXM_MODULE_MPU_DEFAULT
CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup
#else
CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
// Is the MPU already set up for this module?
MOV r1, #5 // Select region 5 from MPU
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 5
#endif
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 5
BIC r2, r2, #0x10 // Clear VALID bit
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifdef TXM_MODULE_MPU_DEFAULT
B config_mpu // configure MPU for module
default_mpu:
LDR r0, =txm_module_default_mpu_registers // default MPU configuration
#endif
config_mpu:
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7
@@ -412,6 +423,7 @@ __tx_ts_restore
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 8-11
STM r1,{r2-r9} // Store MPU regions 8-11
// Regions 12-15 are reserved for the user to define.
LDM r0,{r2-r9} // Load MPU regions 12-15
STM r1,{r2-r9} // Store MPU regions 12-15
#endif
@@ -420,6 +432,7 @@ _tx_enable_mpu
MOV r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU
skip_mpu_setup
CPSIE i // Enable interrupts
LDMIA r12!, {LR} // Pickup LR
#ifdef __TARGET_FPU_VFP
TST LR, #0x10 // Determine if the VFP extended frame is present
@@ -573,14 +586,14 @@ _tx_no_lazy_clear:
#endif
/* Copy kernel hardware stack to module thread stack. */
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2} // Get r0, r1 from kernel stack
STM r0!, {r1-r2} // Insert r0, r1 into thread stack
LDM r3!, {r1-r2} // Get r2, r3 from kernel stack
STM r0!, {r1-r2} // Insert r2, r3 into thread stack
LDM r3!, {r1-r2} // Get r12, lr from kernel stack
STM r0!, {r1-r2} // Insert r12, lr into thread stack
LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack
STM r0!, {r1-r2} // Insert pc, xpsr into thread stack
SUB r0, r0, #32 // Subtract 32 to get back to top of stack
MSR PSP, r0 // Set thread stack pointer

71
ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -25,6 +25,43 @@
#include "tx_api.h"
#include "txm_module.h"
#ifdef TXM_MODULE_MPU_DEFAULT
const ULONG txm_module_default_mpu_registers[32] =
{
TXM_MODULE_MPU_DEFAULT_RBAR_0,
TXM_MODULE_MPU_DEFAULT_RASR_0,
TXM_MODULE_MPU_DEFAULT_RBAR_1,
TXM_MODULE_MPU_DEFAULT_RASR_1,
TXM_MODULE_MPU_DEFAULT_RBAR_2,
TXM_MODULE_MPU_DEFAULT_RASR_2,
TXM_MODULE_MPU_DEFAULT_RBAR_3,
TXM_MODULE_MPU_DEFAULT_RASR_3,
TXM_MODULE_MPU_DEFAULT_RBAR_4,
TXM_MODULE_MPU_DEFAULT_RASR_4,
TXM_MODULE_MPU_DEFAULT_RBAR_5,
TXM_MODULE_MPU_DEFAULT_RASR_5,
TXM_MODULE_MPU_DEFAULT_RBAR_6,
TXM_MODULE_MPU_DEFAULT_RASR_6,
TXM_MODULE_MPU_DEFAULT_RBAR_7,
TXM_MODULE_MPU_DEFAULT_RASR_7,
TXM_MODULE_MPU_DEFAULT_RBAR_8,
TXM_MODULE_MPU_DEFAULT_RASR_8,
TXM_MODULE_MPU_DEFAULT_RBAR_9,
TXM_MODULE_MPU_DEFAULT_RASR_9,
TXM_MODULE_MPU_DEFAULT_RBAR_10,
TXM_MODULE_MPU_DEFAULT_RASR_10,
TXM_MODULE_MPU_DEFAULT_RBAR_11,
TXM_MODULE_MPU_DEFAULT_RASR_11,
TXM_MODULE_MPU_DEFAULT_RBAR_12,
TXM_MODULE_MPU_DEFAULT_RASR_12,
TXM_MODULE_MPU_DEFAULT_RBAR_13,
TXM_MODULE_MPU_DEFAULT_RASR_13,
TXM_MODULE_MPU_DEFAULT_RBAR_14,
TXM_MODULE_MPU_DEFAULT_RASR_14,
TXM_MODULE_MPU_DEFAULT_RBAR_15,
TXM_MODULE_MPU_DEFAULT_RASR_15
};
#endif
/**************************************************************************/
/* */
@@ -231,7 +268,7 @@ UINT srd_bit_index;
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M4 */
/* 6.1.9 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -267,10 +304,10 @@ UINT srd_bit_index;
/* 9 Module shared memory region */
/* 10 Module shared memory region */
/* 11 Module shared memory region */
/* 12 Unused region */
/* 13 Unused region */
/* 14 Unused region */
/* 15 Unused region */
/* 12 User-defined region */
/* 13 User-defined region */
/* 14 User-defined region */
/* 15 User-defined region */
/* */
/* */
/* INPUT */
@@ -294,6 +331,8 @@ UINT srd_bit_index;
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 07-29-2022 Scott Larson Enable user defined regions, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
@@ -456,18 +495,18 @@ UINT i;
/* Increment MPU table index. */
mpu_table_index++;
}
/* Setup MPU for the remaining regions. */
while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES)
{
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10;
/* Increment MPU table index. */
mpu_table_index++;
}
#else
/* Setup user-defined regions (12-15). */
module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12;
module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12;
module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13;
module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13;
module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14;
module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14;
module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15;
module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15;
#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */
ULONG code_address;
ULONG code_size;

61
ports_module/cortex_m4/ac6/inc/txm_module_port.h
View File

@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M4/AC6 */
/* 6.1.10 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -44,6 +44,9 @@
/* 01-31-2022 Scott Larson Modified comments and made */
/* heap user-configurable, */
/* resulting in version 6.1.10 */
/* 07-29-2022 Scott Larson Enabled user-defined and */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
@@ -119,6 +122,60 @@ The following extensions must also be defined in tx_port.h:
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
#endif
/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15)
are not used by ThreadX. These may be defined by the user. */
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0
/* Users can define these default MPU configuration values.
If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled
when a thread that is not owned by a module is running
and the defines below are not used.
If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the
below values when a thread that is not owned by a module is running. */
#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0
#define TXM_MODULE_MPU_DEFAULT_RASR_0 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0
#define TXM_MODULE_MPU_DEFAULT_RASR_1 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0
#define TXM_MODULE_MPU_DEFAULT_RASR_2 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0
#define TXM_MODULE_MPU_DEFAULT_RASR_3 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0
#define TXM_MODULE_MPU_DEFAULT_RASR_4 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0
#define TXM_MODULE_MPU_DEFAULT_RASR_5 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0
#define TXM_MODULE_MPU_DEFAULT_RASR_6 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0
#define TXM_MODULE_MPU_DEFAULT_RASR_7 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0
#define TXM_MODULE_MPU_DEFAULT_RASR_8 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0
#define TXM_MODULE_MPU_DEFAULT_RASR_9 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0
#define TXM_MODULE_MPU_DEFAULT_RASR_10 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0
#define TXM_MODULE_MPU_DEFAULT_RASR_11 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0
#define TXM_MODULE_MPU_DEFAULT_RASR_12 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0
#define TXM_MODULE_MPU_DEFAULT_RASR_13 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0
#define TXM_MODULE_MPU_DEFAULT_RASR_14 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0
#define TXM_MODULE_MPU_DEFAULT_RASR_15 0
/* Define constants specific to the tools the module can be built with for this particular modules port. */
#define TXM_MODULE_IAR_COMPILER 0x00000000
@@ -384,6 +441,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC6 Version 6.1.9 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC6 Version 6.1.12 *";
#endif

2
ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c
View File

@@ -57,7 +57,7 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top);
/* FUNCTION RELEASE */
/* */
/* _txm_module_thread_shell_entry Cortex-M4/AC6 */
/* 6.1.10 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */

36
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S
View File

@@ -42,7 +42,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M4/AC6 */
/* 6.1.11 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -78,6 +78,10 @@
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* added BASEPRI support, */
/* resulting in version 6.1.11 */
/* 07-29-2022 Scott Larson Removed the code path to skip */
/* MPU reloading, optional */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -398,26 +402,33 @@ __tx_ts_restore:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r3, #0 // Build disable value
CPSID i // Disable interrupts
STR r3, [r0] // Disable MPU
LDR r0, [r1, #0x90] // Pickup the module instance pointer
#ifdef TXM_MODULE_MPU_DEFAULT
CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup
#else
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
#endif
LDR r2, [r0, #0x8C] // Pickup MPU region 5 address
#ifdef TXM_MODULE_MPU_DEFAULT
CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup
#else
CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
// Is the MPU already set up for this module?
MOV r1, #5 // Select region 5 from MPU
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 5
#endif
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 5
BIC r2, r2, #0x10 // Clear VALID bit
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifdef TXM_MODULE_MPU_DEFAULT
B config_mpu // configure MPU for module
default_mpu:
LDR r0, =txm_module_default_mpu_registers // default MPU configuration
#endif
config_mpu:
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7
@@ -425,14 +436,17 @@ __tx_ts_restore:
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 8-11
STM r1,{r2-r9} // Store MPU regions 8-11
// Regions 12-15 are reserved for the user to define.
LDM r0,{r2-r9} // Load MPU regions 12-15
STM r1,{r2-r9} // Store MPU regions 12-15
#endif
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU
skip_mpu_setup:
CPSIE i // Enable interrupts
LDMIA r12!, {LR} // Pickup LR
#ifdef __ARM_FP
TST LR, #0x10 // Determine if the VFP extended frame is present

71
ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -25,6 +25,43 @@
#include "tx_api.h"
#include "txm_module.h"
#ifdef TXM_MODULE_MPU_DEFAULT
const ULONG txm_module_default_mpu_registers[32] =
{
TXM_MODULE_MPU_DEFAULT_RBAR_0,
TXM_MODULE_MPU_DEFAULT_RASR_0,
TXM_MODULE_MPU_DEFAULT_RBAR_1,
TXM_MODULE_MPU_DEFAULT_RASR_1,
TXM_MODULE_MPU_DEFAULT_RBAR_2,
TXM_MODULE_MPU_DEFAULT_RASR_2,
TXM_MODULE_MPU_DEFAULT_RBAR_3,
TXM_MODULE_MPU_DEFAULT_RASR_3,
TXM_MODULE_MPU_DEFAULT_RBAR_4,
TXM_MODULE_MPU_DEFAULT_RASR_4,
TXM_MODULE_MPU_DEFAULT_RBAR_5,
TXM_MODULE_MPU_DEFAULT_RASR_5,
TXM_MODULE_MPU_DEFAULT_RBAR_6,
TXM_MODULE_MPU_DEFAULT_RASR_6,
TXM_MODULE_MPU_DEFAULT_RBAR_7,
TXM_MODULE_MPU_DEFAULT_RASR_7,
TXM_MODULE_MPU_DEFAULT_RBAR_8,
TXM_MODULE_MPU_DEFAULT_RASR_8,
TXM_MODULE_MPU_DEFAULT_RBAR_9,
TXM_MODULE_MPU_DEFAULT_RASR_9,
TXM_MODULE_MPU_DEFAULT_RBAR_10,
TXM_MODULE_MPU_DEFAULT_RASR_10,
TXM_MODULE_MPU_DEFAULT_RBAR_11,
TXM_MODULE_MPU_DEFAULT_RASR_11,
TXM_MODULE_MPU_DEFAULT_RBAR_12,
TXM_MODULE_MPU_DEFAULT_RASR_12,
TXM_MODULE_MPU_DEFAULT_RBAR_13,
TXM_MODULE_MPU_DEFAULT_RASR_13,
TXM_MODULE_MPU_DEFAULT_RBAR_14,
TXM_MODULE_MPU_DEFAULT_RASR_14,
TXM_MODULE_MPU_DEFAULT_RBAR_15,
TXM_MODULE_MPU_DEFAULT_RASR_15
};
#endif
/**************************************************************************/
/* */
@@ -231,7 +268,7 @@ UINT srd_bit_index;
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M4 */
/* 6.1.9 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -267,10 +304,10 @@ UINT srd_bit_index;
/* 9 Module shared memory region */
/* 10 Module shared memory region */
/* 11 Module shared memory region */
/* 12 Unused region */
/* 13 Unused region */
/* 14 Unused region */
/* 15 Unused region */
/* 12 User-defined region */
/* 13 User-defined region */
/* 14 User-defined region */
/* 15 User-defined region */
/* */
/* */
/* INPUT */
@@ -294,6 +331,8 @@ UINT srd_bit_index;
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 07-29-2022 Scott Larson Enable user defined regions, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
@@ -456,18 +495,18 @@ UINT i;
/* Increment MPU table index. */
mpu_table_index++;
}
/* Setup MPU for the remaining regions. */
while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES)
{
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10;
/* Increment MPU table index. */
mpu_table_index++;
}
#else
/* Setup user-defined regions (12-15). */
module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12;
module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12;
module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13;
module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13;
module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14;
module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14;
module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15;
module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15;
#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */
ULONG code_address;
ULONG code_size;

5
ports_module/cortex_m4/gnu/example_build/build_threadx_sample.bat Normal file
View File

@@ -0,0 +1,5 @@
arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb cortexm_vectors.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb cortexm_crt0.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb tx_initialize_low_level.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I..\inc -I..\..\..\..\common\inc sample_threadx.c
arm-none-eabi-gcc -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -T sample_threadx.ld -ereset_handler -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm_vectors.o cortexm_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a

127
ports_module/cortex_m4/gnu/example_build/cortexm_crt0.S Normal file
View File

@@ -0,0 +1,127 @@
.global _start
.extern main
.section .init, "ax"
.code 16
.align 2
.thumb_func
_start:
CPSID i
ldr r1, =__stack_end__
mov sp, r1
/* Copy initialised sections into RAM if required. */
ldr r0, =__data_load_start__
ldr r1, =__data_start__
ldr r2, =__data_end__
bl crt0_memory_copy
ldr r0, =__text_load_start__
ldr r1, =__text_start__
ldr r2, =__text_end__
bl crt0_memory_copy
ldr r0, =__fast_load_start__
ldr r1, =__fast_start__
ldr r2, =__fast_end__
bl crt0_memory_copy
ldr r0, =__ctors_load_start__
ldr r1, =__ctors_start__
ldr r2, =__ctors_end__
bl crt0_memory_copy
ldr r0, =__dtors_load_start__
ldr r1, =__dtors_start__
ldr r2, =__dtors_end__
bl crt0_memory_copy
ldr r0, =__rodata_load_start__
ldr r1, =__rodata_start__
ldr r2, =__rodata_end__
bl crt0_memory_copy
/* Zero bss. */
ldr r0, =__bss_start__
ldr r1, =__bss_end__
mov r2, #0
bl crt0_memory_set
/* Setup heap - not recommended for Threadx but here for compatibility reasons */
ldr r0, = __heap_start__
ldr r1, = __heap_end__
sub r1, r1, r0
mov r2, #0
str r2, [r0]
add r0, r0, #4
str r1, [r0]
/* constructors in case of using C++ */
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
crt0_ctor_loop:
cmp r0, r1
beq crt0_ctor_end
ldr r2, [r0]
add r0, #4
push {r0-r1}
blx r2
pop {r0-r1}
b crt0_ctor_loop
crt0_ctor_end:
/* Setup call frame for main() */
mov r0, #0
mov lr, r0
mov r12, sp
start:
/* Jump to main() */
mov r0, #0
mov r1, #0
ldr r2, =main
blx r2
/* when main returns, loop forever. */
crt0_exit_loop:
b crt0_exit_loop
/* Startup helper functions. */
crt0_memory_copy:
cmp r0, r1
beq memory_copy_done
sub r2, r2, r1
beq memory_copy_done
memory_copy_loop:
ldrb r3, [r0]
add r0, r0, #1
strb r3, [r1]
add r1, r1, #1
sub r2, r2, #1
bne memory_copy_loop
memory_copy_done:
bx lr
crt0_memory_set:
cmp r0, r1
beq memory_set_done
strb r2, [r0]
add r0, r0, #1
b crt0_memory_set
memory_set_done:
bx lr
/* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
.section .stack, "wa", %nobits
.section .stack_process, "wa", %nobits
.section .heap, "wa", %nobits

77
ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S Normal file
View File

@@ -0,0 +1,77 @@
.global reset_handler
.global __tx_NMIHandler
.global __tx_BadHandler
.global __tx_SVCallHandler
.global __tx_DBGHandler
.global __tx_PendSVHandler
.global __tx_SysTickHandler
.global __tx_BadHandler
.syntax unified
.section .vectors, "ax"
.code 16
.align 0
.global _vectors
_vectors:
.word __stack_end__
.word reset_handler
.word __tx_NMIHandler
.word __tx_HardfaultHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler //
.word __tx_DBGHandler
.word 0 // Reserved
.word __tx_PendSVHandler
.word __tx_SysTickHandler // Used by Threadx timer functionality
.word __tx_BadHandler // Populate with user Interrupt handler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.word __tx_BadHandler
.section .init, "ax"
.thumb_func
reset_handler:
// low level hardware config, such as PLL setup goes here
b _start

61
ports_module/cortex_m4/gnu/inc/txm_module_port.h
View File

@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M4/GNU */
/* 6.1.9 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -41,6 +41,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 07-29-2022 Scott Larson Enabled user-defined and */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
@@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h:
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
#endif
/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15)
are not used by ThreadX. These may be defined by the user. */
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0
/* Users can define these default MPU configuration values.
If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled
when a thread that is not owned by a module is running
and the defines below are not used.
If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the
below values when a thread that is not owned by a module is running. */
#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0
#define TXM_MODULE_MPU_DEFAULT_RASR_0 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0
#define TXM_MODULE_MPU_DEFAULT_RASR_1 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0
#define TXM_MODULE_MPU_DEFAULT_RASR_2 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0
#define TXM_MODULE_MPU_DEFAULT_RASR_3 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0
#define TXM_MODULE_MPU_DEFAULT_RASR_4 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0
#define TXM_MODULE_MPU_DEFAULT_RASR_5 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0
#define TXM_MODULE_MPU_DEFAULT_RASR_6 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0
#define TXM_MODULE_MPU_DEFAULT_RASR_7 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0
#define TXM_MODULE_MPU_DEFAULT_RASR_8 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0
#define TXM_MODULE_MPU_DEFAULT_RASR_9 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0
#define TXM_MODULE_MPU_DEFAULT_RASR_10 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0
#define TXM_MODULE_MPU_DEFAULT_RASR_11 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0
#define TXM_MODULE_MPU_DEFAULT_RASR_12 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0
#define TXM_MODULE_MPU_DEFAULT_RASR_13 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0
#define TXM_MODULE_MPU_DEFAULT_RASR_14 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0
#define TXM_MODULE_MPU_DEFAULT_RASR_15 0
/* Define constants specific to the tools the module can be built with for this particular modules port. */
#define TXM_MODULE_IAR_COMPILER 0x00000000
@@ -376,6 +433,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/GNU Version 6.1.9 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/GNU Version 6.1.12 *";
#endif

52
ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S
View File

@@ -40,7 +40,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M4/GNU */
/* 6.1.11 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -78,6 +78,10 @@
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* added BASEPRI support, */
/* resulting in version 6.1.11 */
/* 07-29-2022 Scott Larson Removed the code path to skip */
/* MPU reloading, optional */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -398,26 +402,33 @@ __tx_ts_restore:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r3, #0 // Build disable value
CPSID i // Disable interrupts
STR r3, [r0] // Disable MPU
LDR r0, [r1, #0x90] // Pickup the module instance pointer
#ifdef TXM_MODULE_MPU_DEFAULT
CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup
#else
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
#endif
LDR r2, [r0, #0x8C] // Pickup MPU region 5 address
#ifdef TXM_MODULE_MPU_DEFAULT
CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup
#else
CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
// Is the MPU already set up for this module?
MOV r1, #5 // Select region 5 from MPU
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 5
#endif
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 5
BIC r2, r2, #0x10 // Clear VALID bit
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifdef TXM_MODULE_MPU_DEFAULT
B config_mpu // configure MPU for module
default_mpu:
LDR r0, =txm_module_default_mpu_registers // default MPU configuration
#endif
config_mpu:
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7
@@ -425,14 +436,17 @@ __tx_ts_restore:
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 8-11
STM r1,{r2-r9} // Store MPU regions 8-11
// Regions 12-15 are reserved for the user to define.
LDM r0,{r2-r9} // Load MPU regions 12-15
STM r1,{r2-r9} // Store MPU regions 12-15
#endif
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU
skip_mpu_setup:
CPSIE i // Enable interrupts
LDMIA r12!, {LR} // Pickup LR
#ifdef __ARM_FP
TST LR, #0x10 // Determine if the VFP extended frame is present
@@ -588,14 +602,14 @@ _tx_no_lazy_clear:
#endif
/* Copy kernel hardware stack to module thread stack. */
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2} // Get r0, r1 from kernel stack
STM r0!, {r1-r2} // Insert r0, r1 into thread stack
LDM r3!, {r1-r2} // Get r2, r3 from kernel stack
STM r0!, {r1-r2} // Insert r2, r3 into thread stack
LDM r3!, {r1-r2} // Get r12, lr from kernel stack
STM r0!, {r1-r2} // Insert r12, lr into thread stack
LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack
STM r0!, {r1-r2} // Insert pc, xpsr into thread stack
SUB r0, r0, #32 // Subtract 32 to get back to top of stack
MSR PSP, r0 // Set thread stack pointer

71
ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -25,6 +25,43 @@
#include "tx_api.h"
#include "txm_module.h"
#ifdef TXM_MODULE_MPU_DEFAULT
const ULONG txm_module_default_mpu_registers[32] =
{
TXM_MODULE_MPU_DEFAULT_RBAR_0,
TXM_MODULE_MPU_DEFAULT_RASR_0,
TXM_MODULE_MPU_DEFAULT_RBAR_1,
TXM_MODULE_MPU_DEFAULT_RASR_1,
TXM_MODULE_MPU_DEFAULT_RBAR_2,
TXM_MODULE_MPU_DEFAULT_RASR_2,
TXM_MODULE_MPU_DEFAULT_RBAR_3,
TXM_MODULE_MPU_DEFAULT_RASR_3,
TXM_MODULE_MPU_DEFAULT_RBAR_4,
TXM_MODULE_MPU_DEFAULT_RASR_4,
TXM_MODULE_MPU_DEFAULT_RBAR_5,
TXM_MODULE_MPU_DEFAULT_RASR_5,
TXM_MODULE_MPU_DEFAULT_RBAR_6,
TXM_MODULE_MPU_DEFAULT_RASR_6,
TXM_MODULE_MPU_DEFAULT_RBAR_7,
TXM_MODULE_MPU_DEFAULT_RASR_7,
TXM_MODULE_MPU_DEFAULT_RBAR_8,
TXM_MODULE_MPU_DEFAULT_RASR_8,
TXM_MODULE_MPU_DEFAULT_RBAR_9,
TXM_MODULE_MPU_DEFAULT_RASR_9,
TXM_MODULE_MPU_DEFAULT_RBAR_10,
TXM_MODULE_MPU_DEFAULT_RASR_10,
TXM_MODULE_MPU_DEFAULT_RBAR_11,
TXM_MODULE_MPU_DEFAULT_RASR_11,
TXM_MODULE_MPU_DEFAULT_RBAR_12,
TXM_MODULE_MPU_DEFAULT_RASR_12,
TXM_MODULE_MPU_DEFAULT_RBAR_13,
TXM_MODULE_MPU_DEFAULT_RASR_13,
TXM_MODULE_MPU_DEFAULT_RBAR_14,
TXM_MODULE_MPU_DEFAULT_RASR_14,
TXM_MODULE_MPU_DEFAULT_RBAR_15,
TXM_MODULE_MPU_DEFAULT_RASR_15
};
#endif
/**************************************************************************/
/* */
@@ -231,7 +268,7 @@ UINT srd_bit_index;
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M4 */
/* 6.1.9 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -267,10 +304,10 @@ UINT srd_bit_index;
/* 9 Module shared memory region */
/* 10 Module shared memory region */
/* 11 Module shared memory region */
/* 12 Unused region */
/* 13 Unused region */
/* 14 Unused region */
/* 15 Unused region */
/* 12 User-defined region */
/* 13 User-defined region */
/* 14 User-defined region */
/* 15 User-defined region */
/* */
/* */
/* INPUT */
@@ -294,6 +331,8 @@ UINT srd_bit_index;
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 07-29-2022 Scott Larson Enable user defined regions, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
@@ -456,18 +495,18 @@ UINT i;
/* Increment MPU table index. */
mpu_table_index++;
}
/* Setup MPU for the remaining regions. */
while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES)
{
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10;
/* Increment MPU table index. */
mpu_table_index++;
}
#else
/* Setup user-defined regions (12-15). */
module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12;
module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12;
module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13;
module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13;
module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14;
module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14;
module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15;
module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15;
#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */
ULONG code_address;
ULONG code_size;

61
ports_module/cortex_m4/iar/inc/txm_module_port.h
View File

@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-M4/IAR */
/* 6.1.9 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -41,6 +41,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 07-29-2022 Scott Larson Enabled user-defined and */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
@@ -112,6 +115,60 @@ The following extensions must also be defined in tx_port.h:
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
#endif
/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15)
are not used by ThreadX. These may be defined by the user. */
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0
#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0
#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0
/* Users can define these default MPU configuration values.
If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled
when a thread that is not owned by a module is running
and the defines below are not used.
If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the
below values when a thread that is not owned by a module is running. */
#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0
#define TXM_MODULE_MPU_DEFAULT_RASR_0 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0
#define TXM_MODULE_MPU_DEFAULT_RASR_1 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0
#define TXM_MODULE_MPU_DEFAULT_RASR_2 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0
#define TXM_MODULE_MPU_DEFAULT_RASR_3 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0
#define TXM_MODULE_MPU_DEFAULT_RASR_4 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0
#define TXM_MODULE_MPU_DEFAULT_RASR_5 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0
#define TXM_MODULE_MPU_DEFAULT_RASR_6 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0
#define TXM_MODULE_MPU_DEFAULT_RASR_7 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0
#define TXM_MODULE_MPU_DEFAULT_RASR_8 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0
#define TXM_MODULE_MPU_DEFAULT_RASR_9 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0
#define TXM_MODULE_MPU_DEFAULT_RASR_10 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0
#define TXM_MODULE_MPU_DEFAULT_RASR_11 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0
#define TXM_MODULE_MPU_DEFAULT_RASR_12 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0
#define TXM_MODULE_MPU_DEFAULT_RASR_13 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0
#define TXM_MODULE_MPU_DEFAULT_RASR_14 0
#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0
#define TXM_MODULE_MPU_DEFAULT_RASR_15 0
/* Define constants specific to the tools the module can be built with for this particular modules port. */
#define TXM_MODULE_IAR_COMPILER 0x00000000
@@ -377,6 +434,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance
#define TXM_MODULE_MANAGER_VERSION_ID \
CHAR _txm_module_manager_version_id[] = \
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/IAR Version 6.1.10 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/IAR Version 6.1.12 *";
#endif

53
ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s
View File

@@ -28,6 +28,7 @@
EXTERN _tx_thread_preempt_disable
EXTERN _txm_module_manager_memory_fault_handler
EXTERN _txm_module_manager_memory_fault_info
EXTERN txm_module_default_mpu_registers
SECTION `.text`:CODE:NOROOT(2)
THUMB
@@ -36,7 +37,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M4/IAR */
/* 6.1.11 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -72,6 +73,10 @@
/* 04-25-2022 Scott Larson Optimized MPU configuration, */
/* added BASEPRI support, */
/* resulting in version 6.1.11 */
/* 07-29-2022 Scott Larson Removed the code path to skip */
/* MPU reloading, optional */
/* default MPU settings, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -385,26 +390,33 @@ __tx_ts_restore:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r3, #0 // Build disable value
CPSID i // Disable interrupts
STR r3, [r0] // Disable MPU
LDR r0, [r1, #0x90] // Pickup the module instance pointer
#ifdef TXM_MODULE_MPU_DEFAULT
CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup
#else
CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup
#endif
LDR r2, [r0, #0x8C] // Pickup MPU region 5 address
#ifdef TXM_MODULE_MPU_DEFAULT
CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup
#else
CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup
// Is the MPU already set up for this module?
MOV r1, #5 // Select region 5 from MPU
LDR r3, =0xE000ED98 // MPU_RNR register address
STR r1, [r3] // Set region to 5
#endif
LDR r1, =0xE000ED9C // MPU_RBAR register address
LDR r3, [r1] // Load address stored in MPU region 5
BIC r2, r2, #0x10 // Clear VALID bit
CMP r2, r3 // Is module already loaded?
BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration
// Use alias registers to quickly load MPU
ADD r0, r0, #100 // Build address of MPU register start in thread control block
#ifdef TXM_MODULE_MPU_DEFAULT
B config_mpu // configure MPU for module
default_mpu:
LDR r0, =txm_module_default_mpu_registers // default MPU configuration
#endif
config_mpu:
LDM r0!,{r2-r9} // Load MPU regions 0-3
STM r1,{r2-r9} // Store MPU regions 0-3
LDM r0!,{r2-r9} // Load MPU regions 4-7
@@ -412,14 +424,17 @@ __tx_ts_restore:
#ifdef TXM_MODULE_MANAGER_16_MPU
LDM r0!,{r2-r9} // Load MPU regions 8-11
STM r1,{r2-r9} // Store MPU regions 8-11
// Regions 12-15 are reserved for the user to define.
LDM r0,{r2-r9} // Load MPU regions 12-15
STM r1,{r2-r9} // Store MPU regions 12-15
#endif
_tx_enable_mpu:
LDR r0, =0xE000ED94 // Build MPU control reg address
MOV r1, #5 // Build enable value with background region enabled
STR r1, [r0] // Enable MPU
skip_mpu_setup:
CPSIE i // Enable interrupts
LDMIA r12!, {LR} // Pickup LR
#ifdef __ARMVFP__
TST LR, #0x10 // Determine if the VFP extended frame is present
@@ -574,14 +589,14 @@ _tx_no_lazy_clear:
#endif
/* Copy kernel hardware stack to module thread stack. */
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2}
STM r0!, {r1-r2}
LDM r3!, {r1-r2} // Get r0, r1 from kernel stack
STM r0!, {r1-r2} // Insert r0, r1 into thread stack
LDM r3!, {r1-r2} // Get r2, r3 from kernel stack
STM r0!, {r1-r2} // Insert r2, r3 into thread stack
LDM r3!, {r1-r2} // Get r12, lr from kernel stack
STM r0!, {r1-r2} // Insert r12, lr into thread stack
LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack
STM r0!, {r1-r2} // Insert pc, xpsr into thread stack
SUB r0, r0, #32 // Subtract 32 to get back to top of stack
MSR PSP, r0 // Set thread stack pointer

71
ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c
View File

@@ -25,6 +25,43 @@
#include "tx_api.h"
#include "txm_module.h"
#ifdef TXM_MODULE_MPU_DEFAULT
const ULONG txm_module_default_mpu_registers[32] =
{
TXM_MODULE_MPU_DEFAULT_RBAR_0,
TXM_MODULE_MPU_DEFAULT_RASR_0,
TXM_MODULE_MPU_DEFAULT_RBAR_1,
TXM_MODULE_MPU_DEFAULT_RASR_1,
TXM_MODULE_MPU_DEFAULT_RBAR_2,
TXM_MODULE_MPU_DEFAULT_RASR_2,
TXM_MODULE_MPU_DEFAULT_RBAR_3,
TXM_MODULE_MPU_DEFAULT_RASR_3,
TXM_MODULE_MPU_DEFAULT_RBAR_4,
TXM_MODULE_MPU_DEFAULT_RASR_4,
TXM_MODULE_MPU_DEFAULT_RBAR_5,
TXM_MODULE_MPU_DEFAULT_RASR_5,
TXM_MODULE_MPU_DEFAULT_RBAR_6,
TXM_MODULE_MPU_DEFAULT_RASR_6,
TXM_MODULE_MPU_DEFAULT_RBAR_7,
TXM_MODULE_MPU_DEFAULT_RASR_7,
TXM_MODULE_MPU_DEFAULT_RBAR_8,
TXM_MODULE_MPU_DEFAULT_RASR_8,
TXM_MODULE_MPU_DEFAULT_RBAR_9,
TXM_MODULE_MPU_DEFAULT_RASR_9,
TXM_MODULE_MPU_DEFAULT_RBAR_10,
TXM_MODULE_MPU_DEFAULT_RASR_10,
TXM_MODULE_MPU_DEFAULT_RBAR_11,
TXM_MODULE_MPU_DEFAULT_RASR_11,
TXM_MODULE_MPU_DEFAULT_RBAR_12,
TXM_MODULE_MPU_DEFAULT_RASR_12,
TXM_MODULE_MPU_DEFAULT_RBAR_13,
TXM_MODULE_MPU_DEFAULT_RASR_13,
TXM_MODULE_MPU_DEFAULT_RBAR_14,
TXM_MODULE_MPU_DEFAULT_RASR_14,
TXM_MODULE_MPU_DEFAULT_RBAR_15,
TXM_MODULE_MPU_DEFAULT_RASR_15
};
#endif
/**************************************************************************/
/* */
@@ -231,7 +268,7 @@ UINT srd_bit_index;
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_mm_register_setup Cortex-M4 */
/* 6.1.9 */
/* 6.1.12 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -267,10 +304,10 @@ UINT srd_bit_index;
/* 9 Module shared memory region */
/* 10 Module shared memory region */
/* 11 Module shared memory region */
/* 12 Unused region */
/* 13 Unused region */
/* 14 Unused region */
/* 15 Unused region */
/* 12 User-defined region */
/* 13 User-defined region */
/* 14 User-defined region */
/* 15 User-defined region */
/* */
/* */
/* INPUT */
@@ -294,6 +331,8 @@ UINT srd_bit_index;
/* DATE NAME DESCRIPTION */
/* */
/* 10-15-2021 Scott Larson Initial Version 6.1.9 */
/* 07-29-2022 Scott Larson Enable user defined regions, */
/* resulting in version 6.1.12 */
/* */
/**************************************************************************/
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
@@ -456,18 +495,18 @@ UINT i;
/* Increment MPU table index. */
mpu_table_index++;
}
/* Setup MPU for the remaining regions. */
while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES)
{
/* Build the base address register with address, MPU region, set Valid bit. */
module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10;
/* Increment MPU table index. */
mpu_table_index++;
}
#else
/* Setup user-defined regions (12-15). */
module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12;
module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12;
module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13;
module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13;
module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14;
module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14;
module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15;
module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15;
#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */
ULONG code_address;
ULONG code_size;