mirror of
https://github.com/eclipse-threadx/threadx.git
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Fixed the issue of the data/bss section cannot be read from ARM FVP d… (#301)
* Fixed the issue of the data/bss section cannot be read from ARM FVP debug tool in cortex-A7 GNU port. https://msazure.visualstudio.com/One/_workitems/edit/24597276/ * remove untracked files.
This commit is contained in:
Yajun Xia
@@ -79,6 +79,14 @@ _mainCRTStartup:
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#endif
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#endif
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.global _fini
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.type _fini,function
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_fini:
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#ifdef __THUMB_INTERWORK
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BX lr // Return to caller
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#else
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MOV pc, lr // Return to caller
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#endif
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/* Workspace for Angel calls. */
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.data
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@@ -109,7 +109,7 @@ SECTIONS
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.eh_frame_hdr : { *(.eh_frame_hdr) }
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/* Adjust the address for the data segment. We want to adjust up to
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the same address within the page on the next page up. */
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. = ALIGN(256) + (. & (256 - 1));
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. = 0x2E000000;
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.data :
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{
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*(.data)
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@@ -1,311 +0,0 @@
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/**************************************************************************/
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/* */
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/* Copyright (c) Microsoft Corporation. All rights reserved. */
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/* */
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/* This software is licensed under the Microsoft Software License */
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/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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/* and in the root directory of this software. */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Initialize */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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#ifdef TX_INCLUDE_USER_DEFINE_FILE
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#include "tx_user.h"
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#endif
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.arm
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SVC_MODE = 0xD3 // Disable IRQ/FIQ SVC mode
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IRQ_MODE = 0xD2 // Disable IRQ/FIQ IRQ mode
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FIQ_MODE = 0xD1 // Disable IRQ/FIQ FIQ mode
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SYS_MODE = 0xDF // Disable IRQ/FIQ SYS mode
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FIQ_STACK_SIZE = 512 // FIQ stack size
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IRQ_STACK_SIZE = 1024 // IRQ stack size
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SYS_STACK_SIZE = 1024 // System stack size
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.global _tx_thread_system_stack_ptr
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.global _tx_initialize_unused_memory
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.global _tx_thread_context_save
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.global _tx_thread_context_restore
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.global _tx_timer_interrupt
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.global _end
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.global _sp
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.global _stack_bottom
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/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for
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applications calling this function from to 16-bit Thumb mode. */
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.text
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.align 2
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.thumb
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.global $_tx_initialize_low_level
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.type $_tx_initialize_low_level,function
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$_tx_initialize_low_level:
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BX pc // Switch to 32-bit mode
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NOP //
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.arm
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STMFD sp!, {lr} // Save return address
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BL _tx_initialize_low_level // Call _tx_initialize_low_level function
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LDMFD sp!, {lr} // Recover saved return address
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BX lr // Return to 16-bit caller
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.text
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.align 2
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* _tx_initialize_low_level ARMv7-A */
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/* 6.x */
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/* AUTHOR */
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/* */
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/* William E. Lamie, Microsoft Corporation */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function is responsible for any low-level processor */
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/* initialization, including setting up interrupt vectors, setting */
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/* up a periodic timer interrupt source, saving the system stack */
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/* pointer for use in ISR processing later, and finding the first */
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/* available RAM memory address for tx_application_define. */
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/* */
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/* INPUT */
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/* */
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/* None */
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/* */
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/* OUTPUT */
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/* */
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/* None */
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/* */
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/* CALLS */
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/* */
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/* None */
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/* */
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/* CALLED BY */
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/* */
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/* _tx_initialize_kernel_enter ThreadX entry function */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 09-30-2020 William E. Lamie Initial Version 6.1 */
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/* 04-25-2022 Zhen Kong Updated comments, */
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/* resulting in version 6.1.11 */
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/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */
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/* #include tx_user.h, */
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/* resulting in version 6.x */
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/* */
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/**************************************************************************/
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.global _tx_initialize_low_level
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.type _tx_initialize_low_level,function
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_tx_initialize_low_level:
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/* We must be in SVC mode at this point! */
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/* Setup various stack pointers. */
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LDR r1, =_sp // Get pointer to stack area
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#ifdef TX_ENABLE_IRQ_NESTING
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/* Setup the system mode stack for nested interrupt support */
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LDR r2, =SYS_STACK_SIZE // Pickup stack size
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MOV r3, #SYS_MODE // Build SYS mode CPSR
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MSR CPSR_c, r3 // Enter SYS mode
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SUB r1, r1, #1 // Backup 1 byte
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BIC r1, r1, #7 // Ensure 8-byte alignment
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MOV sp, r1 // Setup SYS stack pointer
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SUB r1, r1, r2 // Calculate start of next stack
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#endif
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LDR r2, =FIQ_STACK_SIZE // Pickup stack size
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MOV r0, #FIQ_MODE // Build FIQ mode CPSR
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MSR CPSR, r0 // Enter FIQ mode
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SUB r1, r1, #1 // Backup 1 byte
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BIC r1, r1, #7 // Ensure 8-byte alignment
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MOV sp, r1 // Setup FIQ stack pointer
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SUB r1, r1, r2 // Calculate start of next stack
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LDR r2, =IRQ_STACK_SIZE // Pickup IRQ stack size
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MOV r0, #IRQ_MODE // Build IRQ mode CPSR
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MSR CPSR, r0 // Enter IRQ mode
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SUB r1, r1, #1 // Backup 1 byte
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BIC r1, r1, #7 // Ensure 8-byte alignment
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MOV sp, r1 // Setup IRQ stack pointer
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SUB r3, r1, r2 // Calculate end of IRQ stack
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MOV r0, #SVC_MODE // Build SVC mode CPSR
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MSR CPSR, r0 // Enter SVC mode
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LDR r2, =_stack_bottom // Pickup stack bottom
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CMP r3, r2 // Compare the current stack end with the bottom
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_stack_error_loop:
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BLT _stack_error_loop // If the IRQ stack exceeds the stack bottom, just sit here!
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LDR r2, =_tx_thread_system_stack_ptr // Pickup stack pointer
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STR r1, [r2] // Save the system stack
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LDR r1, =_end // Get end of non-initialized RAM area
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LDR r2, =_tx_initialize_unused_memory // Pickup unused memory ptr address
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ADD r1, r1, #8 // Increment to next free word
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STR r1, [r2] // Save first free memory address
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#ifdef __THUMB_INTERWORK
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BX lr // Return to caller
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#else
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MOV pc, lr // Return to caller
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#endif
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/* Define shells for each of the interrupt vectors. */
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.global __tx_undefined
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__tx_undefined:
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B __tx_undefined // Undefined handler
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.global __tx_swi_interrupt
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__tx_swi_interrupt:
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B __tx_swi_interrupt // Software interrupt handler
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.global __tx_prefetch_handler
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__tx_prefetch_handler:
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B __tx_prefetch_handler // Prefetch exception handler
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.global __tx_abort_handler
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__tx_abort_handler:
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B __tx_abort_handler // Abort exception handler
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.global __tx_reserved_handler
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__tx_reserved_handler:
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B __tx_reserved_handler // Reserved exception handler
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.global __tx_irq_handler
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.global __tx_irq_processing_return
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__tx_irq_handler:
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/* Jump to context save to save system context. */
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B _tx_thread_context_save
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__tx_irq_processing_return:
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//
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/* At this point execution is still in the IRQ mode. The CPSR, point of
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interrupt, and all C scratch registers are available for use. In
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addition, IRQ interrupts may be re-enabled - with certain restrictions -
|
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if nested IRQ interrupts are desired. Interrupts may be re-enabled over
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small code sequences where lr is saved before enabling interrupts and
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restored after interrupts are again disabled. */
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/* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
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from IRQ mode with interrupts disabled. This routine switches to the
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system mode and returns with IRQ interrupts enabled.
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NOTE: It is very important to ensure all IRQ interrupts are cleared
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prior to enabling nested IRQ interrupts. */
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#ifdef TX_ENABLE_IRQ_NESTING
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BL _tx_thread_irq_nesting_start
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#endif
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/* For debug purpose, execute the timer interrupt processing here. In
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a real system, some kind of status indication would have to be checked
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before the timer interrupt handler could be called. */
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BL _tx_timer_interrupt // Timer interrupt handler
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/* If interrupt nesting was started earlier, the end of interrupt nesting
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service must be called before returning to _tx_thread_context_restore.
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This routine returns in processing in IRQ mode with interrupts disabled. */
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#ifdef TX_ENABLE_IRQ_NESTING
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BL _tx_thread_irq_nesting_end
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#endif
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/* Jump to context restore to restore system context. */
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B _tx_thread_context_restore
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/* This is an example of a vectored IRQ handler. */
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/* Save initial context and call context save to prepare for
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vectored ISR execution. */
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/* At this point execution is still in the IRQ mode. The CPSR, point of
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interrupt, and all C scratch registers are available for use. In
|
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addition, IRQ interrupts may be re-enabled - with certain restrictions -
|
||||
if nested IRQ interrupts are desired. Interrupts may be re-enabled over
|
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small code sequences where lr is saved before enabling interrupts and
|
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restored after interrupts are again disabled. */
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/* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
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from IRQ mode with interrupts disabled. This routine switches to the
|
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system mode and returns with IRQ interrupts enabled.
|
||||
|
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NOTE: It is very important to ensure all IRQ interrupts are cleared
|
||||
prior to enabling nested IRQ interrupts. */
|
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|
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/* Application IRQ handlers can be called here! */
|
||||
|
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/* If interrupt nesting was started earlier, the end of interrupt nesting
|
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service must be called before returning to _tx_thread_context_restore.
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This routine returns in processing in IRQ mode with interrupts disabled. */
|
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|
||||
#ifdef TX_ENABLE_FIQ_SUPPORT
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.global __tx_fiq_handler
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.global __tx_fiq_processing_return
|
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__tx_fiq_handler:
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/* Jump to fiq context save to save system context. */
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B _tx_thread_fiq_context_save
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__tx_fiq_processing_return:
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/* At this point execution is still in the FIQ mode. The CPSR, point of
|
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interrupt, and all C scratch registers are available for use. */
|
||||
|
||||
/* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start
|
||||
from FIQ mode with interrupts disabled. This routine switches to the
|
||||
system mode and returns with FIQ interrupts enabled.
|
||||
|
||||
NOTE: It is very important to ensure all FIQ interrupts are cleared
|
||||
prior to enabling nested FIQ interrupts. */
|
||||
#ifdef TX_ENABLE_FIQ_NESTING
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||||
BL _tx_thread_fiq_nesting_start
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||||
#endif
|
||||
|
||||
/* Application FIQ handlers can be called here! */
|
||||
|
||||
/* If interrupt nesting was started earlier, the end of interrupt nesting
|
||||
service must be called before returning to _tx_thread_fiq_context_restore. */
|
||||
#ifdef TX_ENABLE_FIQ_NESTING
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BL _tx_thread_fiq_nesting_end
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||||
#endif
|
||||
|
||||
/* Jump to fiq context restore to restore system context. */
|
||||
B _tx_thread_fiq_context_restore
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||||
|
||||
|
||||
#else
|
||||
.global __tx_fiq_handler
|
||||
__tx_fiq_handler:
|
||||
B __tx_fiq_handler // FIQ interrupt handler
|
||||
#endif
|
||||
|
||||
|
||||
BUILD_OPTIONS:
|
||||
.word _tx_build_options // Reference to bring in
|
||||
VERSION_ID:
|
||||
.word _tx_version_id // Reference to bring in
|
||||
|
||||
|
||||
|
||||
155
ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h
Normal file
155
ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h
Normal file
@@ -0,0 +1,155 @@
|
||||
// ------------------------------------------------------------
|
||||
// v7-A Cache, TLB and Branch Prediction Maintenance Operations
|
||||
// Header File
|
||||
//
|
||||
// Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved.
|
||||
// Use, modification and redistribution of this file is subject to your possession of a
|
||||
// valid End User License Agreement for the Arm Product of which these examples are part of
|
||||
// and your compliance with all applicable terms and conditions of such licence agreement.
|
||||
// ------------------------------------------------------------
|
||||
|
||||
#ifndef _ARMV7A_GENERIC_H
|
||||
#define _ARMV7A_GENERIC_H
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Memory barrier mnemonics
|
||||
enum MemBarOpt {
|
||||
RESERVED_0 = 0, RESERVED_1 = 1, OSHST = 2, OSH = 3,
|
||||
RESERVED_4 = 4, RESERVED_5 = 5, NSHST = 6, NSH = 7,
|
||||
RESERVED_8 = 8, RESERVED_9 = 9, ISHST = 10, ISH = 11,
|
||||
RESERVED_12 = 12, RESERVED_13 = 13, ST = 14, SY = 15
|
||||
};
|
||||
|
||||
//
|
||||
// Note:
|
||||
// *_IS() stands for "inner shareable"
|
||||
// DO NOT USE THESE FUNCTIONS ON A CORTEX-A8
|
||||
//
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Interrupts
|
||||
// Enable/disables IRQs (not FIQs)
|
||||
void enableInterrupts(void);
|
||||
void disableInterrupts(void);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Caches
|
||||
|
||||
void invalidateCaches_IS(void);
|
||||
void cleanInvalidateDCache(void);
|
||||
void invalidateCaches_IS(void);
|
||||
void enableCaches(void);
|
||||
void disableCaches(void);
|
||||
void invalidateCaches(void);
|
||||
void cleanDCache(void);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// TLBs
|
||||
|
||||
void invalidateUnifiedTLB(void);
|
||||
void invalidateUnifiedTLB_IS(void);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Branch prediction
|
||||
|
||||
void flushBranchTargetCache(void);
|
||||
void flushBranchTargetCache_IS(void);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// High Vecs
|
||||
|
||||
void enableHighVecs(void);
|
||||
void disableHighVecs(void);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// ID Registers
|
||||
|
||||
unsigned int getMIDR(void);
|
||||
|
||||
#define MIDR_IMPL_SHIFT 24
|
||||
#define MIDR_IMPL_MASK 0xFF
|
||||
#define MIDR_VAR_SHIFT 20
|
||||
#define MIDR_VAR_MASK 0xF
|
||||
#define MIDR_ARCH_SHIFT 16
|
||||
#define MIDR_ARCH_MASK 0xF
|
||||
#define MIDR_PART_SHIFT 4
|
||||
#define MIDR_PART_MASK 0xFFF
|
||||
#define MIDR_REV_SHIFT 0
|
||||
#define MIDR_REV_MASK 0xF
|
||||
|
||||
// tmp = get_MIDR();
|
||||
// implementor = (tmp >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
|
||||
// variant = (tmp >> MIDR_VAR_SHIFT) & MIDR_VAR_MASK;
|
||||
// architecture= (tmp >> MIDR_ARCH_SHIFT) & MIDR_ARCH_MASK;
|
||||
// part_number = (tmp >> MIDR_PART_SHIFT) & MIDR_PART_MASK;
|
||||
// revision = tmp & MIDR_REV_MASK;
|
||||
|
||||
#define MIDR_PART_CA5 0xC05
|
||||
#define MIDR_PART_CA8 0xC08
|
||||
#define MIDR_PART_CA9 0xC09
|
||||
|
||||
unsigned int getMPIDR(void);
|
||||
|
||||
#define MPIDR_FORMAT_SHIFT 31
|
||||
#define MPIDR_FORMAT_MASK 0x1
|
||||
#define MPIDR_UBIT_SHIFT 30
|
||||
#define MPIDR_UBIT_MASK 0x1
|
||||
#define MPIDR_CLUSTER_SHIFT 7
|
||||
#define MPIDR_CLUSTER_MASK 0xF
|
||||
#define MPIDR_CPUID_SHIFT 0
|
||||
#define MPIDR_CPUID_MASK 0x3
|
||||
|
||||
#define MPIDR_CPUID_CPU0 0x0
|
||||
#define MPIDR_CPUID_CPU1 0x1
|
||||
#define MPIDR_CPUID_CPU2 0x2
|
||||
#define MPIDR_CPUID_CPU3 0x3
|
||||
|
||||
#define MPIDR_UNIPROCESSPR 0x1
|
||||
|
||||
#define MPDIR_NEW_FORMAT 0x1
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Context ID
|
||||
|
||||
unsigned int getContextID(void);
|
||||
|
||||
void setContextID(unsigned int);
|
||||
|
||||
#define CONTEXTID_ASID_SHIFT 0
|
||||
#define CONTEXTID_ASID_MASK 0xFF
|
||||
#define CONTEXTID_PROCID_SHIFT 8
|
||||
#define CONTEXTID_PROCID_MASK 0x00FFFFFF
|
||||
|
||||
// tmp = getContextID();
|
||||
// ASID = tmp & CONTEXTID_ASID_MASK;
|
||||
// PROCID = (tmp >> CONTEXTID_PROCID_SHIFT) & CONTEXTID_PROCID_MASK;
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// SMP related for Armv7-A MPCore processors
|
||||
//
|
||||
// DO NOT CALL THESE FUNCTIONS ON A CORTEX-A8
|
||||
|
||||
// Returns the base address of the private peripheral memory space
|
||||
unsigned int getBaseAddr(void);
|
||||
|
||||
// Returns the CPU ID (0 to 3) of the CPU executed on
|
||||
#define MP_CPU0 (0)
|
||||
#define MP_CPU1 (1)
|
||||
#define MP_CPU2 (2)
|
||||
#define MP_CPU3 (3)
|
||||
unsigned int getCPUID(void);
|
||||
|
||||
// Set this core as participating in SMP
|
||||
void joinSMP(void);
|
||||
|
||||
// Set this core as NOT participating in SMP
|
||||
void leaveSMP(void);
|
||||
|
||||
// Go to sleep, never returns
|
||||
void goToSleep(void);
|
||||
|
||||
#endif
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// End of v7.h
|
||||
// ------------------------------------------------------------
|
||||
476
ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.s
Normal file
476
ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.s
Normal file
@@ -0,0 +1,476 @@
|
||||
// ------------------------------------------------------------
|
||||
// v7-A Cache and Branch Prediction Maintenance Operations
|
||||
//
|
||||
// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved.
|
||||
// Use, modification and redistribution of this file is subject to your possession of a
|
||||
// valid End User License Agreement for the Arm Product of which these examples are part of
|
||||
// and your compliance with all applicable terms and conditions of such licence agreement.
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.arm
|
||||
// ------------------------------------------------------------
|
||||
// Interrupt enable/disable
|
||||
// ------------------------------------------------------------
|
||||
|
||||
// Could use intrinsic instead of these
|
||||
|
||||
.global enableInterrupts
|
||||
.type enableInterrupts,function
|
||||
// void enableInterrupts(void)//
|
||||
enableInterrupts:
|
||||
CPSIE i
|
||||
BX lr
|
||||
|
||||
|
||||
.global disableInterrupts
|
||||
.type disableInterrupts,function
|
||||
// void disableInterrupts(void)//
|
||||
disableInterrupts:
|
||||
CPSID i
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Cache Maintenance
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global enableCaches
|
||||
.type enableCaches,function
|
||||
// void enableCaches(void)//
|
||||
enableCaches:
|
||||
MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
|
||||
ORR r0, r0, #(1 << 2) // Set C bit
|
||||
ORR r0, r0, #(1 << 12) // Set I bit
|
||||
MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
|
||||
ISB
|
||||
BX lr
|
||||
|
||||
|
||||
|
||||
.global disableCaches
|
||||
.type disableCaches,function
|
||||
// void disableCaches(void)
|
||||
disableCaches:
|
||||
MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
|
||||
BIC r0, r0, #(1 << 2) // Clear C bit
|
||||
BIC r0, r0, #(1 << 12) // Clear I bit
|
||||
MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
|
||||
ISB
|
||||
BX lr
|
||||
|
||||
|
||||
|
||||
.global cleanDCache
|
||||
.type cleanDCache,function
|
||||
// void cleanDCache(void)//
|
||||
cleanDCache:
|
||||
PUSH {r4-r12}
|
||||
|
||||
//
|
||||
// Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B)
|
||||
//
|
||||
|
||||
MRC p15, 1, r0, c0, c0, 1 // Read CLIDR
|
||||
ANDS r3, r0, #0x7000000
|
||||
MOV r3, r3, LSR #23 // Cache level value (naturally aligned)
|
||||
BEQ clean_dcache_finished
|
||||
MOV r10, #0
|
||||
|
||||
clean_dcache_loop1:
|
||||
ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
|
||||
MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level
|
||||
AND r1, r1, #7 // get those 3 bits alone
|
||||
CMP r1, #2
|
||||
BLT clean_dcache_skip // no cache or only instruction cache at this level
|
||||
MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
|
||||
ISB // ISB to sync the change to the CacheSizeID reg
|
||||
MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register
|
||||
AND r2, r1, #7 // extract the line length field
|
||||
ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes)
|
||||
LDR r4, =0x3FF
|
||||
ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned)
|
||||
CLZ r5, r4 // R5 is the bit position of the way size increment
|
||||
LDR r7, =0x00007FFF
|
||||
ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned)
|
||||
|
||||
clean_dcache_loop2:
|
||||
MOV r9, R4 // R9 working copy of the max way size (right aligned)
|
||||
|
||||
clean_dcache_loop3:
|
||||
ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
|
||||
ORR r11, r11, r7, LSL r2 // factor in the index number
|
||||
MCR p15, 0, r11, c7, c10, 2 // DCCSW - clean by set/way
|
||||
SUBS r9, r9, #1 // decrement the way number
|
||||
BGE clean_dcache_loop3
|
||||
SUBS r7, r7, #1 // decrement the index
|
||||
BGE clean_dcache_loop2
|
||||
|
||||
clean_dcache_skip:
|
||||
ADD r10, r10, #2 // increment the cache number
|
||||
CMP r3, r10
|
||||
BGT clean_dcache_loop1
|
||||
|
||||
clean_dcache_finished:
|
||||
POP {r4-r12}
|
||||
|
||||
BX lr
|
||||
|
||||
|
||||
.global cleanInvalidateDCache
|
||||
.type cleanInvalidateDCache,function
|
||||
// void cleanInvalidateDCache(void)//
|
||||
cleanInvalidateDCache:
|
||||
PUSH {r4-r12}
|
||||
|
||||
//
|
||||
// Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B)
|
||||
//
|
||||
|
||||
MRC p15, 1, r0, c0, c0, 1 // Read CLIDR
|
||||
ANDS r3, r0, #0x7000000
|
||||
MOV r3, r3, LSR #23 // Cache level value (naturally aligned)
|
||||
BEQ clean_invalidate_dcache_finished
|
||||
MOV r10, #0
|
||||
|
||||
clean_invalidate_dcache_loop1:
|
||||
ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
|
||||
MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level
|
||||
AND r1, r1, #7 // get those 3 bits alone
|
||||
CMP r1, #2
|
||||
BLT clean_invalidate_dcache_skip // no cache or only instruction cache at this level
|
||||
MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
|
||||
ISB // ISB to sync the change to the CacheSizeID reg
|
||||
MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register
|
||||
AND r2, r1, #7 // extract the line length field
|
||||
ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes)
|
||||
LDR r4, =0x3FF
|
||||
ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned)
|
||||
CLZ r5, r4 // R5 is the bit position of the way size increment
|
||||
LDR r7, =0x00007FFF
|
||||
ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned)
|
||||
|
||||
clean_invalidate_dcache_loop2:
|
||||
MOV r9, R4 // R9 working copy of the max way size (right aligned)
|
||||
|
||||
clean_invalidate_dcache_loop3:
|
||||
ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
|
||||
ORR r11, r11, r7, LSL r2 // factor in the index number
|
||||
MCR p15, 0, r11, c7, c14, 2 // DCCISW - clean and invalidate by set/way
|
||||
SUBS r9, r9, #1 // decrement the way number
|
||||
BGE clean_invalidate_dcache_loop3
|
||||
SUBS r7, r7, #1 // decrement the index
|
||||
BGE clean_invalidate_dcache_loop2
|
||||
|
||||
clean_invalidate_dcache_skip:
|
||||
ADD r10, r10, #2 // increment the cache number
|
||||
CMP r3, r10
|
||||
BGT clean_invalidate_dcache_loop1
|
||||
|
||||
clean_invalidate_dcache_finished:
|
||||
POP {r4-r12}
|
||||
|
||||
BX lr
|
||||
|
||||
|
||||
|
||||
.global invalidateCaches
|
||||
.type invalidateCaches,function
|
||||
// void invalidateCaches(void)//
|
||||
invalidateCaches:
|
||||
PUSH {r4-r12}
|
||||
|
||||
//
|
||||
// Based on code example given in section B2.2.4/11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B)
|
||||
//
|
||||
|
||||
MOV r0, #0
|
||||
MCR p15, 0, r0, c7, c5, 0 // ICIALLU - Invalidate entire I Cache, and flushes branch target cache
|
||||
|
||||
MRC p15, 1, r0, c0, c0, 1 // Read CLIDR
|
||||
ANDS r3, r0, #0x7000000
|
||||
MOV r3, r3, LSR #23 // Cache level value (naturally aligned)
|
||||
BEQ invalidate_caches_finished
|
||||
MOV r10, #0
|
||||
|
||||
invalidate_caches_loop1:
|
||||
ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
|
||||
MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level
|
||||
AND r1, r1, #7 // get those 3 bits alone
|
||||
CMP r1, #2
|
||||
BLT invalidate_caches_skip // no cache or only instruction cache at this level
|
||||
MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
|
||||
ISB // ISB to sync the change to the CacheSizeID reg
|
||||
MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register
|
||||
AND r2, r1, #7 // extract the line length field
|
||||
ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes)
|
||||
LDR r4, =0x3FF
|
||||
ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned)
|
||||
CLZ r5, r4 // R5 is the bit position of the way size increment
|
||||
LDR r7, =0x00007FFF
|
||||
ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned)
|
||||
|
||||
invalidate_caches_loop2:
|
||||
MOV r9, R4 // R9 working copy of the max way size (right aligned)
|
||||
|
||||
invalidate_caches_loop3:
|
||||
ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
|
||||
ORR r11, r11, r7, LSL r2 // factor in the index number
|
||||
MCR p15, 0, r11, c7, c6, 2 // DCISW - invalidate by set/way
|
||||
SUBS r9, r9, #1 // decrement the way number
|
||||
BGE invalidate_caches_loop3
|
||||
SUBS r7, r7, #1 // decrement the index
|
||||
BGE invalidate_caches_loop2
|
||||
|
||||
invalidate_caches_skip:
|
||||
ADD r10, r10, #2 // increment the cache number
|
||||
CMP r3, r10
|
||||
BGT invalidate_caches_loop1
|
||||
|
||||
invalidate_caches_finished:
|
||||
POP {r4-r12}
|
||||
BX lr
|
||||
|
||||
|
||||
|
||||
.global invalidateCaches_IS
|
||||
.type invalidateCaches_IS,function
|
||||
// void invalidateCaches_IS(void)//
|
||||
invalidateCaches_IS:
|
||||
PUSH {r4-r12}
|
||||
|
||||
MOV r0, #0
|
||||
MCR p15, 0, r0, c7, c1, 0 // ICIALLUIS - Invalidate entire I Cache inner shareable
|
||||
|
||||
MRC p15, 1, r0, c0, c0, 1 // Read CLIDR
|
||||
ANDS r3, r0, #0x7000000
|
||||
MOV r3, r3, LSR #23 // Cache level value (naturally aligned)
|
||||
BEQ invalidate_caches_is_finished
|
||||
MOV r10, #0
|
||||
|
||||
invalidate_caches_is_loop1:
|
||||
ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
|
||||
MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level
|
||||
AND r1, r1, #7 // get those 3 bits alone
|
||||
CMP r1, #2
|
||||
BLT invalidate_caches_is_skip // no cache or only instruction cache at this level
|
||||
MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
|
||||
ISB // ISB to sync the change to the CacheSizeID reg
|
||||
MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register
|
||||
AND r2, r1, #7 // extract the line length field
|
||||
ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes)
|
||||
LDR r4, =0x3FF
|
||||
ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned)
|
||||
CLZ r5, r4 // R5 is the bit position of the way size increment
|
||||
LDR r7, =0x00007FFF
|
||||
ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned)
|
||||
|
||||
invalidate_caches_is_loop2:
|
||||
MOV r9, R4 // R9 working copy of the max way size (right aligned)
|
||||
|
||||
invalidate_caches_is_loop3:
|
||||
ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
|
||||
ORR r11, r11, r7, LSL r2 // factor in the index number
|
||||
MCR p15, 0, r11, c7, c6, 2 // DCISW - clean by set/way
|
||||
SUBS r9, r9, #1 // decrement the way number
|
||||
BGE invalidate_caches_is_loop3
|
||||
SUBS r7, r7, #1 // decrement the index
|
||||
BGE invalidate_caches_is_loop2
|
||||
|
||||
invalidate_caches_is_skip:
|
||||
ADD r10, r10, #2 // increment the cache number
|
||||
CMP r3, r10
|
||||
BGT invalidate_caches_is_loop1
|
||||
|
||||
invalidate_caches_is_finished:
|
||||
POP {r4-r12}
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// TLB
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global invalidateUnifiedTLB
|
||||
.type invalidateUnifiedTLB,function
|
||||
// void invalidateUnifiedTLB(void)//
|
||||
invalidateUnifiedTLB:
|
||||
MOV r0, #0
|
||||
MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB
|
||||
BX lr
|
||||
|
||||
|
||||
.global invalidateUnifiedTLB_IS
|
||||
.type invalidateUnifiedTLB_IS,function
|
||||
// void invalidateUnifiedTLB_IS(void)//
|
||||
invalidateUnifiedTLB_IS:
|
||||
MOV r0, #1
|
||||
MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Branch Prediction
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global flushBranchTargetCache
|
||||
.type flushBranchTargetCache,function
|
||||
// void flushBranchTargetCache(void)
|
||||
flushBranchTargetCache:
|
||||
MOV r0, #0
|
||||
MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array
|
||||
BX lr
|
||||
|
||||
|
||||
.global flushBranchTargetCache_IS
|
||||
.type flushBranchTargetCache_IS,function
|
||||
// void flushBranchTargetCache_IS(void)
|
||||
flushBranchTargetCache_IS:
|
||||
MOV r0, #0
|
||||
MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// High Vecs
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global enableHighVecs
|
||||
.type enableHighVecs,function
|
||||
// void enableHighVecs(void)//
|
||||
enableHighVecs:
|
||||
MRC p15, 0, r0, c1, c0, 0 // Read Control Register
|
||||
ORR r0, r0, #(1 << 13) // Set the V bit (bit 13)
|
||||
MCR p15, 0, r0, c1, c0, 0 // Write Control Register
|
||||
ISB
|
||||
BX lr
|
||||
|
||||
|
||||
.global disableHighVecs
|
||||
.type disableHighVecs,function
|
||||
// void disable_highvecs(void)//
|
||||
disableHighVecs:
|
||||
MRC p15, 0, r0, c1, c0, 0 // Read Control Register
|
||||
BIC r0, r0, #(1 << 13) // Clear the V bit (bit 13)
|
||||
MCR p15, 0, r0, c1, c0, 0 // Write Control Register
|
||||
ISB
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Context ID
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global getContextID
|
||||
.type getContextID,function
|
||||
// uint32_t getContextIDd(void)//
|
||||
getContextID:
|
||||
MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register
|
||||
BX lr
|
||||
|
||||
|
||||
.global setContextID
|
||||
.type setContextID,function
|
||||
// void setContextID(uint32_t)//
|
||||
setContextID:
|
||||
MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// ID registers
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global getMIDR
|
||||
.type getMIDR,function
|
||||
// uint32_t getMIDR(void)//
|
||||
getMIDR:
|
||||
MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR)
|
||||
BX lr
|
||||
|
||||
|
||||
.global getMPIDR
|
||||
.type getMPIDR,function
|
||||
// uint32_t getMPIDR(void)//
|
||||
getMPIDR:
|
||||
MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR)
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// CP15 SMP related
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global getBaseAddr
|
||||
.type getBaseAddr,function
|
||||
// uint32_t getBaseAddr(void)
|
||||
// Returns the value CBAR (base address of the private peripheral memory space)
|
||||
getBaseAddr:
|
||||
MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global getCPUID
|
||||
.type getCPUID,function
|
||||
// uint32_t getCPUID(void)
|
||||
// Returns the CPU ID (0 to 3) of the CPU executed on
|
||||
getCPUID:
|
||||
MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register
|
||||
AND r0, r0, #0x03 // Mask off, leaving the CPU ID field
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global goToSleep
|
||||
.type goToSleep,function
|
||||
// void goToSleep(void)
|
||||
goToSleep:
|
||||
DSB // Clear all pending data accesses
|
||||
WFI // Go into standby
|
||||
B goToSleep // Catch in case of rogue events
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global joinSMP
|
||||
.type joinSMP,function
|
||||
// void joinSMP(void)
|
||||
// Sets the ACTRL.SMP bit
|
||||
joinSMP:
|
||||
|
||||
// SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
|
||||
MOV r1, r0
|
||||
ORR r0, r0, #0x040 // Set bit 6
|
||||
CMP r0, r1
|
||||
MCRNE p15, 0, r0, c1, c0, 1 // Write ACTLR
|
||||
ISB
|
||||
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
|
||||
.global leaveSMP
|
||||
.type leaveSMP,function
|
||||
// void leaveSMP(void)
|
||||
// Clear the ACTRL.SMP bit
|
||||
leaveSMP:
|
||||
|
||||
// SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
|
||||
BIC r0, r0, #0x040 // Clear bit 6
|
||||
MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
|
||||
ISB
|
||||
|
||||
BX lr
|
||||
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// End of v7.s
|
||||
// ------------------------------------------------------------
|
||||
Reference in New Issue
Block a user