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apply 6.0.2 patch

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This commit is contained in:
Scott Larson
2020-08-14 09:10:48 -07:00
parent 6a018a4cfd
commit 40a402b827
227 changed files with 2232 additions and 3212 deletions
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42
ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S
View File

@@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_initialize.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
@@ -59,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M4/GNU */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -95,7 +85,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */
@/* GNU assembly comment, */
@/* resulting in version 6.0.1 */
@/* resulting in version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@@ -109,17 +102,17 @@ _tx_initialize_low_level:
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
@
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =__RAM_segment_used_end__ @ Build first free address
ADD r1, r1, #4 @
LDR r1, =__RAM_segment_used_end__ @ Build first free address
ADD r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
@
@ /* Setup Vector Table Offset Register. */
@
@
MOV r0, #0xE000E000 @ Build address of NVIC registers
LDR r1, =_vectors @ Pickup address of vector table
STR r1, [r0, #0xD08] @ Set vector table address
LDR r1, =_vectors @ Pickup address of vector table
STR r1, [r0, #0xD08] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
@@ -133,7 +126,7 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 @ Build address of DWT register
LDR r1, [r0] @ Pickup the current value
ORR r1, r1, #1 @ Set the CYCCNTENA bit
STR r1, [r0] @ Enable the cycle count register
STR r1, [r0] @ Enable the cycle count register
@
@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@
@@ -155,11 +148,11 @@ _tx_initialize_low_level:
LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers
@ Note: PnSV must be lowest priority, which is 0xFF
@
@ /* Return to caller. */
@
BX lr
@
BX lr
@}
@
@@ -195,7 +188,7 @@ __tx_IntHandler:
PUSH {r0, lr}
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_enter @ Call the ISR enter function
#endif
#endif
@ /* Do interrupt handler work here */
@ /* BL <your C Function>.... */
@@ -231,7 +224,7 @@ SysTick_Handler:
@ /* NMI, DBG handlers */
.global __tx_NMIHandler
.global __tx_NMIHandler
.thumb_func
__tx_NMIHandler:
B __tx_NMIHandler
@@ -240,4 +233,3 @@ __tx_NMIHandler:
.thumb_func
__tx_DBGHandler:
B __tx_DBGHandler

5
ports/cortex_m4/gnu/readme_threadx.txt
View File

@@ -208,6 +208,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M4/GNU port. The following files were
changed/added for port specific version 6.0.2:
*.S Modified comments and whitespace.
05/19/2020 Initial ThreadX 6.0 version for Cortex-M4 using GNU tools.

18
ports/cortex_m4/gnu/src/tx_thread_context_restore.S
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@@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@@ -49,13 +39,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M4/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function restores the interrupt context if it is processing a */
@/* nested interrupt. If not, it returns to the interrupt thread if no */
@/* preemption is necessary. Otherwise, if preemption is necessary or */
@@ -82,6 +74,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
@@ -93,4 +88,3 @@ _tx_thread_context_restore:
@ /* Not needed for this port - just return! */
BX lr
@}

17
ports/cortex_m4/gnu/src/tx_thread_context_save.S
View File

@@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@@ -44,13 +34,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M4/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function saves the context of an executing thread in the */
@/* beginning of interrupt processing. The function also ensures that */
@/* the system stack is used upon return to the calling ISR. */
@@ -76,6 +68,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)

16
ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S
View File

@@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@@ -37,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M4/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,6 +60,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -87,6 +82,3 @@ _tx_thread_interrupt_control:
BX lr @ Return to caller
@/* } */

53
ports/cortex_m4/gnu/src/tx_thread_schedule.S
View File

@@ -21,15 +21,6 @@
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
@@ -46,7 +37,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M4/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -80,6 +71,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -93,7 +87,7 @@ _tx_thread_schedule:
@ from the PendSV handling routines below. */
@
@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
@
@
MOV r0, #0 @ Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
STR r0, [r2, #0] @ Clear preempt disable flag
@@ -102,14 +96,14 @@ _tx_thread_schedule:
@
#ifdef TX_ENABLE_FPU_SUPPORT
MRS r0, CONTROL @ Pickup current CONTROL register
BIC r0, r0, #4 @ Clear the FPCA bit
BIC r0, r0, #4 @ Clear the FPCA bit
MSR CONTROL, r0 @ Setup new CONTROL register
#endif
@
@ /* Enable interrupts */
@
CPSIE i
@
@
@ /* Enter the scheduler for the first time. */
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
@@ -119,14 +113,14 @@ _tx_thread_schedule:
ISB @ Flush pipeline
@
@ /* Wait here for the PendSV to take place. */
@
@
__tx_wait_here:
B __tx_wait_here @ Wait for the PendSV to happen
@}
@
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ common for both PendSV and SVCall. */
@
@
.global PendSV_Handler
.global __tx_PendSVHandler
.thumb_func
@@ -135,8 +129,8 @@ PendSV_Handler:
__tx_PendSVHandler:
@
@ /* Get current thread value and new thread pointer. */
@
__tx_ts_handler:
@
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@@ -154,7 +148,7 @@ __tx_ts_handler:
LDR r1, [r0] @ Pickup current thread pointer
@
@ /* Determine if there is a current thread to finish preserving. */
@
@
CBZ r1, __tx_ts_new @ If NULL, skip preservation
@
@ /* Recover PSP and preserve current thread context. */
@@ -185,7 +179,7 @@ _skip_vfp_save:
@
STR r3, [r4] @ Clear time-slice
@
@
@
@ /* Executing thread is now completely preserved!!! */
@
__tx_ts_new:
@@ -229,7 +223,7 @@ __tx_ts_restore:
LDMIA r12!, {LR} @ Pickup LR
#ifdef TX_ENABLE_FPU_SUPPORT
TST LR, #0x10 @ Determine if the VFP extended frame is present
BNE _skip_vfp_restore @ If not, skip VFP restore
BNE _skip_vfp_restore @ If not, skip VFP restore
VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers
_skip_vfp_restore:
#endif
@@ -237,11 +231,11 @@ _skip_vfp_restore:
MSR PSP, r12 @ Setup the thread's stack pointer
@
@ /* Return to thread. */
@
@
BX lr @ Return to thread!
@
@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ are disabled to allow use of WFI for waiting for a thread to arrive. */
@
__tx_ts_wait:
@@ -257,19 +251,18 @@ __tx_ts_wait:
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ already in the handler! */
@
__tx_ts_ready:
MOV r7, #0x08000000 @ Build clear PendSV value
MOV r8, #0xE000E000 @ Build base NVIC address
STR r7, [r8, #0xD04] @ Clear any PendSV
STR r7, [r8, #0xD04] @ Clear any PendSV
@
@ /* Re-enable interrupts and restore new thread. */
@
@
CPSIE i @ Enable interrupts
B __tx_ts_restore @ Restore the thread
#ifdef TX_ENABLE_FPU_SUPPORT
@@ -277,7 +270,7 @@ __tx_ts_ready:
.thumb_func
tx_thread_fpu_enable:
@
@ /* Automatic VPF logic is supported, this function is present only for
@ /* Automatic VPF logic is supported, this function is present only for
@ backward compatibility purposes and therefore simply returns. */
@
BX LR @ Return to caller
@@ -286,11 +279,9 @@ tx_thread_fpu_enable:
.thumb_func
tx_thread_fpu_disable:
@
@ /* Automatic VPF logic is supported, this function is present only for
@ /* Automatic VPF logic is supported, this function is present only for
@ backward compatibility purposes and therefore simply returns. */
@
BX LR @ Return to caller
#endif

22
ports/cortex_m4/gnu/src/tx_thread_stack_build.S
View File

@@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@
@
.text
.align 4
@@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M4/GNU */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -76,6 +67,9 @@
@/* needed. Removed references */
@/* to stack frame, resulting */
@/* in version 6.0.1 */
@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -84,11 +78,11 @@
.thumb_func
_tx_thread_stack_build:
@
@
@
@ /* Build a fake interrupt frame. The form of the fake interrupt stack
@ on the Cortex-M4 should look like the following after it is built:
@
@ Stack Top:
@
@ Stack Top:
@ LR Interrupted LR (LR at time of PENDSV)
@ r4 Initial value for r4
@ r5 Initial value for r5
@@ -147,5 +141,3 @@ _tx_thread_stack_build:
@ control block
BX lr @ Return to caller
@}

21
ports/cortex_m4/gnu/src/tx_thread_system_return.S
View File

@@ -19,15 +19,6 @@
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@/* #define TX_SOURCE_CODE */
@
@
@/* Include necessary system files. */
@
@/* #include "tx_api.h"
@ #include "tx_thread.h"
@ #include "tx_timer.h" */
.text 32
@@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M4/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
@@ -79,9 +73,9 @@
.global _tx_thread_system_return
_tx_thread_system_return:
@
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ replaced with in-line assembly in tx_port.h to improved performance. */
@
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
MOV r1, #0xE000E000 @ Load NVIC base
STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR
@@ -92,7 +86,6 @@ _tx_thread_system_return:
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
_isr_context:
BX lr @ Return to caller
BX lr @ Return to caller
@/* } */

24
ports/cortex_m4/gnu/src/tx_timer_interrupt.S
View File

@@ -20,17 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_timer.h"
@#include "tx_thread.h"
@
@
@Define Assembly language external references...
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@@ -51,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M4/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -86,6 +75,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
@@ -110,7 +102,7 @@ _tx_timer_interrupt:
@ if (_tx_timer_time_slice)
@ {
@
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r2, [r3, #0] @ Pickup time-slice
CMP r2, #0 @ Is it non-active?
BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing
@@ -228,13 +220,13 @@ __tx_timer_dont_activate:
@ if (_tx_timer_expired_time_slice)
@ {
@
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r2, [r3, #0] @ Pickup the actual flag
CMP r2, #0 @ See if the flag is set
BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing
@
@ /* Time slice interrupted thread. */
@ _tx_thread_time_slice();
@ _tx_thread_time_slice();
@
BL _tx_thread_time_slice @ Call time-slice processing
LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag
@@ -266,5 +258,3 @@ __tx_timer_nothing_expired:
BX lr @ Return to caller
@
@}