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apply 6.0.2 patch

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This commit is contained in:
Scott Larson
2020-08-14 09:10:48 -07:00
parent 6a018a4cfd
commit 40a402b827
227 changed files with 2232 additions and 3212 deletions
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19
ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S
View File

@@ -34,7 +34,7 @@ HEAP_SIZE = 0x00000000
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -68,6 +68,9 @@ HEAP_SIZE = 0x00000000
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)
@@ -87,7 +90,7 @@ _tx_initialize_low_level:
/* Set base of available memory to end of non-initialised RAM area. */
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address
ADD r1, r1, #4 //
ADD r1, r1, #4 //
STR r1, [r0] // Setup first unused memory pointer
/* Setup Vector Table Offset Register. */
@@ -99,7 +102,7 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 // Build address of DWT register
LDR r1, [r0] // Pickup the current value
ORR r1, r1, #1 // Set the CYCCNTENA bit
STR r1, [r0] // Enable the cycle count register
STR r1, [r0] // Enable the cycle count register
/* Set system stack pointer from vector value. */
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
@@ -154,7 +157,7 @@ __tx_IntHandler:
// VOID InterruptHandler (VOID)
// {
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
/* Do interrupt handler work here */
/* .... */
@@ -206,23 +209,23 @@ UsageFault_Handler:
TST r1, #0x00100000 // Check for Stack Overflow
_unhandled_usage_loop:
BEQ _unhandled_usage_loop // If not stack overflow then loop
// Handle stack overflow
STR r1, [r0] // Clear CFSR flag(s)
#ifdef __ARM_PCS_VFP
LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address
LDR r1, [r0] // Load FPCCR
BIC r1, r1, #1 // Clear the lazy preservation active bit
STR r1, [r0] // Store the value
#endif
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
LDR r0,[r0] // Pick up current thread pointer
PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment)
BL _tx_thread_stack_error_handler // Call ThreadX/user handler
POP {r0,lr} // Restore LR and dummy reg
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
// Call the thread exit function to indicate the thread is no longer executing.
PUSH {r0, lr} // Save LR (and r0 just for alignment)

8
ports/cortex_m33/ac6/readme_threadx.txt
View File

@@ -204,6 +204,14 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M33/AC6 port. The following files were
changed/added for port specific version 6.0.2:
tx_thread_context_restore.S Remove execution profile kit call.
tx_thread_context_save.S Remove execution profile kit call.
tx_timer_interrupt.S Add DSB instruction before returning.
*.S Modified comments and whitespace.
06-30-2020 Initial ThreadX 6.0.1 version for Cortex-M33 using AC6 tools.

18
ports/cortex_m33/ac6/src/tx_thread_context_restore.S
View File

@@ -26,17 +26,14 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function restores the interrupt context if it is processing a */
/* nested interrupt. If not, it returns to the interrupt thread if no */
/* preemption is necessary. Otherwise, if preemption is necessary or */
/* if no thread was running, the function returns to the scheduler. */
/* This function is not needed for Cortex-M. */
/* */
/* INPUT */
/* */
@@ -59,6 +56,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), remove */
/* EPK, clean up whitespace */
/* resulting in version 6.0.2 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -71,14 +71,6 @@
.thumb_func
.type _tx_thread_context_restore, function
_tx_thread_context_restore:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
/* Call the ISR exit function to indicate an ISR is complete. */
PUSH {r0,lr} // Save ISR lr (and r0 for 8-byte stack alignment)
BL _tx_execution_isr_exit
POP {r0,lr}
#endif
/* Just return! */
BX lr
// }

17
ports/cortex_m33/ac6/src/tx_thread_context_save.S
View File

@@ -26,16 +26,14 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function saves the context of an executing thread in the */
/* beginning of interrupt processing. The function also ensures that */
/* the system stack is used upon return to the calling ISR. */
/* This function is not needed for Cortex-M. */
/* */
/* INPUT */
/* */
@@ -58,6 +56,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), remove */
/* EPK, clean up whitespace */
/* resulting in version 6.0.2 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)
@@ -70,14 +71,6 @@
.thumb_func
.type _tx_thread_context_save, function
_tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
/* Call the ISR enter function to indicate an ISR is executing. */
PUSH {r0,lr} // Save ISR lr (and r0 for 8-byte stack alignment)
BL _tx_execution_isr_enter // Call the ISR enter function
POP {r0,lr} // Recover ISR lr (and r0)
#endif
/* Return to interrupt processing. */
BX lr
// }

5
ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +57,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

5
ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +57,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(UINT new_posture)

5
ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +57,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT new_posture)

23
ports/cortex_m33/ac6/src/tx_thread_schedule.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +59,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -84,7 +87,7 @@ _tx_thread_schedule:
#ifdef __ARM_PCS_VFP
MRS r0, CONTROL // Pickup current CONTROL register
BIC r0, r0, #4 // Clear the FPCA bit
BIC r0, r0, #4 // Clear the FPCA bit
MSR CONTROL, r0 // Setup new CONTROL register
#endif
@@ -106,7 +109,7 @@ __tx_wait_here:
// }
/* Generic context switching PendSV handler. */
.section .text
.balign 4
.syntax unified
@@ -151,7 +154,7 @@ _skip_vfp_save:
LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
STMDB r12!, {LR} // Save LR on the stack
STR r12, [r1, #8] // Save the thread stack pointer
#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE))
// Save secure context
LDR r5, [r1,#0x90] // Load secure stack index
@@ -229,7 +232,7 @@ _skip_secure_restore:
LDMIA r12!, {LR} // Pickup LR
#ifdef __ARM_PCS_VFP
TST LR, #0x10 // Determine if the VFP extended frame is present
BNE _skip_vfp_restore // If not, skip VFP restore
BNE _skip_vfp_restore // If not, skip VFP restore
VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers
_skip_vfp_restore:
#endif
@@ -240,7 +243,7 @@ _skip_vfp_restore:
BX lr // Return to thread!
/* The following is the idle wait processing... in this case, no threads are ready for execution and the
system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
are disabled to allow use of WFI for waiting for a thread to arrive. */
__tx_ts_wait:
@@ -256,12 +259,12 @@ __tx_ts_wait:
CPSIE i // Enable interrupts
B __tx_ts_wait // Loop to continue waiting
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
/* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
already in the handler! */
__tx_ts_ready:
MOV r7, #0x08000000 // Build clear PendSV value
MOV r8, #0xE000E000 // Build base NVIC address
STR r7, [r8, #0xD04] // Clear any PendSV
STR r7, [r8, #0xD04] // Clear any PendSV
/* Re-enable interrupts and restore new thread. */
CPSIE i // Enable interrupts
@@ -291,10 +294,10 @@ SVC_Handler:
CMP r1, #2 // Is it a secure stack free request?
BEQ _tx_svc_secure_free // Yes, go there
// Unknown SVC argument - just return
BX lr
_tx_svc_secure_alloc:
PUSH {r0,lr} // Save SP and EXC_RETURN
LDM r0, {r0-r3} // Load function parameters from stack

5
ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_allocate Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,6 +58,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)

5
ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_free Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,6 +56,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)

5
ports/cortex_m33/ac6/src/tx_thread_stack_build.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +59,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

9
ports/cortex_m33/ac6/src/tx_thread_system_return.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +59,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)
@@ -71,7 +74,7 @@
.thumb_func
.type _tx_thread_system_return, function
_tx_thread_system_return:
/* Return to real scheduler via PendSV. Note that this routine is often
/* Return to real scheduler via PendSV. Note that this routine is often
replaced with in-line assembly in tx_port.h to improved performance. */
MOV r0, #0x10000000 // Load PENDSVSET bit
@@ -84,6 +87,6 @@ _tx_thread_system_return:
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
_isr_context:
BX lr // Return to caller
BX lr // Return to caller
// }
.end

13
ports/cortex_m33/ac6/src/tx_timer_interrupt.S
View File

@@ -26,7 +26,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-M33/AC6 */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -61,6 +61,10 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, add DSB before */
/* returning, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
/* VOID _tx_timer_interrupt(VOID)
@@ -90,7 +94,7 @@ _tx_timer_interrupt:
// if (_tx_timer_time_slice)
// {
LDR r3, =_tx_timer_time_slice // Pickup address of time-slice
LDR r3, =_tx_timer_time_slice // Pickup address of time-slice
LDR r2, [r3, #0] // Pickup time-slice
CBZ r2, __tx_timer_no_time_slice // Is it non-active?
// Yes, skip time-slice processing
@@ -206,13 +210,13 @@ __tx_timer_dont_activate:
// if (_tx_timer_expired_time_slice)
// {
LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired
LDR r2, [r3, #0] // Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set
// No, skip time-slice processing
/* Time slice interrupted thread. */
// _tx_thread_time_slice();
// _tx_thread_time_slice();
BL _tx_thread_time_slice // Call time-slice processing
LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag
@@ -239,6 +243,7 @@ __tx_timer_not_ts_expiration:
__tx_timer_nothing_expired:
DSB // Complete all memory access
BX lr // Return to caller
// }

7
ports/cortex_m33/iar/readme_threadx.txt
View File

@@ -198,6 +198,13 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M33/IAR port. The following files were
changed/added for port specific version 6.0.2:
tx_thread_context_restore.s Remove execution profile kit call.
tx_thread_context_save.s Remove execution profile kit call.
*.s Modified comments and whitespace.
06-30-2020 Initial ThreadX 6.0.1 version for Cortex-M33 using IAR's ARM tools.

31
ports/cortex_m33/iar/src/tx_initialize_low_level.s
View File

@@ -48,7 +48,7 @@ __tx_free_memory_start
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -82,6 +82,9 @@ __tx_free_memory_start
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
@@ -94,13 +97,13 @@ _tx_initialize_low_level:
CPSID i
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
LDR r1, =__tx_free_memory_start ; Build first free address
STR r1, [r0] ; Setup first unused memory pointer
;
; /* Setup Vector Table Offset Register. */
;
;
MOV r0, #0xE000E000 ; Build address of NVIC registers
LDR r1, =__vector_table ; Pickup address of vector table
STR r1, [r0, #0xD08] ; Set vector table address
@@ -110,7 +113,7 @@ _tx_initialize_low_level:
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
; STR r1, [r0] ; Enable the cycle count register
;
; /* Set system stack pointer from vector value. */
;
@@ -141,7 +144,7 @@ _tx_initialize_low_level:
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
;
BX lr
;}
;
@@ -158,7 +161,7 @@ __tx_IntHandler:
; VOID InterruptHandler (VOID)
; {
PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment)
; /* Do interrupt handler work here */
; /* .... */
@@ -194,34 +197,34 @@ UsageFault_Handler:
TST r1, #0x00100000 ; Check for Stack Overflow
_unhandled_usage_loop
BEQ _unhandled_usage_loop ; If not stack overflow then loop
; Handle stack overflow
STR r1, [r0] ; Clear CFSR flag(s)
#ifdef __ARMVFP__
LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address
LDR r1, [r0] ; Load FPCCR
BIC r1, r1, #1 ; Clear the lazy preservation active bit
STR r1, [r0] ; Store the value
#endif
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
LDR r0,[r0] ; Pick up current thread pointer
PUSH {r0,lr} ; Save LR (and r0 to maintain stack alignment)
BL _tx_thread_stack_error_handler ; Call ThreadX/user handler
POP {r0,lr} ; Restore LR and dummy reg
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
; Call the thread exit function to indicate the thread is no longer executing.
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit ; Call the thread exit function
POP {r0, lr} ; Recover LR
#endif
MOV r1, #0 ; Build NULL value
LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer
STR r1, [r0] ; Clear current thread pointer
; Return from UsageFault_Handler exception
LDR r0, =0xE000ED04 ; Load ICSR
LDR r1, =0x10000000 ; Set PENDSVSET bit
@@ -234,8 +237,8 @@ _unhandled_usage_loop
PUBLIC __tx_NMIHandler
__tx_NMIHandler:
B __tx_NMIHandler
PUBLIC __tx_DBGHandler
__tx_DBGHandler:
B __tx_DBGHandler

25
ports/cortex_m33/iar/src/tx_thread_context_restore.s
View File

@@ -20,9 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
EXTERN _tx_execution_isr_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
@@ -31,17 +28,14 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* This function is not needed for Cortex-M. */
;/* */
;/* INPUT */
;/* */
@@ -64,25 +58,18 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), remove */
;/* EPK, clean up whitespace */
;/* resulting in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
;{
PUBLIC _tx_thread_context_restore
_tx_thread_context_restore:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;
PUSH {r0, lr} ; Save return address
BL _tx_execution_isr_exit ; Call the ISR exit function
POP {r0, lr} ; Recover Save return address
#endif
;
; /* Return to interrupt processing. */
;
BX lr
;}
END
END

24
ports/cortex_m33/iar/src/tx_thread_context_save.s
View File

@@ -20,9 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
EXTERN _tx_execution_isr_enter
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
@@ -31,16 +28,14 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* This function is not needed for Cortex-M. */
;/* */
;/* INPUT */
;/* */
@@ -63,24 +58,19 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), remove */
;/* EPK, clean up whitespace */
;/* resulting in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
;{
PUBLIC _tx_thread_context_save
_tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
PUSH {r0, lr} ; Save return address
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, lr} ; Recover return address
#endif
;
; /* Return to interrupt processing. */
;
BX lr
;}
END
END

7
ports/cortex_m33/iar/src/tx_thread_interrupt_control.s
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -59,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -74,4 +77,4 @@ _tx_thread_interrupt_control:
BX lr
;
;}
END
END

9
ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s
View File

@@ -21,14 +21,14 @@
;/**************************************************************************/
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_disable Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -59,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

5
ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -59,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

31
ports/cortex_m33/iar/src/tx_thread_schedule.s
View File

@@ -41,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -74,6 +74,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -86,7 +89,7 @@ _tx_thread_schedule:
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@@ -95,7 +98,7 @@ _tx_thread_schedule:
;
#ifdef __ARMVFP__
MRS r0, CONTROL ; Pickup current CONTROL register
BIC r0, r0, #4 ; Clear the FPCA bit
BIC r0, r0, #4 ; Clear the FPCA bit
MSR CONTROL, r0 ; Setup new CONTROL register
#endif
;
@@ -118,12 +121,12 @@ __tx_wait_here:
;}
;
; /* Generic context switching PendSV handler. */
;
;
PUBLIC PendSV_Handler
PendSV_Handler:
;
; /* Get current thread value and new thread pointer. */
;
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@@ -159,7 +162,7 @@ _skip_vfp_save:
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
STMDB r12!, {LR} ; Save LR on the stack
STR r12, [r1, #8] ; Save the thread stack pointer
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
; Save secure context
LDR r5, [r1,#0x90] ; Load secure stack index
@@ -183,7 +186,7 @@ _skip_secure_save:
; /* Clear the global time-slice. */
;
STR r3, [r4] ; Clear time-slice
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new:
@@ -241,7 +244,7 @@ _skip_secure_restore:
LDMIA r12!, {LR} ; Pickup LR
#ifdef __ARMVFP__
TST LR, #0x10 ; Determine if the VFP extended frame is present
BNE _skip_vfp_restore ; If not, skip VFP restore
BNE _skip_vfp_restore ; If not, skip VFP restore
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
_skip_vfp_restore:
#endif
@@ -253,7 +256,7 @@ _skip_vfp_restore:
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait:
@@ -269,16 +272,16 @@ __tx_ts_wait:
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready:
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
@@ -301,10 +304,10 @@ SVC_Handler:
CMP r1, #2 ; Is it a secure stack free request?
BEQ _tx_svc_secure_free ; Yes, go there
; Unknown SVC argument - just return
BX lr
_tx_svc_secure_alloc:
PUSH {r0,lr} ; Save SP and EXC_RETURN
LDM r0, {r0-r3} ; Load function parameters from stack

7
ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_secure_stack_allocate Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -60,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
@@ -78,5 +81,5 @@ _tx_thread_secure_stack_allocate:
#endif
_alloc_return_interrupt_enabled
BX lr
END

6
ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_secure_stack_free Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -58,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)
@@ -77,4 +80,3 @@ _tx_thread_secure_stack_free:
_free_return_interrupt_enabled
BX lr
END

6
ports/cortex_m33/iar/src/tx_thread_stack_build.s
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -61,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -135,4 +138,3 @@ _tx_thread_stack_build:
BX lr ; Return to caller
;}
END

13
ports/cortex_m33/iar/src/tx_thread_system_return.s
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -61,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@@ -69,9 +72,9 @@
_tx_thread_system_return??rA:
_tx_thread_system_return:
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
@@ -82,6 +85,6 @@ _tx_thread_system_return:
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context:
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

12
ports/cortex_m33/iar/src/tx_timer_interrupt.s
View File

@@ -42,7 +42,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M33/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* Scott Larson, Microsoft Corporation */
@@ -76,6 +76,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -98,7 +101,7 @@ _tx_timer_interrupt:
; if (_tx_timer_time_slice)
; {
;
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@@ -215,13 +218,13 @@ __tx_timer_dont_activate:
; if (_tx_timer_expired_time_slice)
; {
;
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
@@ -254,4 +257,3 @@ __tx_timer_nothing_expired:
;
;}
END