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Release 6.2.0

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This commit is contained in:
Tiejun Zhou
2022-10-26 23:41:13 +00:00
parent b871c33620
commit 3e8e85cdc1
173 changed files with 26264 additions and 3989 deletions
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26
ports/cortex_m55/ac6/example_build/AzureRTOS.uvmpw Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<WorkspaceName>WorkSpace</WorkspaceName>
<project>
<PathAndName>.\demo_secure_zone\demo_secure_zone.uvprojx</PathAndName>
<NodeIsActive>1</NodeIsActive>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
<project>
<PathAndName>.\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx</PathAndName>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
<project>
<PathAndName>.\ThreadX_Library.uvprojx</PathAndName>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
</ProjectWorkspace>

137
ports/cortex_m55/ac6/example_build/CS300_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc
; command above MUST be in first line (no comment above!)
;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*
ID From To Alias Security NSC
1 0x0000_0000 0x000F_FFFF 1MB Code ITCM 4 NS n/a
2 0x0010_0000 0x002F_FFFF 2MB Code SRAM (only 2MB) 5 NS n/a
4 0x1000_0000 0x100F_FFFF 1MB Code ITCM 1 S n/a
5 0x1100_0000 0x102F_FFFF 2MB Code SRAM (only 2MB) 2 S CODE NSC
7 0x2000_0000 0x203F_FFFF 4MB SRAM DTCM (4 x 1MB) 11 NS n/a
11 0x3000_0000 0x303F_FFFF 4MB SRAM DTCM (4 x 1MB) 7 S n/a
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00080000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20080000
#define __RAM_SIZE 0x00080000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
/*--------------------- CMSE Veneer Configuration ---------------------------
; <h> CMSE Veneer Configuration
; <o0> CMSE VeneerBase Address <0x0-0xFFFFFFFF:8>
; <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)
; <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
; </h>
*----------------------------------------------------------------------------*/
#define __CMSEVENEER_BASE 0x10100000
#define __CMSEVENEER_SIZE 0x00000400
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif
/*----------------------------------------------------------------------------
Region base & size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)
#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
#else
#define __CV_BASE ( __CMSEVENEER_BASE )
#endif
#define __CV_SIZE ( __CMSEVENEER_SIZE )
#else
#define __CV_SIZE ( 0 )
#endif
#define __RO_BASE ( __ROM_BASE )
#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
#define __RW_BASE ( __RAM_BASE )
#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
/*----------------------------------------------------------------------------
Scatter Region definition
*----------------------------------------------------------------------------*/
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
ER_CMSE_VENEER __CV_BASE __CV_SIZE {
*(Veneer$$CMSE)
}
}
#endif

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ports/cortex_m55/ac6/example_build/CS300_ac6_s.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse
; command above MUST be in first line (no comment above!)
;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*
ID From To Alias Security NSC
1 0x0000_0000 0x000F_FFFF 1MB Code ITCM 4 NS n/a
2 0x0010_0000 0x002F_FFFF 2MB Code SRAM (only 2MB) 5 NS n/a
4 0x1000_0000 0x100F_FFFF 1MB Code ITCM 1 S n/a
5 0x1100_0000 0x102F_FFFF 2MB Code SRAM (only 2MB) 2 S CODE NSC
7 0x2000_0000 0x203F_FFFF 4MB SRAM DTCM (4 x 1MB) 11 NS n/a
11 0x3000_0000 0x303F_FFFF 4MB SRAM DTCM (4 x 1MB) 7 S n/a
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x10000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x30000000
#define __RAM_SIZE 0x00080000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
/*--------------------- CMSE Veneer Configuration ---------------------------
; <h> CMSE Veneer Configuration
; <o0> CMSE VeneerBase Address <0x0-0xFFFFFFFF:8>
; <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)
; <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
; </h>
*----------------------------------------------------------------------------*/
#define __CMSEVENEER_BASE 0x11000000
#define __CMSEVENEER_SIZE 0x00000400
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif
/*----------------------------------------------------------------------------
Region base & size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)
#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
#else
#define __CV_BASE ( __CMSEVENEER_BASE )
#endif
#define __CV_SIZE ( __CMSEVENEER_SIZE )
#else
#define __CV_SIZE ( 0 )
#endif
#define __RO_BASE ( __ROM_BASE )
#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
#define __RW_BASE ( __RAM_BASE )
#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
/*----------------------------------------------------------------------------
Scatter Region definition
*----------------------------------------------------------------------------*/
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
ER_CMSE_VENEER __CV_BASE __CV_SIZE {
*(Veneer$$CMSE)
}
}
#endif

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ports/cortex_m55/ac6/example_build/CS300_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
#cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
#cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
#cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
#cpu0.SAU=8 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
#cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
#cpu0.INITSVTOR=0x10000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
#cpu0.INITNSVTOR=0x00000000 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#NSC_CFG_0=1 # (bool , init-time) default = '0' : Whether 0x10000000..0x1FFFFFFF is non-secure-callable
#NSC_CFG_1=0 # (bool , init-time) default = '0' : Whether 0x30000000..0x3FFFFFFF is non-secure-callable
#mps3_board.platform_type=1 # (int , init-time) default = '0x1' : 0:Original MPS3; 1:SSE-300
mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
#cpu_core.mps3_board.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#------------------------------------------------------------------------------

4
ports/cortex_m55/ac6/example_build/Debug.ini Normal file
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LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental
LOAD "..\\demo_secure_zone\\Objects\\secure_app.axf" incremental
RESET
g, \\secure_app\main_s\main

21
ports/cortex_m55/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'ThreadX_Library'
* Target: 'ThreadX_Library_Project'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM55.h"
#endif /* RTE_COMPONENTS_H */

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ports/cortex_m55/ac6/example_build/ThreadX_Library.uvoptx Normal file
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84
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/RTE_Device.h Normal file
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/*
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
#define RTE_USART0 1
// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
#define RTE_USART1 1
// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
#define RTE_ISRAM0_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
#define RTE_ISRAM1_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
#define RTE_SRAM_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
#define RTE_QSPI_MPC 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP2 1
// <q> Flash device emulated by SRAM [Driver_Flash0]
// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
#define RTE_FLASH0 1
// <q> I2C SBCon [Driver_I2C0]
// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
#define RTE_I2C0 1
#endif /* __RTE_DEVICE_H */

25
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h Normal file
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/*
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_DRIVER_CONFIG_H__
#define __CMSIS_DRIVER_CONFIG_H__
#include "system_SSE300MPS3.h"
#include "device_cfg.h"
#include "device_definition.h"
#include "platform_base_address.h"
#endif /* __CMSIS_DRIVER_CONFIG_H__ */

149
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/device_cfg.h Normal file
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/*
* Copyright (c) 2020-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __DEVICE_CFG_H__
#define __DEVICE_CFG_H__
/**
* \file device_cfg.h
* \brief Configuration file native driver re-targeting
*
* \details This file can be used to add native driver specific macro
* definitions to select which peripherals are available in the build.
*
* This is a default device configuration file with all peripherals enabled.
*/
/* Secure only peripheral configuration */
/* ARM MPS3 IO SCC */
#define MPS3_IO_S
#define MPS3_IO_DEV MPS3_IO_DEV_S
/* I2C_SBCon */
#define I2C0_SBCON_S
#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S
/* I2S */
#define MPS3_I2S_S
#define MPS3_I2S_DEV MPS3_I2S_DEV_S
/* ARM UART Controller PL011 */
#define UART0_CMSDK_S
#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S
#define UART1_CMSDK_S
#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S
#define DEFAULT_UART_BAUDRATE 115200U
/* To be used as CODE and DATA sram */
#define MPC_ISRAM0_S
#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S
#define MPC_ISRAM1_S
#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S
#define MPC_SRAM_S
#define MPC_SRAM_DEV MPC_SRAM_DEV_S
#define MPC_QSPI_S
#define MPC_QSPI_DEV MPC_QSPI_DEV_S
/** System Counter Armv8-M */
#define SYSCOUNTER_CNTRL_ARMV8_M_S
#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
#define SYSCOUNTER_READ_ARMV8_M_S
#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S
/**
* Arbitrary scaling values for test purposes
*/
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u
/* System timer */
#define SYSTIMER0_ARMV8_M_S
#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S
#define SYSTIMER1_ARMV8_M_S
#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S
#define SYSTIMER2_ARMV8_M_S
#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S
#define SYSTIMER3_ARMV8_M_S
#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S
#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
/* CMSDK GPIO driver structures */
#define GPIO0_CMSDK_S
#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
#define GPIO1_CMSDK_S
#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
#define GPIO2_CMSDK_S
#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
#define GPIO3_CMSDK_S
#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
/* System Watchdogs */
#define SYSWDOG_ARMV8_M_S
#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
/* ARM MPC SIE 300 driver structures */
#define MPC_VM0_S
#define MPC_VM0_DEV MPC_VM0_DEV_S
#define MPC_VM1_S
#define MPC_VM1_DEV MPC_VM1_DEV_S
#define MPC_SSRAM2_S
#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
#define MPC_SSRAM3_S
#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
/* ARM PPC driver structures */
#define PPC_SSE300_MAIN0_S
#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
#define PPC_SSE300_MAIN_EXP0_S
#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
#define PPC_SSE300_MAIN_EXP1_S
#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
#define PPC_SSE300_MAIN_EXP2_S
#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
#define PPC_SSE300_MAIN_EXP3_S
#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
#define PPC_SSE300_PERIPH0_S
#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
#define PPC_SSE300_PERIPH1_S
#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
#define PPC_SSE300_PERIPH_EXP0_S
#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
#define PPC_SSE300_PERIPH_EXP1_S
#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
#define PPC_SSE300_PERIPH_EXP2_S
#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
#define PPC_SSE300_PERIPH_EXP3_S
#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
/* ARM SPI PL022 */
/* Invalid device stubs are not defined */
#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */
#define SPI1_PL022_S
#define SPI1_PL022_DEV SPI1_PL022_DEV_S
#endif /* __DEVICE_CFG_H__ */

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#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
;/*
; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; */
#include "region_defs.h"
LR_CODE S_CODE_START {
ER_CODE S_CODE_START {
*.o (RESET +First)
.ANY (+RO)
}
/*
* Place the CMSE Veneers (containing the SG instruction) after the code, in
* a separate 32 bytes aligned region so that the SAU can programmed to just
* set this region as Non-Secure Callable. The maximum size of this
* executable region makes it only used the space left over by the ER_CODE
* region so that you can rely on code+veneer size combined will not exceed
* the S_CODE_SIZE value. We also substract from the available space the
* area used to align this section on 32 bytes boundary (for SAU conf).
*/
ER_CODE_CMSE_VENEER +0 ALIGN 32 {
*(Veneer$$CMSE)
}
/*
* This dummy region ensures that the next one will be aligned on a 32 bytes
* boundary, so that the following region will not be mistakenly configured
* as Non-Secure Callable by the SAU.
*/
ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
CODE_WATERMARK +0 EMPTY 0x0 {
}
/* Make sure that the sections allocated in the SRAM does not exceed the
* size of the SRAM available.
*/
ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
ER_DATA S_DATA_START {
.ANY (+ZI +RW)
}
#if HEAP_SIZE > 0
ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack
}
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
SRAM_WATERMARK +0 EMPTY 0x0 {
}
/* Make sure that the sections allocated in the SRAM does not exceed the
* size of the SRAM available.
*/
ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
}

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/*
* Copyright (c) 2019-2021 Arm Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file platform_base_address.h
* \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 +
* Ethos-U55 platform.
*/
#ifndef __PLATFORM_BASE_ADDRESS_H__
#define __PLATFORM_BASE_ADDRESS_H__
/* ======= Defines peripherals memory map addresses ======= */
/* Non-secure memory map addresses */
#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */
#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */
#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */
#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */
#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */
#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */
#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */
#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */
#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */
#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */
/* Non-Secure MSTEXPPILL Peripheral region */
#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */
#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */
#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */
#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */
#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */
#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */
#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */
#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */
#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */
#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */
#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */
#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */
#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */
#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */
#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */
#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */
#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */
#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */
#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */
#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */
#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */
#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */
#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */
/* Non-Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */
#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */
#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */
#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */
#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */
#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */
#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */
#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */
#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */
#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */
#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */
#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */
#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */
#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */
#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */
#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */
#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */
#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */
#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */
#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */
#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */
#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */
#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */
#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */
#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */
#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */
/* Secure memory map addresses */
#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */
#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */
#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */
#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */
#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */
#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */
#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */
#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */
#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */
/* Secure Subsystem peripheral region */
#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */
#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */
#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */
#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */
#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */
#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */
/* Secure MSTEXPPILL Peripheral region */
#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */
#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */
#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */
#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */
#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */
#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */
#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */
#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */
#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */
#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */
#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */
#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */
#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */
#define USB_BASE_S 0x51500000 /* USB Secure base address */
#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */
#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */
#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */
#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */
#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */
#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */
#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */
#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */
#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */
/* Secure Subsystem peripheral region */
#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */
#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */
#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */
#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */
#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */
#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */
#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */
#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */
#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */
#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */
#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */
#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */
#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */
/* Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */
#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */
#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */
#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */
#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */
#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */
#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */
#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */
#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */
#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */
#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */
#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */
#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */
#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */
#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */
#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */
#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */
#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */
#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */
#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */
#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */
#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */
#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */
#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */
#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */
#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */
/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller
* Access from Non-secure software is only allowed
* if AIRCR.BFHFNMINS is set to 1 */
/* Memory size definitions */
#define ITCM_SIZE (0x00080000) /* 512 kB */
#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */
#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
#define SRAM_SIZE (0x00100000) /* 1 MB */
#define ISRAM0_SIZE (0x00100000) /* 1 MB */
#define ISRAM1_SIZE (0x00100000) /* 1 MB */
#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */
#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */
#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */
/* Defines for Driver MPC's */
/* SRAM -- 2 MB */
#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS)
#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1)
#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S)
#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1)
#define MPC_SRAM_RANGE_OFFSET_S (0x0)
/* QSPI -- 8 MB*/
#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS)
#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S)
#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
#define MPC_QSPI_RANGE_OFFSET_S (0x0)
/* ISRAM0 -- 2 MB*/
#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS)
#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S)
#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1)
#define MPC_ISRAM0_RANGE_OFFSET_S (0x0)
/* ISRAM1 -- 2 MB*/
#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS)
#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S)
#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1)
#define MPC_ISRAM1_RANGE_OFFSET_S (0x0)
/* DDR4 -- 2GB (8 * 256 MB) */
#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S)
#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS)
#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS)
#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS)
#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S)
#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
#endif /* __PLATFORM_BASE_ADDRESS_H__ */

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/*
* Copyright (c) 2016-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_DEFS_H__
#define __REGION_DEFS_H__
#include "region_limits.h"
/* **************************************************************
* WARNING: this file is parsed both by the C/C++ compiler
* and the linker. As a result the syntax must be valid not only
* for C/C++ but for the linker scripts too.
* Beware of the following limitations:
* - LD (GCC linker) requires white space around operators.
* - UL postfix for macros is not suported by the linker script
****************************************************************/
/* Secure regions */
#define S_CODE_START ( S_ROM_ALIAS )
#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE )
#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE )
#define S_DATA_START ( S_RAM_ALIAS )
#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE )
#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE )
#define S_DDR4_START ( S_DDR4_ALIAS )
#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE )
#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE )
#endif /* __REGION_DEFS_H__ */

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/*
* Copyright (c) 2018-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_LIMITS_H__
#define __REGION_LIMITS_H__
/* **************************************************************
* WARNING: this file is parsed both by the C/C++ compiler
* and the linker. As a result the syntax must be valid not only
* for C/C++ but for the linker scripts too.
* Beware of the following limitations:
* - LD (GCC linker) requires white space around operators.
* - UL postfix for macros is not suported by the linker script
****************************************************************/
/* Secure Code */
#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */
#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */
/* Secure Data */
#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */
#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */
/* Secure DDR4 */
#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */
#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */
/* Heap and Stack sizes for secure and nonsecure applications */
#define HEAP_SIZE (0x00000400) /* 1 KiB */
#define STACK_SIZE (0x00000400) /* 1 KiB */
#endif /* __REGION_LIMITS_H__ */

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/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#include "SSE300MPS3.h"
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern void __PROGRAM_START(void) __NO_RETURN;
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Reset_Handler (void) __NO_RETURN;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
#define DEFAULT_IRQ_HANDLER(handler_name) \
void __WEAK __NO_RETURN handler_name(void); \
void handler_name(void) { \
while(1); \
}
/* Exceptions */
DEFAULT_IRQ_HANDLER(NMI_Handler)
DEFAULT_IRQ_HANDLER(HardFault_Handler)
DEFAULT_IRQ_HANDLER(MemManage_Handler)
DEFAULT_IRQ_HANDLER(BusFault_Handler)
DEFAULT_IRQ_HANDLER(UsageFault_Handler)
DEFAULT_IRQ_HANDLER(SecureFault_Handler)
DEFAULT_IRQ_HANDLER(SVC_Handler)
DEFAULT_IRQ_HANDLER(DebugMon_Handler)
DEFAULT_IRQ_HANDLER(PendSV_Handler)
DEFAULT_IRQ_HANDLER(SysTick_Handler)
DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
DEFAULT_IRQ_HANDLER(TIMER0_Handler)
DEFAULT_IRQ_HANDLER(TIMER1_Handler)
DEFAULT_IRQ_HANDLER(TIMER2_Handler)
DEFAULT_IRQ_HANDLER(MPC_Handler)
DEFAULT_IRQ_HANDLER(PPC_Handler)
DEFAULT_IRQ_HANDLER(MSC_Handler)
DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
DEFAULT_IRQ_HANDLER(TIMER3_Handler)
DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
DEFAULT_IRQ_HANDLER(I2S_Handler)
DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
DEFAULT_IRQ_HANDLER(USB_Handler)
DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
DEFAULT_IRQ_HANDLER(UART5_Handler)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const pFunc __VECTOR_TABLE[496];
const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
HardFault_Handler, /* -13: Hard Fault Handler */
MemManage_Handler, /* -12: MPU Fault Handler */
BusFault_Handler, /* -11: Bus Fault Handler */
UsageFault_Handler, /* -10: Usage Fault Handler */
SecureFault_Handler, /* -9: Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5: SVCall Handler */
DebugMon_Handler, /* -4: Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2: PendSV Handler */
SysTick_Handler, /* -1: SysTick Handler */
NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */
NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
TIMER0_Handler, /* 3: TIMER 0 Handler */
TIMER1_Handler, /* 4: TIMER 1 Handler */
TIMER2_Handler, /* 5: TIMER 2 Handler */
0, /* 6: Reserved */
0, /* 7: Reserved */
0, /* 8: Reserved */
MPC_Handler, /* 9: MPC Combined (Secure) Handler */
PPC_Handler, /* 10: PPC Combined (Secure) Handler */
MSC_Handler, /* 11: MSC Combined (Secure) Handler */
BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
0, /* 13: Reserved */
MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
SYS_PPU_Handler, /* 15: SYS PPU Handler */
CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
0, /* 17: Reserved */
0, /* 18: Reserved */
0, /* 19: Reserved */
0, /* 20: Reserved */
0, /* 21: Reserved */
0, /* 22: Reserved */
0, /* 23: Reserved */
0, /* 24: Reserved */
0, /* 25: Reserved */
DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
TIMER3_Handler, /* 27: TIMER 3 Handler */
CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */
CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */
0, /* 30: Reserved */
0, /* 31: Reserved */
/* External interrupts */
System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
UARTRX0_Handler, /* 33: UART 0 RX Handler */
UARTTX0_Handler, /* 34: UART 0 TX Handler */
UARTRX1_Handler, /* 35: UART 1 RX Handler */
UARTTX1_Handler, /* 36: UART 1 TX Handler */
UARTRX2_Handler, /* 37: UART 2 RX Handler */
UARTTX2_Handler, /* 38: UART 2 TX Handler */
UARTRX3_Handler, /* 39: UART 3 RX Handler */
UARTTX3_Handler, /* 40: UART 3 TX Handler */
UARTRX4_Handler, /* 41: UART 4 RX Handler */
UARTTX4_Handler, /* 42: UART 4 TX Handler */
UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
ETHERNET_Handler, /* 49: Ethernet Handler */
I2S_Handler, /* 50: Audio I2S Handler */
TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
USB_Handler, /* 52: USB Handler */
SPI_ADC_Handler, /* 53: SPI ADC Handler */
SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
0, /* 57: Reserved */
0, /* 58: Reserved */
0, /* 59: Reserved */
0, /* 60: Reserved */
0, /* 61: Reserved */
0, /* 62: Reserved */
0, /* 63: Reserved */
0, /* 64: Reserved */
0, /* 65: Reserved */
0, /* 66: Reserved */
0, /* 67: Reserved */
0, /* 68: Reserved */
GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
UART5_Handler, /* 127: UART 5 combined Interrupt */
0, /* 128: Reserved */
0, /* 129: Reserved */
0, /* 130: Reserved */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}

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/*
* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#include "SSE300MPS3.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_CS300.h"
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (32000000UL)
#define SYSTEM_CLOCK (XTAL)
#define PERIPHERAL_CLOCK (25000000UL)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __VECTOR_TABLE;
#endif
/*****************************************************************/
/*------------------- Memory Protection Controller -----------------------------*/
typedef struct
{
__IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
uint32_t RESERVED0[3];
__IM uint32_t BLK_MAX; /* Offset: 0x010 (R/ ) Block Maximum Register */
__IM uint32_t BLK_CFG; /* Offset: 0x014 (R/ ) Block Configuration Register */
__IOM uint32_t BLK_IDX; /* Offset: 0x018 (R/W) Block Index Register */
__IOM uint32_t BLK_LUT; /* Offset: 0x01C (R/W) Block Lookup Tabe Register */
__IM uint32_t INT_STAT; /* Offset: 0x020 (R/ ) Interrupt Status Register */
__OM uint32_t INT_CLEAR; /* Offset: 0x024 ( /W) Interrupt Clear Register */
__IOM uint32_t INT_EN; /* Offset: 0x028 (R/W) Interrupt Enable Register */
__IM uint32_t INT_INFO1; /* Offset: 0x02C (R/ ) Interrupt Info1 Register */
__IM uint32_t INT_INFO2; /* Offset: 0x030 (R/ ) Interrupt Info2 Register */
__OM uint32_t INT_SET; /* Offset: 0x034 ( /W) Interrupt Set Register */
} MPC_TypeDef;
#define MPC_SRAM ((MPC_TypeDef *) MPC_SRAM_BASE_S )
#define MPC_ISRAM0 ((MPC_TypeDef *) MPC_ISRAM0_BASE_S )
/*------------------- Secure Privilege Control Block -----------------------------*/
typedef struct
{
uint32_t RESERVED0[5U];
__IOM uint32_t NSCCFG; /* Offset: 0x014 (R/W) Non Secure Callable Configuration for IDAU */
} SAC_TypeDef;
#define SAC ((SAC_TypeDef *) SSE300_SACFG_BASE_S )
/*------------------- TCM Gating Unit --------------------------------------------*/
typedef struct /* see "Arm Cortex-Mxx Technical Reference Manual r0p1"
" */
{
__IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Gate Control Register */
__IM uint32_t CFG; /* Offset: 0x004 (R/ ) Gate Configuration Register */
uint32_t RESERVED0[2];
__IOM uint32_t LUT[16]; /* Offset: 0x010 (R/W) Gate Look-up Table Register */
} TGU_TypeDef;
#define ITGU_BASE (0xE001E500UL) /* ITCM Gating Unit */
#define DTGU_BASE (0xE001E600UL) /* DTCM Gating Unit */
#define ITGU ((TGU_TypeDef *) ITGU_BASE)
#define DTGU ((TGU_TypeDef *) DTGU_BASE)
/*****************************************************************/
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
uint32_t PeripheralClock = PERIPHERAL_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
PeripheralClock = PERIPHERAL_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
/* Set low-power state for PDEPU */
/* 0b00 | ON, PDEPU is not in low-power state */
/* 0b01 | ON, but the clock is off */
/* 0b10 | RET(ention) */
/* 0b11 | OFF */
/* Clear ELPSTATE, value is 0b11 on Cold reset */
PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);
/* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
/* PDEPU ON, Clock OFF */
PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
/* Enable Loop and branch info cache */
SCB->CCR |= SCB_CCR_LOB_Msk;
__DSB();
__ISB();
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Enable BusFault, UsageFault, MemManageFault and SecureFault to ease diagnostic */
SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk |
SCB_SHCSR_BUSFAULTENA_Msk |
SCB_SHCSR_MEMFAULTENA_Msk |
SCB_SHCSR_SECUREFAULTENA_Msk);
/* BFSR register setting to enable precise errors */
SCB->CFSR |= SCB_CFSR_PRECISERR_Msk;
/* configure unsecure code area: ITCM 512K 0x00080000 - 0x00100000 */
// blk_cfg = ITGU->CFG & 0xF; /* = 0x7 */
// blk_size = 1UL << (blk_cfg + 5U); /* = 0x1000 (4K) */
ITGU->LUT[4] = 0xFFFFFFFF;
ITGU->LUT[5] = 0xFFFFFFFF;
ITGU->LUT[6] = 0xFFFFFFFF;
ITGU->LUT[7] = 0xFFFFFFFF;
/* configure unsecure data area: DTCM 512K 0x20080000 - 0x20100000 */
// blk_cfg = DTGU->CFG & 0xF; /* = 0x7 */
// blk_size = 1UL << (blk_cfg + 5U); /* = 0x1000 (4K) */
DTGU->LUT[4] = 0xFFFFFFFF;
DTGU->LUT[5] = 0xFFFFFFFF;
DTGU->LUT[6] = 0xFFFFFFFF;
DTGU->LUT[7] = 0xFFFFFFFF;
/* Non Secure Callable Configuration for IDAU (NSCCFG register) */
SAC->NSCCFG |= 1U; /* Configure CODE region (0x1000_0000 to 0x1FFF_FFFF) Non-secure Callable */
//SAC->NSCCFG |= 2U; /* Configure RAM region (0x3000_0000 to 0x3FFF_FFFF) Non-secure Callable */
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

48
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h Normal file
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/*
* Copyright (c) 2009-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#ifndef __SYSTEM_CORE_INIT_H__
#define __SYSTEM_CORE_INIT_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
/**
* \brief Initializes the system
*/
extern void SystemInit(void);
/**
* \brief Restores system core clock
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_CORE_INIT_H__ */

21
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'demo_secure_zone'
* Target: 'FVP Simulation Model'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "SSE300MPS3.h"
#endif /* RTE_COMPONENTS_H */

366
ports/cortex_m55/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx Normal file
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@@ -0,0 +1,366 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>0</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>..\Debug.ini</tIfile>
<pMon>BIN\DbgFMv8M.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2V8M</Key>
<Name>UL2V8M(-S0 -C0 -P0 -FC1000 -FD01000000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S"System Generator:cpu_core" -L"cpu0" -O4102 -C0 -MC"$K\ARM\VHT\VHT_MPS3_Corstone_SSE-300.exe" -MF"..\CS300_config.txt" -PF -MA</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=4619,189,4877,920,0)(6015=3743,140,4001,762,0)(6003=-1,-1,-1,-1,0)(6000=4424,206,4877,538,0)(6020=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>48</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>268439734</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>&lt;1&gt;.\main_s.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\secure_app\main_s.c\48</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>thread_0_counter</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>thread_1_counter</ItemText>
</Ww>
<Ww>
<count>2</count>
<WinNumber>1</WinNumber>
<ItemText>thread_2_counter</ItemText>
</Ww>
<Ww>
<count>3</count>
<WinNumber>1</WinNumber>
<ItemText>thread_3_counter</ItemText>
</Ww>
<Ww>
<count>4</count>
<WinNumber>1</WinNumber>
<ItemText>thread_4_counter</ItemText>
</Ww>
<Ww>
<count>5</count>
<WinNumber>1</WinNumber>
<ItemText>thread_5_counter</ItemText>
</Ww>
<Ww>
<count>6</count>
<WinNumber>1</WinNumber>
<ItemText>thread_6_counter</ItemText>
</Ww>
<Ww>
<count>7</count>
<WinNumber>1</WinNumber>
<ItemText>thread_7_counter</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>2</SubType>
<ItemText>0x01000400</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>Secure Code</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main_s.c</PathWithFileName>
<FilenameWithoutPath>main_s.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\tx_thread_secure_stack.c</PathWithFileName>
<FilenameWithoutPath>tx_thread_secure_stack.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\tx_thread_interrupt_disable.S</PathWithFileName>
<FilenameWithoutPath>tx_thread_interrupt_disable.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\tx_thread_interrupt_restore.S</PathWithFileName>
<FilenameWithoutPath>tx_thread_interrupt_restore.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Interface</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\interface.c</PathWithFileName>
<FilenameWithoutPath>interface.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Native Driver</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

580
ports/cortex_m55/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx Normal file
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@@ -0,0 +1,580 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6180000::V6.18::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>SSE-300-MPS3</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.V2M_MPS3_SSE_300_BSP.1.3.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x00000000,0x00080000) IRAM2(0x01000000,0x00200000) XRAM(0x20000000,0x00020000) XRAM2(0x20020000,0x00020000) XRAM3(0x20040000,0x00020000) CPUTYPE("Cortex-M55") FPU3(DFPU) DSP TZ MVE(FP) CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD01000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:SSE-300-MPS3$Device\Include\SSE300MPS3.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:SSE-300-MPS3$SVD\SSE300.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>secure_app</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>1</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName></SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll></SimDlgDll>
<SimDlgDllArguments></SimDlgDllArguments>
<TargetDllName>SARMV8M.DLL</TargetDllName>
<TargetDllArguments> -MPU -MVE</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM55</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>0</Capability>
<DriverSelection>4102</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2V8M.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M55"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>1</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>3</RvdsVP>
<RvdsMve>2</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>0</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>1</nSecure>
<RoSelD>0</RoSelD>
<RwSelD>4</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x200000</Size>
</IROM>
<XRAM>
<Type>1</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x20020000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x20040000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x1000000</StartAddress>
<Size>0x200000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>2</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>3</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-documentation -Wno-documentation-unknown-command -Wno-license-management -Wno-missing-noreturn -Wno-missing-prototypes -Wno-missing-variable-declarations -Wno-nonportable-include-path -Wno-packed -Wno-parentheses-equality -Wno-reserved-id-macro -Wno-unused-macros -xc</MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>.\RTE\Device\SSE-300-MPS3, ..\..\..\..\..\common\inc, ..\..\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>2</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x00000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>..\CS300_ac6_s.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--import-cmse-lib-out="..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o" --summary_stderr --info summarysizes --load_addr_map_info --entry=Reset_Handler</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Secure Code</GroupName>
<Files>
<File>
<FileName>main_s.c</FileName>
<FileType>1</FileType>
<FilePath>.\main_s.c</FilePath>
</File>
<File>
<FileName>tx_thread_secure_stack.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\tx_thread_secure_stack.c</FilePath>
</File>
<File>
<FileName>tx_thread_interrupt_disable.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\src\tx_thread_interrupt_disable.S</FilePath>
</File>
<File>
<FileName>tx_thread_interrupt_restore.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\src\tx_thread_interrupt_restore.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Interface</GroupName>
<Files>
<File>
<FileName>interface.c</FileName>
<FileType>1</FileType>
<FilePath>.\interface.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
<Group>
<GroupName>::Native Driver</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0" condition="SSE-300-MPS3 Device">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0" condition="SSE-300-MPS3 Device">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0" condition="SSE-300-MPS3 Systimer Syscounter">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="linkerScript" condition="Startup ARMCC6 Secure" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6_s.sct" version="1.1.0">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6_s.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="header" condition="TZ Secure" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.1">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.1.0">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.1">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="header" name="CMSIS_Driver\Config\RTE_Device.h" version="1.1.0">
<instance index="0">RTE\Device\SSE-300-MPS3\RTE_Device.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS_Driver\Config\Baremetal\cmsis_driver_config.h" version="1.1.1">
<instance index="0">RTE\Device\SSE-300-MPS3\cmsis_driver_config.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Device\Config\Baremetal\device_cfg.h" version="1.1.3">
<instance index="0">RTE\Device\SSE-300-MPS3\device_cfg.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="linkerScript" name="Device\Source\armclang\fvp_sse300_mps3_s.sct" version="1.1.0">
<instance index="0">RTE\Device\SSE-300-MPS3\fvp_sse300_mps3_s.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Board\Platform\platform_base_address.h" version="1.1.2">
<instance index="0">RTE\Device\SSE-300-MPS3\platform_base_address.h</instance>
<component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Device\Include\region_defs.h" version="1.0.0">
<instance index="0">RTE\Device\SSE-300-MPS3\region_defs.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Device\Include\region_limits.h" version="1.0.0">
<instance index="0">RTE\Device\SSE-300-MPS3\region_limits.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="source" name="Device\Source\startup_fvp_sse300_mps3.c" version="1.1.1">
<instance index="0">RTE\Device\SSE-300-MPS3\startup_fvp_sse300_mps3.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="source" name="Device\Source\system_SSE300MPS3.c" version="1.1.1">
<instance index="0">RTE\Device\SSE-300-MPS3\system_SSE300MPS3.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Device\Include\system_SSE300MPS3.h" version="1.1.1">
<instance index="0">RTE\Device\SSE-300-MPS3\system_SSE300MPS3.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
</files>
</RTE>
</Project>

49
ports/cortex_m55/ac6/example_build/demo_secure_zone/interface.c Normal file
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@@ -0,0 +1,49 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* interface.c Secure/non-secure callable application code
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
#include <arm_cmse.h> // CMSE definitions
#include "interface.h" // Header file with secure interface API
/* typedef for non-secure callback functions */
typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));
/* Non-secure callable (entry) function */
int func1(int x) __attribute__((cmse_nonsecure_entry)) {
return x+3;
}
/* Non-secure callable (entry) function, calling a non-secure callback function */
int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) {
funcptr_NS callback_NS; // non-secure callback function pointer
int y;
/* return function pointer with cleared LSB */
callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);
y = callback_NS (x+1);
return (y+2);
}

31
ports/cortex_m55/ac6/example_build/demo_secure_zone/interface.h Normal file
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@@ -0,0 +1,31 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* interface.h API definition for the non-secure state
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
/* Function pointer declaration */
typedef int (*funcptr)(int);
/* Non-secure callable functions */
extern int func1(int x);
extern int func2(funcptr callback, int x);

60
ports/cortex_m55/ac6/example_build/demo_secure_zone/main_s.c Normal file
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@@ -0,0 +1,60 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Code template for secure main function
*
*---------------------------------------------------------------------------*/
#include "region_limits.h"
#include "RTE_Components.h"
#include CMSIS_device_header
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS 0x00080000U
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}

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/*
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Context Management for ARMv8-M TrustZone - Sample implementation
*
*---------------------------------------------------------------------------*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "tz_context.h"
/// Number of process slots (threads may call secure library code)
#ifndef TZ_PROCESS_STACK_SLOTS
#define TZ_PROCESS_STACK_SLOTS 8U
#endif
/// Stack size of the secure library code
#ifndef TZ_PROCESS_STACK_SIZE
#define TZ_PROCESS_STACK_SIZE 256U
#endif
typedef struct {
uint32_t sp_top; // stack space top
uint32_t sp_limit; // stack space limit
uint32_t sp; // current stack pointer
} stack_info_t;
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_InitContextSystem_S (void) {
uint32_t n;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
ProcessStackInfo[n].sp = 0U;
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
}
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
ProcessStackFreeSlot = 0U;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
// Privileged Thread Mode using PSP
__set_CONTROL(0x02U);
return 1U; // Success
}
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
__attribute__((cmse_nonsecure_entry))
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
uint32_t slot;
(void)module; // Ignore (fixed Stack size)
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
return 0U; // No slot available
}
slot = ProcessStackFreeSlot;
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
return (slot + 1U);
}
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
ProcessStackInfo[slot].sp = 0U;
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
ProcessStackFreeSlot = slot;
return 1U; // Success
}
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
// Setup process stack pointer and stack limit
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
__set_PSP (ProcessStackInfo[slot].sp);
return 1U; // Success
}
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
uint32_t slot;
uint32_t sp;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
sp = __get_PSP();
if ((sp < ProcessStackInfo[slot].sp_limit) ||
(sp > ProcessStackInfo[slot].sp_top)) {
return 0U; // SP out of range
}
ProcessStackInfo[slot].sp = sp;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
return 1U; // Success
}

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/*
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
#define RTE_USART0 1
// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
#define RTE_USART1 1
// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
#define RTE_ISRAM0_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
#define RTE_ISRAM1_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
#define RTE_SRAM_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
#define RTE_QSPI_MPC 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP2 1
// <q> Flash device emulated by SRAM [Driver_Flash0]
// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
#define RTE_FLASH0 1
// <q> I2C SBCon [Driver_I2C0]
// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
#define RTE_I2C0 1
#endif /* __RTE_DEVICE_H */

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/*
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_DRIVER_CONFIG_H__
#define __CMSIS_DRIVER_CONFIG_H__
#include "system_SSE300MPS3.h"
#include "device_cfg.h"
#include "device_definition.h"
#include "platform_base_address.h"
#endif /* __CMSIS_DRIVER_CONFIG_H__ */

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/*
* Copyright (c) 2020-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __DEVICE_CFG_H__
#define __DEVICE_CFG_H__
/**
* \file device_cfg.h
* \brief Configuration file native driver re-targeting
*
* \details This file can be used to add native driver specific macro
* definitions to select which peripherals are available in the build.
*
* This is a default device configuration file with all peripherals enabled.
*/
/* Secure only peripheral configuration */
/* ARM MPS3 IO SCC */
#define MPS3_IO_S
#define MPS3_IO_DEV MPS3_IO_DEV_S
/* I2C_SBCon */
#define I2C0_SBCON_S
#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S
/* I2S */
#define MPS3_I2S_S
#define MPS3_I2S_DEV MPS3_I2S_DEV_S
/* ARM UART Controller PL011 */
#define UART0_CMSDK_S
#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S
#define UART1_CMSDK_S
#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S
#define DEFAULT_UART_BAUDRATE 115200U
/* To be used as CODE and DATA sram */
#define MPC_ISRAM0_S
#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S
#define MPC_ISRAM1_S
#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S
#define MPC_SRAM_S
#define MPC_SRAM_DEV MPC_SRAM_DEV_S
#define MPC_QSPI_S
#define MPC_QSPI_DEV MPC_QSPI_DEV_S
/** System Counter Armv8-M */
#define SYSCOUNTER_CNTRL_ARMV8_M_S
#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
#define SYSCOUNTER_READ_ARMV8_M_S
#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S
/**
* Arbitrary scaling values for test purposes
*/
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u
/* System timer */
#define SYSTIMER0_ARMV8_M_S
#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S
#define SYSTIMER1_ARMV8_M_S
#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S
#define SYSTIMER2_ARMV8_M_S
#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S
#define SYSTIMER3_ARMV8_M_S
#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S
#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
/* CMSDK GPIO driver structures */
#define GPIO0_CMSDK_S
#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
#define GPIO1_CMSDK_S
#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
#define GPIO2_CMSDK_S
#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
#define GPIO3_CMSDK_S
#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
/* System Watchdogs */
#define SYSWDOG_ARMV8_M_S
#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
/* ARM MPC SIE 300 driver structures */
#define MPC_VM0_S
#define MPC_VM0_DEV MPC_VM0_DEV_S
#define MPC_VM1_S
#define MPC_VM1_DEV MPC_VM1_DEV_S
#define MPC_SSRAM2_S
#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
#define MPC_SSRAM3_S
#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
/* ARM PPC driver structures */
#define PPC_SSE300_MAIN0_S
#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
#define PPC_SSE300_MAIN_EXP0_S
#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
#define PPC_SSE300_MAIN_EXP1_S
#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
#define PPC_SSE300_MAIN_EXP2_S
#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
#define PPC_SSE300_MAIN_EXP3_S
#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
#define PPC_SSE300_PERIPH0_S
#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
#define PPC_SSE300_PERIPH1_S
#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
#define PPC_SSE300_PERIPH_EXP0_S
#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
#define PPC_SSE300_PERIPH_EXP1_S
#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
#define PPC_SSE300_PERIPH_EXP2_S
#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
#define PPC_SSE300_PERIPH_EXP3_S
#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
/* ARM SPI PL022 */
/* Invalid device stubs are not defined */
#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */
#define SPI1_PL022_S
#define SPI1_PL022_DEV SPI1_PL022_DEV_S
#endif /* __DEVICE_CFG_H__ */

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#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
;/*
; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; */
#include "region_defs.h"
LR_CODE S_CODE_START {
ER_CODE S_CODE_START {
*.o (RESET +First)
.ANY (+RO)
}
/*
* Place the CMSE Veneers (containing the SG instruction) after the code, in
* a separate 32 bytes aligned region so that the SAU can programmed to just
* set this region as Non-Secure Callable. The maximum size of this
* executable region makes it only used the space left over by the ER_CODE
* region so that you can rely on code+veneer size combined will not exceed
* the S_CODE_SIZE value. We also substract from the available space the
* area used to align this section on 32 bytes boundary (for SAU conf).
*/
ER_CODE_CMSE_VENEER +0 ALIGN 32 {
*(Veneer$$CMSE)
}
/*
* This dummy region ensures that the next one will be aligned on a 32 bytes
* boundary, so that the following region will not be mistakenly configured
* as Non-Secure Callable by the SAU.
*/
ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
CODE_WATERMARK +0 EMPTY 0x0 {
}
/* Make sure that the sections allocated in the SRAM does not exceed the
* size of the SRAM available.
*/
ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
ER_DATA S_DATA_START {
.ANY (+ZI +RW)
}
#if HEAP_SIZE > 0
ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack
}
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
SRAM_WATERMARK +0 EMPTY 0x0 {
}
/* Make sure that the sections allocated in the SRAM does not exceed the
* size of the SRAM available.
*/
ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
}

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/*
* Copyright (c) 2019-2021 Arm Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file platform_base_address.h
* \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 +
* Ethos-U55 platform.
*/
#ifndef __PLATFORM_BASE_ADDRESS_H__
#define __PLATFORM_BASE_ADDRESS_H__
/* ======= Defines peripherals memory map addresses ======= */
/* Non-secure memory map addresses */
#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */
#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */
#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */
#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */
#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */
#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */
#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */
#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */
#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */
#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */
/* Non-Secure MSTEXPPILL Peripheral region */
#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */
#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */
#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */
#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */
#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */
#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */
#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */
#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */
#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */
#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */
#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */
#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */
#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */
#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */
#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */
#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */
#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */
#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */
#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */
#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */
#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */
#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */
#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */
/* Non-Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */
#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */
#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */
#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */
#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */
#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */
#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */
#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */
#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */
#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */
#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */
#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */
#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */
#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */
#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */
#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */
#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */
#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */
#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */
#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */
#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */
#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */
#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */
#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */
#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */
#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */
/* Secure memory map addresses */
#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */
#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */
#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */
#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */
#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */
#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */
#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */
#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */
#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */
/* Secure Subsystem peripheral region */
#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */
#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */
#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */
#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */
#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */
#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */
/* Secure MSTEXPPILL Peripheral region */
#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */
#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */
#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */
#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */
#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */
#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */
#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */
#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */
#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */
#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */
#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */
#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */
#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */
#define USB_BASE_S 0x51500000 /* USB Secure base address */
#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */
#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */
#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */
#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */
#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */
#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */
#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */
#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */
#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */
/* Secure Subsystem peripheral region */
#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */
#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */
#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */
#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */
#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */
#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */
#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */
#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */
#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */
#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */
#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */
#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */
#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */
/* Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */
#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */
#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */
#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */
#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */
#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */
#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */
#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */
#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */
#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */
#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */
#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */
#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */
#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */
#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */
#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */
#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */
#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */
#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */
#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */
#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */
#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */
#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */
#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */
#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */
#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */
/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller
* Access from Non-secure software is only allowed
* if AIRCR.BFHFNMINS is set to 1 */
/* Memory size definitions */
#define ITCM_SIZE (0x00080000) /* 512 kB */
#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */
#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
#define SRAM_SIZE (0x00100000) /* 1 MB */
#define ISRAM0_SIZE (0x00100000) /* 1 MB */
#define ISRAM1_SIZE (0x00100000) /* 1 MB */
#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */
#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */
#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */
/* Defines for Driver MPC's */
/* SRAM -- 2 MB */
#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS)
#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1)
#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S)
#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1)
#define MPC_SRAM_RANGE_OFFSET_S (0x0)
/* QSPI -- 8 MB*/
#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS)
#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S)
#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
#define MPC_QSPI_RANGE_OFFSET_S (0x0)
/* ISRAM0 -- 2 MB*/
#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS)
#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S)
#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1)
#define MPC_ISRAM0_RANGE_OFFSET_S (0x0)
/* ISRAM1 -- 2 MB*/
#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS)
#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S)
#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1)
#define MPC_ISRAM1_RANGE_OFFSET_S (0x0)
/* DDR4 -- 2GB (8 * 256 MB) */
#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S)
#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS)
#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS)
#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS)
#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S)
#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
#endif /* __PLATFORM_BASE_ADDRESS_H__ */

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/*
* Copyright (c) 2016-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_DEFS_H__
#define __REGION_DEFS_H__
#include "region_limits.h"
/* **************************************************************
* WARNING: this file is parsed both by the C/C++ compiler
* and the linker. As a result the syntax must be valid not only
* for C/C++ but for the linker scripts too.
* Beware of the following limitations:
* - LD (GCC linker) requires white space around operators.
* - UL postfix for macros is not suported by the linker script
****************************************************************/
/* Secure regions */
#define S_CODE_START ( S_ROM_ALIAS )
#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE )
#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE )
#define S_DATA_START ( S_RAM_ALIAS )
#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE )
#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE )
#define S_DDR4_START ( S_DDR4_ALIAS )
#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE )
#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE )
#endif /* __REGION_DEFS_H__ */

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/*
* Copyright (c) 2018-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_LIMITS_H__
#define __REGION_LIMITS_H__
/* **************************************************************
* WARNING: this file is parsed both by the C/C++ compiler
* and the linker. As a result the syntax must be valid not only
* for C/C++ but for the linker scripts too.
* Beware of the following limitations:
* - LD (GCC linker) requires white space around operators.
* - UL postfix for macros is not suported by the linker script
****************************************************************/
/* Secure Code */
#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */
#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */
/* Secure Data */
#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */
#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */
/* Secure DDR4 */
#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */
#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */
/* Heap and Stack sizes for secure and nonsecure applications */
#define HEAP_SIZE (0x00000400) /* 1 KiB */
#define STACK_SIZE (0x00000400) /* 1 KiB */
#endif /* __REGION_LIMITS_H__ */

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/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#include "SSE300MPS3.h"
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern void __PROGRAM_START(void) __NO_RETURN;
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Reset_Handler (void) __NO_RETURN;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
#define DEFAULT_IRQ_HANDLER(handler_name) \
void __WEAK __NO_RETURN handler_name(void); \
void handler_name(void) { \
while(1); \
}
/* Exceptions */
DEFAULT_IRQ_HANDLER(NMI_Handler)
DEFAULT_IRQ_HANDLER(HardFault_Handler)
DEFAULT_IRQ_HANDLER(MemManage_Handler)
DEFAULT_IRQ_HANDLER(BusFault_Handler)
DEFAULT_IRQ_HANDLER(UsageFault_Handler)
DEFAULT_IRQ_HANDLER(SecureFault_Handler)
DEFAULT_IRQ_HANDLER(SVC_Handler)
DEFAULT_IRQ_HANDLER(DebugMon_Handler)
DEFAULT_IRQ_HANDLER(PendSV_Handler)
DEFAULT_IRQ_HANDLER(SysTick_Handler)
DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
DEFAULT_IRQ_HANDLER(TIMER0_Handler)
DEFAULT_IRQ_HANDLER(TIMER1_Handler)
DEFAULT_IRQ_HANDLER(TIMER2_Handler)
DEFAULT_IRQ_HANDLER(MPC_Handler)
DEFAULT_IRQ_HANDLER(PPC_Handler)
DEFAULT_IRQ_HANDLER(MSC_Handler)
DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
DEFAULT_IRQ_HANDLER(TIMER3_Handler)
DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
DEFAULT_IRQ_HANDLER(I2S_Handler)
DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
DEFAULT_IRQ_HANDLER(USB_Handler)
DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
DEFAULT_IRQ_HANDLER(UART5_Handler)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const pFunc __VECTOR_TABLE[496];
const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
HardFault_Handler, /* -13: Hard Fault Handler */
MemManage_Handler, /* -12: MPU Fault Handler */
BusFault_Handler, /* -11: Bus Fault Handler */
UsageFault_Handler, /* -10: Usage Fault Handler */
SecureFault_Handler, /* -9: Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5: SVCall Handler */
DebugMon_Handler, /* -4: Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2: PendSV Handler */
SysTick_Handler, /* -1: SysTick Handler */
NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */
NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
TIMER0_Handler, /* 3: TIMER 0 Handler */
TIMER1_Handler, /* 4: TIMER 1 Handler */
TIMER2_Handler, /* 5: TIMER 2 Handler */
0, /* 6: Reserved */
0, /* 7: Reserved */
0, /* 8: Reserved */
MPC_Handler, /* 9: MPC Combined (Secure) Handler */
PPC_Handler, /* 10: PPC Combined (Secure) Handler */
MSC_Handler, /* 11: MSC Combined (Secure) Handler */
BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
0, /* 13: Reserved */
MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
SYS_PPU_Handler, /* 15: SYS PPU Handler */
CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
0, /* 17: Reserved */
0, /* 18: Reserved */
0, /* 19: Reserved */
0, /* 20: Reserved */
0, /* 21: Reserved */
0, /* 22: Reserved */
0, /* 23: Reserved */
0, /* 24: Reserved */
0, /* 25: Reserved */
DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
TIMER3_Handler, /* 27: TIMER 3 Handler */
CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */
CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */
0, /* 30: Reserved */
0, /* 31: Reserved */
/* External interrupts */
System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
UARTRX0_Handler, /* 33: UART 0 RX Handler */
UARTTX0_Handler, /* 34: UART 0 TX Handler */
UARTRX1_Handler, /* 35: UART 1 RX Handler */
UARTTX1_Handler, /* 36: UART 1 TX Handler */
UARTRX2_Handler, /* 37: UART 2 RX Handler */
UARTTX2_Handler, /* 38: UART 2 TX Handler */
UARTRX3_Handler, /* 39: UART 3 RX Handler */
UARTTX3_Handler, /* 40: UART 3 TX Handler */
UARTRX4_Handler, /* 41: UART 4 RX Handler */
UARTTX4_Handler, /* 42: UART 4 TX Handler */
UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
ETHERNET_Handler, /* 49: Ethernet Handler */
I2S_Handler, /* 50: Audio I2S Handler */
TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
USB_Handler, /* 52: USB Handler */
SPI_ADC_Handler, /* 53: SPI ADC Handler */
SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
0, /* 57: Reserved */
0, /* 58: Reserved */
0, /* 59: Reserved */
0, /* 60: Reserved */
0, /* 61: Reserved */
0, /* 62: Reserved */
0, /* 63: Reserved */
0, /* 64: Reserved */
0, /* 65: Reserved */
0, /* 66: Reserved */
0, /* 67: Reserved */
0, /* 68: Reserved */
GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
UART5_Handler, /* 127: UART 5 combined Interrupt */
0, /* 128: Reserved */
0, /* 129: Reserved */
0, /* 130: Reserved */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}

86
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c Normal file
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/*
* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#include "SSE300MPS3.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (32000000UL)
#define SYSTEM_CLOCK (XTAL)
#define PERIPHERAL_CLOCK (25000000UL)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __VECTOR_TABLE;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
uint32_t PeripheralClock = PERIPHERAL_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
PeripheralClock = PERIPHERAL_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
/* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set
* CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU
* into retention state
*/
PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL;
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
/* Enable Loop and branch info cache */
SCB->CCR |= SCB_CCR_LOB_Msk;
__DSB();
__ISB();
}

48
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h Normal file
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/*
* Copyright (c) 2009-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#ifndef __SYSTEM_CORE_INIT_H__
#define __SYSTEM_CORE_INIT_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
/**
* \brief Initializes the system
*/
extern void SystemInit(void);
/**
* \brief Restores system core clock
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_CORE_INIT_H__ */

21
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h Normal file
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@@ -0,0 +1,21 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'demo_threadx_non-secure_zone'
* Target: 'FVP Simulation Model'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "SSE300MPS3.h"
#endif /* RTE_COMPONENTS_H */

305
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt Normal file
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@@ -0,0 +1,305 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>ThreadX_Demo</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>1</uSim>
<uTrg>0</uTrg>
<sLdApp>1</sLdApp>
<sGomain>0</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>0</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>-1</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon></pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name>-T5F</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
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401
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c Normal file
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/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete
description of this demonstration. */
#include "tx_api.h"
#include "..\demo_secure_zone\interface.h" /* Interface to sample secure functions. */
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9120
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define the ThreadX object control blocks... */
static TX_THREAD thread_0;
static TX_THREAD thread_1;
static TX_THREAD thread_2;
static TX_THREAD thread_3;
static TX_THREAD thread_4;
static TX_THREAD thread_5;
static TX_THREAD thread_6;
static TX_THREAD thread_7;
static TX_QUEUE queue_0;
static TX_SEMAPHORE semaphore_0;
static TX_MUTEX mutex_0;
static TX_EVENT_FLAGS_GROUP event_flags_0;
static TX_BYTE_POOL byte_pool_0;
static TX_BLOCK_POOL block_pool_0;
/* Define byte pool memory. */
static UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE];
/* Define event buffer. */
#ifdef TX_ENABLE_EVENT_TRACE
UCHAR trace_buffer[0x10000];
#endif
/* Define the counters used in the demo application... */
static ULONG thread_0_counter;
static ULONG thread_1_counter;
static ULONG thread_1_messages_sent;
static ULONG thread_2_counter;
static ULONG thread_2_messages_received;
static ULONG thread_3_counter;
static ULONG thread_4_counter;
static ULONG thread_5_counter;
static ULONG thread_6_counter;
static ULONG thread_7_counter;
/* Define thread prototypes. */
void thread_0_entry(ULONG thread_input);
void thread_1_entry(ULONG thread_input);
void thread_2_entry(ULONG thread_input);
void thread_3_and_4_entry(ULONG thread_input);
void thread_5_entry(ULONG thread_input);
void thread_6_and_7_entry(ULONG thread_input);
/* Define main entry point. */
int main()
{
/* Please refer to Chapter 6 of the ThreadX User Guide for a complete
description of this demonstration. */
/* Enter the ThreadX kernel. */
tx_kernel_enter();
}
/* Define what the initial system looks like. */
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer;
(VOID)first_unused_memory; /* unused parameter. */
#ifdef TX_ENABLE_EVENT_TRACE
tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32);
#endif
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE);
/* Put system definition stuff in here, e.g. thread creates and other assorted
create information. */
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
/* Create the message queue shared by threads 1 and 2. */
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
/* Create the semaphore used by threads 3 and 4. */
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
/* Create the event flags group used by threads 1 and 5. */
tx_event_flags_create(&event_flags_0, "event flags 0");
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
/* Allocate the memory for a small block pool. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
/* Create a block memory pool to allocate a message buffer from. */
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
/* Allocate a block and release the block memory. */
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
/* Release the block back to the pool. */
tx_block_release(pointer);
tx_thread_secure_stack_allocate(&thread_0,256);
tx_thread_secure_stack_allocate(&thread_1,256);
tx_thread_secure_stack_allocate(&thread_2,256);
tx_thread_secure_stack_allocate(&thread_3,256);
tx_thread_secure_stack_allocate(&thread_4,256);
tx_thread_secure_stack_allocate(&thread_5,256);
tx_thread_secure_stack_allocate(&thread_6,256);
tx_thread_secure_stack_allocate(&thread_7,256);
}
/* Define the test threads. */
void thread_0_entry(ULONG thread_input)
{
UINT status;
(VOID)thread_input; /* unused parameter. */
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
/* Increment the thread counter. */
thread_0_counter++;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_1_entry(ULONG thread_input)
{
UINT status;
(VOID)thread_input; /* unused parameter. */
/* This thread simply sends messages to a queue shared by thread 2. */
while(1)
{
/* Increment the thread counter. */
thread_1_counter++;
/* Send message to queue 0. */
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
/* Check completion status. */
if (status != TX_SUCCESS)
break;
/* Increment the message sent. */
thread_1_messages_sent++;
}
}
void thread_2_entry(ULONG thread_input)
{
ULONG received_message;
UINT status;
(VOID)thread_input; /* unused parameter. */
/* This thread retrieves messages placed on the queue by thread 1. */
while(1)
{
/* Increment the thread counter. */
thread_2_counter++;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
}
void thread_3_and_4_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 3 and thread 4. As the loop
below shows, these function compete for ownership of semaphore_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 3)
thread_3_counter++;
else
thread_4_counter++;
/* Get the semaphore with suspension. */
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the semaphore. */
tx_thread_sleep(2);
/* Release the semaphore. */
status = tx_semaphore_put(&semaphore_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_5_entry(ULONG thread_input)
{
UINT status;
ULONG actual_flags;
(VOID)thread_input; /* unused parameter. */
/* This thread simply waits for an event in a forever loop. */
while(1)
{
/* Increment the thread counter. */
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
break;
}
}
void thread_6_and_7_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 6 and thread 7. As the loop
below shows, these function compete for ownership of mutex_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 6)
thread_6_counter++;
else
thread_7_counter++;
/* Get the mutex with suspension. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Get the mutex again with suspension. This shows
that an owning thread may retrieve the mutex it
owns multiple times. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the mutex. */
tx_thread_sleep(2);
/* Release the mutex. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}

342
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx Normal file
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<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6180000::V6.18::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>SSE-300-MPS3</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.V2M_MPS3_SSE_300_BSP.1.3.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x00000000,0x00080000) IRAM2(0x01000000,0x00200000) XRAM(0x20000000,0x00020000) XRAM2(0x20020000,0x00020000) XRAM3(0x20040000,0x00020000) CPUTYPE("Cortex-M55") FPU3(DFPU) DSP TZ MVE(FP) CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD01000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:SSE-300-MPS3$Device\Include\SSE300MPS3.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:SSE-300-MPS3$SVD\SSE300.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>demo_threadx_non-secure_zone</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>1</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName></SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll></SimDlgDll>
<SimDlgDllArguments></SimDlgDllArguments>
<TargetDllName>SARMV8M.DLL</TargetDllName>
<TargetDllArguments> -MPU -MVE</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM55</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>0</Capability>
<DriverSelection>4102</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2V8M.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M55"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>1</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>3</RvdsVP>
<RvdsMve>2</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>0</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>0</RoSelD>
<RwSelD>4</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x200000</Size>
</IROM>
<XRAM>
<Type>1</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x20020000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x20040000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x1000000</StartAddress>
<Size>0x200000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>2</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>3</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\..\common\inc, ..\..\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>..\CS300_ac6.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Non-secure Code</GroupName>
<Files>
<File>
<FileName>demo_threadx.c</FileName>
<FileType>1</FileType>
<FilePath>.\demo_threadx.c</FilePath>
</File>
<File>
<FileName>ThreadX_Library.lib</FileName>
<FileType>4</FileType>
<FilePath>..\ThreadX_Library.lib</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CMSE Library</GroupName>
<Files>
<File>
<FileName>interface.h</FileName>
<FileType>5</FileType>
<FilePath>..\demo_secure_zone\interface.h</FilePath>
</File>
<File>
<FileName>demo_secure_zone_CMSE_Lib.o</FileName>
<FileType>3</FileType>
<FilePath>..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
<Group>
<GroupName>::Native Driver</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0" condition="SSE-300-MPS3 Device">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0" condition="SSE-300-MPS3 Device">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0" condition="SSE-300-MPS3 Systimer Syscounter">
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="linkerScript" condition="Startup ARMCC6 Unsecure" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.1.0">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.1.0">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.1">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="header" name="CMSIS_Driver\Config\RTE_Device.h" version="1.1.0">
<instance index="0">RTE\Device\SSE-300-MPS3\RTE_Device.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS_Driver\Config\Baremetal\cmsis_driver_config.h" version="1.1.1">
<instance index="0">RTE\Device\SSE-300-MPS3\cmsis_driver_config.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Device\Config\Baremetal\device_cfg.h" version="1.1.3">
<instance index="0">RTE\Device\SSE-300-MPS3\device_cfg.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="linkerScript" name="Device\Source\armclang\fvp_sse300_mps3_s.sct" version="1.1.0">
<instance index="0">RTE\Device\SSE-300-MPS3\fvp_sse300_mps3_s.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Board\Platform\platform_base_address.h" version="1.1.2">
<instance index="0">RTE\Device\SSE-300-MPS3\platform_base_address.h</instance>
<component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Device\Include\region_defs.h" version="1.0.0">
<instance index="0">RTE\Device\SSE-300-MPS3\region_defs.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Device\Include\region_limits.h" version="1.0.0">
<instance index="0">RTE\Device\SSE-300-MPS3\region_limits.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="source" name="Device\Source\startup_fvp_sse300_mps3.c" version="1.1.1">
<instance index="0">RTE\Device\SSE-300-MPS3\startup_fvp_sse300_mps3.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="source" name="Device\Source\system_SSE300MPS3.c" version="1.1.1">
<instance index="0">RTE\Device\SSE-300-MPS3\system_SSE300MPS3.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Device\Include\system_SSE300MPS3.h" version="1.1.1">
<instance index="0">RTE\Device\SSE-300-MPS3\system_SSE300MPS3.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" condition="SSE-300-MPS3 Device"/>
<package name="V2M_MPS3_SSE_300_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="1.3.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
</files>
</RTE>
</Project>

278
ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S Normal file
View File

@@ -0,0 +1,278 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
/**************************************************************************/
/**************************************************************************/
SYSTEM_CLOCK = 25000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
/* Setup the stack and heap areas. */
STACK_SIZE = 0x00000400
HEAP_SIZE = 0x00000000
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M33/AC6 */
/* 6.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)
// {
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global _tx_initialize_low_level
.thumb_func
.type _tx_initialize_low_level, function
_tx_initialize_low_level:
/* Disable interrupts during ThreadX initialization. */
CPSID i
/* Set base of available memory to end of non-initialised RAM area. */
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address
ADD r1, r1, #4 //
STR r1, [r0] // Setup first unused memory pointer
/* Setup Vector Table Offset Register. */
MOV r0, #0xE000E000 // Build address of NVIC registers
LDR r1, =__Vectors // Pickup address of vector table
STR r1, [r0, #0xD08] // Set vector table address
/* Enable the cycle count register. */
LDR r0, =0xE0001000 // Build address of DWT register
LDR r1, [r0] // Pickup the current value
ORR r1, r1, #1 // Set the CYCCNTENA bit
STR r1, [r0] // Enable the cycle count register
/* Set system stack pointer from vector value. */
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
LDR r1, =__Vectors // Pickup address of vector table
LDR r1, [r1] // Pickup reset stack pointer
STR r1, [r0] // Save system stack pointer
/* Configure SysTick. */
MOV r0, #0xE000E000 // Build address of NVIC registers
LDR r1, =SYSTICK_CYCLES
STR r1, [r0, #0x14] // Setup SysTick Reload Value
MOV r1, #0x7 // Build SysTick Control Enable Value
STR r1, [r0, #0x10] // Setup SysTick Control
/* Configure handler priorities. */
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers
// Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers
// Note: PnSV must be lowest priority, which is 0xFF
/* Return to caller. */
BX lr
// }
/* Define shells for each of the unused vectors. */
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global __tx_BadHandler
.thumb_func
.type __tx_BadHandler, function
__tx_BadHandler:
B __tx_BadHandler
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global __tx_IntHandler
.thumb_func
.type __tx_IntHandler, function
__tx_IntHandler:
// VOID InterruptHandler (VOID)
// {
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_enter // Call the ISR enter function
#endif
/* Do interrupt handler work here */
/* .... */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_exit // Call the ISR exit function
#endif
POP {r0,lr}
BX LR
// }
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global SysTick_Handler
.thumb_func
.type SysTick_Handler, function
SysTick_Handler:
// VOID TimerInterruptHandler (VOID)
// {
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_enter // Call the ISR enter function
#endif
BL _tx_timer_interrupt
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_exit // Call the ISR exit function
#endif
POP {r0,lr}
BX LR
// }
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global HardFault_Handler
.thumb_func
.type HardFault_Handler, function
HardFault_Handler:
B HardFault_Handler
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global UsageFault_Handler
.thumb_func
.type UsageFault_Handler, function
UsageFault_Handler:
CPSID i // Disable interrupts
// Check for stack limit fault
LDR r0, =0xE000ED28 // CFSR address
LDR r1,[r0] // Pick up CFSR
TST r1, #0x00100000 // Check for Stack Overflow
_unhandled_usage_loop:
BEQ _unhandled_usage_loop // If not stack overflow then loop
// Handle stack overflow
STR r1, [r0] // Clear CFSR flag(s)
#ifdef __ARM_PCS_VFP
LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address
LDR r1, [r0] // Load FPCCR
BIC r1, r1, #1 // Clear the lazy preservation active bit
STR r1, [r0] // Store the value
#endif
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
LDR r0,[r0] // Pick up current thread pointer
PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment)
BL _tx_thread_stack_error_handler // Call ThreadX/user handler
POP {r0,lr} // Restore LR and dummy reg
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
// Call the thread exit function to indicate the thread is no longer executing.
PUSH {r0, lr} // Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit // Call the thread exit function
POP {r0, lr} // Recover LR
#endif
MOV r1, #0 // Build NULL value
LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer
STR r1, [r0] // Clear current thread pointer
// Return from UsageFault_Handler exception
LDR r0, =0xE000ED04 // Load ICSR
LDR r1, =0x10000000 // Set PENDSVSET bit
STR r1, [r0] // Store ICSR
DSB // Wait for memory access to complete
CPSIE i // Enable interrupts
BX lr // Return from exception
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global __tx_NMIHandler
.thumb_func
.type __tx_NMIHandler, function
__tx_NMIHandler:
B __tx_NMIHandler
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global __tx_DBGHandler
.thumb_func
.type __tx_DBGHandler, function
__tx_DBGHandler:
B __tx_DBGHandler
.end

5
ports/cortex_m55/iar/src/tx_misra.s
View File

@@ -111,9 +111,9 @@
PUBLIC _tx_misra_semaphore_put_notify_not_used
PUBLIC _tx_misra_thread_entry_exit_notify_not_used
PUBLIC _tx_misra_thread_not_used
PUBLIC _tx_version_id
#ifdef TX_MISRA_ENABLE
PUBLIC _tx_version_id
SECTION `.data`:DATA:REORDER:NOROOT(2)
DATA
@@ -130,6 +130,7 @@ _tx_version_id:
DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H
DC8 6EH, 74H, 20H, 2AH, 0
DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
#endif //TX_MISRA_ENABLE
/**************************************************************************/
/**************************************************************************/